Commit | Line | Data |
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669a5db4 JG |
1 | /* |
2 | * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers. | |
3 | * | |
4 | * This driver is heavily based upon: | |
5 | * | |
6 | * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 | |
7 | * | |
8 | * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> | |
9 | * Portions Copyright (C) 2001 Sun Microsystems, Inc. | |
10 | * Portions Copyright (C) 2003 Red Hat Inc | |
8e834c2e | 11 | * Portions Copyright (C) 2005-2010 MontaVista Software, Inc. |
669a5db4 JG |
12 | * |
13 | * TODO | |
d44a65f7 | 14 | * Look into engine reset on timeout errors. Should not be required. |
669a5db4 JG |
15 | */ |
16 | ||
8d7b1c70 JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
669a5db4 JG |
19 | #include <linux/kernel.h> |
20 | #include <linux/module.h> | |
21 | #include <linux/pci.h> | |
669a5db4 JG |
22 | #include <linux/blkdev.h> |
23 | #include <linux/delay.h> | |
24 | #include <scsi/scsi_host.h> | |
25 | #include <linux/libata.h> | |
26 | ||
27 | #define DRV_NAME "pata_hpt37x" | |
8d7b1c70 | 28 | #define DRV_VERSION "0.6.23" |
669a5db4 JG |
29 | |
30 | struct hpt_clock { | |
31 | u8 xfer_speed; | |
32 | u32 timing; | |
33 | }; | |
34 | ||
35 | struct hpt_chip { | |
36 | const char *name; | |
37 | unsigned int base; | |
38 | struct hpt_clock const *clocks[4]; | |
39 | }; | |
40 | ||
41 | /* key for bus clock timings | |
42 | * bit | |
fd5e62e2 SS |
43 | * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. |
44 | * cycles = value + 1 | |
45 | * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. | |
46 | * cycles = value + 1 | |
47 | * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file | |
669a5db4 | 48 | * register access. |
fd5e62e2 | 49 | * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file |
669a5db4 | 50 | * register access. |
fd5e62e2 SS |
51 | * 18:20 udma_cycle_time. Clock cycles for UDMA xfer. |
52 | * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock. | |
53 | * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer. | |
54 | * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file | |
669a5db4 | 55 | * register access. |
fd5e62e2 SS |
56 | * 28 UDMA enable. |
57 | * 29 DMA enable. | |
58 | * 30 PIO_MST enable. If set, the chip is in bus master mode during | |
59 | * PIO xfer. | |
60 | * 31 FIFO enable. Only for PIO. | |
669a5db4 JG |
61 | */ |
62 | ||
fcc2f69a AC |
63 | static struct hpt_clock hpt37x_timings_33[] = { |
64 | { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */ | |
65 | { XFER_UDMA_5, 0x12446231 }, | |
66 | { XFER_UDMA_4, 0x12446231 }, | |
67 | { XFER_UDMA_3, 0x126c6231 }, | |
68 | { XFER_UDMA_2, 0x12486231 }, | |
69 | { XFER_UDMA_1, 0x124c6233 }, | |
70 | { XFER_UDMA_0, 0x12506297 }, | |
71 | ||
72 | { XFER_MW_DMA_2, 0x22406c31 }, | |
73 | { XFER_MW_DMA_1, 0x22406c33 }, | |
74 | { XFER_MW_DMA_0, 0x22406c97 }, | |
75 | ||
76 | { XFER_PIO_4, 0x06414e31 }, | |
77 | { XFER_PIO_3, 0x06414e42 }, | |
78 | { XFER_PIO_2, 0x06414e53 }, | |
79 | { XFER_PIO_1, 0x06814e93 }, | |
80 | { XFER_PIO_0, 0x06814ea7 } | |
669a5db4 JG |
81 | }; |
82 | ||
fcc2f69a AC |
83 | static struct hpt_clock hpt37x_timings_50[] = { |
84 | { XFER_UDMA_6, 0x12848242 }, | |
85 | { XFER_UDMA_5, 0x12848242 }, | |
86 | { XFER_UDMA_4, 0x12ac8242 }, | |
87 | { XFER_UDMA_3, 0x128c8242 }, | |
88 | { XFER_UDMA_2, 0x120c8242 }, | |
89 | { XFER_UDMA_1, 0x12148254 }, | |
90 | { XFER_UDMA_0, 0x121882ea }, | |
91 | ||
92 | { XFER_MW_DMA_2, 0x22808242 }, | |
93 | { XFER_MW_DMA_1, 0x22808254 }, | |
94 | { XFER_MW_DMA_0, 0x228082ea }, | |
95 | ||
96 | { XFER_PIO_4, 0x0a81f442 }, | |
97 | { XFER_PIO_3, 0x0a81f443 }, | |
98 | { XFER_PIO_2, 0x0a81f454 }, | |
99 | { XFER_PIO_1, 0x0ac1f465 }, | |
100 | { XFER_PIO_0, 0x0ac1f48a } | |
669a5db4 JG |
101 | }; |
102 | ||
fcc2f69a AC |
103 | static struct hpt_clock hpt37x_timings_66[] = { |
104 | { XFER_UDMA_6, 0x1c869c62 }, | |
105 | { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */ | |
106 | { XFER_UDMA_4, 0x1c8a9c62 }, | |
107 | { XFER_UDMA_3, 0x1c8e9c62 }, | |
108 | { XFER_UDMA_2, 0x1c929c62 }, | |
109 | { XFER_UDMA_1, 0x1c9a9c62 }, | |
110 | { XFER_UDMA_0, 0x1c829c62 }, | |
111 | ||
112 | { XFER_MW_DMA_2, 0x2c829c62 }, | |
113 | { XFER_MW_DMA_1, 0x2c829c66 }, | |
114 | { XFER_MW_DMA_0, 0x2c829d2e }, | |
115 | ||
116 | { XFER_PIO_4, 0x0c829c62 }, | |
117 | { XFER_PIO_3, 0x0c829c84 }, | |
118 | { XFER_PIO_2, 0x0c829ca6 }, | |
119 | { XFER_PIO_1, 0x0d029d26 }, | |
120 | { XFER_PIO_0, 0x0d029d5e } | |
669a5db4 JG |
121 | }; |
122 | ||
669a5db4 JG |
123 | |
124 | static const struct hpt_chip hpt370 = { | |
125 | "HPT370", | |
126 | 48, | |
127 | { | |
fcc2f69a | 128 | hpt37x_timings_33, |
669a5db4 JG |
129 | NULL, |
130 | NULL, | |
a4734468 | 131 | NULL |
669a5db4 JG |
132 | } |
133 | }; | |
134 | ||
135 | static const struct hpt_chip hpt370a = { | |
136 | "HPT370A", | |
137 | 48, | |
138 | { | |
fcc2f69a | 139 | hpt37x_timings_33, |
669a5db4 | 140 | NULL, |
fcc2f69a | 141 | hpt37x_timings_50, |
a4734468 | 142 | NULL |
669a5db4 JG |
143 | } |
144 | }; | |
145 | ||
146 | static const struct hpt_chip hpt372 = { | |
147 | "HPT372", | |
148 | 55, | |
149 | { | |
fcc2f69a | 150 | hpt37x_timings_33, |
669a5db4 | 151 | NULL, |
fcc2f69a AC |
152 | hpt37x_timings_50, |
153 | hpt37x_timings_66 | |
669a5db4 JG |
154 | } |
155 | }; | |
156 | ||
157 | static const struct hpt_chip hpt302 = { | |
158 | "HPT302", | |
159 | 66, | |
160 | { | |
fcc2f69a | 161 | hpt37x_timings_33, |
669a5db4 | 162 | NULL, |
fcc2f69a AC |
163 | hpt37x_timings_50, |
164 | hpt37x_timings_66 | |
669a5db4 JG |
165 | } |
166 | }; | |
167 | ||
168 | static const struct hpt_chip hpt371 = { | |
169 | "HPT371", | |
170 | 66, | |
171 | { | |
fcc2f69a | 172 | hpt37x_timings_33, |
669a5db4 | 173 | NULL, |
fcc2f69a AC |
174 | hpt37x_timings_50, |
175 | hpt37x_timings_66 | |
669a5db4 JG |
176 | } |
177 | }; | |
178 | ||
179 | static const struct hpt_chip hpt372a = { | |
180 | "HPT372A", | |
181 | 66, | |
182 | { | |
fcc2f69a | 183 | hpt37x_timings_33, |
669a5db4 | 184 | NULL, |
fcc2f69a AC |
185 | hpt37x_timings_50, |
186 | hpt37x_timings_66 | |
669a5db4 JG |
187 | } |
188 | }; | |
189 | ||
190 | static const struct hpt_chip hpt374 = { | |
191 | "HPT374", | |
192 | 48, | |
193 | { | |
fcc2f69a | 194 | hpt37x_timings_33, |
669a5db4 JG |
195 | NULL, |
196 | NULL, | |
197 | NULL | |
198 | } | |
199 | }; | |
200 | ||
201 | /** | |
202 | * hpt37x_find_mode - reset the hpt37x bus | |
203 | * @ap: ATA port | |
204 | * @speed: transfer mode | |
205 | * | |
206 | * Return the 32bit register programming information for this channel | |
207 | * that matches the speed provided. | |
208 | */ | |
85cd7251 | 209 | |
669a5db4 JG |
210 | static u32 hpt37x_find_mode(struct ata_port *ap, int speed) |
211 | { | |
212 | struct hpt_clock *clocks = ap->host->private_data; | |
85cd7251 | 213 | |
49bfbd38 | 214 | while (clocks->xfer_speed) { |
669a5db4 JG |
215 | if (clocks->xfer_speed == speed) |
216 | return clocks->timing; | |
217 | clocks++; | |
218 | } | |
219 | BUG(); | |
220 | return 0xffffffffU; /* silence compiler warning */ | |
221 | } | |
222 | ||
49bfbd38 SS |
223 | static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, |
224 | const char * const list[]) | |
669a5db4 | 225 | { |
8bfa79fc | 226 | unsigned char model_num[ATA_ID_PROD_LEN + 1]; |
dc85ca57 | 227 | int i; |
669a5db4 | 228 | |
8bfa79fc | 229 | ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); |
669a5db4 | 230 | |
dc85ca57 AS |
231 | i = match_string(list, -1, model_num); |
232 | if (i >= 0) { | |
233 | pr_warn("%s is not supported for %s\n", modestr, list[i]); | |
234 | return 1; | |
669a5db4 JG |
235 | } |
236 | return 0; | |
237 | } | |
238 | ||
49bfbd38 SS |
239 | static const char * const bad_ata33[] = { |
240 | "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", | |
241 | "Maxtor 90845U3", "Maxtor 90650U2", | |
242 | "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", | |
243 | "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", | |
244 | "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", | |
245 | "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", | |
669a5db4 JG |
246 | "Maxtor 90510D4", |
247 | "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", | |
49bfbd38 SS |
248 | "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", |
249 | "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", | |
250 | "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", | |
251 | "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", | |
669a5db4 JG |
252 | NULL |
253 | }; | |
254 | ||
49bfbd38 | 255 | static const char * const bad_ata100_5[] = { |
669a5db4 JG |
256 | "IBM-DTLA-307075", |
257 | "IBM-DTLA-307060", | |
258 | "IBM-DTLA-307045", | |
259 | "IBM-DTLA-307030", | |
260 | "IBM-DTLA-307020", | |
261 | "IBM-DTLA-307015", | |
262 | "IBM-DTLA-305040", | |
263 | "IBM-DTLA-305030", | |
264 | "IBM-DTLA-305020", | |
265 | "IC35L010AVER07-0", | |
266 | "IC35L020AVER07-0", | |
267 | "IC35L030AVER07-0", | |
268 | "IC35L040AVER07-0", | |
269 | "IC35L060AVER07-0", | |
270 | "WDC AC310200R", | |
271 | NULL | |
272 | }; | |
273 | ||
274 | /** | |
275 | * hpt370_filter - mode selection filter | |
669a5db4 JG |
276 | * @adev: ATA device |
277 | * | |
278 | * Block UDMA on devices that cause trouble with this controller. | |
279 | */ | |
85cd7251 | 280 | |
a76b62ca | 281 | static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask) |
669a5db4 | 282 | { |
6929da44 | 283 | if (adev->class == ATA_DEV_ATA) { |
669a5db4 JG |
284 | if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33)) |
285 | mask &= ~ATA_MASK_UDMA; | |
286 | if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) | |
6ddd6861 | 287 | mask &= ~(0xE0 << ATA_SHIFT_UDMA); |
669a5db4 | 288 | } |
c7087652 | 289 | return mask; |
669a5db4 JG |
290 | } |
291 | ||
292 | /** | |
293 | * hpt370a_filter - mode selection filter | |
669a5db4 JG |
294 | * @adev: ATA device |
295 | * | |
296 | * Block UDMA on devices that cause trouble with this controller. | |
297 | */ | |
85cd7251 | 298 | |
a76b62ca | 299 | static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask) |
669a5db4 | 300 | { |
73946f9f | 301 | if (adev->class == ATA_DEV_ATA) { |
669a5db4 | 302 | if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) |
6ddd6861 | 303 | mask &= ~(0xE0 << ATA_SHIFT_UDMA); |
669a5db4 | 304 | } |
c7087652 | 305 | return mask; |
669a5db4 | 306 | } |
85cd7251 | 307 | |
8e834c2e SS |
308 | /** |
309 | * hpt372_filter - mode selection filter | |
310 | * @adev: ATA device | |
311 | * @mask: mode mask | |
312 | * | |
313 | * The Marvell bridge chips used on the HighPoint SATA cards do not seem | |
314 | * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes... | |
315 | */ | |
316 | static unsigned long hpt372_filter(struct ata_device *adev, unsigned long mask) | |
317 | { | |
318 | if (ata_id_is_sata(adev->id)) | |
319 | mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA); | |
320 | ||
321 | return mask; | |
322 | } | |
323 | ||
9e87be9e BZ |
324 | /** |
325 | * hpt37x_cable_detect - Detect the cable type | |
326 | * @ap: ATA port to detect on | |
327 | * | |
328 | * Return the cable type attached to this port | |
329 | */ | |
330 | ||
331 | static int hpt37x_cable_detect(struct ata_port *ap) | |
332 | { | |
333 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
334 | u8 scr2, ata66; | |
335 | ||
336 | pci_read_config_byte(pdev, 0x5B, &scr2); | |
337 | pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); | |
10a9c969 BZ |
338 | |
339 | udelay(10); /* debounce */ | |
340 | ||
9e87be9e BZ |
341 | /* Cable register now active */ |
342 | pci_read_config_byte(pdev, 0x5A, &ata66); | |
343 | /* Restore state */ | |
344 | pci_write_config_byte(pdev, 0x5B, scr2); | |
345 | ||
346 | if (ata66 & (2 >> ap->port_no)) | |
347 | return ATA_CBL_PATA40; | |
348 | else | |
349 | return ATA_CBL_PATA80; | |
350 | } | |
351 | ||
352 | /** | |
353 | * hpt374_fn1_cable_detect - Detect the cable type | |
354 | * @ap: ATA port to detect on | |
355 | * | |
356 | * Return the cable type attached to this port | |
357 | */ | |
358 | ||
359 | static int hpt374_fn1_cable_detect(struct ata_port *ap) | |
360 | { | |
361 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
362 | unsigned int mcrbase = 0x50 + 4 * ap->port_no; | |
363 | u16 mcr3; | |
364 | u8 ata66; | |
365 | ||
366 | /* Do the extra channel work */ | |
367 | pci_read_config_word(pdev, mcrbase + 2, &mcr3); | |
368 | /* Set bit 15 of 0x52 to enable TCBLID as input */ | |
369 | pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000); | |
370 | pci_read_config_byte(pdev, 0x5A, &ata66); | |
371 | /* Reset TCBLID/FCBLID to output */ | |
372 | pci_write_config_word(pdev, mcrbase + 2, mcr3); | |
373 | ||
374 | if (ata66 & (2 >> ap->port_no)) | |
375 | return ATA_CBL_PATA40; | |
376 | else | |
377 | return ATA_CBL_PATA80; | |
378 | } | |
379 | ||
669a5db4 JG |
380 | /** |
381 | * hpt37x_pre_reset - reset the hpt37x bus | |
cc0680a5 | 382 | * @link: ATA link to reset |
d4b2bab4 | 383 | * @deadline: deadline jiffies for the operation |
669a5db4 | 384 | * |
ab81a505 | 385 | * Perform the initial reset handling for the HPT37x. |
669a5db4 | 386 | */ |
85cd7251 | 387 | |
cc0680a5 | 388 | static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline) |
669a5db4 | 389 | { |
cc0680a5 | 390 | struct ata_port *ap = link->ap; |
669a5db4 | 391 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
b5bf24b9 AC |
392 | static const struct pci_bits hpt37x_enable_bits[] = { |
393 | { 0x50, 1, 0x04, 0x04 }, | |
394 | { 0x54, 1, 0x04, 0x04 } | |
395 | }; | |
49bfbd38 | 396 | |
b5bf24b9 AC |
397 | if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no])) |
398 | return -ENOENT; | |
f20b16ff | 399 | |
669a5db4 | 400 | /* Reset the state machine */ |
fcc2f69a | 401 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); |
669a5db4 | 402 | udelay(100); |
85cd7251 | 403 | |
9363c382 | 404 | return ata_sff_prereset(link, deadline); |
669a5db4 JG |
405 | } |
406 | ||
1a1b172b SS |
407 | static void hpt370_set_mode(struct ata_port *ap, struct ata_device *adev, |
408 | u8 mode) | |
669a5db4 JG |
409 | { |
410 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
411 | u32 addr1, addr2; | |
1a1b172b | 412 | u32 reg, timing, mask; |
669a5db4 JG |
413 | u8 fast; |
414 | ||
415 | addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); | |
416 | addr2 = 0x51 + 4 * ap->port_no; | |
85cd7251 | 417 | |
669a5db4 JG |
418 | /* Fast interrupt prediction disable, hold off interrupt disable */ |
419 | pci_read_config_byte(pdev, addr2, &fast); | |
420 | fast &= ~0x02; | |
421 | fast |= 0x01; | |
422 | pci_write_config_byte(pdev, addr2, fast); | |
85cd7251 | 423 | |
1a1b172b SS |
424 | /* Determine timing mask and find matching mode entry */ |
425 | if (mode < XFER_MW_DMA_0) | |
426 | mask = 0xcfc3ffff; | |
427 | else if (mode < XFER_UDMA_0) | |
428 | mask = 0x31c001ff; | |
429 | else | |
430 | mask = 0x303c0000; | |
431 | ||
432 | timing = hpt37x_find_mode(ap, mode); | |
433 | ||
669a5db4 | 434 | pci_read_config_dword(pdev, addr1, ®); |
1a1b172b SS |
435 | reg = (reg & ~mask) | (timing & mask); |
436 | pci_write_config_dword(pdev, addr1, reg); | |
437 | } | |
438 | /** | |
439 | * hpt370_set_piomode - PIO setup | |
440 | * @ap: ATA interface | |
441 | * @adev: device on the interface | |
442 | * | |
443 | * Perform PIO mode setup. | |
444 | */ | |
445 | ||
446 | static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
447 | { | |
448 | hpt370_set_mode(ap, adev, adev->pio_mode); | |
669a5db4 JG |
449 | } |
450 | ||
451 | /** | |
452 | * hpt370_set_dmamode - DMA timing setup | |
453 | * @ap: ATA interface | |
454 | * @adev: Device being configured | |
455 | * | |
1a1b172b | 456 | * Set up the channel for MWDMA or UDMA modes. |
669a5db4 | 457 | */ |
85cd7251 | 458 | |
669a5db4 JG |
459 | static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
460 | { | |
1a1b172b | 461 | hpt370_set_mode(ap, adev, adev->dma_mode); |
669a5db4 JG |
462 | } |
463 | ||
669a5db4 JG |
464 | /** |
465 | * hpt370_bmdma_end - DMA engine stop | |
466 | * @qc: ATA command | |
467 | * | |
468 | * Work around the HPT370 DMA engine. | |
469 | */ | |
85cd7251 | 470 | |
669a5db4 JG |
471 | static void hpt370_bmdma_stop(struct ata_queued_cmd *qc) |
472 | { | |
473 | struct ata_port *ap = qc->ap; | |
474 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
0d5ff566 | 475 | void __iomem *bmdma = ap->ioaddr.bmdma_addr; |
56f46f8c SS |
476 | u8 dma_stat = ioread8(bmdma + ATA_DMA_STATUS); |
477 | u8 dma_cmd; | |
85cd7251 | 478 | |
56f46f8c | 479 | if (dma_stat & ATA_DMA_ACTIVE) { |
669a5db4 | 480 | udelay(20); |
56f46f8c | 481 | dma_stat = ioread8(bmdma + ATA_DMA_STATUS); |
669a5db4 | 482 | } |
56f46f8c | 483 | if (dma_stat & ATA_DMA_ACTIVE) { |
669a5db4 JG |
484 | /* Clear the engine */ |
485 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); | |
486 | udelay(10); | |
487 | /* Stop DMA */ | |
56f46f8c SS |
488 | dma_cmd = ioread8(bmdma + ATA_DMA_CMD); |
489 | iowrite8(dma_cmd & ~ATA_DMA_START, bmdma + ATA_DMA_CMD); | |
669a5db4 | 490 | /* Clear Error */ |
56f46f8c SS |
491 | dma_stat = ioread8(bmdma + ATA_DMA_STATUS); |
492 | iowrite8(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR, | |
493 | bmdma + ATA_DMA_STATUS); | |
669a5db4 JG |
494 | /* Clear the engine */ |
495 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); | |
496 | udelay(10); | |
497 | } | |
498 | ata_bmdma_stop(qc); | |
499 | } | |
500 | ||
1a1b172b SS |
501 | static void hpt372_set_mode(struct ata_port *ap, struct ata_device *adev, |
502 | u8 mode) | |
669a5db4 JG |
503 | { |
504 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
505 | u32 addr1, addr2; | |
1a1b172b | 506 | u32 reg, timing, mask; |
669a5db4 JG |
507 | u8 fast; |
508 | ||
509 | addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); | |
510 | addr2 = 0x51 + 4 * ap->port_no; | |
85cd7251 | 511 | |
669a5db4 JG |
512 | /* Fast interrupt prediction disable, hold off interrupt disable */ |
513 | pci_read_config_byte(pdev, addr2, &fast); | |
514 | fast &= ~0x07; | |
515 | pci_write_config_byte(pdev, addr2, fast); | |
85cd7251 | 516 | |
1a1b172b SS |
517 | /* Determine timing mask and find matching mode entry */ |
518 | if (mode < XFER_MW_DMA_0) | |
519 | mask = 0xcfc3ffff; | |
520 | else if (mode < XFER_UDMA_0) | |
521 | mask = 0x31c001ff; | |
522 | else | |
523 | mask = 0x303c0000; | |
524 | ||
525 | timing = hpt37x_find_mode(ap, mode); | |
526 | ||
669a5db4 | 527 | pci_read_config_dword(pdev, addr1, ®); |
1a1b172b SS |
528 | reg = (reg & ~mask) | (timing & mask); |
529 | pci_write_config_dword(pdev, addr1, reg); | |
530 | } | |
85cd7251 | 531 | |
1a1b172b SS |
532 | /** |
533 | * hpt372_set_piomode - PIO setup | |
534 | * @ap: ATA interface | |
535 | * @adev: device on the interface | |
536 | * | |
537 | * Perform PIO mode setup. | |
538 | */ | |
539 | ||
540 | static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
541 | { | |
542 | hpt372_set_mode(ap, adev, adev->pio_mode); | |
669a5db4 JG |
543 | } |
544 | ||
545 | /** | |
546 | * hpt372_set_dmamode - DMA timing setup | |
547 | * @ap: ATA interface | |
548 | * @adev: Device being configured | |
549 | * | |
1a1b172b | 550 | * Set up the channel for MWDMA or UDMA modes. |
669a5db4 | 551 | */ |
85cd7251 | 552 | |
669a5db4 JG |
553 | static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
554 | { | |
1a1b172b | 555 | hpt372_set_mode(ap, adev, adev->dma_mode); |
669a5db4 JG |
556 | } |
557 | ||
558 | /** | |
559 | * hpt37x_bmdma_end - DMA engine stop | |
560 | * @qc: ATA command | |
561 | * | |
562 | * Clean up after the HPT372 and later DMA engine | |
563 | */ | |
85cd7251 | 564 | |
669a5db4 JG |
565 | static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc) |
566 | { | |
567 | struct ata_port *ap = qc->ap; | |
568 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
6929da44 | 569 | int mscreg = 0x50 + 4 * ap->port_no; |
669a5db4 | 570 | u8 bwsr_stat, msc_stat; |
85cd7251 | 571 | |
669a5db4 JG |
572 | pci_read_config_byte(pdev, 0x6A, &bwsr_stat); |
573 | pci_read_config_byte(pdev, mscreg, &msc_stat); | |
574 | if (bwsr_stat & (1 << ap->port_no)) | |
575 | pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); | |
576 | ata_bmdma_stop(qc); | |
577 | } | |
578 | ||
579 | ||
580 | static struct scsi_host_template hpt37x_sht = { | |
68d1d07b | 581 | ATA_BMDMA_SHT(DRV_NAME), |
669a5db4 JG |
582 | }; |
583 | ||
584 | /* | |
585 | * Configuration for HPT370 | |
586 | */ | |
85cd7251 | 587 | |
669a5db4 | 588 | static struct ata_port_operations hpt370_port_ops = { |
029cfd6b | 589 | .inherits = &ata_bmdma_port_ops, |
669a5db4 | 590 | |
669a5db4 | 591 | .bmdma_stop = hpt370_bmdma_stop, |
669a5db4 | 592 | |
029cfd6b | 593 | .mode_filter = hpt370_filter, |
9e87be9e | 594 | .cable_detect = hpt37x_cable_detect, |
029cfd6b TH |
595 | .set_piomode = hpt370_set_piomode, |
596 | .set_dmamode = hpt370_set_dmamode, | |
a1efdaba | 597 | .prereset = hpt37x_pre_reset, |
85cd7251 | 598 | }; |
669a5db4 JG |
599 | |
600 | /* | |
601 | * Configuration for HPT370A. Close to 370 but less filters | |
602 | */ | |
85cd7251 | 603 | |
669a5db4 | 604 | static struct ata_port_operations hpt370a_port_ops = { |
029cfd6b | 605 | .inherits = &hpt370_port_ops, |
669a5db4 | 606 | .mode_filter = hpt370a_filter, |
85cd7251 | 607 | }; |
669a5db4 JG |
608 | |
609 | /* | |
8e834c2e SS |
610 | * Configuration for HPT371 and HPT302. Slightly different PIO and DMA |
611 | * mode setting functionality. | |
669a5db4 | 612 | */ |
85cd7251 | 613 | |
8e834c2e | 614 | static struct ata_port_operations hpt302_port_ops = { |
029cfd6b | 615 | .inherits = &ata_bmdma_port_ops, |
669a5db4 | 616 | |
669a5db4 | 617 | .bmdma_stop = hpt37x_bmdma_stop, |
669a5db4 | 618 | |
9e87be9e | 619 | .cable_detect = hpt37x_cable_detect, |
029cfd6b TH |
620 | .set_piomode = hpt372_set_piomode, |
621 | .set_dmamode = hpt372_set_dmamode, | |
a1efdaba | 622 | .prereset = hpt37x_pre_reset, |
85cd7251 | 623 | }; |
669a5db4 JG |
624 | |
625 | /* | |
8e834c2e SS |
626 | * Configuration for HPT372. Mode setting works like 371 and 302 |
627 | * but we have a mode filter. | |
628 | */ | |
629 | ||
630 | static struct ata_port_operations hpt372_port_ops = { | |
631 | .inherits = &hpt302_port_ops, | |
632 | .mode_filter = hpt372_filter, | |
633 | }; | |
634 | ||
635 | /* | |
636 | * Configuration for HPT374. Mode setting and filtering works like 372 | |
a1efdaba | 637 | * but we have a different cable detection procedure for function 1. |
669a5db4 | 638 | */ |
85cd7251 | 639 | |
a1efdaba | 640 | static struct ata_port_operations hpt374_fn1_port_ops = { |
029cfd6b | 641 | .inherits = &hpt372_port_ops, |
9e87be9e | 642 | .cable_detect = hpt374_fn1_cable_detect, |
85cd7251 | 643 | }; |
669a5db4 JG |
644 | |
645 | /** | |
ad452d64 | 646 | * hpt37x_clock_slot - Turn timing to PC clock entry |
669a5db4 JG |
647 | * @freq: Reported frequency timing |
648 | * @base: Base timing | |
649 | * | |
650 | * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50 | |
651 | * and 3 for 66Mhz) | |
652 | */ | |
85cd7251 | 653 | |
669a5db4 JG |
654 | static int hpt37x_clock_slot(unsigned int freq, unsigned int base) |
655 | { | |
656 | unsigned int f = (base * freq) / 192; /* Mhz */ | |
657 | if (f < 40) | |
658 | return 0; /* 33Mhz slot */ | |
659 | if (f < 45) | |
660 | return 1; /* 40Mhz slot */ | |
661 | if (f < 55) | |
662 | return 2; /* 50Mhz slot */ | |
663 | return 3; /* 60Mhz slot */ | |
664 | } | |
665 | ||
666 | /** | |
667 | * hpt37x_calibrate_dpll - Calibrate the DPLL loop | |
85cd7251 | 668 | * @dev: PCI device |
669a5db4 JG |
669 | * |
670 | * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this | |
671 | * succeeds | |
672 | */ | |
673 | ||
674 | static int hpt37x_calibrate_dpll(struct pci_dev *dev) | |
675 | { | |
676 | u8 reg5b; | |
677 | u32 reg5c; | |
678 | int tries; | |
85cd7251 | 679 | |
49bfbd38 | 680 | for (tries = 0; tries < 0x5000; tries++) { |
669a5db4 JG |
681 | udelay(50); |
682 | pci_read_config_byte(dev, 0x5b, ®5b); | |
683 | if (reg5b & 0x80) { | |
684 | /* See if it stays set */ | |
49bfbd38 | 685 | for (tries = 0; tries < 0x1000; tries++) { |
669a5db4 JG |
686 | pci_read_config_byte(dev, 0x5b, ®5b); |
687 | /* Failed ? */ | |
688 | if ((reg5b & 0x80) == 0) | |
689 | return 0; | |
690 | } | |
691 | /* Turn off tuning, we have the DPLL set */ | |
692 | pci_read_config_dword(dev, 0x5c, ®5c); | |
49bfbd38 | 693 | pci_write_config_dword(dev, 0x5c, reg5c & ~0x100); |
669a5db4 JG |
694 | return 1; |
695 | } | |
696 | } | |
697 | /* Never went stable */ | |
698 | return 0; | |
699 | } | |
73946f9f AC |
700 | |
701 | static u32 hpt374_read_freq(struct pci_dev *pdev) | |
702 | { | |
703 | u32 freq; | |
704 | unsigned long io_base = pci_resource_start(pdev, 4); | |
49bfbd38 | 705 | |
73946f9f | 706 | if (PCI_FUNC(pdev->devfn) & 1) { |
40f46f17 AM |
707 | struct pci_dev *pdev_0; |
708 | ||
709 | pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1); | |
73946f9f AC |
710 | /* Someone hot plugged the controller on us ? */ |
711 | if (pdev_0 == NULL) | |
712 | return 0; | |
713 | io_base = pci_resource_start(pdev_0, 4); | |
714 | freq = inl(io_base + 0x90); | |
715 | pci_dev_put(pdev_0); | |
40f46f17 | 716 | } else |
73946f9f AC |
717 | freq = inl(io_base + 0x90); |
718 | return freq; | |
719 | } | |
720 | ||
669a5db4 JG |
721 | /** |
722 | * hpt37x_init_one - Initialise an HPT37X/302 | |
723 | * @dev: PCI device | |
724 | * @id: Entry in match table | |
725 | * | |
726 | * Initialise an HPT37x device. There are some interesting complications | |
727 | * here. Firstly the chip may report 366 and be one of several variants. | |
728 | * Secondly all the timings depend on the clock for the chip which we must | |
729 | * detect and look up | |
730 | * | |
731 | * This is the known chip mappings. It may be missing a couple of later | |
732 | * releases. | |
733 | * | |
734 | * Chip version PCI Rev Notes | |
735 | * HPT366 4 (HPT366) 0 Other driver | |
736 | * HPT366 4 (HPT366) 1 Other driver | |
737 | * HPT368 4 (HPT366) 2 Other driver | |
738 | * HPT370 4 (HPT366) 3 UDMA100 | |
739 | * HPT370A 4 (HPT366) 4 UDMA100 | |
740 | * HPT372 4 (HPT366) 5 UDMA133 (1) | |
741 | * HPT372N 4 (HPT366) 6 Other driver | |
742 | * HPT372A 5 (HPT372) 1 UDMA133 (1) | |
743 | * HPT372N 5 (HPT372) 2 Other driver | |
744 | * HPT302 6 (HPT302) 1 UDMA133 | |
745 | * HPT302N 6 (HPT302) 2 Other driver | |
746 | * HPT371 7 (HPT371) * UDMA133 | |
747 | * HPT374 8 (HPT374) * UDMA133 4 channel | |
748 | * HPT372N 9 (HPT372N) * Other driver | |
749 | * | |
750 | * (1) UDMA133 support depends on the bus clock | |
751 | */ | |
85cd7251 | 752 | |
669a5db4 JG |
753 | static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
754 | { | |
755 | /* HPT370 - UDMA100 */ | |
1626aeb8 | 756 | static const struct ata_port_info info_hpt370 = { |
1d2808fd | 757 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
758 | .pio_mask = ATA_PIO4, |
759 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 760 | .udma_mask = ATA_UDMA5, |
669a5db4 JG |
761 | .port_ops = &hpt370_port_ops |
762 | }; | |
763 | /* HPT370A - UDMA100 */ | |
1626aeb8 | 764 | static const struct ata_port_info info_hpt370a = { |
1d2808fd | 765 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
766 | .pio_mask = ATA_PIO4, |
767 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 768 | .udma_mask = ATA_UDMA5, |
669a5db4 JG |
769 | .port_ops = &hpt370a_port_ops |
770 | }; | |
fc2698d5 | 771 | /* HPT370 - UDMA66 */ |
1626aeb8 | 772 | static const struct ata_port_info info_hpt370_33 = { |
1d2808fd | 773 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
774 | .pio_mask = ATA_PIO4, |
775 | .mwdma_mask = ATA_MWDMA2, | |
fc2698d5 | 776 | .udma_mask = ATA_UDMA4, |
fcc2f69a AC |
777 | .port_ops = &hpt370_port_ops |
778 | }; | |
fc2698d5 | 779 | /* HPT370A - UDMA66 */ |
1626aeb8 | 780 | static const struct ata_port_info info_hpt370a_33 = { |
1d2808fd | 781 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
782 | .pio_mask = ATA_PIO4, |
783 | .mwdma_mask = ATA_MWDMA2, | |
fc2698d5 | 784 | .udma_mask = ATA_UDMA4, |
fcc2f69a AC |
785 | .port_ops = &hpt370a_port_ops |
786 | }; | |
8e834c2e | 787 | /* HPT372 - UDMA133 */ |
1626aeb8 | 788 | static const struct ata_port_info info_hpt372 = { |
1d2808fd | 789 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
790 | .pio_mask = ATA_PIO4, |
791 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 792 | .udma_mask = ATA_UDMA6, |
669a5db4 JG |
793 | .port_ops = &hpt372_port_ops |
794 | }; | |
8e834c2e SS |
795 | /* HPT371, 302 - UDMA133 */ |
796 | static const struct ata_port_info info_hpt302 = { | |
797 | .flags = ATA_FLAG_SLAVE_POSS, | |
798 | .pio_mask = ATA_PIO4, | |
799 | .mwdma_mask = ATA_MWDMA2, | |
800 | .udma_mask = ATA_UDMA6, | |
801 | .port_ops = &hpt302_port_ops | |
802 | }; | |
defed559 | 803 | /* HPT374 - UDMA100, function 1 uses different cable_detect method */ |
a1efdaba TH |
804 | static const struct ata_port_info info_hpt374_fn0 = { |
805 | .flags = ATA_FLAG_SLAVE_POSS, | |
14bdef98 EIB |
806 | .pio_mask = ATA_PIO4, |
807 | .mwdma_mask = ATA_MWDMA2, | |
a1efdaba TH |
808 | .udma_mask = ATA_UDMA5, |
809 | .port_ops = &hpt372_port_ops | |
810 | }; | |
811 | static const struct ata_port_info info_hpt374_fn1 = { | |
1d2808fd | 812 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
813 | .pio_mask = ATA_PIO4, |
814 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 815 | .udma_mask = ATA_UDMA5, |
a1efdaba | 816 | .port_ops = &hpt374_fn1_port_ops |
669a5db4 JG |
817 | }; |
818 | ||
819 | static const int MHz[4] = { 33, 40, 50, 66 }; | |
1626aeb8 | 820 | void *private_data = NULL; |
887125e3 | 821 | const struct ata_port_info *ppi[] = { NULL, NULL }; |
89d3b360 | 822 | u8 rev = dev->revision; |
669a5db4 | 823 | u8 irqmask; |
fcc2f69a | 824 | u8 mcr1; |
669a5db4 | 825 | u32 freq; |
fcc2f69a | 826 | int prefer_dpll = 1; |
a617c09f | 827 | |
fcc2f69a | 828 | unsigned long iobase = pci_resource_start(dev, 4); |
669a5db4 JG |
829 | |
830 | const struct hpt_chip *chip_table; | |
831 | int clock_slot; | |
f08048e9 TH |
832 | int rc; |
833 | ||
834 | rc = pcim_enable_device(dev); | |
835 | if (rc) | |
836 | return rc; | |
669a5db4 | 837 | |
910f7bb1 SS |
838 | switch (dev->device) { |
839 | case PCI_DEVICE_ID_TTI_HPT366: | |
669a5db4 JG |
840 | /* May be a later chip in disguise. Check */ |
841 | /* Older chips are in the HPT366 driver. Ignore them */ | |
89d3b360 | 842 | if (rev < 3) |
669a5db4 JG |
843 | return -ENODEV; |
844 | /* N series chips have their own driver. Ignore */ | |
89d3b360 | 845 | if (rev == 6) |
669a5db4 JG |
846 | return -ENODEV; |
847 | ||
49bfbd38 SS |
848 | switch (rev) { |
849 | case 3: | |
850 | ppi[0] = &info_hpt370; | |
851 | chip_table = &hpt370; | |
852 | prefer_dpll = 0; | |
853 | break; | |
854 | case 4: | |
855 | ppi[0] = &info_hpt370a; | |
856 | chip_table = &hpt370a; | |
857 | prefer_dpll = 0; | |
858 | break; | |
859 | case 5: | |
860 | ppi[0] = &info_hpt372; | |
861 | chip_table = &hpt372; | |
862 | break; | |
863 | default: | |
8d7b1c70 JP |
864 | pr_err("Unknown HPT366 subtype, please report (%d)\n", |
865 | rev); | |
49bfbd38 | 866 | return -ENODEV; |
669a5db4 | 867 | } |
910f7bb1 SS |
868 | break; |
869 | case PCI_DEVICE_ID_TTI_HPT372: | |
870 | /* 372N if rev >= 2 */ | |
871 | if (rev >= 2) | |
872 | return -ENODEV; | |
873 | ppi[0] = &info_hpt372; | |
874 | chip_table = &hpt372a; | |
875 | break; | |
876 | case PCI_DEVICE_ID_TTI_HPT302: | |
877 | /* 302N if rev > 1 */ | |
878 | if (rev > 1) | |
879 | return -ENODEV; | |
880 | ppi[0] = &info_hpt302; | |
881 | /* Check this */ | |
882 | chip_table = &hpt302; | |
883 | break; | |
884 | case PCI_DEVICE_ID_TTI_HPT371: | |
885 | if (rev > 1) | |
886 | return -ENODEV; | |
887 | ppi[0] = &info_hpt302; | |
888 | chip_table = &hpt371; | |
889 | /* | |
890 | * Single channel device, master is not present but the BIOS | |
891 | * (or us for non x86) must mark it absent | |
892 | */ | |
893 | pci_read_config_byte(dev, 0x50, &mcr1); | |
894 | mcr1 &= ~0x04; | |
895 | pci_write_config_byte(dev, 0x50, mcr1); | |
896 | break; | |
897 | case PCI_DEVICE_ID_TTI_HPT374: | |
898 | chip_table = &hpt374; | |
899 | if (!(PCI_FUNC(dev->devfn) & 1)) | |
900 | *ppi = &info_hpt374_fn0; | |
901 | else | |
902 | *ppi = &info_hpt374_fn1; | |
903 | break; | |
904 | default: | |
8d7b1c70 | 905 | pr_err("PCI table is bogus, please report (%d)\n", dev->device); |
910f7bb1 | 906 | return -ENODEV; |
669a5db4 JG |
907 | } |
908 | /* Ok so this is a chip we support */ | |
909 | ||
910 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); | |
911 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); | |
912 | pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); | |
913 | pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); | |
914 | ||
915 | pci_read_config_byte(dev, 0x5A, &irqmask); | |
916 | irqmask &= ~0x10; | |
917 | pci_write_config_byte(dev, 0x5a, irqmask); | |
918 | ||
919 | /* | |
920 | * default to pci clock. make sure MA15/16 are set to output | |
921 | * to prevent drives having problems with 40-pin cables. Needed | |
922 | * for some drives such as IBM-DTLA which will not enter ready | |
923 | * state on reset when PDIAG is a input. | |
924 | */ | |
925 | ||
85cd7251 | 926 | pci_write_config_byte(dev, 0x5b, 0x23); |
a617c09f | 927 | |
fcc2f69a AC |
928 | /* |
929 | * HighPoint does this for HPT372A. | |
930 | * NOTE: This register is only writeable via I/O space. | |
931 | */ | |
932 | if (chip_table == &hpt372a) | |
933 | outb(0x0e, iobase + 0x9c); | |
85cd7251 | 934 | |
49bfbd38 SS |
935 | /* |
936 | * Some devices do not let this value be accessed via PCI space | |
937 | * according to the old driver. In addition we must use the value | |
938 | * from FN 0 on the HPT374. | |
939 | */ | |
73946f9f AC |
940 | |
941 | if (chip_table == &hpt374) { | |
942 | freq = hpt374_read_freq(dev); | |
943 | if (freq == 0) | |
944 | return -ENODEV; | |
945 | } else | |
946 | freq = inl(iobase + 0x90); | |
fcc2f69a | 947 | |
669a5db4 JG |
948 | if ((freq >> 12) != 0xABCDE) { |
949 | int i; | |
950 | u8 sr; | |
951 | u32 total = 0; | |
85cd7251 | 952 | |
8d7b1c70 | 953 | pr_warn("BIOS has not set timing clocks\n"); |
85cd7251 | 954 | |
669a5db4 | 955 | /* This is the process the HPT371 BIOS is reported to use */ |
49bfbd38 | 956 | for (i = 0; i < 128; i++) { |
669a5db4 | 957 | pci_read_config_byte(dev, 0x78, &sr); |
fcc2f69a | 958 | total += sr & 0x1FF; |
669a5db4 JG |
959 | udelay(15); |
960 | } | |
961 | freq = total / 128; | |
962 | } | |
963 | freq &= 0x1FF; | |
85cd7251 | 964 | |
669a5db4 JG |
965 | /* |
966 | * Turn the frequency check into a band and then find a timing | |
967 | * table to match it. | |
968 | */ | |
a617c09f | 969 | |
669a5db4 | 970 | clock_slot = hpt37x_clock_slot(freq, chip_table->base); |
fcc2f69a | 971 | if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) { |
669a5db4 JG |
972 | /* |
973 | * We need to try PLL mode instead | |
fcc2f69a AC |
974 | * |
975 | * For non UDMA133 capable devices we should | |
976 | * use a 50MHz DPLL by choice | |
669a5db4 | 977 | */ |
fcc2f69a | 978 | unsigned int f_low, f_high; |
960c8a10 | 979 | int dpll, adjust; |
a617c09f | 980 | |
960c8a10 | 981 | /* Compute DPLL */ |
887125e3 | 982 | dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; |
a617c09f | 983 | |
960c8a10 | 984 | f_low = (MHz[clock_slot] * 48) / MHz[dpll]; |
fcc2f69a | 985 | f_high = f_low + 2; |
960c8a10 AC |
986 | if (clock_slot > 1) |
987 | f_high += 2; | |
fcc2f69a AC |
988 | |
989 | /* Select the DPLL clock. */ | |
990 | pci_write_config_byte(dev, 0x5b, 0x21); | |
49bfbd38 SS |
991 | pci_write_config_dword(dev, 0x5C, |
992 | (f_high << 16) | f_low | 0x100); | |
85cd7251 | 993 | |
49bfbd38 | 994 | for (adjust = 0; adjust < 8; adjust++) { |
669a5db4 JG |
995 | if (hpt37x_calibrate_dpll(dev)) |
996 | break; | |
49bfbd38 SS |
997 | /* |
998 | * See if it'll settle at a fractionally | |
999 | * different clock | |
1000 | */ | |
64a81709 AC |
1001 | if (adjust & 1) |
1002 | f_low -= adjust >> 1; | |
1003 | else | |
1004 | f_high += adjust >> 1; | |
49bfbd38 SS |
1005 | pci_write_config_dword(dev, 0x5C, |
1006 | (f_high << 16) | f_low | 0x100); | |
669a5db4 JG |
1007 | } |
1008 | if (adjust == 8) { | |
8d7b1c70 | 1009 | pr_err("DPLL did not stabilize!\n"); |
669a5db4 JG |
1010 | return -ENODEV; |
1011 | } | |
960c8a10 | 1012 | if (dpll == 3) |
1626aeb8 | 1013 | private_data = (void *)hpt37x_timings_66; |
fcc2f69a | 1014 | else |
1626aeb8 | 1015 | private_data = (void *)hpt37x_timings_50; |
85cd7251 | 1016 | |
8d7b1c70 | 1017 | pr_info("bus clock %dMHz, using %dMHz DPLL\n", |
40d69ba0 | 1018 | MHz[clock_slot], MHz[dpll]); |
669a5db4 | 1019 | } else { |
1626aeb8 | 1020 | private_data = (void *)chip_table->clocks[clock_slot]; |
669a5db4 | 1021 | /* |
a4734468 AC |
1022 | * Perform a final fixup. Note that we will have used the |
1023 | * DPLL on the HPT372 which means we don't have to worry | |
1024 | * about lack of UDMA133 support on lower clocks | |
49bfbd38 | 1025 | */ |
85cd7251 | 1026 | |
887125e3 TH |
1027 | if (clock_slot < 2 && ppi[0] == &info_hpt370) |
1028 | ppi[0] = &info_hpt370_33; | |
1029 | if (clock_slot < 2 && ppi[0] == &info_hpt370a) | |
1030 | ppi[0] = &info_hpt370a_33; | |
40d69ba0 | 1031 | |
8d7b1c70 | 1032 | pr_info("%s using %dMHz bus clock\n", |
40d69ba0 | 1033 | chip_table->name, MHz[clock_slot]); |
669a5db4 | 1034 | } |
fcc2f69a | 1035 | |
669a5db4 | 1036 | /* Now kick off ATA set up */ |
1c5afdf7 | 1037 | return ata_pci_bmdma_init_one(dev, ppi, &hpt37x_sht, private_data, 0); |
669a5db4 JG |
1038 | } |
1039 | ||
2d2744fc JG |
1040 | static const struct pci_device_id hpt37x[] = { |
1041 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, | |
1042 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), }, | |
1043 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), }, | |
1044 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), }, | |
1045 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), }, | |
1046 | ||
1047 | { }, | |
669a5db4 JG |
1048 | }; |
1049 | ||
1050 | static struct pci_driver hpt37x_pci_driver = { | |
49bfbd38 | 1051 | .name = DRV_NAME, |
669a5db4 | 1052 | .id_table = hpt37x, |
49bfbd38 | 1053 | .probe = hpt37x_init_one, |
669a5db4 JG |
1054 | .remove = ata_pci_remove_one |
1055 | }; | |
1056 | ||
2fc75da0 | 1057 | module_pci_driver(hpt37x_pci_driver); |
669a5db4 | 1058 | |
669a5db4 JG |
1059 | MODULE_AUTHOR("Alan Cox"); |
1060 | MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x"); | |
1061 | MODULE_LICENSE("GPL"); | |
1062 | MODULE_DEVICE_TABLE(pci, hpt37x); | |
1063 | MODULE_VERSION(DRV_VERSION); |