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09c434b8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
669a5db4 JG |
2 | /* |
3 | * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers. | |
4 | * | |
5 | * This driver is heavily based upon: | |
6 | * | |
7 | * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 | |
8 | * | |
9 | * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> | |
10 | * Portions Copyright (C) 2001 Sun Microsystems, Inc. | |
11 | * Portions Copyright (C) 2003 Red Hat Inc | |
8e834c2e | 12 | * Portions Copyright (C) 2005-2010 MontaVista Software, Inc. |
669a5db4 JG |
13 | * |
14 | * TODO | |
d44a65f7 | 15 | * Look into engine reset on timeout errors. Should not be required. |
669a5db4 | 16 | */ |
669a5db4 JG |
17 | #include <linux/kernel.h> |
18 | #include <linux/module.h> | |
19 | #include <linux/pci.h> | |
669a5db4 JG |
20 | #include <linux/blkdev.h> |
21 | #include <linux/delay.h> | |
22 | #include <scsi/scsi_host.h> | |
23 | #include <linux/libata.h> | |
24 | ||
25 | #define DRV_NAME "pata_hpt37x" | |
75b4d58c | 26 | #define DRV_VERSION "0.6.30" |
669a5db4 JG |
27 | |
28 | struct hpt_clock { | |
29 | u8 xfer_speed; | |
30 | u32 timing; | |
31 | }; | |
32 | ||
33 | struct hpt_chip { | |
34 | const char *name; | |
35 | unsigned int base; | |
36 | struct hpt_clock const *clocks[4]; | |
37 | }; | |
38 | ||
39 | /* key for bus clock timings | |
40 | * bit | |
fd5e62e2 SS |
41 | * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. |
42 | * cycles = value + 1 | |
43 | * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. | |
44 | * cycles = value + 1 | |
45 | * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file | |
669a5db4 | 46 | * register access. |
fd5e62e2 | 47 | * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file |
669a5db4 | 48 | * register access. |
fd5e62e2 SS |
49 | * 18:20 udma_cycle_time. Clock cycles for UDMA xfer. |
50 | * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock. | |
51 | * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer. | |
52 | * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file | |
669a5db4 | 53 | * register access. |
fd5e62e2 SS |
54 | * 28 UDMA enable. |
55 | * 29 DMA enable. | |
56 | * 30 PIO_MST enable. If set, the chip is in bus master mode during | |
57 | * PIO xfer. | |
58 | * 31 FIFO enable. Only for PIO. | |
669a5db4 JG |
59 | */ |
60 | ||
fcc2f69a AC |
61 | static struct hpt_clock hpt37x_timings_33[] = { |
62 | { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */ | |
63 | { XFER_UDMA_5, 0x12446231 }, | |
64 | { XFER_UDMA_4, 0x12446231 }, | |
65 | { XFER_UDMA_3, 0x126c6231 }, | |
66 | { XFER_UDMA_2, 0x12486231 }, | |
67 | { XFER_UDMA_1, 0x124c6233 }, | |
68 | { XFER_UDMA_0, 0x12506297 }, | |
69 | ||
70 | { XFER_MW_DMA_2, 0x22406c31 }, | |
71 | { XFER_MW_DMA_1, 0x22406c33 }, | |
72 | { XFER_MW_DMA_0, 0x22406c97 }, | |
73 | ||
74 | { XFER_PIO_4, 0x06414e31 }, | |
75 | { XFER_PIO_3, 0x06414e42 }, | |
76 | { XFER_PIO_2, 0x06414e53 }, | |
77 | { XFER_PIO_1, 0x06814e93 }, | |
78 | { XFER_PIO_0, 0x06814ea7 } | |
669a5db4 JG |
79 | }; |
80 | ||
fcc2f69a AC |
81 | static struct hpt_clock hpt37x_timings_50[] = { |
82 | { XFER_UDMA_6, 0x12848242 }, | |
83 | { XFER_UDMA_5, 0x12848242 }, | |
84 | { XFER_UDMA_4, 0x12ac8242 }, | |
85 | { XFER_UDMA_3, 0x128c8242 }, | |
86 | { XFER_UDMA_2, 0x120c8242 }, | |
87 | { XFER_UDMA_1, 0x12148254 }, | |
88 | { XFER_UDMA_0, 0x121882ea }, | |
89 | ||
90 | { XFER_MW_DMA_2, 0x22808242 }, | |
91 | { XFER_MW_DMA_1, 0x22808254 }, | |
92 | { XFER_MW_DMA_0, 0x228082ea }, | |
93 | ||
94 | { XFER_PIO_4, 0x0a81f442 }, | |
95 | { XFER_PIO_3, 0x0a81f443 }, | |
96 | { XFER_PIO_2, 0x0a81f454 }, | |
97 | { XFER_PIO_1, 0x0ac1f465 }, | |
98 | { XFER_PIO_0, 0x0ac1f48a } | |
669a5db4 JG |
99 | }; |
100 | ||
fcc2f69a AC |
101 | static struct hpt_clock hpt37x_timings_66[] = { |
102 | { XFER_UDMA_6, 0x1c869c62 }, | |
103 | { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */ | |
104 | { XFER_UDMA_4, 0x1c8a9c62 }, | |
105 | { XFER_UDMA_3, 0x1c8e9c62 }, | |
106 | { XFER_UDMA_2, 0x1c929c62 }, | |
107 | { XFER_UDMA_1, 0x1c9a9c62 }, | |
108 | { XFER_UDMA_0, 0x1c829c62 }, | |
109 | ||
110 | { XFER_MW_DMA_2, 0x2c829c62 }, | |
111 | { XFER_MW_DMA_1, 0x2c829c66 }, | |
112 | { XFER_MW_DMA_0, 0x2c829d2e }, | |
113 | ||
114 | { XFER_PIO_4, 0x0c829c62 }, | |
115 | { XFER_PIO_3, 0x0c829c84 }, | |
116 | { XFER_PIO_2, 0x0c829ca6 }, | |
117 | { XFER_PIO_1, 0x0d029d26 }, | |
118 | { XFER_PIO_0, 0x0d029d5e } | |
669a5db4 JG |
119 | }; |
120 | ||
669a5db4 JG |
121 | |
122 | static const struct hpt_chip hpt370 = { | |
123 | "HPT370", | |
124 | 48, | |
125 | { | |
fcc2f69a | 126 | hpt37x_timings_33, |
669a5db4 JG |
127 | NULL, |
128 | NULL, | |
a4734468 | 129 | NULL |
669a5db4 JG |
130 | } |
131 | }; | |
132 | ||
133 | static const struct hpt_chip hpt370a = { | |
134 | "HPT370A", | |
135 | 48, | |
136 | { | |
fcc2f69a | 137 | hpt37x_timings_33, |
669a5db4 | 138 | NULL, |
fcc2f69a | 139 | hpt37x_timings_50, |
a4734468 | 140 | NULL |
669a5db4 JG |
141 | } |
142 | }; | |
143 | ||
144 | static const struct hpt_chip hpt372 = { | |
145 | "HPT372", | |
146 | 55, | |
147 | { | |
fcc2f69a | 148 | hpt37x_timings_33, |
669a5db4 | 149 | NULL, |
fcc2f69a AC |
150 | hpt37x_timings_50, |
151 | hpt37x_timings_66 | |
669a5db4 JG |
152 | } |
153 | }; | |
154 | ||
155 | static const struct hpt_chip hpt302 = { | |
156 | "HPT302", | |
157 | 66, | |
158 | { | |
fcc2f69a | 159 | hpt37x_timings_33, |
669a5db4 | 160 | NULL, |
fcc2f69a AC |
161 | hpt37x_timings_50, |
162 | hpt37x_timings_66 | |
669a5db4 JG |
163 | } |
164 | }; | |
165 | ||
166 | static const struct hpt_chip hpt371 = { | |
167 | "HPT371", | |
168 | 66, | |
169 | { | |
fcc2f69a | 170 | hpt37x_timings_33, |
669a5db4 | 171 | NULL, |
fcc2f69a AC |
172 | hpt37x_timings_50, |
173 | hpt37x_timings_66 | |
669a5db4 JG |
174 | } |
175 | }; | |
176 | ||
177 | static const struct hpt_chip hpt372a = { | |
178 | "HPT372A", | |
179 | 66, | |
180 | { | |
fcc2f69a | 181 | hpt37x_timings_33, |
669a5db4 | 182 | NULL, |
fcc2f69a AC |
183 | hpt37x_timings_50, |
184 | hpt37x_timings_66 | |
669a5db4 JG |
185 | } |
186 | }; | |
187 | ||
188 | static const struct hpt_chip hpt374 = { | |
189 | "HPT374", | |
190 | 48, | |
191 | { | |
fcc2f69a | 192 | hpt37x_timings_33, |
669a5db4 JG |
193 | NULL, |
194 | NULL, | |
195 | NULL | |
196 | } | |
197 | }; | |
198 | ||
199 | /** | |
200 | * hpt37x_find_mode - reset the hpt37x bus | |
201 | * @ap: ATA port | |
202 | * @speed: transfer mode | |
203 | * | |
204 | * Return the 32bit register programming information for this channel | |
205 | * that matches the speed provided. | |
206 | */ | |
85cd7251 | 207 | |
669a5db4 JG |
208 | static u32 hpt37x_find_mode(struct ata_port *ap, int speed) |
209 | { | |
210 | struct hpt_clock *clocks = ap->host->private_data; | |
85cd7251 | 211 | |
49bfbd38 | 212 | while (clocks->xfer_speed) { |
669a5db4 JG |
213 | if (clocks->xfer_speed == speed) |
214 | return clocks->timing; | |
215 | clocks++; | |
216 | } | |
217 | BUG(); | |
218 | return 0xffffffffU; /* silence compiler warning */ | |
219 | } | |
220 | ||
49bfbd38 SS |
221 | static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, |
222 | const char * const list[]) | |
669a5db4 | 223 | { |
8bfa79fc | 224 | unsigned char model_num[ATA_ID_PROD_LEN + 1]; |
dc85ca57 | 225 | int i; |
669a5db4 | 226 | |
8bfa79fc | 227 | ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); |
669a5db4 | 228 | |
dc85ca57 AS |
229 | i = match_string(list, -1, model_num); |
230 | if (i >= 0) { | |
f06c13aa HR |
231 | ata_dev_warn(dev, "%s is not supported for %s\n", |
232 | modestr, list[i]); | |
dc85ca57 | 233 | return 1; |
669a5db4 JG |
234 | } |
235 | return 0; | |
236 | } | |
237 | ||
49bfbd38 SS |
238 | static const char * const bad_ata33[] = { |
239 | "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", | |
240 | "Maxtor 90845U3", "Maxtor 90650U2", | |
241 | "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", | |
242 | "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", | |
243 | "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", | |
244 | "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", | |
669a5db4 JG |
245 | "Maxtor 90510D4", |
246 | "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", | |
49bfbd38 SS |
247 | "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", |
248 | "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", | |
249 | "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", | |
250 | "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", | |
669a5db4 JG |
251 | NULL |
252 | }; | |
253 | ||
49bfbd38 | 254 | static const char * const bad_ata100_5[] = { |
669a5db4 JG |
255 | "IBM-DTLA-307075", |
256 | "IBM-DTLA-307060", | |
257 | "IBM-DTLA-307045", | |
258 | "IBM-DTLA-307030", | |
259 | "IBM-DTLA-307020", | |
260 | "IBM-DTLA-307015", | |
261 | "IBM-DTLA-305040", | |
262 | "IBM-DTLA-305030", | |
263 | "IBM-DTLA-305020", | |
264 | "IC35L010AVER07-0", | |
265 | "IC35L020AVER07-0", | |
266 | "IC35L030AVER07-0", | |
267 | "IC35L040AVER07-0", | |
268 | "IC35L060AVER07-0", | |
269 | "WDC AC310200R", | |
270 | NULL | |
271 | }; | |
272 | ||
273 | /** | |
274 | * hpt370_filter - mode selection filter | |
669a5db4 | 275 | * @adev: ATA device |
a51746f4 | 276 | * @mask: mode mask |
669a5db4 JG |
277 | * |
278 | * Block UDMA on devices that cause trouble with this controller. | |
279 | */ | |
85cd7251 | 280 | |
f0a6d77b | 281 | static unsigned int hpt370_filter(struct ata_device *adev, unsigned int mask) |
669a5db4 | 282 | { |
6929da44 | 283 | if (adev->class == ATA_DEV_ATA) { |
669a5db4 JG |
284 | if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33)) |
285 | mask &= ~ATA_MASK_UDMA; | |
286 | if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) | |
6ddd6861 | 287 | mask &= ~(0xE0 << ATA_SHIFT_UDMA); |
669a5db4 | 288 | } |
c7087652 | 289 | return mask; |
669a5db4 JG |
290 | } |
291 | ||
292 | /** | |
293 | * hpt370a_filter - mode selection filter | |
669a5db4 | 294 | * @adev: ATA device |
a51746f4 | 295 | * @mask: mode mask |
669a5db4 JG |
296 | * |
297 | * Block UDMA on devices that cause trouble with this controller. | |
298 | */ | |
85cd7251 | 299 | |
f0a6d77b | 300 | static unsigned int hpt370a_filter(struct ata_device *adev, unsigned int mask) |
669a5db4 | 301 | { |
73946f9f | 302 | if (adev->class == ATA_DEV_ATA) { |
669a5db4 | 303 | if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) |
6ddd6861 | 304 | mask &= ~(0xE0 << ATA_SHIFT_UDMA); |
669a5db4 | 305 | } |
c7087652 | 306 | return mask; |
669a5db4 | 307 | } |
85cd7251 | 308 | |
8e834c2e SS |
309 | /** |
310 | * hpt372_filter - mode selection filter | |
311 | * @adev: ATA device | |
312 | * @mask: mode mask | |
313 | * | |
314 | * The Marvell bridge chips used on the HighPoint SATA cards do not seem | |
315 | * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes... | |
316 | */ | |
f0a6d77b | 317 | static unsigned int hpt372_filter(struct ata_device *adev, unsigned int mask) |
8e834c2e SS |
318 | { |
319 | if (ata_id_is_sata(adev->id)) | |
320 | mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA); | |
321 | ||
322 | return mask; | |
323 | } | |
324 | ||
9e87be9e BZ |
325 | /** |
326 | * hpt37x_cable_detect - Detect the cable type | |
327 | * @ap: ATA port to detect on | |
328 | * | |
329 | * Return the cable type attached to this port | |
330 | */ | |
331 | ||
332 | static int hpt37x_cable_detect(struct ata_port *ap) | |
333 | { | |
334 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
335 | u8 scr2, ata66; | |
336 | ||
337 | pci_read_config_byte(pdev, 0x5B, &scr2); | |
338 | pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); | |
10a9c969 BZ |
339 | |
340 | udelay(10); /* debounce */ | |
341 | ||
9e87be9e BZ |
342 | /* Cable register now active */ |
343 | pci_read_config_byte(pdev, 0x5A, &ata66); | |
344 | /* Restore state */ | |
345 | pci_write_config_byte(pdev, 0x5B, scr2); | |
346 | ||
347 | if (ata66 & (2 >> ap->port_no)) | |
348 | return ATA_CBL_PATA40; | |
349 | else | |
350 | return ATA_CBL_PATA80; | |
351 | } | |
352 | ||
353 | /** | |
354 | * hpt374_fn1_cable_detect - Detect the cable type | |
355 | * @ap: ATA port to detect on | |
356 | * | |
357 | * Return the cable type attached to this port | |
358 | */ | |
359 | ||
360 | static int hpt374_fn1_cable_detect(struct ata_port *ap) | |
361 | { | |
362 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
363 | unsigned int mcrbase = 0x50 + 4 * ap->port_no; | |
364 | u16 mcr3; | |
365 | u8 ata66; | |
366 | ||
367 | /* Do the extra channel work */ | |
368 | pci_read_config_word(pdev, mcrbase + 2, &mcr3); | |
369 | /* Set bit 15 of 0x52 to enable TCBLID as input */ | |
370 | pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000); | |
371 | pci_read_config_byte(pdev, 0x5A, &ata66); | |
372 | /* Reset TCBLID/FCBLID to output */ | |
373 | pci_write_config_word(pdev, mcrbase + 2, mcr3); | |
374 | ||
375 | if (ata66 & (2 >> ap->port_no)) | |
376 | return ATA_CBL_PATA40; | |
377 | else | |
378 | return ATA_CBL_PATA80; | |
379 | } | |
380 | ||
669a5db4 JG |
381 | /** |
382 | * hpt37x_pre_reset - reset the hpt37x bus | |
cc0680a5 | 383 | * @link: ATA link to reset |
d4b2bab4 | 384 | * @deadline: deadline jiffies for the operation |
669a5db4 | 385 | * |
ab81a505 | 386 | * Perform the initial reset handling for the HPT37x. |
669a5db4 | 387 | */ |
85cd7251 | 388 | |
cc0680a5 | 389 | static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline) |
669a5db4 | 390 | { |
cc0680a5 | 391 | struct ata_port *ap = link->ap; |
669a5db4 | 392 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
b5bf24b9 AC |
393 | static const struct pci_bits hpt37x_enable_bits[] = { |
394 | { 0x50, 1, 0x04, 0x04 }, | |
395 | { 0x54, 1, 0x04, 0x04 } | |
396 | }; | |
6110530b | 397 | u8 mcr2; |
49bfbd38 | 398 | |
b5bf24b9 AC |
399 | if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no])) |
400 | return -ENOENT; | |
f20b16ff | 401 | |
669a5db4 | 402 | /* Reset the state machine */ |
fcc2f69a | 403 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); |
669a5db4 | 404 | udelay(100); |
85cd7251 | 405 | |
6110530b SS |
406 | /* |
407 | * Disable the "fast interrupt" prediction. Don't hold off | |
408 | * on interrupts. (== 0x01 despite what the docs say) | |
409 | */ | |
410 | pci_read_config_byte(pdev, 0x51 + 4 * ap->port_no, &mcr2); | |
411 | /* Is it HPT370/A? */ | |
412 | if (pdev->device == PCI_DEVICE_ID_TTI_HPT366 && pdev->revision < 5) { | |
413 | mcr2 &= ~0x02; | |
414 | mcr2 |= 0x01; | |
415 | } else { | |
416 | mcr2 &= ~0x07; | |
417 | } | |
418 | pci_write_config_byte(pdev, 0x51 + 4 * ap->port_no, mcr2); | |
419 | ||
9363c382 | 420 | return ata_sff_prereset(link, deadline); |
669a5db4 JG |
421 | } |
422 | ||
9256766f | 423 | static void hpt37x_set_mode(struct ata_port *ap, struct ata_device *adev, |
1a1b172b | 424 | u8 mode) |
669a5db4 JG |
425 | { |
426 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
6110530b | 427 | int addr = 0x40 + 4 * (adev->devno + 2 * ap->port_no); |
1a1b172b | 428 | u32 reg, timing, mask; |
85cd7251 | 429 | |
1a1b172b SS |
430 | /* Determine timing mask and find matching mode entry */ |
431 | if (mode < XFER_MW_DMA_0) | |
432 | mask = 0xcfc3ffff; | |
433 | else if (mode < XFER_UDMA_0) | |
434 | mask = 0x31c001ff; | |
435 | else | |
436 | mask = 0x303c0000; | |
437 | ||
438 | timing = hpt37x_find_mode(ap, mode); | |
439 | ||
6110530b | 440 | pci_read_config_dword(pdev, addr, ®); |
1a1b172b | 441 | reg = (reg & ~mask) | (timing & mask); |
6110530b | 442 | pci_write_config_dword(pdev, addr, reg); |
1a1b172b SS |
443 | } |
444 | /** | |
9256766f | 445 | * hpt37x_set_piomode - PIO setup |
1a1b172b SS |
446 | * @ap: ATA interface |
447 | * @adev: device on the interface | |
448 | * | |
449 | * Perform PIO mode setup. | |
450 | */ | |
451 | ||
9256766f | 452 | static void hpt37x_set_piomode(struct ata_port *ap, struct ata_device *adev) |
1a1b172b | 453 | { |
9256766f | 454 | hpt37x_set_mode(ap, adev, adev->pio_mode); |
669a5db4 JG |
455 | } |
456 | ||
457 | /** | |
9256766f | 458 | * hpt37x_set_dmamode - DMA timing setup |
669a5db4 JG |
459 | * @ap: ATA interface |
460 | * @adev: Device being configured | |
461 | * | |
1a1b172b | 462 | * Set up the channel for MWDMA or UDMA modes. |
669a5db4 | 463 | */ |
85cd7251 | 464 | |
9256766f | 465 | static void hpt37x_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
669a5db4 | 466 | { |
9256766f | 467 | hpt37x_set_mode(ap, adev, adev->dma_mode); |
669a5db4 JG |
468 | } |
469 | ||
669a5db4 | 470 | /** |
a51746f4 | 471 | * hpt370_bmdma_stop - DMA engine stop |
669a5db4 JG |
472 | * @qc: ATA command |
473 | * | |
474 | * Work around the HPT370 DMA engine. | |
475 | */ | |
85cd7251 | 476 | |
669a5db4 JG |
477 | static void hpt370_bmdma_stop(struct ata_queued_cmd *qc) |
478 | { | |
479 | struct ata_port *ap = qc->ap; | |
480 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
0d5ff566 | 481 | void __iomem *bmdma = ap->ioaddr.bmdma_addr; |
56f46f8c SS |
482 | u8 dma_stat = ioread8(bmdma + ATA_DMA_STATUS); |
483 | u8 dma_cmd; | |
85cd7251 | 484 | |
56f46f8c | 485 | if (dma_stat & ATA_DMA_ACTIVE) { |
669a5db4 | 486 | udelay(20); |
56f46f8c | 487 | dma_stat = ioread8(bmdma + ATA_DMA_STATUS); |
669a5db4 | 488 | } |
56f46f8c | 489 | if (dma_stat & ATA_DMA_ACTIVE) { |
669a5db4 JG |
490 | /* Clear the engine */ |
491 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); | |
492 | udelay(10); | |
493 | /* Stop DMA */ | |
56f46f8c SS |
494 | dma_cmd = ioread8(bmdma + ATA_DMA_CMD); |
495 | iowrite8(dma_cmd & ~ATA_DMA_START, bmdma + ATA_DMA_CMD); | |
669a5db4 | 496 | /* Clear Error */ |
56f46f8c SS |
497 | dma_stat = ioread8(bmdma + ATA_DMA_STATUS); |
498 | iowrite8(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR, | |
499 | bmdma + ATA_DMA_STATUS); | |
669a5db4 JG |
500 | /* Clear the engine */ |
501 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); | |
502 | udelay(10); | |
503 | } | |
504 | ata_bmdma_stop(qc); | |
505 | } | |
506 | ||
669a5db4 | 507 | /** |
a51746f4 | 508 | * hpt37x_bmdma_stop - DMA engine stop |
669a5db4 JG |
509 | * @qc: ATA command |
510 | * | |
511 | * Clean up after the HPT372 and later DMA engine | |
512 | */ | |
85cd7251 | 513 | |
669a5db4 JG |
514 | static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc) |
515 | { | |
516 | struct ata_port *ap = qc->ap; | |
517 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
6929da44 | 518 | int mscreg = 0x50 + 4 * ap->port_no; |
669a5db4 | 519 | u8 bwsr_stat, msc_stat; |
85cd7251 | 520 | |
669a5db4 JG |
521 | pci_read_config_byte(pdev, 0x6A, &bwsr_stat); |
522 | pci_read_config_byte(pdev, mscreg, &msc_stat); | |
523 | if (bwsr_stat & (1 << ap->port_no)) | |
524 | pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); | |
525 | ata_bmdma_stop(qc); | |
526 | } | |
527 | ||
528 | ||
25df73d9 | 529 | static const struct scsi_host_template hpt37x_sht = { |
68d1d07b | 530 | ATA_BMDMA_SHT(DRV_NAME), |
669a5db4 JG |
531 | }; |
532 | ||
533 | /* | |
534 | * Configuration for HPT370 | |
535 | */ | |
85cd7251 | 536 | |
669a5db4 | 537 | static struct ata_port_operations hpt370_port_ops = { |
029cfd6b | 538 | .inherits = &ata_bmdma_port_ops, |
669a5db4 | 539 | |
669a5db4 | 540 | .bmdma_stop = hpt370_bmdma_stop, |
669a5db4 | 541 | |
029cfd6b | 542 | .mode_filter = hpt370_filter, |
9e87be9e | 543 | .cable_detect = hpt37x_cable_detect, |
9256766f SS |
544 | .set_piomode = hpt37x_set_piomode, |
545 | .set_dmamode = hpt37x_set_dmamode, | |
a1efdaba | 546 | .prereset = hpt37x_pre_reset, |
85cd7251 | 547 | }; |
669a5db4 JG |
548 | |
549 | /* | |
550 | * Configuration for HPT370A. Close to 370 but less filters | |
551 | */ | |
85cd7251 | 552 | |
669a5db4 | 553 | static struct ata_port_operations hpt370a_port_ops = { |
029cfd6b | 554 | .inherits = &hpt370_port_ops, |
669a5db4 | 555 | .mode_filter = hpt370a_filter, |
85cd7251 | 556 | }; |
669a5db4 JG |
557 | |
558 | /* | |
9256766f | 559 | * Configuration for HPT371 and HPT302. |
669a5db4 | 560 | */ |
85cd7251 | 561 | |
8e834c2e | 562 | static struct ata_port_operations hpt302_port_ops = { |
029cfd6b | 563 | .inherits = &ata_bmdma_port_ops, |
669a5db4 | 564 | |
669a5db4 | 565 | .bmdma_stop = hpt37x_bmdma_stop, |
669a5db4 | 566 | |
9e87be9e | 567 | .cable_detect = hpt37x_cable_detect, |
9256766f SS |
568 | .set_piomode = hpt37x_set_piomode, |
569 | .set_dmamode = hpt37x_set_dmamode, | |
a1efdaba | 570 | .prereset = hpt37x_pre_reset, |
85cd7251 | 571 | }; |
669a5db4 JG |
572 | |
573 | /* | |
8e834c2e SS |
574 | * Configuration for HPT372. Mode setting works like 371 and 302 |
575 | * but we have a mode filter. | |
576 | */ | |
577 | ||
578 | static struct ata_port_operations hpt372_port_ops = { | |
579 | .inherits = &hpt302_port_ops, | |
580 | .mode_filter = hpt372_filter, | |
581 | }; | |
582 | ||
583 | /* | |
584 | * Configuration for HPT374. Mode setting and filtering works like 372 | |
a1efdaba | 585 | * but we have a different cable detection procedure for function 1. |
669a5db4 | 586 | */ |
85cd7251 | 587 | |
a1efdaba | 588 | static struct ata_port_operations hpt374_fn1_port_ops = { |
029cfd6b | 589 | .inherits = &hpt372_port_ops, |
9e87be9e | 590 | .cable_detect = hpt374_fn1_cable_detect, |
85cd7251 | 591 | }; |
669a5db4 JG |
592 | |
593 | /** | |
ad452d64 | 594 | * hpt37x_clock_slot - Turn timing to PC clock entry |
305f8db7 | 595 | * @freq: Reported frequency in MHz |
669a5db4 | 596 | * |
305f8db7 | 597 | * Turn the timing data into a clock slot (0 for 33, 1 for 40, 2 for 50 |
669a5db4 JG |
598 | * and 3 for 66Mhz) |
599 | */ | |
85cd7251 | 600 | |
305f8db7 | 601 | static int hpt37x_clock_slot(unsigned int freq) |
669a5db4 | 602 | { |
305f8db7 | 603 | if (freq < 40) |
669a5db4 | 604 | return 0; /* 33Mhz slot */ |
305f8db7 | 605 | if (freq < 45) |
669a5db4 | 606 | return 1; /* 40Mhz slot */ |
305f8db7 | 607 | if (freq < 55) |
669a5db4 JG |
608 | return 2; /* 50Mhz slot */ |
609 | return 3; /* 60Mhz slot */ | |
610 | } | |
611 | ||
612 | /** | |
613 | * hpt37x_calibrate_dpll - Calibrate the DPLL loop | |
85cd7251 | 614 | * @dev: PCI device |
669a5db4 JG |
615 | * |
616 | * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this | |
617 | * succeeds | |
618 | */ | |
619 | ||
620 | static int hpt37x_calibrate_dpll(struct pci_dev *dev) | |
621 | { | |
622 | u8 reg5b; | |
623 | u32 reg5c; | |
624 | int tries; | |
85cd7251 | 625 | |
49bfbd38 | 626 | for (tries = 0; tries < 0x5000; tries++) { |
669a5db4 JG |
627 | udelay(50); |
628 | pci_read_config_byte(dev, 0x5b, ®5b); | |
629 | if (reg5b & 0x80) { | |
630 | /* See if it stays set */ | |
49bfbd38 | 631 | for (tries = 0; tries < 0x1000; tries++) { |
669a5db4 JG |
632 | pci_read_config_byte(dev, 0x5b, ®5b); |
633 | /* Failed ? */ | |
634 | if ((reg5b & 0x80) == 0) | |
635 | return 0; | |
636 | } | |
637 | /* Turn off tuning, we have the DPLL set */ | |
638 | pci_read_config_dword(dev, 0x5c, ®5c); | |
49bfbd38 | 639 | pci_write_config_dword(dev, 0x5c, reg5c & ~0x100); |
669a5db4 JG |
640 | return 1; |
641 | } | |
642 | } | |
643 | /* Never went stable */ | |
644 | return 0; | |
645 | } | |
73946f9f | 646 | |
96c34ac4 SS |
647 | static int hpt37x_pci_clock(struct pci_dev *pdev, unsigned int base) |
648 | { | |
649 | unsigned int freq; | |
650 | u32 fcnt; | |
651 | ||
652 | /* | |
653 | * Some devices do not let this value be accessed via PCI space | |
654 | * according to the old driver. In addition we must use the value | |
655 | * from FN 0 on the HPT374. | |
656 | */ | |
75b4d58c SS |
657 | if (pdev->device == PCI_DEVICE_ID_TTI_HPT374 && |
658 | (PCI_FUNC(pdev->devfn) & 1)) { | |
659 | struct pci_dev *pdev_fn0; | |
660 | ||
661 | pdev_fn0 = pci_get_slot(pdev->bus, pdev->devfn - 1); | |
662 | /* Someone hot plugged the controller on us? */ | |
663 | if (!pdev_fn0) | |
96c34ac4 | 664 | return 0; |
75b4d58c SS |
665 | fcnt = inl(pci_resource_start(pdev_fn0, 4) + 0x90); |
666 | pci_dev_put(pdev_fn0); | |
96c34ac4 SS |
667 | } else { |
668 | fcnt = inl(pci_resource_start(pdev, 4) + 0x90); | |
669 | } | |
670 | ||
671 | if ((fcnt >> 12) != 0xABCDE) { | |
672 | u32 total = 0; | |
673 | int i; | |
674 | u16 sr; | |
675 | ||
676 | dev_warn(&pdev->dev, "BIOS clock data not set\n"); | |
677 | ||
678 | /* This is the process the HPT371 BIOS is reported to use */ | |
679 | for (i = 0; i < 128; i++) { | |
680 | pci_read_config_word(pdev, 0x78, &sr); | |
681 | total += sr & 0x1FF; | |
682 | udelay(15); | |
683 | } | |
684 | fcnt = total / 128; | |
685 | } | |
686 | fcnt &= 0x1FF; | |
687 | ||
688 | freq = (fcnt * base) / 192; /* in MHz */ | |
689 | ||
690 | /* Clamp to bands */ | |
691 | if (freq < 40) | |
692 | return 33; | |
693 | if (freq < 45) | |
694 | return 40; | |
695 | if (freq < 55) | |
696 | return 50; | |
697 | return 66; | |
698 | } | |
699 | ||
669a5db4 JG |
700 | /** |
701 | * hpt37x_init_one - Initialise an HPT37X/302 | |
702 | * @dev: PCI device | |
703 | * @id: Entry in match table | |
704 | * | |
705 | * Initialise an HPT37x device. There are some interesting complications | |
706 | * here. Firstly the chip may report 366 and be one of several variants. | |
707 | * Secondly all the timings depend on the clock for the chip which we must | |
708 | * detect and look up | |
709 | * | |
710 | * This is the known chip mappings. It may be missing a couple of later | |
711 | * releases. | |
712 | * | |
713 | * Chip version PCI Rev Notes | |
714 | * HPT366 4 (HPT366) 0 Other driver | |
715 | * HPT366 4 (HPT366) 1 Other driver | |
716 | * HPT368 4 (HPT366) 2 Other driver | |
717 | * HPT370 4 (HPT366) 3 UDMA100 | |
718 | * HPT370A 4 (HPT366) 4 UDMA100 | |
719 | * HPT372 4 (HPT366) 5 UDMA133 (1) | |
720 | * HPT372N 4 (HPT366) 6 Other driver | |
721 | * HPT372A 5 (HPT372) 1 UDMA133 (1) | |
722 | * HPT372N 5 (HPT372) 2 Other driver | |
723 | * HPT302 6 (HPT302) 1 UDMA133 | |
724 | * HPT302N 6 (HPT302) 2 Other driver | |
725 | * HPT371 7 (HPT371) * UDMA133 | |
726 | * HPT374 8 (HPT374) * UDMA133 4 channel | |
727 | * HPT372N 9 (HPT372N) * Other driver | |
728 | * | |
729 | * (1) UDMA133 support depends on the bus clock | |
730 | */ | |
85cd7251 | 731 | |
669a5db4 JG |
732 | static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
733 | { | |
734 | /* HPT370 - UDMA100 */ | |
1626aeb8 | 735 | static const struct ata_port_info info_hpt370 = { |
1d2808fd | 736 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
737 | .pio_mask = ATA_PIO4, |
738 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 739 | .udma_mask = ATA_UDMA5, |
669a5db4 JG |
740 | .port_ops = &hpt370_port_ops |
741 | }; | |
742 | /* HPT370A - UDMA100 */ | |
1626aeb8 | 743 | static const struct ata_port_info info_hpt370a = { |
1d2808fd | 744 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
745 | .pio_mask = ATA_PIO4, |
746 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 747 | .udma_mask = ATA_UDMA5, |
669a5db4 JG |
748 | .port_ops = &hpt370a_port_ops |
749 | }; | |
fc2698d5 | 750 | /* HPT370 - UDMA66 */ |
1626aeb8 | 751 | static const struct ata_port_info info_hpt370_33 = { |
1d2808fd | 752 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
753 | .pio_mask = ATA_PIO4, |
754 | .mwdma_mask = ATA_MWDMA2, | |
fc2698d5 | 755 | .udma_mask = ATA_UDMA4, |
fcc2f69a AC |
756 | .port_ops = &hpt370_port_ops |
757 | }; | |
fc2698d5 | 758 | /* HPT370A - UDMA66 */ |
1626aeb8 | 759 | static const struct ata_port_info info_hpt370a_33 = { |
1d2808fd | 760 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
761 | .pio_mask = ATA_PIO4, |
762 | .mwdma_mask = ATA_MWDMA2, | |
fc2698d5 | 763 | .udma_mask = ATA_UDMA4, |
fcc2f69a AC |
764 | .port_ops = &hpt370a_port_ops |
765 | }; | |
8e834c2e | 766 | /* HPT372 - UDMA133 */ |
1626aeb8 | 767 | static const struct ata_port_info info_hpt372 = { |
1d2808fd | 768 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
769 | .pio_mask = ATA_PIO4, |
770 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 771 | .udma_mask = ATA_UDMA6, |
669a5db4 JG |
772 | .port_ops = &hpt372_port_ops |
773 | }; | |
8e834c2e SS |
774 | /* HPT371, 302 - UDMA133 */ |
775 | static const struct ata_port_info info_hpt302 = { | |
776 | .flags = ATA_FLAG_SLAVE_POSS, | |
777 | .pio_mask = ATA_PIO4, | |
778 | .mwdma_mask = ATA_MWDMA2, | |
779 | .udma_mask = ATA_UDMA6, | |
780 | .port_ops = &hpt302_port_ops | |
781 | }; | |
defed559 | 782 | /* HPT374 - UDMA100, function 1 uses different cable_detect method */ |
a1efdaba TH |
783 | static const struct ata_port_info info_hpt374_fn0 = { |
784 | .flags = ATA_FLAG_SLAVE_POSS, | |
14bdef98 EIB |
785 | .pio_mask = ATA_PIO4, |
786 | .mwdma_mask = ATA_MWDMA2, | |
a1efdaba TH |
787 | .udma_mask = ATA_UDMA5, |
788 | .port_ops = &hpt372_port_ops | |
789 | }; | |
790 | static const struct ata_port_info info_hpt374_fn1 = { | |
1d2808fd | 791 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
792 | .pio_mask = ATA_PIO4, |
793 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 794 | .udma_mask = ATA_UDMA5, |
a1efdaba | 795 | .port_ops = &hpt374_fn1_port_ops |
669a5db4 JG |
796 | }; |
797 | ||
798 | static const int MHz[4] = { 33, 40, 50, 66 }; | |
1626aeb8 | 799 | void *private_data = NULL; |
887125e3 | 800 | const struct ata_port_info *ppi[] = { NULL, NULL }; |
89d3b360 | 801 | u8 rev = dev->revision; |
669a5db4 | 802 | u8 irqmask; |
fcc2f69a | 803 | u8 mcr1; |
305f8db7 | 804 | unsigned int freq; /* MHz */ |
fcc2f69a | 805 | int prefer_dpll = 1; |
a617c09f | 806 | |
fcc2f69a | 807 | unsigned long iobase = pci_resource_start(dev, 4); |
669a5db4 JG |
808 | |
809 | const struct hpt_chip *chip_table; | |
810 | int clock_slot; | |
f08048e9 TH |
811 | int rc; |
812 | ||
813 | rc = pcim_enable_device(dev); | |
814 | if (rc) | |
815 | return rc; | |
669a5db4 | 816 | |
910f7bb1 SS |
817 | switch (dev->device) { |
818 | case PCI_DEVICE_ID_TTI_HPT366: | |
669a5db4 JG |
819 | /* May be a later chip in disguise. Check */ |
820 | /* Older chips are in the HPT366 driver. Ignore them */ | |
89d3b360 | 821 | if (rev < 3) |
669a5db4 JG |
822 | return -ENODEV; |
823 | /* N series chips have their own driver. Ignore */ | |
89d3b360 | 824 | if (rev == 6) |
669a5db4 JG |
825 | return -ENODEV; |
826 | ||
49bfbd38 SS |
827 | switch (rev) { |
828 | case 3: | |
829 | ppi[0] = &info_hpt370; | |
830 | chip_table = &hpt370; | |
831 | prefer_dpll = 0; | |
832 | break; | |
833 | case 4: | |
834 | ppi[0] = &info_hpt370a; | |
835 | chip_table = &hpt370a; | |
836 | prefer_dpll = 0; | |
837 | break; | |
838 | case 5: | |
839 | ppi[0] = &info_hpt372; | |
840 | chip_table = &hpt372; | |
841 | break; | |
842 | default: | |
f06c13aa HR |
843 | dev_err(&dev->dev, |
844 | "Unknown HPT366 subtype, please report (%d)\n", | |
8d7b1c70 | 845 | rev); |
49bfbd38 | 846 | return -ENODEV; |
669a5db4 | 847 | } |
910f7bb1 SS |
848 | break; |
849 | case PCI_DEVICE_ID_TTI_HPT372: | |
850 | /* 372N if rev >= 2 */ | |
851 | if (rev >= 2) | |
852 | return -ENODEV; | |
853 | ppi[0] = &info_hpt372; | |
854 | chip_table = &hpt372a; | |
855 | break; | |
856 | case PCI_DEVICE_ID_TTI_HPT302: | |
857 | /* 302N if rev > 1 */ | |
858 | if (rev > 1) | |
859 | return -ENODEV; | |
860 | ppi[0] = &info_hpt302; | |
861 | /* Check this */ | |
862 | chip_table = &hpt302; | |
863 | break; | |
864 | case PCI_DEVICE_ID_TTI_HPT371: | |
865 | if (rev > 1) | |
866 | return -ENODEV; | |
867 | ppi[0] = &info_hpt302; | |
868 | chip_table = &hpt371; | |
869 | /* | |
870 | * Single channel device, master is not present but the BIOS | |
871 | * (or us for non x86) must mark it absent | |
872 | */ | |
873 | pci_read_config_byte(dev, 0x50, &mcr1); | |
874 | mcr1 &= ~0x04; | |
875 | pci_write_config_byte(dev, 0x50, mcr1); | |
876 | break; | |
877 | case PCI_DEVICE_ID_TTI_HPT374: | |
878 | chip_table = &hpt374; | |
879 | if (!(PCI_FUNC(dev->devfn) & 1)) | |
880 | *ppi = &info_hpt374_fn0; | |
881 | else | |
882 | *ppi = &info_hpt374_fn1; | |
883 | break; | |
884 | default: | |
f06c13aa HR |
885 | dev_err(&dev->dev, "PCI table is bogus, please report (%d)\n", |
886 | dev->device); | |
910f7bb1 | 887 | return -ENODEV; |
669a5db4 JG |
888 | } |
889 | /* Ok so this is a chip we support */ | |
890 | ||
891 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); | |
892 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); | |
893 | pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); | |
894 | pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); | |
895 | ||
896 | pci_read_config_byte(dev, 0x5A, &irqmask); | |
897 | irqmask &= ~0x10; | |
898 | pci_write_config_byte(dev, 0x5a, irqmask); | |
899 | ||
8d093e02 SS |
900 | /* |
901 | * HPT371 chips physically have only one channel, the secondary one, | |
902 | * but the primary channel registers do exist! Go figure... | |
903 | * So, we manually disable the non-existing channel here | |
904 | * (if the BIOS hasn't done this already). | |
905 | */ | |
906 | if (dev->device == PCI_DEVICE_ID_TTI_HPT371) { | |
907 | u8 mcr1; | |
908 | ||
909 | pci_read_config_byte(dev, 0x50, &mcr1); | |
910 | mcr1 &= ~0x04; | |
911 | pci_write_config_byte(dev, 0x50, mcr1); | |
912 | } | |
913 | ||
669a5db4 JG |
914 | /* |
915 | * default to pci clock. make sure MA15/16 are set to output | |
916 | * to prevent drives having problems with 40-pin cables. Needed | |
917 | * for some drives such as IBM-DTLA which will not enter ready | |
918 | * state on reset when PDIAG is a input. | |
919 | */ | |
920 | ||
85cd7251 | 921 | pci_write_config_byte(dev, 0x5b, 0x23); |
a617c09f | 922 | |
fcc2f69a AC |
923 | /* |
924 | * HighPoint does this for HPT372A. | |
925 | * NOTE: This register is only writeable via I/O space. | |
926 | */ | |
927 | if (chip_table == &hpt372a) | |
928 | outb(0x0e, iobase + 0x9c); | |
85cd7251 | 929 | |
96c34ac4 SS |
930 | freq = hpt37x_pci_clock(dev, chip_table->base); |
931 | if (!freq) | |
932 | return -ENODEV; | |
85cd7251 | 933 | |
669a5db4 JG |
934 | /* |
935 | * Turn the frequency check into a band and then find a timing | |
936 | * table to match it. | |
937 | */ | |
a617c09f | 938 | |
305f8db7 | 939 | clock_slot = hpt37x_clock_slot(freq); |
fcc2f69a | 940 | if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) { |
669a5db4 JG |
941 | /* |
942 | * We need to try PLL mode instead | |
fcc2f69a AC |
943 | * |
944 | * For non UDMA133 capable devices we should | |
945 | * use a 50MHz DPLL by choice | |
669a5db4 | 946 | */ |
fcc2f69a | 947 | unsigned int f_low, f_high; |
960c8a10 | 948 | int dpll, adjust; |
a617c09f | 949 | |
960c8a10 | 950 | /* Compute DPLL */ |
887125e3 | 951 | dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; |
a617c09f | 952 | |
960c8a10 | 953 | f_low = (MHz[clock_slot] * 48) / MHz[dpll]; |
fcc2f69a | 954 | f_high = f_low + 2; |
960c8a10 AC |
955 | if (clock_slot > 1) |
956 | f_high += 2; | |
fcc2f69a AC |
957 | |
958 | /* Select the DPLL clock. */ | |
959 | pci_write_config_byte(dev, 0x5b, 0x21); | |
49bfbd38 SS |
960 | pci_write_config_dword(dev, 0x5C, |
961 | (f_high << 16) | f_low | 0x100); | |
85cd7251 | 962 | |
49bfbd38 | 963 | for (adjust = 0; adjust < 8; adjust++) { |
669a5db4 JG |
964 | if (hpt37x_calibrate_dpll(dev)) |
965 | break; | |
49bfbd38 SS |
966 | /* |
967 | * See if it'll settle at a fractionally | |
968 | * different clock | |
969 | */ | |
64a81709 AC |
970 | if (adjust & 1) |
971 | f_low -= adjust >> 1; | |
972 | else | |
973 | f_high += adjust >> 1; | |
49bfbd38 SS |
974 | pci_write_config_dword(dev, 0x5C, |
975 | (f_high << 16) | f_low | 0x100); | |
669a5db4 JG |
976 | } |
977 | if (adjust == 8) { | |
f06c13aa | 978 | dev_err(&dev->dev, "DPLL did not stabilize!\n"); |
669a5db4 JG |
979 | return -ENODEV; |
980 | } | |
960c8a10 | 981 | if (dpll == 3) |
1626aeb8 | 982 | private_data = (void *)hpt37x_timings_66; |
fcc2f69a | 983 | else |
1626aeb8 | 984 | private_data = (void *)hpt37x_timings_50; |
85cd7251 | 985 | |
f06c13aa | 986 | dev_info(&dev->dev, "bus clock %dMHz, using %dMHz DPLL\n", |
40d69ba0 | 987 | MHz[clock_slot], MHz[dpll]); |
669a5db4 | 988 | } else { |
1626aeb8 | 989 | private_data = (void *)chip_table->clocks[clock_slot]; |
669a5db4 | 990 | /* |
a4734468 AC |
991 | * Perform a final fixup. Note that we will have used the |
992 | * DPLL on the HPT372 which means we don't have to worry | |
993 | * about lack of UDMA133 support on lower clocks | |
49bfbd38 | 994 | */ |
85cd7251 | 995 | |
887125e3 TH |
996 | if (clock_slot < 2 && ppi[0] == &info_hpt370) |
997 | ppi[0] = &info_hpt370_33; | |
998 | if (clock_slot < 2 && ppi[0] == &info_hpt370a) | |
999 | ppi[0] = &info_hpt370a_33; | |
40d69ba0 | 1000 | |
f06c13aa | 1001 | dev_info(&dev->dev, "%s using %dMHz bus clock\n", |
40d69ba0 | 1002 | chip_table->name, MHz[clock_slot]); |
669a5db4 | 1003 | } |
fcc2f69a | 1004 | |
669a5db4 | 1005 | /* Now kick off ATA set up */ |
1c5afdf7 | 1006 | return ata_pci_bmdma_init_one(dev, ppi, &hpt37x_sht, private_data, 0); |
669a5db4 JG |
1007 | } |
1008 | ||
2d2744fc JG |
1009 | static const struct pci_device_id hpt37x[] = { |
1010 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, | |
1011 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), }, | |
1012 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), }, | |
1013 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), }, | |
1014 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), }, | |
1015 | ||
1016 | { }, | |
669a5db4 JG |
1017 | }; |
1018 | ||
1019 | static struct pci_driver hpt37x_pci_driver = { | |
49bfbd38 | 1020 | .name = DRV_NAME, |
669a5db4 | 1021 | .id_table = hpt37x, |
49bfbd38 | 1022 | .probe = hpt37x_init_one, |
669a5db4 JG |
1023 | .remove = ata_pci_remove_one |
1024 | }; | |
1025 | ||
2fc75da0 | 1026 | module_pci_driver(hpt37x_pci_driver); |
669a5db4 | 1027 | |
669a5db4 JG |
1028 | MODULE_AUTHOR("Alan Cox"); |
1029 | MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x"); | |
1030 | MODULE_LICENSE("GPL"); | |
1031 | MODULE_DEVICE_TABLE(pci, hpt37x); | |
1032 | MODULE_VERSION(DRV_VERSION); |