[linux-2.6-block.git] / drivers / ata / pata_efar.c

/*
 *    pata_efar.c - EFAR PIIX clone controller driver
 *
 *	(C) 2005 Red Hat <alan@redhat.com>
 *
 *    Some parts based on ata_piix.c by Jeff Garzik and others.
 *
 *    The EFAR is a PIIX4 clone with UDMA66 support. Unlike the later
 *    Intel ICH controllers the EFAR widened the UDMA mode register bits
 *    and doesn't require the funky clock selection.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include <linux/ata.h>

#define DRV_NAME	"pata_efar"
#define DRV_VERSION	"0.4.4"

/**
 *	efar_pre_reset	-	Enable bits
 *	@ap: Port
 *
 *	Perform cable detection for the EFAR ATA interface. This is
 *	different to the PIIX arrangement
 */

static int efar_pre_reset(struct ata_port *ap)
{
	static const struct pci_bits efar_enable_bits[] = {
		{ 0x41U, 1U, 0x80UL, 0x80UL },	/* port 0 */
		{ 0x43U, 1U, 0x80UL, 0x80UL },	/* port 1 */
	};
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	if (!pci_test_config_bits(pdev, &efar_enable_bits[ap->port_no]))
		return -ENOENT;

	return ata_std_prereset(ap);
}

/**
 *	efar_probe_reset - Probe specified port on PATA host controller
 *	@ap: Port to probe
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void efar_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, efar_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
}

/**
 *	efar_cable_detect	-	check for 40/80 pin
 *	@ap: Port
 *
 *	Perform cable detection for the EFAR ATA interface. This is
 *	different to the PIIX arrangement
 */

static int efar_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 tmp;

	pci_read_config_byte(pdev, 0x47, &tmp);
	if (tmp & (2 >> ap->port_no))
		return ATA_CBL_PATA40;
	return ATA_CBL_PATA80;
}

/**
 *	efar_set_piomode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: um
 *
 *	Set PIO mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void efar_set_piomode (struct ata_port *ap, struct ata_device *adev)
{
	unsigned int pio	= adev->pio_mode - XFER_PIO_0;
	struct pci_dev *dev	= to_pci_dev(ap->host->dev);
	unsigned int idetm_port= ap->port_no ? 0x42 : 0x40;
	u16 idetm_data;
	int control = 0;

	/*
	 *	See Intel Document 298600-004 for the timing programing rules
	 *	for PIIX/ICH. The EFAR is a clone so very similar
	 */

	static const	 /* ISP  RTC */
	u8 timings[][2]	= { { 0, 0 },
			    { 0, 0 },
			    { 1, 0 },
			    { 2, 1 },
			    { 2, 3 }, };

	if (pio > 2)
		control |= 1;	/* TIME1 enable */
	if (ata_pio_need_iordy(adev))	/* PIO 3/4 require IORDY */
		control |= 2;	/* IE enable */
	/* Intel specifies that the PPE functionality is for disk only */
	if (adev->class == ATA_DEV_ATA)
		control |= 4;	/* PPE enable */

	pci_read_config_word(dev, idetm_port, &idetm_data);

	/* Enable PPE, IE and TIME as appropriate */

	if (adev->devno == 0) {
		idetm_data &= 0xCCF0;
		idetm_data |= control;
		idetm_data |= (timings[pio][0] << 12) |
			(timings[pio][1] << 8);
	} else {
		int shift = 4 * ap->port_no;
		u8 slave_data;

		idetm_data &= 0xCC0F;
		idetm_data |= (control << 4);

		/* Slave timing in seperate register */
		pci_read_config_byte(dev, 0x44, &slave_data);
		slave_data &= 0x0F << shift;
		slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << shift;
		pci_write_config_byte(dev, 0x44, slave_data);
	}

	idetm_data |= 0x4000;	/* Ensure SITRE is enabled */
	pci_write_config_word(dev, idetm_port, idetm_data);
}

/**
 *	efar_set_dmamode - Initialize host controller PATA DMA timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device to program
 *
 *	Set UDMA/MWDMA mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void efar_set_dmamode (struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *dev	= to_pci_dev(ap->host->dev);
	u8 master_port		= ap->port_no ? 0x42 : 0x40;
	u16 master_data;
	u8 speed		= adev->dma_mode;
	int devid		= adev->devno + 2 * ap->port_no;
	u8 udma_enable;

	static const	 /* ISP  RTC */
	u8 timings[][2]	= { { 0, 0 },
			    { 0, 0 },
			    { 1, 0 },
			    { 2, 1 },
			    { 2, 3 }, };

	pci_read_config_word(dev, master_port, &master_data);
	pci_read_config_byte(dev, 0x48, &udma_enable);

	if (speed >= XFER_UDMA_0) {
		unsigned int udma	= adev->dma_mode - XFER_UDMA_0;
		u16 udma_timing;

		udma_enable |= (1 << devid);

		/* Load the UDMA mode number */
		pci_read_config_word(dev, 0x4A, &udma_timing);
		udma_timing &= ~(7 << (4 * devid));
		udma_timing |= udma << (4 * devid);
		pci_write_config_word(dev, 0x4A, udma_timing);
	} else {
		/*
		 * MWDMA is driven by the PIO timings. We must also enable
		 * IORDY unconditionally along with TIME1. PPE has already
		 * been set when the PIO timing was set.
		 */
		unsigned int mwdma	= adev->dma_mode - XFER_MW_DMA_0;
		unsigned int control;
		u8 slave_data;
		const unsigned int needed_pio[3] = {
			XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
		};
		int pio = needed_pio[mwdma] - XFER_PIO_0;

		control = 3;	/* IORDY|TIME1 */

		/* If the drive MWDMA is faster than it can do PIO then
		   we must force PIO into PIO0 */

		if (adev->pio_mode < needed_pio[mwdma])
			/* Enable DMA timing only */
			control |= 8;	/* PIO cycles in PIO0 */

		if (adev->devno) {	/* Slave */
			master_data &= 0xFF4F;  /* Mask out IORDY|TIME1|DMAONLY */
			master_data |= control << 4;
			pci_read_config_byte(dev, 0x44, &slave_data);
			slave_data &= (0x0F + 0xE1 * ap->port_no);
			/* Load the matching timing */
			slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
			pci_write_config_byte(dev, 0x44, slave_data);
		} else { 	/* Master */
			master_data &= 0xCCF4;	/* Mask out IORDY|TIME1|DMAONLY
						   and master timing bits */
			master_data |= control;
			master_data |=
				(timings[pio][0] << 12) |
				(timings[pio][1] << 8);
		}
		udma_enable &= ~(1 << devid);
		pci_write_config_word(dev, master_port, master_data);
	}
	pci_write_config_byte(dev, 0x48, udma_enable);
}

static struct scsi_host_template efar_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
#ifdef CONFIG_PM
	.resume			= ata_scsi_device_resume,
	.suspend		= ata_scsi_device_suspend,
#endif
};

static const struct ata_port_operations efar_ops = {
	.port_disable		= ata_port_disable,
	.set_piomode		= efar_set_piomode,
	.set_dmamode		= efar_set_dmamode,
	.mode_filter		= ata_pci_default_filter,

	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,

	.freeze			= ata_bmdma_freeze,
	.thaw			= ata_bmdma_thaw,
	.error_handler		= efar_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
	.cable_detect		= efar_cable_detect,

	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.data_xfer		= ata_data_xfer,

	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.irq_on			= ata_irq_on,
	.irq_ack		= ata_irq_ack,

	.port_start		= ata_port_start,
};


/**
 *	efar_init_one - Register EFAR ATA PCI device with kernel services
 *	@pdev: PCI device to register
 *	@ent: Entry in efar_pci_tbl matching with @pdev
 *
 *	Called from kernel PCI layer.
 *
 *	LOCKING:
 *	Inherited from PCI layer (may sleep).
 *
 *	RETURNS:
 *	Zero on success, or -ERRNO value.
 */

static int efar_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version;
	static struct ata_port_info info = {
		.sht		= &efar_sht,
		.flags		= ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma1-2 */
		.udma_mask 	= 0x0f, /* UDMA 66 */
		.port_ops	= &efar_ops,
	};
	static struct ata_port_info *port_info[2] = { &info, &info };

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev,
			   "version " DRV_VERSION "\n");

	return ata_pci_init_one(pdev, port_info, 2);
}

static const struct pci_device_id efar_pci_tbl[] = {
	{ PCI_VDEVICE(EFAR, 0x9130), },

	{ }	/* terminate list */
};

static struct pci_driver efar_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= efar_pci_tbl,
	.probe			= efar_init_one,
	.remove			= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend		= ata_pci_device_suspend,
	.resume			= ata_pci_device_resume,
#endif
};

static int __init efar_init(void)
{
	return pci_register_driver(&efar_pci_driver);
}

static void __exit efar_exit(void)
{
	pci_unregister_driver(&efar_pci_driver);
}

module_init(efar_init);
module_exit(efar_exit);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("SCSI low-level driver for EFAR PIIX clones");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, efar_pci_tbl);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_efar.c - EFAR PIIX clone controller driver
	3	*
	4	* (C) 2005 Red Hat <alan@redhat.com>
	5	*
	6	* Some parts based on ata_piix.c by Jeff Garzik and others.
	7	*
	8	* The EFAR is a PIIX4 clone with UDMA66 support. Unlike the later
	9	* Intel ICH controllers the EFAR widened the UDMA mode register bits
	10	* and doesn't require the funky clock selection.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/module.h>
	15	#include <linux/pci.h>
	16	#include <linux/init.h>
	17	#include <linux/blkdev.h>
	18	#include <linux/delay.h>
	19	#include <linux/device.h>
	20	#include <scsi/scsi_host.h>
	21	#include <linux/libata.h>
	22	#include <linux/ata.h>
	23
	24	#define DRV_NAME "pata_efar"
6bfed3fb	25	#define DRV_VERSION "0.4.4"
669a5db4 JG	26
669a5db4 JG	27	/**
6bfed3fb	28	* efar_pre_reset - Enable bits
669a5db4 JG	29	* @ap: Port
	30	*
	31	* Perform cable detection for the EFAR ATA interface. This is
	32	* different to the PIIX arrangement
	33	*/
	34
	35	static int efar_pre_reset(struct ata_port *ap)
	36	{
	37	static const struct pci_bits efar_enable_bits[] = {
	38	{ 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
	39	{ 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
	40	};
669a5db4	41	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
669a5db4	42
c961922b AC	43	if (!pci_test_config_bits(pdev, &efar_enable_bits[ap->port_no]))
	44	return -ENOENT;
	45
669a5db4 JG	46	return ata_std_prereset(ap);
	47	}
	48
	49	/**
	50	* efar_probe_reset - Probe specified port on PATA host controller
	51	* @ap: Port to probe
	52	*
	53	* LOCKING:
	54	* None (inherited from caller).
	55	*/
	56
	57	static void efar_error_handler(struct ata_port *ap)
	58	{
	59	ata_bmdma_drive_eh(ap, efar_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
	60	}
	61
6bfed3fb AC	62	/**
	63	* efar_cable_detect - check for 40/80 pin
	64	* @ap: Port
	65	*
	66	* Perform cable detection for the EFAR ATA interface. This is
	67	* different to the PIIX arrangement
	68	*/
	69
	70	static int efar_cable_detect(struct ata_port *ap)
	71	{
	72	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	73	u8 tmp;
	74
	75	pci_read_config_byte(pdev, 0x47, &tmp);
	76	if (tmp & (2 >> ap->port_no))
	77	return ATA_CBL_PATA40;
	78	return ATA_CBL_PATA80;
	79	}
	80
669a5db4 JG	81	/**
	82	* efar_set_piomode - Initialize host controller PATA PIO timings
	83	* @ap: Port whose timings we are configuring
	84	* @adev: um
	85	*
	86	* Set PIO mode for device, in host controller PCI config space.
	87	*
	88	* LOCKING:
	89	* None (inherited from caller).
	90	*/
	91
	92	static void efar_set_piomode (struct ata_port ap, struct ata_device adev)
	93	{
	94	unsigned int pio = adev->pio_mode - XFER_PIO_0;
	95	struct pci_dev *dev = to_pci_dev(ap->host->dev);
	96	unsigned int idetm_port= ap->port_no ? 0x42 : 0x40;
	97	u16 idetm_data;
	98	int control = 0;
	99
	100	/*
	101	* See Intel Document 298600-004 for the timing programing rules
	102	* for PIIX/ICH. The EFAR is a clone so very similar
	103	*/
	104
	105	static const /* ISP RTC */
	106	u8 timings[][2] = { { 0, 0 },
	107	{ 0, 0 },
	108	{ 1, 0 },
	109	{ 2, 1 },
	110	{ 2, 3 }, };
	111
	112	if (pio > 2)
	113	control \|= 1; /* TIME1 enable */
	114	if (ata_pio_need_iordy(adev)) /* PIO 3/4 require IORDY */
	115	control \|= 2; /* IE enable */
	116	/* Intel specifies that the PPE functionality is for disk only */
	117	if (adev->class == ATA_DEV_ATA)
	118	control \|= 4; /* PPE enable */
	119
	120	pci_read_config_word(dev, idetm_port, &idetm_data);
	121
	122	/* Enable PPE, IE and TIME as appropriate */
	123
	124	if (adev->devno == 0) {
	125	idetm_data &= 0xCCF0;
	126	idetm_data \|= control;
	127	idetm_data \|= (timings[pio][0] << 12) \|
	128	(timings[pio][1] << 8);
	129	} else {
	130	int shift = 4 * ap->port_no;
	131	u8 slave_data;
	132
	133	idetm_data &= 0xCC0F;
	134	idetm_data \|= (control << 4);
	135
	136	/* Slave timing in seperate register */
	137	pci_read_config_byte(dev, 0x44, &slave_data);
	138	slave_data &= 0x0F << shift;
	139	slave_data \|= ((timings[pio][0] << 2) \| timings[pio][1]) << shift;
	140	pci_write_config_byte(dev, 0x44, slave_data);
	141	}
	142
	143	idetm_data \|= 0x4000; /* Ensure SITRE is enabled */
	144	pci_write_config_word(dev, idetm_port, idetm_data);
145	}
146
147	/**
148	* efar_set_dmamode - Initialize host controller PATA DMA timings
149	* @ap: Port whose timings we are configuring
150	* @adev: Device to program
151	*
152	* Set UDMA/MWDMA mode for device, in host controller PCI config space.
153	*
154	* LOCKING:
155	* None (inherited from caller).
156	*/
157
158	static void efar_set_dmamode (struct ata_port ap, struct ata_device adev)
159	{
160	struct pci_dev *dev = to_pci_dev(ap->host->dev);
161	u8 master_port = ap->port_no ? 0x42 : 0x40;
162	u16 master_data;
163	u8 speed = adev->dma_mode;
164	int devid = adev->devno + 2 * ap->port_no;
165	u8 udma_enable;
166
167	static const /* ISP RTC */
168	u8 timings[][2] = { { 0, 0 },
169	{ 0, 0 },
170	{ 1, 0 },
171	{ 2, 1 },
172	{ 2, 3 }, };
173
174	pci_read_config_word(dev, master_port, &master_data);
175	pci_read_config_byte(dev, 0x48, &udma_enable);
176
177	if (speed >= XFER_UDMA_0) {
178	unsigned int udma = adev->dma_mode - XFER_UDMA_0;
179	u16 udma_timing;
180
181	udma_enable \|= (1 << devid);
182
183	/* Load the UDMA mode number */
184	pci_read_config_word(dev, 0x4A, &udma_timing);
185	udma_timing &= ~(7 << (4 * devid));
186	udma_timing \|= udma << (4 * devid);
187	pci_write_config_word(dev, 0x4A, udma_timing);
188	} else {
189	/*
190	* MWDMA is driven by the PIO timings. We must also enable
191	* IORDY unconditionally along with TIME1. PPE has already
192	* been set when the PIO timing was set.
193	*/
194	unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
195	unsigned int control;
196	u8 slave_data;
197	const unsigned int needed_pio[3] = {
198	XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
199	};
200	int pio = needed_pio[mwdma] - XFER_PIO_0;
201
202	control = 3; /* IORDY\|TIME1 */
203
204	/* If the drive MWDMA is faster than it can do PIO then
205	we must force PIO into PIO0 */
206
207	if (adev->pio_mode < needed_pio[mwdma])
208	/* Enable DMA timing only */
209	control \|= 8; /* PIO cycles in PIO0 */
210
211	if (adev->devno) { /* Slave */
212	master_data &= 0xFF4F; /* Mask out IORDY\|TIME1\|DMAONLY */
213	master_data \|= control << 4;
214	pci_read_config_byte(dev, 0x44, &slave_data);
215	slave_data &= (0x0F + 0xE1 * ap->port_no);
216	/* Load the matching timing */
217	slave_data \|= ((timings[pio][0] << 2) \| timings[pio][1]) << (ap->port_no ? 4 : 0);
218	pci_write_config_byte(dev, 0x44, slave_data);
219	} else { /* Master */
220	master_data &= 0xCCF4; /* Mask out IORDY\|TIME1\|DMAONLY
221	and master timing bits */
222	master_data \|= control;
223	master_data \|=
224	(timings[pio][0] << 12) \|
225	(timings[pio][1] << 8);
226	}
227	udma_enable &= ~(1 << devid);
228	pci_write_config_word(dev, master_port, master_data);
229	}
230	pci_write_config_byte(dev, 0x48, udma_enable);
231	}
232
233	static struct scsi_host_template efar_sht = {
234	.module = THIS_MODULE,
235	.name = DRV_NAME,
236	.ioctl = ata_scsi_ioctl,
237	.queuecommand = ata_scsi_queuecmd,
238	.can_queue = ATA_DEF_QUEUE,
239	.this_id = ATA_SHT_THIS_ID,
240	.sg_tablesize = LIBATA_MAX_PRD,
669a5db4 JG	241	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	242	.emulated = ATA_SHT_EMULATED,
	243	.use_clustering = ATA_SHT_USE_CLUSTERING,
	244	.proc_name = DRV_NAME,
	245	.dma_boundary = ATA_DMA_BOUNDARY,
	246	.slave_configure = ata_scsi_slave_config,
afdfe899	247	.slave_destroy = ata_scsi_slave_destroy,
669a5db4	248	.bios_param = ata_std_bios_param,
438ac6d5	249	#ifdef CONFIG_PM
30ced0f0 A	250	.resume = ata_scsi_device_resume,
30ced0f0 A	251	.suspend = ata_scsi_device_suspend,
438ac6d5	252	#endif
669a5db4 JG	253	};
	254
	255	static const struct ata_port_operations efar_ops = {
	256	.port_disable = ata_port_disable,
	257	.set_piomode = efar_set_piomode,
	258	.set_dmamode = efar_set_dmamode,
	259	.mode_filter = ata_pci_default_filter,
	260
	261	.tf_load = ata_tf_load,
	262	.tf_read = ata_tf_read,
	263	.check_status = ata_check_status,
	264	.exec_command = ata_exec_command,
	265	.dev_select = ata_std_dev_select,
	266
	267	.freeze = ata_bmdma_freeze,
	268	.thaw = ata_bmdma_thaw,
	269	.error_handler = efar_error_handler,
	270	.post_internal_cmd = ata_bmdma_post_internal_cmd,
6bfed3fb	271	.cable_detect = efar_cable_detect,
669a5db4 JG	272
	273	.bmdma_setup = ata_bmdma_setup,
	274	.bmdma_start = ata_bmdma_start,
	275	.bmdma_stop = ata_bmdma_stop,
	276	.bmdma_status = ata_bmdma_status,
	277	.qc_prep = ata_qc_prep,
	278	.qc_issue = ata_qc_issue_prot,
0d5ff566	279	.data_xfer = ata_data_xfer,
669a5db4	280
669a5db4 JG	281	.irq_handler = ata_interrupt,
669a5db4 JG	282	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	283	.irq_on = ata_irq_on,
246ce3b6 AI	284	.irq_ack = ata_irq_ack,
669a5db4 JG	285
669a5db4 JG	286	.port_start = ata_port_start,
669a5db4 JG	287	};
	288
	289
	290	/**
	291	* efar_init_one - Register EFAR ATA PCI device with kernel services
	292	* @pdev: PCI device to register
	293	* @ent: Entry in efar_pci_tbl matching with @pdev
	294	*
	295	* Called from kernel PCI layer.
	296	*
	297	* LOCKING:
	298	* Inherited from PCI layer (may sleep).
	299	*
	300	* RETURNS:
	301	* Zero on success, or -ERRNO value.
	302	*/
	303
	304	static int efar_init_one (struct pci_dev pdev, const struct pci_device_id ent)
	305	{
	306	static int printed_version;
	307	static struct ata_port_info info = {
	308	.sht = &efar_sht,
	309	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	310	.pio_mask = 0x1f, /* pio0-4 */
	311	.mwdma_mask = 0x07, /* mwdma1-2 */
	312	.udma_mask = 0x0f, /* UDMA 66 */
	313	.port_ops = &efar_ops,
	314	};
	315	static struct ata_port_info *port_info[2] = { &info, &info };
	316
	317	if (!printed_version++)
	318	dev_printk(KERN_DEBUG, &pdev->dev,
	319	"version " DRV_VERSION "\n");
	320
	321	return ata_pci_init_one(pdev, port_info, 2);
	322	}
	323
	324	static const struct pci_device_id efar_pci_tbl[] = {
2d2744fc JG	325	{ PCI_VDEVICE(EFAR, 0x9130), },
2d2744fc JG	326
669a5db4 JG	327	{ } /* terminate list */
	328	};
	329
	330	static struct pci_driver efar_pci_driver = {
	331	.name = DRV_NAME,
	332	.id_table = efar_pci_tbl,
	333	.probe = efar_init_one,
	334	.remove = ata_pci_remove_one,
438ac6d5	335	#ifdef CONFIG_PM
30ced0f0 A	336	.suspend = ata_pci_device_suspend,
30ced0f0 A	337	.resume = ata_pci_device_resume,
438ac6d5	338	#endif
669a5db4 JG	339	};
	340
	341	static int __init efar_init(void)
	342	{
	343	return pci_register_driver(&efar_pci_driver);
	344	}
	345
	346	static void __exit efar_exit(void)
	347	{
	348	pci_unregister_driver(&efar_pci_driver);
	349	}
	350
669a5db4 JG	351	module_init(efar_init);
	352	module_exit(efar_exit);
	353
	354	MODULE_AUTHOR("Alan Cox");
	355	MODULE_DESCRIPTION("SCSI low-level driver for EFAR PIIX clones");
	356	MODULE_LICENSE("GPL");
	357	MODULE_DEVICE_TABLE(pci, efar_pci_tbl);
	358	MODULE_VERSION(DRV_VERSION);
	359