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3957df61 MP |
1 | /* |
2 | * pata_cs5536.c - CS5536 PATA for new ATA layer | |
3 | * (C) 2007 Martin K. Petersen <mkp@mkp.net> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | * | |
18 | * Documentation: | |
19 | * Available from AMD web site. | |
20 | * | |
21 | * The IDE timing registers for the CS5536 live in the Geode Machine | |
22 | * Specific Register file and not PCI config space. Most BIOSes | |
23 | * virtualize the PCI registers so the chip looks like a standard IDE | |
24 | * controller. Unfortunately not all implementations get this right. | |
25 | * In particular some have problems with unaligned accesses to the | |
26 | * virtualized PCI registers. This driver always does full dword | |
27 | * writes to work around the issue. Also, in case of a bad BIOS this | |
28 | * driver can be loaded with the "msr=1" parameter which forces using | |
29 | * the Machine Specific Registers to configure the device. | |
30 | */ | |
31 | ||
32 | #include <linux/kernel.h> | |
33 | #include <linux/module.h> | |
34 | #include <linux/pci.h> | |
35 | #include <linux/init.h> | |
36 | #include <linux/blkdev.h> | |
37 | #include <linux/delay.h> | |
38 | #include <linux/libata.h> | |
39 | #include <scsi/scsi_host.h> | |
40 | #include <asm/msr.h> | |
41 | ||
42 | #define DRV_NAME "pata_cs5536" | |
b6966a61 | 43 | #define DRV_VERSION "0.0.7" |
3957df61 MP |
44 | |
45 | enum { | |
46 | CFG = 0, | |
47 | DTC = 1, | |
48 | CAST = 2, | |
49 | ETC = 3, | |
50 | ||
51 | MSR_IDE_BASE = 0x51300000, | |
52 | MSR_IDE_CFG = (MSR_IDE_BASE + 0x10), | |
53 | MSR_IDE_DTC = (MSR_IDE_BASE + 0x12), | |
54 | MSR_IDE_CAST = (MSR_IDE_BASE + 0x13), | |
55 | MSR_IDE_ETC = (MSR_IDE_BASE + 0x14), | |
56 | ||
57 | PCI_IDE_CFG = 0x40, | |
58 | PCI_IDE_DTC = 0x48, | |
59 | PCI_IDE_CAST = 0x4c, | |
60 | PCI_IDE_ETC = 0x50, | |
61 | ||
62 | IDE_CFG_CHANEN = 0x2, | |
63 | IDE_CFG_CABLE = 0x10000, | |
64 | ||
65 | IDE_D0_SHIFT = 24, | |
66 | IDE_D1_SHIFT = 16, | |
67 | IDE_DRV_MASK = 0xff, | |
68 | ||
69 | IDE_CAST_D0_SHIFT = 6, | |
70 | IDE_CAST_D1_SHIFT = 4, | |
71 | IDE_CAST_DRV_MASK = 0x3, | |
72 | IDE_CAST_CMD_MASK = 0xff, | |
73 | IDE_CAST_CMD_SHIFT = 24, | |
74 | ||
75 | IDE_ETC_NODMA = 0x03, | |
76 | }; | |
77 | ||
78 | static int use_msr; | |
79 | ||
80 | static const u32 msr_reg[4] = { | |
81 | MSR_IDE_CFG, MSR_IDE_DTC, MSR_IDE_CAST, MSR_IDE_ETC, | |
82 | }; | |
83 | ||
84 | static const u8 pci_reg[4] = { | |
85 | PCI_IDE_CFG, PCI_IDE_DTC, PCI_IDE_CAST, PCI_IDE_ETC, | |
86 | }; | |
87 | ||
2072fb55 | 88 | static inline int cs5536_read(struct pci_dev *pdev, int reg, u32 *val) |
3957df61 MP |
89 | { |
90 | if (unlikely(use_msr)) { | |
91 | u32 dummy; | |
92 | ||
93 | rdmsr(msr_reg[reg], *val, dummy); | |
94 | return 0; | |
95 | } | |
96 | ||
97 | return pci_read_config_dword(pdev, pci_reg[reg], val); | |
98 | } | |
99 | ||
100 | static inline int cs5536_write(struct pci_dev *pdev, int reg, int val) | |
101 | { | |
102 | if (unlikely(use_msr)) { | |
103 | wrmsr(msr_reg[reg], val, 0); | |
104 | return 0; | |
105 | } | |
106 | ||
107 | return pci_write_config_dword(pdev, pci_reg[reg], val); | |
108 | } | |
109 | ||
110 | /** | |
111 | * cs5536_cable_detect - detect cable type | |
112 | * @ap: Port to detect on | |
113 | * @deadline: deadline jiffies for the operation | |
114 | * | |
115 | * Perform cable detection for ATA66 capable cable. Return a libata | |
116 | * cable type. | |
117 | */ | |
118 | ||
119 | static int cs5536_cable_detect(struct ata_port *ap) | |
120 | { | |
121 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
122 | u32 cfg; | |
123 | ||
124 | cs5536_read(pdev, CFG, &cfg); | |
125 | ||
126 | if (cfg & (IDE_CFG_CABLE << ap->port_no)) | |
127 | return ATA_CBL_PATA80; | |
128 | else | |
129 | return ATA_CBL_PATA40; | |
130 | } | |
131 | ||
132 | /** | |
133 | * cs5536_set_piomode - PIO setup | |
134 | * @ap: ATA interface | |
135 | * @adev: device on the interface | |
136 | */ | |
137 | ||
138 | static void cs5536_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
139 | { | |
140 | static const u8 drv_timings[5] = { | |
141 | 0x98, 0x55, 0x32, 0x21, 0x20, | |
142 | }; | |
143 | ||
144 | static const u8 addr_timings[5] = { | |
145 | 0x2, 0x1, 0x0, 0x0, 0x0, | |
146 | }; | |
147 | ||
148 | static const u8 cmd_timings[5] = { | |
149 | 0x99, 0x92, 0x90, 0x22, 0x20, | |
150 | }; | |
151 | ||
152 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
153 | struct ata_device *pair = ata_dev_pair(adev); | |
154 | int mode = adev->pio_mode - XFER_PIO_0; | |
155 | int cmdmode = mode; | |
b6966a61 MP |
156 | int dshift = adev->devno ? IDE_D1_SHIFT : IDE_D0_SHIFT; |
157 | int cshift = adev->devno ? IDE_CAST_D1_SHIFT : IDE_CAST_D0_SHIFT; | |
3957df61 MP |
158 | u32 dtc, cast, etc; |
159 | ||
160 | if (pair) | |
161 | cmdmode = min(mode, pair->pio_mode - XFER_PIO_0); | |
162 | ||
163 | cs5536_read(pdev, DTC, &dtc); | |
164 | cs5536_read(pdev, CAST, &cast); | |
165 | cs5536_read(pdev, ETC, &etc); | |
166 | ||
167 | dtc &= ~(IDE_DRV_MASK << dshift); | |
168 | dtc |= drv_timings[mode] << dshift; | |
169 | ||
170 | cast &= ~(IDE_CAST_DRV_MASK << cshift); | |
171 | cast |= addr_timings[mode] << cshift; | |
172 | ||
173 | cast &= ~(IDE_CAST_CMD_MASK << IDE_CAST_CMD_SHIFT); | |
174 | cast |= cmd_timings[cmdmode] << IDE_CAST_CMD_SHIFT; | |
175 | ||
176 | etc &= ~(IDE_DRV_MASK << dshift); | |
177 | etc |= IDE_ETC_NODMA << dshift; | |
178 | ||
179 | cs5536_write(pdev, DTC, dtc); | |
180 | cs5536_write(pdev, CAST, cast); | |
181 | cs5536_write(pdev, ETC, etc); | |
182 | } | |
183 | ||
184 | /** | |
185 | * cs5536_set_dmamode - DMA timing setup | |
186 | * @ap: ATA interface | |
187 | * @adev: Device being configured | |
188 | * | |
189 | */ | |
190 | ||
191 | static void cs5536_set_dmamode(struct ata_port *ap, struct ata_device *adev) | |
192 | { | |
193 | static const u8 udma_timings[6] = { | |
194 | 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, | |
195 | }; | |
196 | ||
197 | static const u8 mwdma_timings[3] = { | |
198 | 0x67, 0x21, 0x20, | |
199 | }; | |
200 | ||
201 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
202 | u32 dtc, etc; | |
203 | int mode = adev->dma_mode; | |
b6966a61 | 204 | int dshift = adev->devno ? IDE_D1_SHIFT : IDE_D0_SHIFT; |
3957df61 MP |
205 | |
206 | if (mode >= XFER_UDMA_0) { | |
207 | cs5536_read(pdev, ETC, &etc); | |
208 | ||
209 | etc &= ~(IDE_DRV_MASK << dshift); | |
210 | etc |= udma_timings[mode - XFER_UDMA_0] << dshift; | |
211 | ||
212 | cs5536_write(pdev, ETC, etc); | |
213 | } else { /* MWDMA */ | |
214 | cs5536_read(pdev, DTC, &dtc); | |
215 | ||
216 | dtc &= ~(IDE_DRV_MASK << dshift); | |
80f6fd38 | 217 | dtc |= mwdma_timings[mode - XFER_MW_DMA_0] << dshift; |
3957df61 MP |
218 | |
219 | cs5536_write(pdev, DTC, dtc); | |
220 | } | |
221 | } | |
222 | ||
223 | static struct scsi_host_template cs5536_sht = { | |
68d1d07b | 224 | ATA_BMDMA_SHT(DRV_NAME), |
3957df61 MP |
225 | }; |
226 | ||
227 | static struct ata_port_operations cs5536_port_ops = { | |
029cfd6b TH |
228 | .inherits = &ata_bmdma_port_ops, |
229 | .cable_detect = cs5536_cable_detect, | |
3957df61 MP |
230 | .set_piomode = cs5536_set_piomode, |
231 | .set_dmamode = cs5536_set_dmamode, | |
3957df61 MP |
232 | }; |
233 | ||
234 | /** | |
235 | * cs5536_init_one | |
236 | * @dev: PCI device | |
237 | * @id: Entry in match table | |
238 | * | |
239 | */ | |
240 | ||
241 | static int cs5536_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
242 | { | |
243 | static const struct ata_port_info info = { | |
3957df61 MP |
244 | .flags = ATA_FLAG_SLAVE_POSS, |
245 | .pio_mask = 0x1f, | |
246 | .mwdma_mask = 0x07, | |
247 | .udma_mask = ATA_UDMA5, | |
248 | .port_ops = &cs5536_port_ops, | |
249 | }; | |
250 | ||
251 | const struct ata_port_info *ppi[] = { &info, &ata_dummy_port_info }; | |
252 | u32 cfg; | |
253 | ||
254 | if (use_msr) | |
255 | printk(KERN_ERR DRV_NAME ": Using MSR regs instead of PCI\n"); | |
256 | ||
257 | cs5536_read(dev, CFG, &cfg); | |
258 | ||
259 | if ((cfg & IDE_CFG_CHANEN) == 0) { | |
260 | printk(KERN_ERR DRV_NAME ": disabled by BIOS\n"); | |
261 | return -ENODEV; | |
262 | } | |
263 | ||
9363c382 | 264 | return ata_pci_sff_init_one(dev, ppi, &cs5536_sht, NULL); |
3957df61 MP |
265 | } |
266 | ||
267 | static const struct pci_device_id cs5536[] = { | |
268 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), }, | |
269 | { }, | |
270 | }; | |
271 | ||
272 | static struct pci_driver cs5536_pci_driver = { | |
273 | .name = DRV_NAME, | |
274 | .id_table = cs5536, | |
275 | .probe = cs5536_init_one, | |
276 | .remove = ata_pci_remove_one, | |
277 | #ifdef CONFIG_PM | |
278 | .suspend = ata_pci_device_suspend, | |
279 | .resume = ata_pci_device_resume, | |
280 | #endif | |
281 | }; | |
282 | ||
283 | static int __init cs5536_init(void) | |
284 | { | |
285 | return pci_register_driver(&cs5536_pci_driver); | |
286 | } | |
287 | ||
288 | static void __exit cs5536_exit(void) | |
289 | { | |
290 | pci_unregister_driver(&cs5536_pci_driver); | |
291 | } | |
292 | ||
293 | MODULE_AUTHOR("Martin K. Petersen"); | |
294 | MODULE_DESCRIPTION("low-level driver for the CS5536 IDE controller"); | |
295 | MODULE_LICENSE("GPL"); | |
296 | MODULE_DEVICE_TABLE(pci, cs5536); | |
297 | MODULE_VERSION(DRV_VERSION); | |
298 | module_param_named(msr, use_msr, int, 0644); | |
299 | MODULE_PARM_DESC(msr, "Force using MSR to configure IDE function (Default: 0)"); | |
300 | ||
301 | module_init(cs5536_init); | |
302 | module_exit(cs5536_exit); |