[linux-2.6-block.git] / drivers / ata / pata_cs5535.c

/*
 * pata-cs5535.c 	- CS5535 PATA for new ATA layer
 *			  (C) 2005-2006 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *
 * based upon cs5535.c from AMD <Jens.Altmann@amd.com> as cleaned up and
 * made readable and Linux style by Wolfgang Zuleger <wolfgang.zuleger@gmx.de
 * and Alexander Kiausch <alex.kiausch@t-online.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 * Loosely based on the piix & svwks drivers.
 *
 * Documentation:
 *	Available from AMD web site.
 * TODO
 *	Review errata to see if serializing is neccessary
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include <asm/msr.h>

#define DRV_NAME	"cs5535"
#define DRV_VERSION	"0.2.10"

/*
 *	The Geode (Aka Athlon GX now) uses an internal MSR based
 *	bus system for control. Demented but there you go.
 */

#define MSR_ATAC_BASE    	0x51300000
#define ATAC_GLD_MSR_CAP 	(MSR_ATAC_BASE+0)
#define ATAC_GLD_MSR_CONFIG    (MSR_ATAC_BASE+0x01)
#define ATAC_GLD_MSR_SMI       (MSR_ATAC_BASE+0x02)
#define ATAC_GLD_MSR_ERROR     (MSR_ATAC_BASE+0x03)
#define ATAC_GLD_MSR_PM        (MSR_ATAC_BASE+0x04)
#define ATAC_GLD_MSR_DIAG      (MSR_ATAC_BASE+0x05)
#define ATAC_IO_BAR            (MSR_ATAC_BASE+0x08)
#define ATAC_RESET             (MSR_ATAC_BASE+0x10)
#define ATAC_CH0D0_PIO         (MSR_ATAC_BASE+0x20)
#define ATAC_CH0D0_DMA         (MSR_ATAC_BASE+0x21)
#define ATAC_CH0D1_PIO         (MSR_ATAC_BASE+0x22)
#define ATAC_CH0D1_DMA         (MSR_ATAC_BASE+0x23)
#define ATAC_PCI_ABRTERR       (MSR_ATAC_BASE+0x24)

#define ATAC_BM0_CMD_PRIM      0x00
#define ATAC_BM0_STS_PRIM      0x02
#define ATAC_BM0_PRD           0x04

#define CS5535_CABLE_DETECT    0x48

#define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL)==0x00009172 )

/**
 *	cs5535_pre_reset	-	detect cable type
 *	@ap: Port to detect on
 *
 *	Perform cable detection for ATA66 capable cable. Return a libata
 *	cable type.
 */

static int cs5535_pre_reset(struct ata_port *ap)
{
	u8 cable;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	pci_read_config_byte(pdev, CS5535_CABLE_DETECT, &cable);
	if (cable & 1)
		ap->cbl = ATA_CBL_PATA80;
	else
		ap->cbl = ATA_CBL_PATA40;
	return ata_std_prereset(ap);
}

/**
 *	cs5535_error_handler		-	reset/probe
 *	@ap: Port to reset
 *
 *	Reset and configure a port
 */

static void cs5535_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, cs5535_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
}

/**
 *	cs5535_set_piomode		-	PIO setup
 *	@ap: ATA interface
 *	@adev: device on the interface
 *
 *	Set our PIO requirements. The CS5535 is pretty clean about all this
 */

static void cs5535_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	static const u16 pio_timings[5] = {
		0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131
	};
	static const u16 pio_cmd_timings[5] = {
		0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131
	};
	u32 reg, dummy;
	struct ata_device *pair = ata_dev_pair(adev);

	int mode = adev->pio_mode - XFER_PIO_0;
	int cmdmode = mode;

	/* Command timing has to be for the lowest of the pair of devices */
	if (pair) {
		int pairmode = pair->pio_mode - XFER_PIO_0;
		cmdmode = min(mode, pairmode);
		/* Write the other drive timing register if it changed */
		if (cmdmode < pairmode)
			wrmsr(ATAC_CH0D0_PIO + 2 * pair->devno,
				pio_cmd_timings[cmdmode] << 16 | pio_timings[pairmode], 0);
	}
	/* Write the drive timing register */
	wrmsr(ATAC_CH0D0_PIO + 2 * adev->devno,
		pio_cmd_timings[cmdmode] << 16 | pio_timings[mode], 0);

	/* Set the PIO "format 1" bit in the DMA timing register */
	rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
	wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg | 0x80000000UL, 0);
}

/**
 *	cs5535_set_dmamode		-	DMA timing setup
 *	@ap: ATA interface
 *	@adev: Device being configured
 *
 */

static void cs5535_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	static const u32 udma_timings[5] = {
		0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061
	};
	static const u32 mwdma_timings[3] = {
		0x7F0FFFF3, 0x7F035352, 0x7F024241
	};
	u32 reg, dummy;
	int mode = adev->dma_mode;

	rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
	reg &= 0x80000000UL;
	if (mode >= XFER_UDMA_0)
		reg |= udma_timings[mode - XFER_UDMA_0];
	else
		reg |= mwdma_timings[mode - XFER_MW_DMA_0];
	wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, 0);
}

static struct scsi_host_template cs5535_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.max_sectors		= ATA_MAX_SECTORS,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
};

static struct ata_port_operations cs5535_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= cs5535_set_piomode,
	.set_dmamode	= cs5535_set_dmamode,
	.mode_filter	= ata_pci_default_filter,

	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= cs5535_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_pio_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,

	.port_start	= ata_port_start,
	.port_stop	= ata_port_stop,
	.host_stop	= ata_host_stop
};

/**
 *	cs5535_init_one		-	Initialise a CS5530
 *	@dev: PCI device
 *	@id: Entry in match table
 *
 *	Install a driver for the newly found CS5530 companion chip. Most of
 *	this is just housekeeping. We have to set the chip up correctly and
 *	turn off various bits of emulation magic.
 */

static int cs5535_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	static struct ata_port_info info = {
		.sht = &cs5535_sht,
		.flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = 0x1f,
		.port_ops = &cs5535_port_ops
	};
	struct ata_port_info *ports[1] = { &info };

	u32 timings, dummy;

	/* Check the BIOS set the initial timing clock. If not set the
	   timings for PIO0 */
	rdmsr(ATAC_CH0D0_PIO, timings, dummy);
	if (CS5535_BAD_PIO(timings))
		wrmsr(ATAC_CH0D0_PIO, 0xF7F4F7F4UL, 0);
	rdmsr(ATAC_CH0D1_PIO, timings, dummy);
	if (CS5535_BAD_PIO(timings))
		wrmsr(ATAC_CH0D1_PIO, 0xF7F4F7F4UL, 0);
	return ata_pci_init_one(dev, ports, 1);
}

static const struct pci_device_id cs5535[] = {
	{ PCI_VDEVICE(NS, 0x002D), },

	{ },
};

static struct pci_driver cs5535_pci_driver = {
	.name		= DRV_NAME,
	.id_table	= cs5535,
	.probe 		= cs5535_init_one,
	.remove		= ata_pci_remove_one
};

static int __init cs5535_init(void)
{
	return pci_register_driver(&cs5535_pci_driver);
}

static void __exit cs5535_exit(void)
{
	pci_unregister_driver(&cs5535_pci_driver);
}

MODULE_AUTHOR("Alan Cox, Jens Altmann, Wolfgan Zuleger, Alexander Kiausch");
MODULE_DESCRIPTION("low-level driver for the NS/AMD 5530");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, cs5535);
MODULE_VERSION(DRV_VERSION);

module_init(cs5535_init);
module_exit(cs5535_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata-cs5535.c - CS5535 PATA for new ATA layer
	3	* (C) 2005-2006 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
	5	*
	6	* based upon cs5535.c from AMD <Jens.Altmann@amd.com> as cleaned up and
	7	* made readable and Linux style by Wolfgang Zuleger <wolfgang.zuleger@gmx.de
	8	* and Alexander Kiausch <alex.kiausch@t-online.de>
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* Loosely based on the piix & svwks drivers.
	24	*
	25	* Documentation:
	26	* Available from AMD web site.
	27	* TODO
	28	* Review errata to see if serializing is neccessary
	29	*/
	30
	31	#include <linux/kernel.h>
	32	#include <linux/module.h>
	33	#include <linux/pci.h>
	34	#include <linux/init.h>
	35	#include <linux/blkdev.h>
	36	#include <linux/delay.h>
	37	#include <scsi/scsi_host.h>
	38	#include <linux/libata.h>
	39	#include <asm/msr.h>
	40
	41	#define DRV_NAME "cs5535"
	42	#define DRV_VERSION "0.2.10"
	43
	44	/*
	45	* The Geode (Aka Athlon GX now) uses an internal MSR based
	46	* bus system for control. Demented but there you go.
	47	*/
	48
	49	#define MSR_ATAC_BASE 0x51300000
	50	#define ATAC_GLD_MSR_CAP (MSR_ATAC_BASE+0)
	51	#define ATAC_GLD_MSR_CONFIG (MSR_ATAC_BASE+0x01)
	52	#define ATAC_GLD_MSR_SMI (MSR_ATAC_BASE+0x02)
	53	#define ATAC_GLD_MSR_ERROR (MSR_ATAC_BASE+0x03)
	54	#define ATAC_GLD_MSR_PM (MSR_ATAC_BASE+0x04)
	55	#define ATAC_GLD_MSR_DIAG (MSR_ATAC_BASE+0x05)
	56	#define ATAC_IO_BAR (MSR_ATAC_BASE+0x08)
	57	#define ATAC_RESET (MSR_ATAC_BASE+0x10)
	58	#define ATAC_CH0D0_PIO (MSR_ATAC_BASE+0x20)
	59	#define ATAC_CH0D0_DMA (MSR_ATAC_BASE+0x21)
	60	#define ATAC_CH0D1_PIO (MSR_ATAC_BASE+0x22)
	61	#define ATAC_CH0D1_DMA (MSR_ATAC_BASE+0x23)
	62	#define ATAC_PCI_ABRTERR (MSR_ATAC_BASE+0x24)
	63
	64	#define ATAC_BM0_CMD_PRIM 0x00
65	#define ATAC_BM0_STS_PRIM 0x02
66	#define ATAC_BM0_PRD 0x04
67
68	#define CS5535_CABLE_DETECT 0x48
69
70	#define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL)==0x00009172 )
71
72	/**
73	* cs5535_pre_reset - detect cable type
74	* @ap: Port to detect on
75	*
76	* Perform cable detection for ATA66 capable cable. Return a libata
77	* cable type.
78	*/
79
80	static int cs5535_pre_reset(struct ata_port *ap)
81	{
82	u8 cable;
83	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
84
85	pci_read_config_byte(pdev, CS5535_CABLE_DETECT, &cable);
86	if (cable & 1)
87	ap->cbl = ATA_CBL_PATA80;
88	else
89	ap->cbl = ATA_CBL_PATA40;
90	return ata_std_prereset(ap);
91	}
92
93	/**
94	* cs5535_error_handler - reset/probe
95	* @ap: Port to reset
96	*
97	* Reset and configure a port
98	*/
99
100	static void cs5535_error_handler(struct ata_port *ap)
101	{
102	ata_bmdma_drive_eh(ap, cs5535_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
103	}
104
105	/**
106	* cs5535_set_piomode - PIO setup
107	* @ap: ATA interface
108	* @adev: device on the interface
109	*
110	* Set our PIO requirements. The CS5535 is pretty clean about all this
111	*/
112
113	static void cs5535_set_piomode(struct ata_port ap, struct ata_device adev)
114	{
115	static const u16 pio_timings[5] = {
116	0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131
117	};
118	static const u16 pio_cmd_timings[5] = {
119	0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131
120	};
121	u32 reg, dummy;
122	struct ata_device *pair = ata_dev_pair(adev);
123
124	int mode = adev->pio_mode - XFER_PIO_0;
125	int cmdmode = mode;
126
127	/* Command timing has to be for the lowest of the pair of devices */
128	if (pair) {
129	int pairmode = pair->pio_mode - XFER_PIO_0;
130	cmdmode = min(mode, pairmode);
131	/* Write the other drive timing register if it changed */
132	if (cmdmode < pairmode)
133	wrmsr(ATAC_CH0D0_PIO + 2 * pair->devno,
134	pio_cmd_timings[cmdmode] << 16 \| pio_timings[pairmode], 0);
135	}
136	/* Write the drive timing register */
137	wrmsr(ATAC_CH0D0_PIO + 2 * adev->devno,
138	pio_cmd_timings[cmdmode] << 16 \| pio_timings[mode], 0);
139
140	/* Set the PIO "format 1" bit in the DMA timing register */
141	rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
142	wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg \| 0x80000000UL, 0);
143	}
144
145	/**
146	* cs5535_set_dmamode - DMA timing setup
147	* @ap: ATA interface
148	* @adev: Device being configured
149	*
150	*/
151
152	static void cs5535_set_dmamode(struct ata_port ap, struct ata_device adev)
153	{
154	static const u32 udma_timings[5] = {
155	0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061
156	};
157	static const u32 mwdma_timings[3] = {
158	0x7F0FFFF3, 0x7F035352, 0x7F024241
159	};
160	u32 reg, dummy;
161	int mode = adev->dma_mode;
162
163	rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
164	reg &= 0x80000000UL;
165	if (mode >= XFER_UDMA_0)
166	reg \|= udma_timings[mode - XFER_UDMA_0];
167	else
168	reg \|= mwdma_timings[mode - XFER_MW_DMA_0];
169	wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, 0);
170	}
171
172	static struct scsi_host_template cs5535_sht = {
173	.module = THIS_MODULE,
174	.name = DRV_NAME,
175	.ioctl = ata_scsi_ioctl,
176	.queuecommand = ata_scsi_queuecmd,
177	.can_queue = ATA_DEF_QUEUE,
178	.this_id = ATA_SHT_THIS_ID,
179	.sg_tablesize = LIBATA_MAX_PRD,
180	.max_sectors = ATA_MAX_SECTORS,
181	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
182	.emulated = ATA_SHT_EMULATED,
183	.use_clustering = ATA_SHT_USE_CLUSTERING,
184	.proc_name = DRV_NAME,
185	.dma_boundary = ATA_DMA_BOUNDARY,
186	.slave_configure = ata_scsi_slave_config,
afdfe899	187	.slave_destroy = ata_scsi_slave_destroy,
669a5db4 JG	188	.bios_param = ata_std_bios_param,
	189	};
	190
	191	static struct ata_port_operations cs5535_port_ops = {
	192	.port_disable = ata_port_disable,
	193	.set_piomode = cs5535_set_piomode,
	194	.set_dmamode = cs5535_set_dmamode,
	195	.mode_filter = ata_pci_default_filter,
	196
	197	.tf_load = ata_tf_load,
	198	.tf_read = ata_tf_read,
	199	.check_status = ata_check_status,
	200	.exec_command = ata_exec_command,
	201	.dev_select = ata_std_dev_select,
	202
	203	.freeze = ata_bmdma_freeze,
	204	.thaw = ata_bmdma_thaw,
	205	.error_handler = cs5535_error_handler,
	206	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	207
	208	.bmdma_setup = ata_bmdma_setup,
	209	.bmdma_start = ata_bmdma_start,
	210	.bmdma_stop = ata_bmdma_stop,
	211	.bmdma_status = ata_bmdma_status,
	212
	213	.qc_prep = ata_qc_prep,
	214	.qc_issue = ata_qc_issue_prot,
bda30288	215
669a5db4 JG	216	.data_xfer = ata_pio_data_xfer,
	217
	218	.irq_handler = ata_interrupt,
	219	.irq_clear = ata_bmdma_irq_clear,
	220
	221	.port_start = ata_port_start,
	222	.port_stop = ata_port_stop,
	223	.host_stop = ata_host_stop
	224	};
	225
	226	/**
	227	* cs5535_init_one - Initialise a CS5530
	228	* @dev: PCI device
	229	* @id: Entry in match table
	230	*
	231	* Install a driver for the newly found CS5530 companion chip. Most of
	232	* this is just housekeeping. We have to set the chip up correctly and
	233	* turn off various bits of emulation magic.
	234	*/
	235
	236	static int cs5535_init_one(struct pci_dev dev, const struct pci_device_id id)
	237	{
	238	static struct ata_port_info info = {
	239	.sht = &cs5535_sht,
	240	.flags = ATA_FLAG_SLAVE_POSS\|ATA_FLAG_SRST,
	241	.pio_mask = 0x1f,
	242	.mwdma_mask = 0x07,
	243	.udma_mask = 0x1f,
	244	.port_ops = &cs5535_port_ops
	245	};
	246	struct ata_port_info *ports[1] = { &info };
	247
	248	u32 timings, dummy;
	249
	250	/* Check the BIOS set the initial timing clock. If not set the
	251	timings for PIO0 */
	252	rdmsr(ATAC_CH0D0_PIO, timings, dummy);
	253	if (CS5535_BAD_PIO(timings))
	254	wrmsr(ATAC_CH0D0_PIO, 0xF7F4F7F4UL, 0);
	255	rdmsr(ATAC_CH0D1_PIO, timings, dummy);
	256	if (CS5535_BAD_PIO(timings))
	257	wrmsr(ATAC_CH0D1_PIO, 0xF7F4F7F4UL, 0);
	258	return ata_pci_init_one(dev, ports, 1);
	259	}
	260
2d2744fc JG	261	static const struct pci_device_id cs5535[] = {
	262	{ PCI_VDEVICE(NS, 0x002D), },
	263
	264	{ },
669a5db4 JG	265	};
	266
	267	static struct pci_driver cs5535_pci_driver = {
	268	.name = DRV_NAME,
	269	.id_table = cs5535,
	270	.probe = cs5535_init_one,
	271	.remove = ata_pci_remove_one
	272	};
	273
	274	static int __init cs5535_init(void)
	275	{
	276	return pci_register_driver(&cs5535_pci_driver);
	277	}
	278
669a5db4 JG	279	static void __exit cs5535_exit(void)
	280	{
	281	pci_unregister_driver(&cs5535_pci_driver);
	282	}
	283
669a5db4 JG	284	MODULE_AUTHOR("Alan Cox, Jens Altmann, Wolfgan Zuleger, Alexander Kiausch");
	285	MODULE_DESCRIPTION("low-level driver for the NS/AMD 5530");
	286	MODULE_LICENSE("GPL");
	287	MODULE_DEVICE_TABLE(pci, cs5535);
	288	MODULE_VERSION(DRV_VERSION);
	289
	290	module_init(cs5535_init);
	291	module_exit(cs5535_exit);