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669a5db4 JG |
1 | /* |
2 | * IDE tuning and bus mastering support for the CS5510/CS5520 | |
3 | * chipsets | |
4 | * | |
5 | * The CS5510/CS5520 are slightly unusual devices. Unlike the | |
6 | * typical IDE controllers they do bus mastering with the drive in | |
7 | * PIO mode and smarter silicon. | |
8 | * | |
9 | * The practical upshot of this is that we must always tune the | |
10 | * drive for the right PIO mode. We must also ignore all the blacklists | |
11 | * and the drive bus mastering DMA information. Also to confuse matters | |
12 | * further we can do DMA on PIO only drives. | |
13 | * | |
14 | * DMA on the 5510 also requires we disable_hlt() during DMA on early | |
15 | * revisions. | |
16 | * | |
17 | * *** This driver is strictly experimental *** | |
18 | * | |
19 | * (c) Copyright Red Hat Inc 2002 | |
20 | * | |
21 | * This program is free software; you can redistribute it and/or modify it | |
22 | * under the terms of the GNU General Public License as published by the | |
23 | * Free Software Foundation; either version 2, or (at your option) any | |
24 | * later version. | |
25 | * | |
26 | * This program is distributed in the hope that it will be useful, but | |
27 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
28 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
29 | * General Public License for more details. | |
30 | * | |
31 | * Documentation: | |
32 | * Not publically available. | |
33 | */ | |
34 | #include <linux/kernel.h> | |
35 | #include <linux/module.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/blkdev.h> | |
39 | #include <linux/delay.h> | |
40 | #include <scsi/scsi_host.h> | |
41 | #include <linux/libata.h> | |
42 | ||
43 | #define DRV_NAME "pata_cs5520" | |
2a3103ce | 44 | #define DRV_VERSION "0.6.6" |
669a5db4 JG |
45 | |
46 | struct pio_clocks | |
47 | { | |
48 | int address; | |
49 | int assert; | |
50 | int recovery; | |
51 | }; | |
52 | ||
53 | static const struct pio_clocks cs5520_pio_clocks[]={ | |
54 | {3, 6, 11}, | |
55 | {2, 5, 6}, | |
56 | {1, 4, 3}, | |
57 | {1, 3, 2}, | |
58 | {1, 2, 1} | |
59 | }; | |
60 | ||
61 | /** | |
62 | * cs5520_set_timings - program PIO timings | |
63 | * @ap: ATA port | |
64 | * @adev: ATA device | |
65 | * | |
66 | * Program the PIO mode timings for the controller according to the pio | |
67 | * clocking table. | |
68 | */ | |
69 | ||
70 | static void cs5520_set_timings(struct ata_port *ap, struct ata_device *adev, int pio) | |
71 | { | |
72 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
73 | int slave = adev->devno; | |
74 | ||
75 | pio -= XFER_PIO_0; | |
76 | ||
77 | /* Channel command timing */ | |
78 | pci_write_config_byte(pdev, 0x62 + ap->port_no, | |
79 | (cs5520_pio_clocks[pio].recovery << 4) | | |
80 | (cs5520_pio_clocks[pio].assert)); | |
81 | /* FIXME: should these use address ? */ | |
82 | /* Read command timing */ | |
83 | pci_write_config_byte(pdev, 0x64 + 4*ap->port_no + slave, | |
84 | (cs5520_pio_clocks[pio].recovery << 4) | | |
85 | (cs5520_pio_clocks[pio].assert)); | |
86 | /* Write command timing */ | |
87 | pci_write_config_byte(pdev, 0x66 + 4*ap->port_no + slave, | |
88 | (cs5520_pio_clocks[pio].recovery << 4) | | |
89 | (cs5520_pio_clocks[pio].assert)); | |
90 | } | |
91 | ||
92 | /** | |
93 | * cs5520_enable_dma - turn on DMA bits | |
94 | * | |
95 | * Turn on the DMA bits for this disk. Needed because the BIOS probably | |
96 | * has not done the work for us. Belongs in the core SATA code. | |
97 | */ | |
98 | ||
99 | static void cs5520_enable_dma(struct ata_port *ap, struct ata_device *adev) | |
100 | { | |
101 | /* Set the DMA enable/disable flag */ | |
0d5ff566 | 102 | u8 reg = ioread8(ap->ioaddr.bmdma_addr + 0x02); |
669a5db4 | 103 | reg |= 1<<(adev->devno + 5); |
0d5ff566 | 104 | iowrite8(reg, ap->ioaddr.bmdma_addr + 0x02); |
669a5db4 JG |
105 | } |
106 | ||
107 | /** | |
108 | * cs5520_set_dmamode - program DMA timings | |
109 | * @ap: ATA port | |
110 | * @adev: ATA device | |
111 | * | |
112 | * Program the DMA mode timings for the controller according to the pio | |
113 | * clocking table. Note that this device sets the DMA timings to PIO | |
114 | * mode values. This may seem bizarre but the 5520 architecture talks | |
115 | * PIO mode to the disk and DMA mode to the controller so the underlying | |
116 | * transfers are PIO timed. | |
117 | */ | |
118 | ||
119 | static void cs5520_set_dmamode(struct ata_port *ap, struct ata_device *adev) | |
120 | { | |
121 | static const int dma_xlate[3] = { XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 }; | |
122 | cs5520_set_timings(ap, adev, dma_xlate[adev->dma_mode]); | |
123 | cs5520_enable_dma(ap, adev); | |
124 | } | |
125 | ||
126 | /** | |
127 | * cs5520_set_piomode - program PIO timings | |
128 | * @ap: ATA port | |
129 | * @adev: ATA device | |
130 | * | |
131 | * Program the PIO mode timings for the controller according to the pio | |
132 | * clocking table. We know pio_mode will equal dma_mode because of the | |
133 | * CS5520 architecture. At least once we turned DMA on and wrote a | |
134 | * mode setter. | |
135 | */ | |
136 | ||
137 | static void cs5520_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
138 | { | |
139 | cs5520_set_timings(ap, adev, adev->pio_mode); | |
140 | } | |
141 | ||
669a5db4 JG |
142 | static struct scsi_host_template cs5520_sht = { |
143 | .module = THIS_MODULE, | |
144 | .name = DRV_NAME, | |
145 | .ioctl = ata_scsi_ioctl, | |
146 | .queuecommand = ata_scsi_queuecmd, | |
147 | .can_queue = ATA_DEF_QUEUE, | |
148 | .this_id = ATA_SHT_THIS_ID, | |
d26fc955 | 149 | .sg_tablesize = LIBATA_DUMB_MAX_PRD, |
669a5db4 JG |
150 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
151 | .emulated = ATA_SHT_EMULATED, | |
152 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
153 | .proc_name = DRV_NAME, | |
154 | .dma_boundary = ATA_DMA_BOUNDARY, | |
155 | .slave_configure = ata_scsi_slave_config, | |
afdfe899 | 156 | .slave_destroy = ata_scsi_slave_destroy, |
669a5db4 JG |
157 | .bios_param = ata_std_bios_param, |
158 | }; | |
159 | ||
160 | static struct ata_port_operations cs5520_port_ops = { | |
669a5db4 JG |
161 | .set_piomode = cs5520_set_piomode, |
162 | .set_dmamode = cs5520_set_dmamode, | |
6bd99b4e | 163 | .mode_filter = ata_pci_default_filter, |
669a5db4 JG |
164 | |
165 | .tf_load = ata_tf_load, | |
166 | .tf_read = ata_tf_read, | |
167 | .check_status = ata_check_status, | |
168 | .exec_command = ata_exec_command, | |
169 | .dev_select = ata_std_dev_select, | |
170 | ||
171 | .freeze = ata_bmdma_freeze, | |
172 | .thaw = ata_bmdma_thaw, | |
a73984a0 | 173 | .error_handler = ata_bmdma_error_handler, |
669a5db4 | 174 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
a73984a0 | 175 | .cable_detect = ata_cable_40wire, |
669a5db4 JG |
176 | |
177 | .bmdma_setup = ata_bmdma_setup, | |
178 | .bmdma_start = ata_bmdma_start, | |
179 | .bmdma_stop = ata_bmdma_stop, | |
180 | .bmdma_status = ata_bmdma_status, | |
d26fc955 | 181 | .qc_prep = ata_dumb_qc_prep, |
669a5db4 | 182 | .qc_issue = ata_qc_issue_prot, |
0d5ff566 | 183 | .data_xfer = ata_data_xfer, |
669a5db4 | 184 | |
669a5db4 | 185 | .irq_clear = ata_bmdma_irq_clear, |
246ce3b6 | 186 | .irq_on = ata_irq_on, |
669a5db4 | 187 | |
81ad1837 | 188 | .port_start = ata_sff_port_start, |
669a5db4 JG |
189 | }; |
190 | ||
5d728824 | 191 | static int __devinit cs5520_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
669a5db4 | 192 | { |
cbcdd875 TH |
193 | static const unsigned int cmd_port[] = { 0x1F0, 0x170 }; |
194 | static const unsigned int ctl_port[] = { 0x3F6, 0x376 }; | |
5d728824 TH |
195 | struct ata_port_info pi = { |
196 | .flags = ATA_FLAG_SLAVE_POSS, | |
197 | .pio_mask = 0x1f, | |
198 | .port_ops = &cs5520_port_ops, | |
199 | }; | |
200 | const struct ata_port_info *ppi[2]; | |
669a5db4 | 201 | u8 pcicfg; |
4ca4e439 | 202 | void __iomem *iomap[5]; |
5d728824 TH |
203 | struct ata_host *host; |
204 | struct ata_ioports *ioaddr; | |
205 | int i, rc; | |
669a5db4 | 206 | |
f08048e9 TH |
207 | rc = pcim_enable_device(pdev); |
208 | if (rc) | |
209 | return rc; | |
210 | ||
669a5db4 | 211 | /* IDE port enable bits */ |
5d728824 | 212 | pci_read_config_byte(pdev, 0x60, &pcicfg); |
669a5db4 JG |
213 | |
214 | /* Check if the ATA ports are enabled */ | |
215 | if ((pcicfg & 3) == 0) | |
216 | return -ENODEV; | |
217 | ||
5d728824 TH |
218 | ppi[0] = ppi[1] = &ata_dummy_port_info; |
219 | if (pcicfg & 1) | |
220 | ppi[0] = π | |
221 | if (pcicfg & 2) | |
222 | ppi[1] = π | |
223 | ||
669a5db4 | 224 | if ((pcicfg & 0x40) == 0) { |
5d728824 TH |
225 | dev_printk(KERN_WARNING, &pdev->dev, |
226 | "DMA mode disabled. Enabling.\n"); | |
227 | pci_write_config_byte(pdev, 0x60, pcicfg | 0x40); | |
669a5db4 JG |
228 | } |
229 | ||
5d728824 TH |
230 | pi.mwdma_mask = id->driver_data; |
231 | ||
232 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); | |
233 | if (!host) | |
234 | return -ENOMEM; | |
235 | ||
669a5db4 | 236 | /* Perform set up for DMA */ |
09483916 | 237 | if (pci_enable_device_io(pdev)) { |
669a5db4 JG |
238 | printk(KERN_ERR DRV_NAME ": unable to configure BAR2.\n"); |
239 | return -ENODEV; | |
240 | } | |
5d728824 TH |
241 | |
242 | if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) { | |
669a5db4 JG |
243 | printk(KERN_ERR DRV_NAME ": unable to configure DMA mask.\n"); |
244 | return -ENODEV; | |
245 | } | |
5d728824 | 246 | if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) { |
669a5db4 JG |
247 | printk(KERN_ERR DRV_NAME ": unable to configure consistent DMA mask.\n"); |
248 | return -ENODEV; | |
249 | } | |
250 | ||
5d728824 | 251 | /* Map IO ports and initialize host accordingly */ |
cbcdd875 TH |
252 | iomap[0] = devm_ioport_map(&pdev->dev, cmd_port[0], 8); |
253 | iomap[1] = devm_ioport_map(&pdev->dev, ctl_port[0], 1); | |
254 | iomap[2] = devm_ioport_map(&pdev->dev, cmd_port[1], 8); | |
255 | iomap[3] = devm_ioport_map(&pdev->dev, ctl_port[1], 1); | |
5d728824 | 256 | iomap[4] = pcim_iomap(pdev, 2, 0); |
0d5ff566 TH |
257 | |
258 | if (!iomap[0] || !iomap[1] || !iomap[2] || !iomap[3] || !iomap[4]) | |
259 | return -ENOMEM; | |
260 | ||
5d728824 TH |
261 | ioaddr = &host->ports[0]->ioaddr; |
262 | ioaddr->cmd_addr = iomap[0]; | |
263 | ioaddr->ctl_addr = iomap[1]; | |
264 | ioaddr->altstatus_addr = iomap[1]; | |
265 | ioaddr->bmdma_addr = iomap[4]; | |
266 | ata_std_ports(ioaddr); | |
267 | ||
cbcdd875 TH |
268 | ata_port_desc(host->ports[0], |
269 | "cmd 0x%x ctl 0x%x", cmd_port[0], ctl_port[0]); | |
270 | ata_port_pbar_desc(host->ports[0], 4, 0, "bmdma"); | |
271 | ||
5d728824 TH |
272 | ioaddr = &host->ports[1]->ioaddr; |
273 | ioaddr->cmd_addr = iomap[2]; | |
274 | ioaddr->ctl_addr = iomap[3]; | |
275 | ioaddr->altstatus_addr = iomap[3]; | |
276 | ioaddr->bmdma_addr = iomap[4] + 8; | |
277 | ata_std_ports(ioaddr); | |
278 | ||
cbcdd875 TH |
279 | ata_port_desc(host->ports[1], |
280 | "cmd 0x%x ctl 0x%x", cmd_port[1], ctl_port[1]); | |
281 | ata_port_pbar_desc(host->ports[1], 4, 8, "bmdma"); | |
282 | ||
5d728824 TH |
283 | /* activate the host */ |
284 | pci_set_master(pdev); | |
285 | rc = ata_host_start(host); | |
286 | if (rc) | |
287 | return rc; | |
288 | ||
289 | for (i = 0; i < 2; i++) { | |
290 | static const int irq[] = { 14, 15 }; | |
8c6b065b | 291 | struct ata_port *ap = host->ports[i]; |
5d728824 TH |
292 | |
293 | if (ata_port_is_dummy(ap)) | |
294 | continue; | |
295 | ||
296 | rc = devm_request_irq(&pdev->dev, irq[ap->port_no], | |
297 | ata_interrupt, 0, DRV_NAME, host); | |
298 | if (rc) | |
299 | return rc; | |
4031826b | 300 | |
cbcdd875 | 301 | ata_port_desc(ap, "irq %d", irq[i]); |
5d728824 TH |
302 | } |
303 | ||
304 | return ata_host_register(host, &cs5520_sht); | |
669a5db4 JG |
305 | } |
306 | ||
438ac6d5 | 307 | #ifdef CONFIG_PM |
8501120f A |
308 | /** |
309 | * cs5520_reinit_one - device resume | |
310 | * @pdev: PCI device | |
311 | * | |
312 | * Do any reconfiguration work needed by a resume from RAM. We need | |
313 | * to restore DMA mode support on BIOSen which disabled it | |
314 | */ | |
f20b16ff | 315 | |
8501120f A |
316 | static int cs5520_reinit_one(struct pci_dev *pdev) |
317 | { | |
f08048e9 | 318 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
8501120f | 319 | u8 pcicfg; |
f08048e9 TH |
320 | int rc; |
321 | ||
322 | rc = ata_pci_device_do_resume(pdev); | |
323 | if (rc) | |
324 | return rc; | |
325 | ||
8501120f A |
326 | pci_read_config_byte(pdev, 0x60, &pcicfg); |
327 | if ((pcicfg & 0x40) == 0) | |
328 | pci_write_config_byte(pdev, 0x60, pcicfg | 0x40); | |
f08048e9 TH |
329 | |
330 | ata_host_resume(host); | |
331 | return 0; | |
8501120f | 332 | } |
aa6de494 A |
333 | |
334 | /** | |
335 | * cs5520_pci_device_suspend - device suspend | |
336 | * @pdev: PCI device | |
337 | * | |
338 | * We have to cut and waste bits from the standard method because | |
339 | * the 5520 is a bit odd and not just a pure ATA device. As a result | |
340 | * we must not disable it. The needed code is short and this avoids | |
341 | * chip specific mess in the core code. | |
342 | */ | |
343 | ||
344 | static int cs5520_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) | |
345 | { | |
346 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
347 | int rc = 0; | |
348 | ||
349 | rc = ata_host_suspend(host, mesg); | |
350 | if (rc) | |
351 | return rc; | |
352 | ||
353 | pci_save_state(pdev); | |
354 | return 0; | |
355 | } | |
438ac6d5 | 356 | #endif /* CONFIG_PM */ |
a84471fe | 357 | |
669a5db4 JG |
358 | /* For now keep DMA off. We can set it for all but A rev CS5510 once the |
359 | core ATA code can handle it */ | |
360 | ||
2d2744fc JG |
361 | static const struct pci_device_id pata_cs5520[] = { |
362 | { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), }, | |
363 | { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), }, | |
364 | ||
365 | { }, | |
669a5db4 JG |
366 | }; |
367 | ||
368 | static struct pci_driver cs5520_pci_driver = { | |
369 | .name = DRV_NAME, | |
370 | .id_table = pata_cs5520, | |
371 | .probe = cs5520_init_one, | |
2855568b | 372 | .remove = ata_pci_remove_one, |
438ac6d5 | 373 | #ifdef CONFIG_PM |
aa6de494 | 374 | .suspend = cs5520_pci_device_suspend, |
8501120f | 375 | .resume = cs5520_reinit_one, |
438ac6d5 | 376 | #endif |
669a5db4 JG |
377 | }; |
378 | ||
669a5db4 JG |
379 | static int __init cs5520_init(void) |
380 | { | |
381 | return pci_register_driver(&cs5520_pci_driver); | |
382 | } | |
383 | ||
384 | static void __exit cs5520_exit(void) | |
385 | { | |
386 | pci_unregister_driver(&cs5520_pci_driver); | |
387 | } | |
388 | ||
389 | MODULE_AUTHOR("Alan Cox"); | |
390 | MODULE_DESCRIPTION("low-level driver for Cyrix CS5510/5520"); | |
391 | MODULE_LICENSE("GPL"); | |
392 | MODULE_DEVICE_TABLE(pci, pata_cs5520); | |
393 | MODULE_VERSION(DRV_VERSION); | |
394 | ||
395 | module_init(cs5520_init); | |
396 | module_exit(cs5520_exit); | |
397 |