[linux-2.6-block.git] / drivers / ata / pata_cmd64x.c

/*
 * pata_cmd64x.c 	- CMD64x PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  Alan Cox <alan@lxorguk.ukuu.org.uk>
 *			  (C) 2009-2010 Bartlomiej Zolnierkiewicz
 *
 * Based upon
 * linux/drivers/ide/pci/cmd64x.c		Version 1.30	Sept 10, 2002
 *
 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
 *           Note, this driver is not used at all on other systems because
 *           there the "BIOS" has done all of the following already.
 *           Due to massive hardware bugs, UltraDMA is only supported
 *           on the 646U2 and not on the 646U.
 *
 * Copyright (C) 1998		Eddie C. Dost  (ecd@skynet.be)
 * Copyright (C) 1998		David S. Miller (davem@redhat.com)
 *
 * Copyright (C) 1999-2002	Andre Hedrick <andre@linux-ide.org>
 *
 * TODO
 *	Testing work
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_cmd64x"
#define DRV_VERSION "0.2.5"

/*
 * CMD64x specific registers definition.
 */

enum {
	CFR 		= 0x50,
		CFR_INTR_CH0  = 0x04,
	CNTRL		= 0x51,
		CNTRL_CH0     = 0x04,
		CNTRL_CH1     = 0x08,
	CMDTIM 		= 0x52,
	ARTTIM0 	= 0x53,
	DRWTIM0 	= 0x54,
	ARTTIM1 	= 0x55,
	DRWTIM1 	= 0x56,
	ARTTIM23 	= 0x57,
		ARTTIM23_DIS_RA2  = 0x04,
		ARTTIM23_DIS_RA3  = 0x08,
		ARTTIM23_INTR_CH1 = 0x10,
	DRWTIM2 	= 0x58,
	BRST 		= 0x59,
	DRWTIM3 	= 0x5b,
	BMIDECR0	= 0x70,
	MRDMODE		= 0x71,
		MRDMODE_INTR_CH0 = 0x04,
		MRDMODE_INTR_CH1 = 0x08,
	BMIDESR0	= 0x72,
	UDIDETCR0	= 0x73,
	DTPR0		= 0x74,
	BMIDECR1	= 0x78,
	BMIDECSR	= 0x79,
	UDIDETCR1	= 0x7B,
	DTPR1		= 0x7C
};

static int cmd648_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 r;

	/* Check cable detect bits */
	pci_read_config_byte(pdev, BMIDECSR, &r);
	if (r & (1 << ap->port_no))
		return ATA_CBL_PATA80;
	return ATA_CBL_PATA40;
}

/**
 *	cmd64x_set_piomode	-	set PIO and MWDMA timing
 *	@ap: ATA interface
 *	@adev: ATA device
 *	@mode: mode
 *
 *	Called to do the PIO and MWDMA mode setup.
 */

static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 mode)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	struct ata_timing t;
	const unsigned long T = 1000000 / 33;
	const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };

	u8 reg;

	/* Port layout is not logical so use a table */
	const u8 arttim_port[2][2] = {
		{ ARTTIM0, ARTTIM1 },
		{ ARTTIM23, ARTTIM23 }
	};
	const u8 drwtim_port[2][2] = {
		{ DRWTIM0, DRWTIM1 },
		{ DRWTIM2, DRWTIM3 }
	};

	int arttim = arttim_port[ap->port_no][adev->devno];
	int drwtim = drwtim_port[ap->port_no][adev->devno];

	/* ata_timing_compute is smart and will produce timings for MWDMA
	   that don't violate the drives PIO capabilities. */
	if (ata_timing_compute(adev, mode, &t, T, 0) < 0) {
		printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
		return;
	}
	if (ap->port_no) {
		/* Slave has shared address setup */
		struct ata_device *pair = ata_dev_pair(adev);

		if (pair) {
			struct ata_timing tp;
			ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
			ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
		}
	}

	printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
		t.active, t.recover, t.setup);
	if (t.recover > 16) {
		t.active += t.recover - 16;
		t.recover = 16;
	}
	if (t.active > 16)
		t.active = 16;

	/* Now convert the clocks into values we can actually stuff into
	   the chip */

	if (t.recover == 16)
		t.recover = 0;
	else if (t.recover > 1)
		t.recover--;
	else
		t.recover = 15;

	if (t.setup > 4)
		t.setup = 0xC0;
	else
		t.setup = setup_data[t.setup];

	t.active &= 0x0F;	/* 0 = 16 */

	/* Load setup timing */
	pci_read_config_byte(pdev, arttim, &reg);
	reg &= 0x3F;
	reg |= t.setup;
	pci_write_config_byte(pdev, arttim, reg);

	/* Load active/recovery */
	pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover);
}

/**
 *	cmd64x_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Used when configuring the devices ot set the PIO timings. All the
 *	actual work is done by the PIO/MWDMA setting helper
 */

static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	cmd64x_set_timing(ap, adev, adev->pio_mode);
}

/**
 *	cmd64x_set_dmamode	-	set initial DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the DMA mode setup.
 */

static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	static const u8 udma_data[] = {
		0x30, 0x20, 0x10, 0x20, 0x10, 0x00
	};

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 regU, regD;

	int pciU = UDIDETCR0 + 8 * ap->port_no;
	int pciD = BMIDESR0 + 8 * ap->port_no;
	int shift = 2 * adev->devno;

	pci_read_config_byte(pdev, pciD, &regD);
	pci_read_config_byte(pdev, pciU, &regU);

	/* DMA bits off */
	regD &= ~(0x20 << adev->devno);
	/* DMA control bits */
	regU &= ~(0x30 << shift);
	/* DMA timing bits */
	regU &= ~(0x05 << adev->devno);

	if (adev->dma_mode >= XFER_UDMA_0) {
		/* Merge the timing value */
		regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
		/* Merge the control bits */
		regU |= 1 << adev->devno; /* UDMA on */
		if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */
			regU |= 4 << adev->devno;
	} else {
		regU &= ~ (1 << adev->devno);	/* UDMA off */
		cmd64x_set_timing(ap, adev, adev->dma_mode);
	}

	regD |= 0x20 << adev->devno;

	pci_write_config_byte(pdev, pciU, regU);
	pci_write_config_byte(pdev, pciD, regD);
}

/**
 *	cmd648_dma_stop	-	DMA stop callback
 *	@qc: Command in progress
 *
 *	DMA has completed.
 */

static void cmd648_bmdma_stop(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 dma_intr;
	int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
	int dma_reg = ap->port_no ? ARTTIM23 : CFR;

	ata_bmdma_stop(qc);

	pci_read_config_byte(pdev, dma_reg, &dma_intr);
	pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask);
}

/**
 *	cmd646r1_dma_stop	-	DMA stop callback
 *	@qc: Command in progress
 *
 *	Stub for now while investigating the r1 quirk in the old driver.
 */

static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
{
	ata_bmdma_stop(qc);
}

static struct scsi_host_template cmd64x_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static const struct ata_port_operations cmd64x_base_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.set_piomode	= cmd64x_set_piomode,
	.set_dmamode	= cmd64x_set_dmamode,
};

static struct ata_port_operations cmd64x_port_ops = {
	.inherits	= &cmd64x_base_ops,
	.cable_detect	= ata_cable_40wire,
};

static struct ata_port_operations cmd646r1_port_ops = {
	.inherits	= &cmd64x_base_ops,
	.bmdma_stop	= cmd646r1_bmdma_stop,
	.cable_detect	= ata_cable_40wire,
};

static struct ata_port_operations cmd648_port_ops = {
	.inherits	= &cmd64x_base_ops,
	.bmdma_stop	= cmd648_bmdma_stop,
	.cable_detect	= cmd648_cable_detect,
};

static void cmd64x_fixup(struct pci_dev *pdev)
{
	u8 mrdmode;

	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
	mrdmode &= ~0x30;	/* IRQ set up */
	mrdmode |= 0x02;	/* Memory read line enable */
	pci_write_config_byte(pdev, MRDMODE, mrdmode);

	/* PPC specific fixup copied from old driver */
#ifdef CONFIG_PPC
	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
#endif
}

static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const struct ata_port_info cmd_info[6] = {
		{	/* CMD 643 - no UDMA */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.port_ops = &cmd64x_port_ops
		},
		{	/* CMD 646 with broken UDMA */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.port_ops = &cmd64x_port_ops
		},
		{	/* CMD 646 with working UDMA */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA2,
			.port_ops = &cmd64x_port_ops
		},
		{	/* CMD 646 rev 1  */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.port_ops = &cmd646r1_port_ops
		},
		{	/* CMD 648 */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA4,
			.port_ops = &cmd648_port_ops
		},
		{	/* CMD 649 */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA5,
			.port_ops = &cmd648_port_ops
		}
	};
	const struct ata_port_info *ppi[] = { 
		&cmd_info[id->driver_data],
		&cmd_info[id->driver_data],
		NULL
	};
	u8 reg;
	int rc;
	struct pci_dev *bridge = pdev->bus->self;
	/* mobility split bridges don't report enabled ports correctly */
	int port_ok = !(bridge && bridge->vendor ==
			PCI_VENDOR_ID_MOBILITY_ELECTRONICS);
	/* all (with exceptions below) apart from 643 have CNTRL_CH0 bit */
	int cntrl_ch0_ok = (id->driver_data != 0);

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	if (id->driver_data == 0)	/* 643 */
		ata_pci_bmdma_clear_simplex(pdev);

	if (pdev->device == PCI_DEVICE_ID_CMD_646) {
		/* Does UDMA work ? */
		if (pdev->revision > 4) {
			ppi[0] = &cmd_info[2];
			ppi[1] = &cmd_info[2];
		}
		/* Early rev with other problems ? */
		else if (pdev->revision == 1) {
			ppi[0] = &cmd_info[3];
			ppi[1] = &cmd_info[3];
		}
		/* revs 1,2 have no CNTRL_CH0 */
		if (pdev->revision < 3)
			cntrl_ch0_ok = 0;
	}

	cmd64x_fixup(pdev);

	/* check for enabled ports */
	pci_read_config_byte(pdev, CNTRL, &reg);
	if (!port_ok)
		dev_printk(KERN_NOTICE, &pdev->dev, "Mobility Bridge detected, ignoring CNTRL port enable/disable\n");
	if (port_ok && cntrl_ch0_ok && !(reg & CNTRL_CH0)) {
		dev_printk(KERN_NOTICE, &pdev->dev, "Primary port is disabled\n");
		ppi[0] = &ata_dummy_port_info;
		
	}
	if (port_ok && !(reg & CNTRL_CH1)) {
		dev_printk(KERN_NOTICE, &pdev->dev, "Secondary port is disabled\n");
		ppi[1] = &ata_dummy_port_info;
	}

	return ata_pci_bmdma_init_one(pdev, ppi, &cmd64x_sht, NULL, 0);
}

#ifdef CONFIG_PM
static int cmd64x_reinit_one(struct pci_dev *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	int rc;

	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;

	cmd64x_fixup(pdev);

	ata_host_resume(host);
	return 0;
}
#endif

static const struct pci_device_id cmd64x[] = {
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 },

	{ },
};

static struct pci_driver cmd64x_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= cmd64x,
	.probe 		= cmd64x_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= cmd64x_reinit_one,
#endif
};

static int __init cmd64x_init(void)
{
	return pci_register_driver(&cmd64x_pci_driver);
}

static void __exit cmd64x_exit(void)
{
	pci_unregister_driver(&cmd64x_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, cmd64x);
MODULE_VERSION(DRV_VERSION);

module_init(cmd64x_init);
module_exit(cmd64x_exit);
Commit	Line	Data
669a5db4	1	/*
fb9f8905	2	* pata_cmd64x.c - CMD64x PATA for new ATA layer
669a5db4	3	* (C) 2005 Red Hat Inc
ab771630	4	* Alan Cox <alan@lxorguk.ukuu.org.uk>
a2bd6220	5	* (C) 2009-2010 Bartlomiej Zolnierkiewicz
669a5db4 JG	6	*
	7	* Based upon
	8	* linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
	9	*
	10	* cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
	11	* Note, this driver is not used at all on other systems because
	12	* there the "BIOS" has done all of the following already.
	13	* Due to massive hardware bugs, UltraDMA is only supported
	14	* on the 646U2 and not on the 646U.
	15	*
	16	* Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
	17	* Copyright (C) 1998 David S. Miller (davem@redhat.com)
	18	*
	19	* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
	20	*
	21	* TODO
	22	* Testing work
	23	*/
85cd7251	24
669a5db4 JG	25	#include <linux/kernel.h>
	26	#include <linux/module.h>
	27	#include <linux/pci.h>
	28	#include <linux/init.h>
	29	#include <linux/blkdev.h>
	30	#include <linux/delay.h>
	31	#include <scsi/scsi_host.h>
	32	#include <linux/libata.h>
	33
	34	#define DRV_NAME "pata_cmd64x"
06393afd	35	#define DRV_VERSION "0.2.5"
669a5db4 JG	36
	37	/*
	38	* CMD64x specific registers definition.
	39	*/
85cd7251	40
669a5db4 JG	41	enum {
669a5db4 JG	42	CFR = 0x50,
03a849e6	43	CFR_INTR_CH0 = 0x04,
9281b16c JB	44	CNTRL = 0x51,
	45	CNTRL_CH0 = 0x04,
	46	CNTRL_CH1 = 0x08,
669a5db4 JG	47	CMDTIM = 0x52,
	48	ARTTIM0 = 0x53,
	49	DRWTIM0 = 0x54,
	50	ARTTIM1 = 0x55,
	51	DRWTIM1 = 0x56,
	52	ARTTIM23 = 0x57,
	53	ARTTIM23_DIS_RA2 = 0x04,
	54	ARTTIM23_DIS_RA3 = 0x08,
	55	ARTTIM23_INTR_CH1 = 0x10,
669a5db4 JG	56	DRWTIM2 = 0x58,
	57	BRST = 0x59,
	58	DRWTIM3 = 0x5b,
	59	BMIDECR0 = 0x70,
	60	MRDMODE = 0x71,
	61	MRDMODE_INTR_CH0 = 0x04,
	62	MRDMODE_INTR_CH1 = 0x08,
669a5db4 JG	63	BMIDESR0 = 0x72,
	64	UDIDETCR0 = 0x73,
	65	DTPR0 = 0x74,
	66	BMIDECR1 = 0x78,
	67	BMIDECSR = 0x79,
669a5db4 JG	68	UDIDETCR1 = 0x7B,
	69	DTPR1 = 0x7C
	70	};
	71
a73984a0	72	static int cmd648_cable_detect(struct ata_port *ap)
669a5db4 JG	73	{
	74	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	75	u8 r;
	76
	77	/* Check cable detect bits */
	78	pci_read_config_byte(pdev, BMIDECSR, &r);
	79	if (r & (1 << ap->port_no))
a73984a0 JG	80	return ATA_CBL_PATA80;
a73984a0 JG	81	return ATA_CBL_PATA40;
669a5db4 JG	82	}
	83
	84	/**
05d1efff	85	* cmd64x_set_piomode - set PIO and MWDMA timing
669a5db4 JG	86	* @ap: ATA interface
669a5db4 JG	87	* @adev: ATA device
05d1efff	88	* @mode: mode
669a5db4	89	*
05d1efff	90	* Called to do the PIO and MWDMA mode setup.
669a5db4	91	*/
85cd7251	92
05d1efff	93	static void cmd64x_set_timing(struct ata_port ap, struct ata_device adev, u8 mode)
669a5db4 JG	94	{
	95	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	96	struct ata_timing t;
	97	const unsigned long T = 1000000 / 33;
	98	const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
85cd7251	99
669a5db4	100	u8 reg;
85cd7251	101
669a5db4	102	/* Port layout is not logical so use a table */
85cd7251	103	const u8 arttim_port[2][2] = {
669a5db4 JG	104	{ ARTTIM0, ARTTIM1 },
	105	{ ARTTIM23, ARTTIM23 }
	106	};
	107	const u8 drwtim_port[2][2] = {
	108	{ DRWTIM0, DRWTIM1 },
	109	{ DRWTIM2, DRWTIM3 }
	110	};
85cd7251	111
669a5db4 JG	112	int arttim = arttim_port[ap->port_no][adev->devno];
669a5db4 JG	113	int drwtim = drwtim_port[ap->port_no][adev->devno];
85cd7251	114
05d1efff AC	115	/* ata_timing_compute is smart and will produce timings for MWDMA
	116	that don't violate the drives PIO capabilities. */
	117	if (ata_timing_compute(adev, mode, &t, T, 0) < 0) {
669a5db4 JG	118	printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
	119	return;
	120	}
	121	if (ap->port_no) {
	122	/* Slave has shared address setup */
	123	struct ata_device *pair = ata_dev_pair(adev);
85cd7251	124
669a5db4 JG	125	if (pair) {
	126	struct ata_timing tp;
	127	ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
	128	ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
	129	}
	130	}
85cd7251	131
669a5db4 JG	132	printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
	133	t.active, t.recover, t.setup);
	134	if (t.recover > 16) {
	135	t.active += t.recover - 16;
	136	t.recover = 16;
	137	}
	138	if (t.active > 16)
	139	t.active = 16;
85cd7251	140
669a5db4 JG	141	/* Now convert the clocks into values we can actually stuff into
669a5db4 JG	142	the chip */
85cd7251	143
a2bd6220 BZ	144	if (t.recover == 16)
	145	t.recover = 0;
	146	else if (t.recover > 1)
669a5db4 JG	147	t.recover--;
	148	else
	149	t.recover = 15;
85cd7251	150
669a5db4 JG	151	if (t.setup > 4)
	152	t.setup = 0xC0;
	153	else
	154	t.setup = setup_data[t.setup];
85cd7251	155
669a5db4	156	t.active &= 0x0F; /* 0 = 16 */
85cd7251	157
669a5db4 JG	158	/* Load setup timing */
	159	pci_read_config_byte(pdev, arttim, &reg);
	160	reg &= 0x3F;
	161	reg \|= t.setup;
	162	pci_write_config_byte(pdev, arttim, reg);
85cd7251	163
669a5db4	164	/* Load active/recovery */
85cd7251	165	pci_write_config_byte(pdev, drwtim, (t.active << 4) \| t.recover);
669a5db4 JG	166	}
669a5db4 JG	167
05d1efff AC	168	/**
	169	* cmd64x_set_piomode - set initial PIO mode data
	170	* @ap: ATA interface
	171	* @adev: ATA device
	172	*
	173	* Used when configuring the devices ot set the PIO timings. All the
	174	* actual work is done by the PIO/MWDMA setting helper
	175	*/
	176
	177	static void cmd64x_set_piomode(struct ata_port ap, struct ata_device adev)
	178	{
	179	cmd64x_set_timing(ap, adev, adev->pio_mode);
	180	}
	181
669a5db4 JG	182	/**
	183	* cmd64x_set_dmamode - set initial DMA mode data
	184	* @ap: ATA interface
	185	* @adev: ATA device
	186	*
	187	* Called to do the DMA mode setup.
	188	*/
85cd7251	189
669a5db4 JG	190	static void cmd64x_set_dmamode(struct ata_port ap, struct ata_device adev)
	191	{
	192	static const u8 udma_data[] = {
6a40da02	193	0x30, 0x20, 0x10, 0x20, 0x10, 0x00
669a5db4	194	};
85cd7251	195
669a5db4 JG	196	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	197	u8 regU, regD;
	198
	199	int pciU = UDIDETCR0 + 8 * ap->port_no;
	200	int pciD = BMIDESR0 + 8 * ap->port_no;
	201	int shift = 2 * adev->devno;
85cd7251	202
669a5db4 JG	203	pci_read_config_byte(pdev, pciD, &regD);
	204	pci_read_config_byte(pdev, pciU, &regU);
	205
6a40da02 A	206	/* DMA bits off */
	207	regD &= ~(0x20 << adev->devno);
	208	/* DMA control bits */
	209	regU &= ~(0x30 << shift);
	210	/* DMA timing bits */
	211	regU &= ~(0x05 << adev->devno);
85cd7251	212
6a40da02	213	if (adev->dma_mode >= XFER_UDMA_0) {
24b7ce98	214	/* Merge the timing value */
669a5db4	215	regU \|= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
6a40da02 A	216	/* Merge the control bits */
6a40da02 A	217	regU \|= 1 << adev->devno; /* UDMA on */
509426bd	218	if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */
6a40da02	219	regU \|= 4 << adev->devno;
05d1efff AC	220	} else {
	221	regU &= ~ (1 << adev->devno); /* UDMA off */
	222	cmd64x_set_timing(ap, adev, adev->dma_mode);
	223	}
669a5db4 JG	224
	225	regD \|= 0x20 << adev->devno;
	226
	227	pci_write_config_byte(pdev, pciU, regU);
	228	pci_write_config_byte(pdev, pciD, regD);
	229	}
	230
	231	/**
	232	* cmd648_dma_stop - DMA stop callback
	233	* @qc: Command in progress
	234	*
	235	* DMA has completed.
	236	*/
	237
	238	static void cmd648_bmdma_stop(struct ata_queued_cmd *qc)
	239	{
	240	struct ata_port *ap = qc->ap;
	241	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	242	u8 dma_intr;
6a40da02	243	int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
c754d9b6	244	int dma_reg = ap->port_no ? ARTTIM23 : CFR;
85cd7251	245
669a5db4	246	ata_bmdma_stop(qc);
85cd7251	247
669a5db4 JG	248	pci_read_config_byte(pdev, dma_reg, &dma_intr);
	249	pci_write_config_byte(pdev, dma_reg, dma_intr \| dma_mask);
	250	}
85cd7251	251
669a5db4	252	/**
06393afd	253	* cmd646r1_dma_stop - DMA stop callback
669a5db4 JG	254	* @qc: Command in progress
669a5db4 JG	255	*
06393afd	256	* Stub for now while investigating the r1 quirk in the old driver.
669a5db4 JG	257	*/
669a5db4 JG	258
06393afd	259	static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
669a5db4 JG	260	{
	261	ata_bmdma_stop(qc);
	262	}
85cd7251	263
669a5db4	264	static struct scsi_host_template cmd64x_sht = {
68d1d07b	265	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	266	};
669a5db4 JG	267
029cfd6b TH	268	static const struct ata_port_operations cmd64x_base_ops = {
029cfd6b TH	269	.inherits = &ata_bmdma_port_ops,
669a5db4 JG	270	.set_piomode = cmd64x_set_piomode,
669a5db4 JG	271	.set_dmamode = cmd64x_set_dmamode,
85cd7251	272	};
669a5db4	273
029cfd6b TH	274	static struct ata_port_operations cmd64x_port_ops = {
029cfd6b TH	275	.inherits = &cmd64x_base_ops,
a73984a0	276	.cable_detect = ata_cable_40wire,
029cfd6b	277	};
669a5db4	278
029cfd6b TH	279	static struct ata_port_operations cmd646r1_port_ops = {
029cfd6b TH	280	.inherits = &cmd64x_base_ops,
06393afd	281	.bmdma_stop = cmd646r1_bmdma_stop,
029cfd6b	282	.cable_detect = ata_cable_40wire,
85cd7251	283	};
669a5db4 JG	284
669a5db4 JG	285	static struct ata_port_operations cmd648_port_ops = {
029cfd6b	286	.inherits = &cmd64x_base_ops,
669a5db4	287	.bmdma_stop = cmd648_bmdma_stop,
029cfd6b	288	.cable_detect = cmd648_cable_detect,
85cd7251 JG	289	};
85cd7251 JG	290
f4c6ae50 BZ	291	static void cmd64x_fixup(struct pci_dev *pdev)
	292	{
	293	u8 mrdmode;
	294
	295	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
	296	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
	297	mrdmode &= ~0x30; /* IRQ set up */
	298	mrdmode \|= 0x02; /* Memory read line enable */
	299	pci_write_config_byte(pdev, MRDMODE, mrdmode);
	300
	301	/* PPC specific fixup copied from old driver */
	302	#ifdef CONFIG_PPC
	303	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
	304	#endif
	305	}
	306
669a5db4 JG	307	static int cmd64x_init_one(struct pci_dev pdev, const struct pci_device_id id)
669a5db4 JG	308	{
1626aeb8	309	static const struct ata_port_info cmd_info[6] = {
669a5db4	310	{ /* CMD 643 - no UDMA */
1d2808fd	311	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	312	.pio_mask = ATA_PIO4,
14bdef98 EIB	313	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	314	.port_ops = &cmd64x_port_ops
	315	},
	316	{ /* CMD 646 with broken UDMA */
1d2808fd	317	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	318	.pio_mask = ATA_PIO4,
14bdef98 EIB	319	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	320	.port_ops = &cmd64x_port_ops
	321	},
	322	{ /* CMD 646 with working UDMA */
1d2808fd	323	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	324	.pio_mask = ATA_PIO4,
14bdef98 EIB	325	.mwdma_mask = ATA_MWDMA2,
dbf0c89c	326	.udma_mask = ATA_UDMA2,
669a5db4 JG	327	.port_ops = &cmd64x_port_ops
	328	},
	329	{ /* CMD 646 rev 1 */
1d2808fd	330	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	331	.pio_mask = ATA_PIO4,
14bdef98 EIB	332	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	333	.port_ops = &cmd646r1_port_ops
	334	},
	335	{ /* CMD 648 */
1d2808fd	336	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	337	.pio_mask = ATA_PIO4,
14bdef98 EIB	338	.mwdma_mask = ATA_MWDMA2,
dbf0c89c	339	.udma_mask = ATA_UDMA4,
669a5db4 JG	340	.port_ops = &cmd648_port_ops
	341	},
	342	{ /* CMD 649 */
1d2808fd	343	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	344	.pio_mask = ATA_PIO4,
14bdef98 EIB	345	.mwdma_mask = ATA_MWDMA2,
dbf0c89c	346	.udma_mask = ATA_UDMA5,
669a5db4 JG	347	.port_ops = &cmd648_port_ops
	348	}
	349	};
9281b16c JB	350	const struct ata_port_info *ppi[] = {
	351	&cmd_info[id->driver_data],
	352	&cmd_info[id->driver_data],
	353	NULL
	354	};
f4c6ae50	355	u8 reg;
f08048e9	356	int rc;
9281b16c JB	357	struct pci_dev *bridge = pdev->bus->self;
	358	/* mobility split bridges don't report enabled ports correctly */
	359	int port_ok = !(bridge && bridge->vendor ==
	360	PCI_VENDOR_ID_MOBILITY_ELECTRONICS);
	361	/* all (with exceptions below) apart from 643 have CNTRL_CH0 bit */
	362	int cntrl_ch0_ok = (id->driver_data != 0);
f08048e9 TH	363
	364	rc = pcim_enable_device(pdev);
	365	if (rc)
	366	return rc;
85cd7251	367
669a5db4	368	if (id->driver_data == 0) /* 643 */
9363c382	369	ata_pci_bmdma_clear_simplex(pdev);
85cd7251	370
669a5db4 JG	371	if (pdev->device == PCI_DEVICE_ID_CMD_646) {
669a5db4 JG	372	/* Does UDMA work ? */
9281b16c	373	if (pdev->revision > 4) {
1626aeb8	374	ppi[0] = &cmd_info[2];
9281b16c JB	375	ppi[1] = &cmd_info[2];
9281b16c JB	376	}
669a5db4	377	/* Early rev with other problems ? */
9281b16c	378	else if (pdev->revision == 1) {
1626aeb8	379	ppi[0] = &cmd_info[3];
9281b16c JB	380	ppi[1] = &cmd_info[3];
	381	}
	382	/* revs 1,2 have no CNTRL_CH0 */
	383	if (pdev->revision < 3)
	384	cntrl_ch0_ok = 0;
669a5db4 JG	385	}
669a5db4 JG	386
f4c6ae50	387	cmd64x_fixup(pdev);
85cd7251	388
9281b16c JB	389	/* check for enabled ports */
	390	pci_read_config_byte(pdev, CNTRL, &reg);
	391	if (!port_ok)
	392	dev_printk(KERN_NOTICE, &pdev->dev, "Mobility Bridge detected, ignoring CNTRL port enable/disable\n");
	393	if (port_ok && cntrl_ch0_ok && !(reg & CNTRL_CH0)) {
	394	dev_printk(KERN_NOTICE, &pdev->dev, "Primary port is disabled\n");
	395	ppi[0] = &ata_dummy_port_info;
	396
	397	}
	398	if (port_ok && !(reg & CNTRL_CH1)) {
	399	dev_printk(KERN_NOTICE, &pdev->dev, "Secondary port is disabled\n");
	400	ppi[1] = &ata_dummy_port_info;
	401	}
	402
1c5afdf7	403	return ata_pci_bmdma_init_one(pdev, ppi, &cmd64x_sht, NULL, 0);
669a5db4 JG	404	}
669a5db4 JG	405
438ac6d5	406	#ifdef CONFIG_PM
7f72a379 A	407	static int cmd64x_reinit_one(struct pci_dev *pdev)
7f72a379 A	408	{
f08048e9	409	struct ata_host *host = dev_get_drvdata(&pdev->dev);
f08048e9 TH	410	int rc;
	411
	412	rc = ata_pci_device_do_resume(pdev);
	413	if (rc)
	414	return rc;
	415
f4c6ae50 BZ	416	cmd64x_fixup(pdev);
f4c6ae50 BZ	417
f08048e9 TH	418	ata_host_resume(host);
f08048e9 TH	419	return 0;
7f72a379	420	}
438ac6d5	421	#endif
7f72a379	422
2d2744fc JG	423	static const struct pci_device_id cmd64x[] = {
	424	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
	425	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
	426	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 },
	427	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 },
	428
	429	{ },
669a5db4 JG	430	};
	431
	432	static struct pci_driver cmd64x_pci_driver = {
2d2744fc	433	.name = DRV_NAME,
669a5db4 JG	434	.id_table = cmd64x,
669a5db4 JG	435	.probe = cmd64x_init_one,
7f72a379	436	.remove = ata_pci_remove_one,
438ac6d5	437	#ifdef CONFIG_PM
7f72a379 A	438	.suspend = ata_pci_device_suspend,
7f72a379 A	439	.resume = cmd64x_reinit_one,
438ac6d5	440	#endif
669a5db4 JG	441	};
	442
	443	static int __init cmd64x_init(void)
	444	{
	445	return pci_register_driver(&cmd64x_pci_driver);
	446	}
	447
669a5db4 JG	448	static void __exit cmd64x_exit(void)
	449	{
	450	pci_unregister_driver(&cmd64x_pci_driver);
	451	}
	452
669a5db4 JG	453	MODULE_AUTHOR("Alan Cox");
	454	MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
	455	MODULE_LICENSE("GPL");
	456	MODULE_DEVICE_TABLE(pci, cmd64x);
	457	MODULE_VERSION(DRV_VERSION);
	458
	459	module_init(cmd64x_init);
	460	module_exit(cmd64x_exit);