Commit | Line | Data |
---|---|---|
669a5db4 | 1 | /* |
fb9f8905 | 2 | * pata_cmd64x.c - CMD64x PATA for new ATA layer |
669a5db4 | 3 | * (C) 2005 Red Hat Inc |
ab771630 | 4 | * Alan Cox <alan@lxorguk.ukuu.org.uk> |
a2bd6220 | 5 | * (C) 2009-2010 Bartlomiej Zolnierkiewicz |
669a5db4 JG |
6 | * |
7 | * Based upon | |
8 | * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002 | |
9 | * | |
10 | * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines. | |
11 | * Note, this driver is not used at all on other systems because | |
12 | * there the "BIOS" has done all of the following already. | |
13 | * Due to massive hardware bugs, UltraDMA is only supported | |
14 | * on the 646U2 and not on the 646U. | |
15 | * | |
16 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) | |
17 | * Copyright (C) 1998 David S. Miller (davem@redhat.com) | |
18 | * | |
19 | * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> | |
20 | * | |
21 | * TODO | |
22 | * Testing work | |
23 | */ | |
85cd7251 | 24 | |
669a5db4 JG |
25 | #include <linux/kernel.h> |
26 | #include <linux/module.h> | |
27 | #include <linux/pci.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/blkdev.h> | |
30 | #include <linux/delay.h> | |
31 | #include <scsi/scsi_host.h> | |
32 | #include <linux/libata.h> | |
33 | ||
34 | #define DRV_NAME "pata_cmd64x" | |
06393afd | 35 | #define DRV_VERSION "0.2.5" |
669a5db4 JG |
36 | |
37 | /* | |
38 | * CMD64x specific registers definition. | |
39 | */ | |
85cd7251 | 40 | |
669a5db4 JG |
41 | enum { |
42 | CFR = 0x50, | |
03a849e6 | 43 | CFR_INTR_CH0 = 0x04, |
669a5db4 JG |
44 | CMDTIM = 0x52, |
45 | ARTTIM0 = 0x53, | |
46 | DRWTIM0 = 0x54, | |
47 | ARTTIM1 = 0x55, | |
48 | DRWTIM1 = 0x56, | |
49 | ARTTIM23 = 0x57, | |
50 | ARTTIM23_DIS_RA2 = 0x04, | |
51 | ARTTIM23_DIS_RA3 = 0x08, | |
52 | ARTTIM23_INTR_CH1 = 0x10, | |
669a5db4 JG |
53 | DRWTIM2 = 0x58, |
54 | BRST = 0x59, | |
55 | DRWTIM3 = 0x5b, | |
56 | BMIDECR0 = 0x70, | |
57 | MRDMODE = 0x71, | |
58 | MRDMODE_INTR_CH0 = 0x04, | |
59 | MRDMODE_INTR_CH1 = 0x08, | |
669a5db4 JG |
60 | BMIDESR0 = 0x72, |
61 | UDIDETCR0 = 0x73, | |
62 | DTPR0 = 0x74, | |
63 | BMIDECR1 = 0x78, | |
64 | BMIDECSR = 0x79, | |
669a5db4 JG |
65 | UDIDETCR1 = 0x7B, |
66 | DTPR1 = 0x7C | |
67 | }; | |
68 | ||
a73984a0 | 69 | static int cmd648_cable_detect(struct ata_port *ap) |
669a5db4 JG |
70 | { |
71 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
72 | u8 r; | |
73 | ||
74 | /* Check cable detect bits */ | |
75 | pci_read_config_byte(pdev, BMIDECSR, &r); | |
76 | if (r & (1 << ap->port_no)) | |
a73984a0 JG |
77 | return ATA_CBL_PATA80; |
78 | return ATA_CBL_PATA40; | |
669a5db4 JG |
79 | } |
80 | ||
81 | /** | |
05d1efff | 82 | * cmd64x_set_piomode - set PIO and MWDMA timing |
669a5db4 JG |
83 | * @ap: ATA interface |
84 | * @adev: ATA device | |
05d1efff | 85 | * @mode: mode |
669a5db4 | 86 | * |
05d1efff | 87 | * Called to do the PIO and MWDMA mode setup. |
669a5db4 | 88 | */ |
85cd7251 | 89 | |
05d1efff | 90 | static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 mode) |
669a5db4 JG |
91 | { |
92 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
93 | struct ata_timing t; | |
94 | const unsigned long T = 1000000 / 33; | |
95 | const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 }; | |
85cd7251 | 96 | |
669a5db4 | 97 | u8 reg; |
85cd7251 | 98 | |
669a5db4 | 99 | /* Port layout is not logical so use a table */ |
85cd7251 | 100 | const u8 arttim_port[2][2] = { |
669a5db4 JG |
101 | { ARTTIM0, ARTTIM1 }, |
102 | { ARTTIM23, ARTTIM23 } | |
103 | }; | |
104 | const u8 drwtim_port[2][2] = { | |
105 | { DRWTIM0, DRWTIM1 }, | |
106 | { DRWTIM2, DRWTIM3 } | |
107 | }; | |
85cd7251 | 108 | |
669a5db4 JG |
109 | int arttim = arttim_port[ap->port_no][adev->devno]; |
110 | int drwtim = drwtim_port[ap->port_no][adev->devno]; | |
85cd7251 | 111 | |
05d1efff AC |
112 | /* ata_timing_compute is smart and will produce timings for MWDMA |
113 | that don't violate the drives PIO capabilities. */ | |
114 | if (ata_timing_compute(adev, mode, &t, T, 0) < 0) { | |
669a5db4 JG |
115 | printk(KERN_ERR DRV_NAME ": mode computation failed.\n"); |
116 | return; | |
117 | } | |
118 | if (ap->port_no) { | |
119 | /* Slave has shared address setup */ | |
120 | struct ata_device *pair = ata_dev_pair(adev); | |
85cd7251 | 121 | |
669a5db4 JG |
122 | if (pair) { |
123 | struct ata_timing tp; | |
124 | ata_timing_compute(pair, pair->pio_mode, &tp, T, 0); | |
125 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); | |
126 | } | |
127 | } | |
85cd7251 | 128 | |
669a5db4 JG |
129 | printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n", |
130 | t.active, t.recover, t.setup); | |
131 | if (t.recover > 16) { | |
132 | t.active += t.recover - 16; | |
133 | t.recover = 16; | |
134 | } | |
135 | if (t.active > 16) | |
136 | t.active = 16; | |
85cd7251 | 137 | |
669a5db4 JG |
138 | /* Now convert the clocks into values we can actually stuff into |
139 | the chip */ | |
85cd7251 | 140 | |
a2bd6220 BZ |
141 | if (t.recover == 16) |
142 | t.recover = 0; | |
143 | else if (t.recover > 1) | |
669a5db4 JG |
144 | t.recover--; |
145 | else | |
146 | t.recover = 15; | |
85cd7251 | 147 | |
669a5db4 JG |
148 | if (t.setup > 4) |
149 | t.setup = 0xC0; | |
150 | else | |
151 | t.setup = setup_data[t.setup]; | |
85cd7251 | 152 | |
669a5db4 | 153 | t.active &= 0x0F; /* 0 = 16 */ |
85cd7251 | 154 | |
669a5db4 JG |
155 | /* Load setup timing */ |
156 | pci_read_config_byte(pdev, arttim, ®); | |
157 | reg &= 0x3F; | |
158 | reg |= t.setup; | |
159 | pci_write_config_byte(pdev, arttim, reg); | |
85cd7251 | 160 | |
669a5db4 | 161 | /* Load active/recovery */ |
85cd7251 | 162 | pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover); |
669a5db4 JG |
163 | } |
164 | ||
05d1efff AC |
165 | /** |
166 | * cmd64x_set_piomode - set initial PIO mode data | |
167 | * @ap: ATA interface | |
168 | * @adev: ATA device | |
169 | * | |
170 | * Used when configuring the devices ot set the PIO timings. All the | |
171 | * actual work is done by the PIO/MWDMA setting helper | |
172 | */ | |
173 | ||
174 | static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
175 | { | |
176 | cmd64x_set_timing(ap, adev, adev->pio_mode); | |
177 | } | |
178 | ||
669a5db4 JG |
179 | /** |
180 | * cmd64x_set_dmamode - set initial DMA mode data | |
181 | * @ap: ATA interface | |
182 | * @adev: ATA device | |
183 | * | |
184 | * Called to do the DMA mode setup. | |
185 | */ | |
85cd7251 | 186 | |
669a5db4 JG |
187 | static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
188 | { | |
189 | static const u8 udma_data[] = { | |
6a40da02 | 190 | 0x30, 0x20, 0x10, 0x20, 0x10, 0x00 |
669a5db4 | 191 | }; |
85cd7251 | 192 | |
669a5db4 JG |
193 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
194 | u8 regU, regD; | |
195 | ||
196 | int pciU = UDIDETCR0 + 8 * ap->port_no; | |
197 | int pciD = BMIDESR0 + 8 * ap->port_no; | |
198 | int shift = 2 * adev->devno; | |
85cd7251 | 199 | |
669a5db4 JG |
200 | pci_read_config_byte(pdev, pciD, ®D); |
201 | pci_read_config_byte(pdev, pciU, ®U); | |
202 | ||
6a40da02 A |
203 | /* DMA bits off */ |
204 | regD &= ~(0x20 << adev->devno); | |
205 | /* DMA control bits */ | |
206 | regU &= ~(0x30 << shift); | |
207 | /* DMA timing bits */ | |
208 | regU &= ~(0x05 << adev->devno); | |
85cd7251 | 209 | |
6a40da02 | 210 | if (adev->dma_mode >= XFER_UDMA_0) { |
24b7ce98 | 211 | /* Merge the timing value */ |
669a5db4 | 212 | regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift; |
6a40da02 A |
213 | /* Merge the control bits */ |
214 | regU |= 1 << adev->devno; /* UDMA on */ | |
509426bd | 215 | if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */ |
6a40da02 | 216 | regU |= 4 << adev->devno; |
05d1efff AC |
217 | } else { |
218 | regU &= ~ (1 << adev->devno); /* UDMA off */ | |
219 | cmd64x_set_timing(ap, adev, adev->dma_mode); | |
220 | } | |
669a5db4 JG |
221 | |
222 | regD |= 0x20 << adev->devno; | |
223 | ||
224 | pci_write_config_byte(pdev, pciU, regU); | |
225 | pci_write_config_byte(pdev, pciD, regD); | |
226 | } | |
227 | ||
228 | /** | |
229 | * cmd648_dma_stop - DMA stop callback | |
230 | * @qc: Command in progress | |
231 | * | |
232 | * DMA has completed. | |
233 | */ | |
234 | ||
235 | static void cmd648_bmdma_stop(struct ata_queued_cmd *qc) | |
236 | { | |
237 | struct ata_port *ap = qc->ap; | |
238 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
239 | u8 dma_intr; | |
6a40da02 | 240 | int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0; |
c754d9b6 | 241 | int dma_reg = ap->port_no ? ARTTIM23 : CFR; |
85cd7251 | 242 | |
669a5db4 | 243 | ata_bmdma_stop(qc); |
85cd7251 | 244 | |
669a5db4 JG |
245 | pci_read_config_byte(pdev, dma_reg, &dma_intr); |
246 | pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask); | |
247 | } | |
85cd7251 | 248 | |
669a5db4 | 249 | /** |
06393afd | 250 | * cmd646r1_dma_stop - DMA stop callback |
669a5db4 JG |
251 | * @qc: Command in progress |
252 | * | |
06393afd | 253 | * Stub for now while investigating the r1 quirk in the old driver. |
669a5db4 JG |
254 | */ |
255 | ||
06393afd | 256 | static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc) |
669a5db4 JG |
257 | { |
258 | ata_bmdma_stop(qc); | |
259 | } | |
85cd7251 | 260 | |
669a5db4 | 261 | static struct scsi_host_template cmd64x_sht = { |
68d1d07b | 262 | ATA_BMDMA_SHT(DRV_NAME), |
669a5db4 JG |
263 | }; |
264 | ||
029cfd6b TH |
265 | static const struct ata_port_operations cmd64x_base_ops = { |
266 | .inherits = &ata_bmdma_port_ops, | |
669a5db4 JG |
267 | .set_piomode = cmd64x_set_piomode, |
268 | .set_dmamode = cmd64x_set_dmamode, | |
85cd7251 | 269 | }; |
669a5db4 | 270 | |
029cfd6b TH |
271 | static struct ata_port_operations cmd64x_port_ops = { |
272 | .inherits = &cmd64x_base_ops, | |
a73984a0 | 273 | .cable_detect = ata_cable_40wire, |
029cfd6b | 274 | }; |
669a5db4 | 275 | |
029cfd6b TH |
276 | static struct ata_port_operations cmd646r1_port_ops = { |
277 | .inherits = &cmd64x_base_ops, | |
06393afd | 278 | .bmdma_stop = cmd646r1_bmdma_stop, |
029cfd6b | 279 | .cable_detect = ata_cable_40wire, |
85cd7251 | 280 | }; |
669a5db4 JG |
281 | |
282 | static struct ata_port_operations cmd648_port_ops = { | |
029cfd6b | 283 | .inherits = &cmd64x_base_ops, |
669a5db4 | 284 | .bmdma_stop = cmd648_bmdma_stop, |
029cfd6b | 285 | .cable_detect = cmd648_cable_detect, |
85cd7251 JG |
286 | }; |
287 | ||
669a5db4 JG |
288 | static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
289 | { | |
1626aeb8 | 290 | static const struct ata_port_info cmd_info[6] = { |
669a5db4 | 291 | { /* CMD 643 - no UDMA */ |
1d2808fd | 292 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
293 | .pio_mask = ATA_PIO4, |
294 | .mwdma_mask = ATA_MWDMA2, | |
669a5db4 JG |
295 | .port_ops = &cmd64x_port_ops |
296 | }, | |
297 | { /* CMD 646 with broken UDMA */ | |
1d2808fd | 298 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
299 | .pio_mask = ATA_PIO4, |
300 | .mwdma_mask = ATA_MWDMA2, | |
669a5db4 JG |
301 | .port_ops = &cmd64x_port_ops |
302 | }, | |
303 | { /* CMD 646 with working UDMA */ | |
1d2808fd | 304 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
305 | .pio_mask = ATA_PIO4, |
306 | .mwdma_mask = ATA_MWDMA2, | |
dbf0c89c | 307 | .udma_mask = ATA_UDMA2, |
669a5db4 JG |
308 | .port_ops = &cmd64x_port_ops |
309 | }, | |
310 | { /* CMD 646 rev 1 */ | |
1d2808fd | 311 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
312 | .pio_mask = ATA_PIO4, |
313 | .mwdma_mask = ATA_MWDMA2, | |
669a5db4 JG |
314 | .port_ops = &cmd646r1_port_ops |
315 | }, | |
316 | { /* CMD 648 */ | |
1d2808fd | 317 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
318 | .pio_mask = ATA_PIO4, |
319 | .mwdma_mask = ATA_MWDMA2, | |
dbf0c89c | 320 | .udma_mask = ATA_UDMA4, |
669a5db4 JG |
321 | .port_ops = &cmd648_port_ops |
322 | }, | |
323 | { /* CMD 649 */ | |
1d2808fd | 324 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
325 | .pio_mask = ATA_PIO4, |
326 | .mwdma_mask = ATA_MWDMA2, | |
dbf0c89c | 327 | .udma_mask = ATA_UDMA5, |
669a5db4 JG |
328 | .port_ops = &cmd648_port_ops |
329 | } | |
330 | }; | |
1626aeb8 | 331 | const struct ata_port_info *ppi[] = { &cmd_info[id->driver_data], NULL }; |
669a5db4 | 332 | u8 mrdmode; |
f08048e9 TH |
333 | int rc; |
334 | ||
335 | rc = pcim_enable_device(pdev); | |
336 | if (rc) | |
337 | return rc; | |
85cd7251 | 338 | |
669a5db4 | 339 | if (id->driver_data == 0) /* 643 */ |
9363c382 | 340 | ata_pci_bmdma_clear_simplex(pdev); |
85cd7251 | 341 | |
669a5db4 JG |
342 | if (pdev->device == PCI_DEVICE_ID_CMD_646) { |
343 | /* Does UDMA work ? */ | |
89d3b360 | 344 | if (pdev->revision > 4) |
1626aeb8 | 345 | ppi[0] = &cmd_info[2]; |
669a5db4 | 346 | /* Early rev with other problems ? */ |
89d3b360 | 347 | else if (pdev->revision == 1) |
1626aeb8 | 348 | ppi[0] = &cmd_info[3]; |
669a5db4 JG |
349 | } |
350 | ||
351 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64); | |
352 | pci_read_config_byte(pdev, MRDMODE, &mrdmode); | |
353 | mrdmode &= ~ 0x30; /* IRQ set up */ | |
354 | mrdmode |= 0x02; /* Memory read line enable */ | |
355 | pci_write_config_byte(pdev, MRDMODE, mrdmode); | |
85cd7251 | 356 | |
06393afd JG |
357 | /* Force PIO 0 here.. */ |
358 | ||
669a5db4 JG |
359 | /* PPC specific fixup copied from old driver */ |
360 | #ifdef CONFIG_PPC | |
361 | pci_write_config_byte(pdev, UDIDETCR0, 0xF0); | |
362 | #endif | |
85cd7251 | 363 | |
1c5afdf7 | 364 | return ata_pci_bmdma_init_one(pdev, ppi, &cmd64x_sht, NULL, 0); |
669a5db4 JG |
365 | } |
366 | ||
438ac6d5 | 367 | #ifdef CONFIG_PM |
7f72a379 A |
368 | static int cmd64x_reinit_one(struct pci_dev *pdev) |
369 | { | |
f08048e9 | 370 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
7f72a379 | 371 | u8 mrdmode; |
f08048e9 TH |
372 | int rc; |
373 | ||
374 | rc = ata_pci_device_do_resume(pdev); | |
375 | if (rc) | |
376 | return rc; | |
377 | ||
7f72a379 A |
378 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64); |
379 | pci_read_config_byte(pdev, MRDMODE, &mrdmode); | |
380 | mrdmode &= ~ 0x30; /* IRQ set up */ | |
381 | mrdmode |= 0x02; /* Memory read line enable */ | |
382 | pci_write_config_byte(pdev, MRDMODE, mrdmode); | |
383 | #ifdef CONFIG_PPC | |
384 | pci_write_config_byte(pdev, UDIDETCR0, 0xF0); | |
385 | #endif | |
f08048e9 TH |
386 | ata_host_resume(host); |
387 | return 0; | |
7f72a379 | 388 | } |
438ac6d5 | 389 | #endif |
7f72a379 | 390 | |
2d2744fc JG |
391 | static const struct pci_device_id cmd64x[] = { |
392 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 }, | |
393 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 }, | |
394 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 }, | |
395 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 }, | |
396 | ||
397 | { }, | |
669a5db4 JG |
398 | }; |
399 | ||
400 | static struct pci_driver cmd64x_pci_driver = { | |
2d2744fc | 401 | .name = DRV_NAME, |
669a5db4 JG |
402 | .id_table = cmd64x, |
403 | .probe = cmd64x_init_one, | |
7f72a379 | 404 | .remove = ata_pci_remove_one, |
438ac6d5 | 405 | #ifdef CONFIG_PM |
7f72a379 A |
406 | .suspend = ata_pci_device_suspend, |
407 | .resume = cmd64x_reinit_one, | |
438ac6d5 | 408 | #endif |
669a5db4 JG |
409 | }; |
410 | ||
411 | static int __init cmd64x_init(void) | |
412 | { | |
413 | return pci_register_driver(&cmd64x_pci_driver); | |
414 | } | |
415 | ||
669a5db4 JG |
416 | static void __exit cmd64x_exit(void) |
417 | { | |
418 | pci_unregister_driver(&cmd64x_pci_driver); | |
419 | } | |
420 | ||
669a5db4 JG |
421 | MODULE_AUTHOR("Alan Cox"); |
422 | MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers"); | |
423 | MODULE_LICENSE("GPL"); | |
424 | MODULE_DEVICE_TABLE(pci, cmd64x); | |
425 | MODULE_VERSION(DRV_VERSION); | |
426 | ||
427 | module_init(cmd64x_init); | |
428 | module_exit(cmd64x_exit); |