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a80ea4cb BZ |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | ||
76a40ca8 BZ |
3 | /* |
4 | * Palmchip BK3710 PATA controller driver | |
5 | * | |
6 | * Copyright (c) 2017 Samsung Electronics Co., Ltd. | |
7 | * http://www.samsung.com | |
8 | * | |
9 | * Based on palm_bk3710.c: | |
10 | * | |
11 | * Copyright (C) 2006 Texas Instruments. | |
12 | * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com> | |
76a40ca8 BZ |
13 | */ |
14 | ||
15 | #include <linux/ata.h> | |
16 | #include <linux/clk.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/ioport.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/libata.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/types.h> | |
25 | ||
26 | #define DRV_NAME "pata_bk3710" | |
27 | ||
28 | #define BK3710_TF_OFFSET 0x1F0 | |
29 | #define BK3710_CTL_OFFSET 0x3F6 | |
30 | ||
31 | #define BK3710_BMISP 0x02 | |
32 | #define BK3710_IDETIMP 0x40 | |
33 | #define BK3710_UDMACTL 0x48 | |
34 | #define BK3710_MISCCTL 0x50 | |
35 | #define BK3710_REGSTB 0x54 | |
36 | #define BK3710_REGRCVR 0x58 | |
37 | #define BK3710_DATSTB 0x5C | |
38 | #define BK3710_DATRCVR 0x60 | |
39 | #define BK3710_DMASTB 0x64 | |
40 | #define BK3710_DMARCVR 0x68 | |
41 | #define BK3710_UDMASTB 0x6C | |
42 | #define BK3710_UDMATRP 0x70 | |
43 | #define BK3710_UDMAENV 0x74 | |
44 | #define BK3710_IORDYTMP 0x78 | |
45 | ||
46 | static struct scsi_host_template pata_bk3710_sht = { | |
47 | ATA_BMDMA_SHT(DRV_NAME), | |
48 | }; | |
49 | ||
50 | static unsigned int ideclk_period; /* in nanoseconds */ | |
51 | ||
52 | struct pata_bk3710_udmatiming { | |
53 | unsigned int rptime; /* tRP -- Ready to pause time (nsec) */ | |
54 | unsigned int cycletime; /* tCYCTYP2/2 -- avg Cycle Time (nsec) */ | |
55 | /* tENV is always a minimum of 20 nsec */ | |
56 | }; | |
57 | ||
58 | static const struct pata_bk3710_udmatiming pata_bk3710_udmatimings[6] = { | |
59 | { 160, 240 / 2 }, /* UDMA Mode 0 */ | |
60 | { 125, 160 / 2 }, /* UDMA Mode 1 */ | |
61 | { 100, 120 / 2 }, /* UDMA Mode 2 */ | |
62 | { 100, 90 / 2 }, /* UDMA Mode 3 */ | |
63 | { 100, 60 / 2 }, /* UDMA Mode 4 */ | |
64 | { 85, 40 / 2 }, /* UDMA Mode 5 */ | |
65 | }; | |
66 | ||
67 | static void pata_bk3710_setudmamode(void __iomem *base, unsigned int dev, | |
68 | unsigned int mode) | |
69 | { | |
70 | u32 val32; | |
71 | u16 val16; | |
72 | u8 tenv, trp, t0; | |
73 | ||
74 | /* DMA Data Setup */ | |
75 | t0 = DIV_ROUND_UP(pata_bk3710_udmatimings[mode].cycletime, | |
76 | ideclk_period) - 1; | |
77 | tenv = DIV_ROUND_UP(20, ideclk_period) - 1; | |
78 | trp = DIV_ROUND_UP(pata_bk3710_udmatimings[mode].rptime, | |
79 | ideclk_period) - 1; | |
80 | ||
81 | /* udmastb Ultra DMA Access Strobe Width */ | |
82 | val32 = ioread32(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8)); | |
83 | val32 |= t0 << (dev ? 8 : 0); | |
84 | iowrite32(val32, base + BK3710_UDMASTB); | |
85 | ||
86 | /* udmatrp Ultra DMA Ready to Pause Time */ | |
87 | val32 = ioread32(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8)); | |
88 | val32 |= trp << (dev ? 8 : 0); | |
89 | iowrite32(val32, base + BK3710_UDMATRP); | |
90 | ||
91 | /* udmaenv Ultra DMA envelop Time */ | |
92 | val32 = ioread32(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8)); | |
93 | val32 |= tenv << (dev ? 8 : 0); | |
94 | iowrite32(val32, base + BK3710_UDMAENV); | |
95 | ||
96 | /* Enable UDMA for Device */ | |
97 | val16 = ioread16(base + BK3710_UDMACTL) | (1 << dev); | |
98 | iowrite16(val16, base + BK3710_UDMACTL); | |
99 | } | |
100 | ||
101 | static void pata_bk3710_setmwdmamode(void __iomem *base, unsigned int dev, | |
102 | unsigned short min_cycle, | |
103 | unsigned int mode) | |
104 | { | |
105 | const struct ata_timing *t; | |
106 | int cycletime; | |
107 | u32 val32; | |
108 | u16 val16; | |
109 | u8 td, tkw, t0; | |
110 | ||
111 | t = ata_timing_find_mode(mode); | |
112 | cycletime = max_t(int, t->cycle, min_cycle); | |
113 | ||
114 | /* DMA Data Setup */ | |
115 | t0 = DIV_ROUND_UP(cycletime, ideclk_period); | |
116 | td = DIV_ROUND_UP(t->active, ideclk_period); | |
117 | tkw = t0 - td - 1; | |
118 | td--; | |
119 | ||
120 | val32 = ioread32(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8)); | |
121 | val32 |= td << (dev ? 8 : 0); | |
122 | iowrite32(val32, base + BK3710_DMASTB); | |
123 | ||
124 | val32 = ioread32(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8)); | |
125 | val32 |= tkw << (dev ? 8 : 0); | |
126 | iowrite32(val32, base + BK3710_DMARCVR); | |
127 | ||
128 | /* Disable UDMA for Device */ | |
129 | val16 = ioread16(base + BK3710_UDMACTL) & ~(1 << dev); | |
130 | iowrite16(val16, base + BK3710_UDMACTL); | |
131 | } | |
132 | ||
133 | static void pata_bk3710_set_dmamode(struct ata_port *ap, | |
134 | struct ata_device *adev) | |
135 | { | |
136 | void __iomem *base = (void __iomem *)ap->ioaddr.bmdma_addr; | |
137 | int is_slave = adev->devno; | |
138 | const u8 xferspeed = adev->dma_mode; | |
139 | ||
140 | if (xferspeed >= XFER_UDMA_0) | |
141 | pata_bk3710_setudmamode(base, is_slave, | |
142 | xferspeed - XFER_UDMA_0); | |
143 | else | |
144 | pata_bk3710_setmwdmamode(base, is_slave, | |
145 | adev->id[ATA_ID_EIDE_DMA_MIN], | |
146 | xferspeed); | |
147 | } | |
148 | ||
149 | static void pata_bk3710_setpiomode(void __iomem *base, struct ata_device *pair, | |
150 | unsigned int dev, unsigned int cycletime, | |
151 | unsigned int mode) | |
152 | { | |
153 | const struct ata_timing *t; | |
154 | u32 val32; | |
155 | u8 t2, t2i, t0; | |
156 | ||
157 | t = ata_timing_find_mode(XFER_PIO_0 + mode); | |
158 | ||
159 | /* PIO Data Setup */ | |
160 | t0 = DIV_ROUND_UP(cycletime, ideclk_period); | |
161 | t2 = DIV_ROUND_UP(t->active, ideclk_period); | |
162 | ||
163 | t2i = t0 - t2 - 1; | |
164 | t2--; | |
165 | ||
166 | val32 = ioread32(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8)); | |
167 | val32 |= t2 << (dev ? 8 : 0); | |
168 | iowrite32(val32, base + BK3710_DATSTB); | |
169 | ||
170 | val32 = ioread32(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8)); | |
171 | val32 |= t2i << (dev ? 8 : 0); | |
172 | iowrite32(val32, base + BK3710_DATRCVR); | |
173 | ||
174 | /* FIXME: this is broken also in the old driver */ | |
175 | if (pair) { | |
176 | u8 mode2 = pair->pio_mode - XFER_PIO_0; | |
177 | ||
178 | if (mode2 < mode) | |
179 | mode = mode2; | |
180 | } | |
181 | ||
182 | /* TASKFILE Setup */ | |
183 | t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period); | |
184 | t2 = DIV_ROUND_UP(t->act8b, ideclk_period); | |
185 | ||
186 | t2i = t0 - t2 - 1; | |
187 | t2--; | |
188 | ||
189 | val32 = ioread32(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8)); | |
190 | val32 |= t2 << (dev ? 8 : 0); | |
191 | iowrite32(val32, base + BK3710_REGSTB); | |
192 | ||
193 | val32 = ioread32(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8)); | |
194 | val32 |= t2i << (dev ? 8 : 0); | |
195 | iowrite32(val32, base + BK3710_REGRCVR); | |
196 | } | |
197 | ||
198 | static void pata_bk3710_set_piomode(struct ata_port *ap, | |
199 | struct ata_device *adev) | |
200 | { | |
201 | void __iomem *base = (void __iomem *)ap->ioaddr.bmdma_addr; | |
202 | struct ata_device *pair = ata_dev_pair(adev); | |
203 | const struct ata_timing *t = ata_timing_find_mode(adev->pio_mode); | |
204 | const u16 *id = adev->id; | |
205 | unsigned int cycle_time = 0; | |
206 | int is_slave = adev->devno; | |
207 | const u8 pio = adev->pio_mode - XFER_PIO_0; | |
208 | ||
209 | if (id[ATA_ID_FIELD_VALID] & 2) { | |
210 | if (ata_id_has_iordy(id)) | |
211 | cycle_time = id[ATA_ID_EIDE_PIO_IORDY]; | |
212 | else | |
213 | cycle_time = id[ATA_ID_EIDE_PIO]; | |
214 | ||
215 | /* conservative "downgrade" for all pre-ATA2 drives */ | |
216 | if (pio < 3 && cycle_time < t->cycle) | |
217 | cycle_time = 0; /* use standard timing */ | |
218 | } | |
219 | ||
220 | if (!cycle_time) | |
221 | cycle_time = t->cycle; | |
222 | ||
223 | pata_bk3710_setpiomode(base, pair, is_slave, cycle_time, pio); | |
224 | } | |
225 | ||
226 | static void pata_bk3710_chipinit(void __iomem *base) | |
227 | { | |
228 | /* | |
229 | * REVISIT: the ATA reset signal needs to be managed through a | |
230 | * GPIO, which means it should come from platform_data. Until | |
231 | * we get and use such information, we have to trust that things | |
232 | * have been reset before we get here. | |
233 | */ | |
234 | ||
235 | /* | |
236 | * Program the IDETIMP Register Value based on the following assumptions | |
237 | * | |
238 | * (ATA_IDETIMP_IDEEN , ENABLE ) | | |
239 | * (ATA_IDETIMP_PREPOST1 , DISABLE) | | |
240 | * (ATA_IDETIMP_PREPOST0 , DISABLE) | | |
241 | * | |
242 | * DM6446 silicon rev 2.1 and earlier have no observed net benefit | |
243 | * from enabling prefetch/postwrite. | |
244 | */ | |
245 | iowrite16(BIT(15), base + BK3710_IDETIMP); | |
246 | ||
247 | /* | |
248 | * UDMACTL Ultra-ATA DMA Control | |
249 | * (ATA_UDMACTL_UDMAP1 , 0 ) | | |
250 | * (ATA_UDMACTL_UDMAP0 , 0 ) | |
251 | * | |
252 | */ | |
253 | iowrite16(0, base + BK3710_UDMACTL); | |
254 | ||
255 | /* | |
256 | * MISCCTL Miscellaneous Conrol Register | |
257 | * (ATA_MISCCTL_HWNHLD1P , 1 cycle) | |
258 | * (ATA_MISCCTL_HWNHLD0P , 1 cycle) | |
259 | * (ATA_MISCCTL_TIMORIDE , 1) | |
260 | */ | |
261 | iowrite32(0x001, base + BK3710_MISCCTL); | |
262 | ||
263 | /* | |
264 | * IORDYTMP IORDY Timer for Primary Register | |
c217ff26 | 265 | * (ATA_IORDYTMP_IORDYTMP , DISABLE) |
76a40ca8 | 266 | */ |
c217ff26 | 267 | iowrite32(0, base + BK3710_IORDYTMP); |
76a40ca8 BZ |
268 | |
269 | /* | |
270 | * Configure BMISP Register | |
271 | * (ATA_BMISP_DMAEN1 , DISABLE ) | | |
272 | * (ATA_BMISP_DMAEN0 , DISABLE ) | | |
273 | * (ATA_BMISP_IORDYINT , CLEAR) | | |
274 | * (ATA_BMISP_INTRSTAT , CLEAR) | | |
275 | * (ATA_BMISP_DMAERROR , CLEAR) | |
276 | */ | |
396ff64d | 277 | iowrite16(0xE, base + BK3710_BMISP); |
76a40ca8 BZ |
278 | |
279 | pata_bk3710_setpiomode(base, NULL, 0, 600, 0); | |
280 | pata_bk3710_setpiomode(base, NULL, 1, 600, 0); | |
281 | } | |
282 | ||
283 | static struct ata_port_operations pata_bk3710_ports_ops = { | |
284 | .inherits = &ata_bmdma_port_ops, | |
285 | .cable_detect = ata_cable_80wire, | |
286 | ||
287 | .set_piomode = pata_bk3710_set_piomode, | |
288 | .set_dmamode = pata_bk3710_set_dmamode, | |
289 | }; | |
290 | ||
291 | static int __init pata_bk3710_probe(struct platform_device *pdev) | |
292 | { | |
293 | struct clk *clk; | |
294 | struct resource *mem; | |
295 | struct ata_host *host; | |
296 | struct ata_port *ap; | |
297 | void __iomem *base; | |
298 | unsigned long rate; | |
299 | int irq; | |
300 | ||
301 | clk = devm_clk_get(&pdev->dev, NULL); | |
302 | if (IS_ERR(clk)) | |
303 | return -ENODEV; | |
304 | ||
305 | clk_enable(clk); | |
306 | rate = clk_get_rate(clk); | |
307 | if (!rate) | |
308 | return -EINVAL; | |
309 | ||
310 | /* NOTE: round *down* to meet minimum timings; we count in clocks */ | |
311 | ideclk_period = 1000000000UL / rate; | |
312 | ||
313 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
314 | ||
315 | irq = platform_get_irq(pdev, 0); | |
316 | if (irq < 0) { | |
317 | pr_err(DRV_NAME ": failed to get IRQ resource\n"); | |
318 | return irq; | |
319 | } | |
320 | ||
321 | base = devm_ioremap_resource(&pdev->dev, mem); | |
322 | if (IS_ERR(base)) | |
323 | return PTR_ERR(base); | |
324 | ||
325 | /* configure the Palmchip controller */ | |
326 | pata_bk3710_chipinit(base); | |
327 | ||
328 | /* allocate host */ | |
329 | host = ata_host_alloc(&pdev->dev, 1); | |
330 | if (!host) | |
331 | return -ENOMEM; | |
332 | ap = host->ports[0]; | |
333 | ||
334 | ap->ops = &pata_bk3710_ports_ops; | |
335 | ap->pio_mask = ATA_PIO4; | |
336 | ap->mwdma_mask = ATA_MWDMA2; | |
337 | ap->udma_mask = rate < 100000000 ? ATA_UDMA4 : ATA_UDMA5; | |
338 | ap->flags |= ATA_FLAG_SLAVE_POSS; | |
339 | ||
340 | ap->ioaddr.data_addr = base + BK3710_TF_OFFSET; | |
341 | ap->ioaddr.error_addr = base + BK3710_TF_OFFSET + 1; | |
342 | ap->ioaddr.feature_addr = base + BK3710_TF_OFFSET + 1; | |
343 | ap->ioaddr.nsect_addr = base + BK3710_TF_OFFSET + 2; | |
344 | ap->ioaddr.lbal_addr = base + BK3710_TF_OFFSET + 3; | |
345 | ap->ioaddr.lbam_addr = base + BK3710_TF_OFFSET + 4; | |
346 | ap->ioaddr.lbah_addr = base + BK3710_TF_OFFSET + 5; | |
347 | ap->ioaddr.device_addr = base + BK3710_TF_OFFSET + 6; | |
348 | ap->ioaddr.status_addr = base + BK3710_TF_OFFSET + 7; | |
349 | ap->ioaddr.command_addr = base + BK3710_TF_OFFSET + 7; | |
350 | ||
351 | ap->ioaddr.altstatus_addr = base + BK3710_CTL_OFFSET; | |
352 | ap->ioaddr.ctl_addr = base + BK3710_CTL_OFFSET; | |
353 | ||
354 | ap->ioaddr.bmdma_addr = base; | |
355 | ||
356 | ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", | |
357 | (unsigned long)base + BK3710_TF_OFFSET, | |
358 | (unsigned long)base + BK3710_CTL_OFFSET); | |
359 | ||
360 | /* activate */ | |
361 | return ata_host_activate(host, irq, ata_sff_interrupt, 0, | |
362 | &pata_bk3710_sht); | |
363 | } | |
364 | ||
365 | /* work with hotplug and coldplug */ | |
366 | MODULE_ALIAS("platform:palm_bk3710"); | |
367 | ||
368 | static struct platform_driver pata_bk3710_driver = { | |
369 | .driver = { | |
370 | .name = "palm_bk3710", | |
371 | }, | |
372 | }; | |
373 | ||
374 | static int __init pata_bk3710_init(void) | |
375 | { | |
376 | return platform_driver_probe(&pata_bk3710_driver, pata_bk3710_probe); | |
377 | } | |
378 | ||
379 | module_init(pata_bk3710_init); | |
a80ea4cb | 380 | MODULE_LICENSE("GPL v2"); |