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libata: always do follow-up SRST if hardreset returned -EAGAIN
[linux-2.6-block.git] / drivers / ata / pata_bf54x.c
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d830d173
SZ		 1/*
2 * File: drivers/ata/pata_bf54x.c
3 * Author: Sonic Zhang <sonic.zhang@analog.com>
4 *
5 * Created:
6 * Description: PATA Driver for blackfin 54x
7 *
8 * Modified:
9 * Copyright 2007 Analog Devices Inc.
10 *
11 * Bugs: Enter bugs at http://blackfin.uclinux.org/
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, see the file COPYING, or write
25 * to the Free Software Foundation, Inc.,
26 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
27 */
28
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/init.h>
33#include <linux/blkdev.h>
34#include <linux/delay.h>
35#include <linux/device.h>
36#include <scsi/scsi_host.h>
37#include <linux/libata.h>
38#include <linux/platform_device.h>
39#include <asm/dma.h>
40#include <asm/gpio.h>
41#include <asm/portmux.h>
42
43#define DRV_NAME "pata-bf54x"
44#define DRV_VERSION "0.9"
45
46#define ATA_REG_CTRL 0x0E
47#define ATA_REG_ALTSTATUS ATA_REG_CTRL
48
49/* These are the offset of the controller's registers */
50#define ATAPI_OFFSET_CONTROL 0x00
51#define ATAPI_OFFSET_STATUS 0x04
52#define ATAPI_OFFSET_DEV_ADDR 0x08
53#define ATAPI_OFFSET_DEV_TXBUF 0x0c
54#define ATAPI_OFFSET_DEV_RXBUF 0x10
55#define ATAPI_OFFSET_INT_MASK 0x14
56#define ATAPI_OFFSET_INT_STATUS 0x18
57#define ATAPI_OFFSET_XFER_LEN 0x1c
58#define ATAPI_OFFSET_LINE_STATUS 0x20
59#define ATAPI_OFFSET_SM_STATE 0x24
60#define ATAPI_OFFSET_TERMINATE 0x28
61#define ATAPI_OFFSET_PIO_TFRCNT 0x2c
62#define ATAPI_OFFSET_DMA_TFRCNT 0x30
63#define ATAPI_OFFSET_UMAIN_TFRCNT 0x34
64#define ATAPI_OFFSET_UDMAOUT_TFRCNT 0x38
65#define ATAPI_OFFSET_REG_TIM_0 0x40
66#define ATAPI_OFFSET_PIO_TIM_0 0x44
67#define ATAPI_OFFSET_PIO_TIM_1 0x48
68#define ATAPI_OFFSET_MULTI_TIM_0 0x50
69#define ATAPI_OFFSET_MULTI_TIM_1 0x54
70#define ATAPI_OFFSET_MULTI_TIM_2 0x58
71#define ATAPI_OFFSET_ULTRA_TIM_0 0x60
72#define ATAPI_OFFSET_ULTRA_TIM_1 0x64
73#define ATAPI_OFFSET_ULTRA_TIM_2 0x68
74#define ATAPI_OFFSET_ULTRA_TIM_3 0x6c
75
76
77#define ATAPI_GET_CONTROL(base)\
78 bfin_read16(base + ATAPI_OFFSET_CONTROL)
79#define ATAPI_SET_CONTROL(base, val)\
80 bfin_write16(base + ATAPI_OFFSET_CONTROL, val)
81#define ATAPI_GET_STATUS(base)\
82 bfin_read16(base + ATAPI_OFFSET_STATUS)
83#define ATAPI_GET_DEV_ADDR(base)\
84 bfin_read16(base + ATAPI_OFFSET_DEV_ADDR)
85#define ATAPI_SET_DEV_ADDR(base, val)\
86 bfin_write16(base + ATAPI_OFFSET_DEV_ADDR, val)
87#define ATAPI_GET_DEV_TXBUF(base)\
88 bfin_read16(base + ATAPI_OFFSET_DEV_TXBUF)
89#define ATAPI_SET_DEV_TXBUF(base, val)\
90 bfin_write16(base + ATAPI_OFFSET_DEV_TXBUF, val)
91#define ATAPI_GET_DEV_RXBUF(base)\
92 bfin_read16(base + ATAPI_OFFSET_DEV_RXBUF)
93#define ATAPI_SET_DEV_RXBUF(base, val)\
94 bfin_write16(base + ATAPI_OFFSET_DEV_RXBUF, val)
95#define ATAPI_GET_INT_MASK(base)\
96 bfin_read16(base + ATAPI_OFFSET_INT_MASK)
97#define ATAPI_SET_INT_MASK(base, val)\
98 bfin_write16(base + ATAPI_OFFSET_INT_MASK, val)
99#define ATAPI_GET_INT_STATUS(base)\
100 bfin_read16(base + ATAPI_OFFSET_INT_STATUS)
101#define ATAPI_SET_INT_STATUS(base, val)\
102 bfin_write16(base + ATAPI_OFFSET_INT_STATUS, val)
103#define ATAPI_GET_XFER_LEN(base)\
104 bfin_read16(base + ATAPI_OFFSET_XFER_LEN)
105#define ATAPI_SET_XFER_LEN(base, val)\
106 bfin_write16(base + ATAPI_OFFSET_XFER_LEN, val)
107#define ATAPI_GET_LINE_STATUS(base)\
108 bfin_read16(base + ATAPI_OFFSET_LINE_STATUS)
109#define ATAPI_GET_SM_STATE(base)\
110 bfin_read16(base + ATAPI_OFFSET_SM_STATE)
111#define ATAPI_GET_TERMINATE(base)\
112 bfin_read16(base + ATAPI_OFFSET_TERMINATE)
113#define ATAPI_SET_TERMINATE(base, val)\
114 bfin_write16(base + ATAPI_OFFSET_TERMINATE, val)
115#define ATAPI_GET_PIO_TFRCNT(base)\
116 bfin_read16(base + ATAPI_OFFSET_PIO_TFRCNT)
117#define ATAPI_GET_DMA_TFRCNT(base)\
118 bfin_read16(base + ATAPI_OFFSET_DMA_TFRCNT)
119#define ATAPI_GET_UMAIN_TFRCNT(base)\
120 bfin_read16(base + ATAPI_OFFSET_UMAIN_TFRCNT)
121#define ATAPI_GET_UDMAOUT_TFRCNT(base)\
122 bfin_read16(base + ATAPI_OFFSET_UDMAOUT_TFRCNT)
123#define ATAPI_GET_REG_TIM_0(base)\
124 bfin_read16(base + ATAPI_OFFSET_REG_TIM_0)
125#define ATAPI_SET_REG_TIM_0(base, val)\
126 bfin_write16(base + ATAPI_OFFSET_REG_TIM_0, val)
127#define ATAPI_GET_PIO_TIM_0(base)\
128 bfin_read16(base + ATAPI_OFFSET_PIO_TIM_0)
129#define ATAPI_SET_PIO_TIM_0(base, val)\
130 bfin_write16(base + ATAPI_OFFSET_PIO_TIM_0, val)
131#define ATAPI_GET_PIO_TIM_1(base)\
132 bfin_read16(base + ATAPI_OFFSET_PIO_TIM_1)
133#define ATAPI_SET_PIO_TIM_1(base, val)\
134 bfin_write16(base + ATAPI_OFFSET_PIO_TIM_1, val)
135#define ATAPI_GET_MULTI_TIM_0(base)\
136 bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_0)
137#define ATAPI_SET_MULTI_TIM_0(base, val)\
138 bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_0, val)
139#define ATAPI_GET_MULTI_TIM_1(base)\
140 bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_1)
141#define ATAPI_SET_MULTI_TIM_1(base, val)\
142 bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_1, val)
143#define ATAPI_GET_MULTI_TIM_2(base)\
144 bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_2)
145#define ATAPI_SET_MULTI_TIM_2(base, val)\
146 bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_2, val)
147#define ATAPI_GET_ULTRA_TIM_0(base)\
148 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_0)
149#define ATAPI_SET_ULTRA_TIM_0(base, val)\
150 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_0, val)
151#define ATAPI_GET_ULTRA_TIM_1(base)\
152 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_1)
153#define ATAPI_SET_ULTRA_TIM_1(base, val)\
154 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_1, val)
155#define ATAPI_GET_ULTRA_TIM_2(base)\
156 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_2)
157#define ATAPI_SET_ULTRA_TIM_2(base, val)\
158 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_2, val)
159#define ATAPI_GET_ULTRA_TIM_3(base)\
160 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_3)
161#define ATAPI_SET_ULTRA_TIM_3(base, val)\
162 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_3, val)
163
164/**
165 * PIO Mode - Frequency compatibility
166 */
167/* mode: 0 1 2 3 4 */
168static const u32 pio_fsclk[] =
169{ 33333333, 33333333, 33333333, 33333333, 33333333 };
170
171/**
172 * MDMA Mode - Frequency compatibility
173 */
174/* mode: 0 1 2 */
175static const u32 mdma_fsclk[] = { 33333333, 33333333, 33333333 };
176
177/**
178 * UDMA Mode - Frequency compatibility
179 *
180 * UDMA5 - 100 MB/s - SCLK = 133 MHz
181 * UDMA4 - 66 MB/s - SCLK >= 80 MHz
182 * UDMA3 - 44.4 MB/s - SCLK >= 50 MHz
183 * UDMA2 - 33 MB/s - SCLK >= 40 MHz
184 */
185/* mode: 0 1 2 3 4 5 */
186static const u32 udma_fsclk[] =
187{ 33333333, 33333333, 40000000, 50000000, 80000000, 133333333 };
188
189/**
190 * Register transfer timing table
191 */
192/* mode: 0 1 2 3 4 */
193/* Cycle Time */
194static const u32 reg_t0min[] = { 600, 383, 330, 180, 120 };
195/* DIOR/DIOW to end cycle */
196static const u32 reg_t2min[] = { 290, 290, 290, 70, 25 };
197/* DIOR/DIOW asserted pulse width */
198static const u32 reg_teocmin[] = { 290, 290, 290, 80, 70 };
199
200/**
201 * PIO timing table
202 */
203/* mode: 0 1 2 3 4 */
204/* Cycle Time */
205static const u32 pio_t0min[] = { 600, 383, 240, 180, 120 };
206/* Address valid to DIOR/DIORW */
207static const u32 pio_t1min[] = { 70, 50, 30, 30, 25 };
208/* DIOR/DIOW to end cycle */
209static const u32 pio_t2min[] = { 165, 125, 100, 80, 70 };
210/* DIOR/DIOW asserted pulse width */
211static const u32 pio_teocmin[] = { 165, 125, 100, 70, 25 };
212/* DIOW data hold */
213static const u32 pio_t4min[] = { 30, 20, 15, 10, 10 };
214
215/* ******************************************************************
216 * Multiword DMA timing table
217 * ******************************************************************
218 */
219/* mode: 0 1 2 */
220/* Cycle Time */
221static const u32 mdma_t0min[] = { 480, 150, 120 };
222/* DIOR/DIOW asserted pulse width */
223static const u32 mdma_tdmin[] = { 215, 80, 70 };
224/* DMACK to read data released */
225static const u32 mdma_thmin[] = { 20, 15, 10 };
226/* DIOR/DIOW to DMACK hold */
227static const u32 mdma_tjmin[] = { 20, 5, 5 };
228/* DIOR negated pulse width */
229static const u32 mdma_tkrmin[] = { 50, 50, 25 };
230/* DIOR negated pulse width */
231static const u32 mdma_tkwmin[] = { 215, 50, 25 };
232/* CS[1:0] valid to DIOR/DIOW */
233static const u32 mdma_tmmin[] = { 50, 30, 25 };
234/* DMACK to read data released */
235static const u32 mdma_tzmax[] = { 20, 25, 25 };
236
237/**
238 * Ultra DMA timing table
239 */
240/* mode: 0 1 2 3 4 5 */
241static const u32 udma_tcycmin[] = { 112, 73, 54, 39, 25, 17 };
242static const u32 udma_tdvsmin[] = { 70, 48, 31, 20, 7, 5 };
243static const u32 udma_tenvmax[] = { 70, 70, 70, 55, 55, 50 };
244static const u32 udma_trpmin[] = { 160, 125, 100, 100, 100, 85 };
245static const u32 udma_tmin[] = { 5, 5, 5, 5, 3, 3 };
246
247
248static const u32 udma_tmlimin = 20;
249static const u32 udma_tzahmin = 20;
250static const u32 udma_tenvmin = 20;
251static const u32 udma_tackmin = 20;
252static const u32 udma_tssmin = 50;
253
254/**
255 *
256 * Function: num_clocks_min
257 *
258 * Description:
259 * calculate number of SCLK cycles to meet minimum timing
260 */
261static unsigned short num_clocks_min(unsigned long tmin,
262 unsigned long fsclk)
263{
264 unsigned long tmp ;
265 unsigned short result;
266
267 tmp = tmin * (fsclk/1000/1000) / 1000;
268 result = (unsigned short)tmp;
269 if ((tmp*1000*1000) < (tmin*(fsclk/1000))) {
270 result++;
271 }
272
273 return result;
274}
275
276/**
277 * bfin_set_piomode - Initialize host controller PATA PIO timings
278 * @ap: Port whose timings we are configuring
279 * @adev: um
280 *
281 * Set PIO mode for device.
282 *
283 * LOCKING:
284 * None (inherited from caller).
285 */
286
287static void bfin_set_piomode(struct ata_port *ap, struct ata_device *adev)
288{
289 int mode = adev->pio_mode - XFER_PIO_0;
290 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
291 unsigned int fsclk = get_sclk();
292 unsigned short teoc_reg, t2_reg, teoc_pio;
293 unsigned short t4_reg, t2_pio, t1_reg;
294 unsigned short n0, n6, t6min = 5;
295
296 /* the most restrictive timing value is t6 and tc, the DIOW - data hold
297 * If one SCLK pulse is longer than this minimum value then register
298 * transfers cannot be supported at this frequency.
299 */
300 n6 = num_clocks_min(t6min, fsclk);
301 if (mode >= 0 && mode <= 4 && n6 >= 1) {
9f24e82d 302 dev_dbg(adev->link->ap->dev, "set piomode: mode=%d, fsclk=%ud\n", mode, fsclk);
d830d173
SZ		 303 /* calculate the timing values for register transfers. */
304 while (mode > 0 && pio_fsclk[mode] > fsclk)
305 mode--;
306
307 /* DIOR/DIOW to end cycle time */
308 t2_reg = num_clocks_min(reg_t2min[mode], fsclk);
309 /* DIOR/DIOW asserted pulse width */
310 teoc_reg = num_clocks_min(reg_teocmin[mode], fsclk);
311 /* Cycle Time */
312 n0 = num_clocks_min(reg_t0min[mode], fsclk);
313
314 /* increase t2 until we meed the minimum cycle length */
315 if (t2_reg + teoc_reg < n0)
316 t2_reg = n0 - teoc_reg;
317
318 /* calculate the timing values for pio transfers. */
319
320 /* DIOR/DIOW to end cycle time */
321 t2_pio = num_clocks_min(pio_t2min[mode], fsclk);
322 /* DIOR/DIOW asserted pulse width */
323 teoc_pio = num_clocks_min(pio_teocmin[mode], fsclk);
324 /* Cycle Time */
325 n0 = num_clocks_min(pio_t0min[mode], fsclk);
326
327 /* increase t2 until we meed the minimum cycle length */
328 if (t2_pio + teoc_pio < n0)
329 t2_pio = n0 - teoc_pio;
330
331 /* Address valid to DIOR/DIORW */
332 t1_reg = num_clocks_min(pio_t1min[mode], fsclk);
333
334 /* DIOW data hold */
335 t4_reg = num_clocks_min(pio_t4min[mode], fsclk);
336
337 ATAPI_SET_REG_TIM_0(base, (teoc_reg<<8 | t2_reg));
338 ATAPI_SET_PIO_TIM_0(base, (t4_reg<<12 | t2_pio<<4 | t1_reg));
339 ATAPI_SET_PIO_TIM_1(base, teoc_pio);
340 if (mode > 2) {
341 ATAPI_SET_CONTROL(base,
342 ATAPI_GET_CONTROL(base) | IORDY_EN);
343 } else {
344 ATAPI_SET_CONTROL(base,
345 ATAPI_GET_CONTROL(base) & ~IORDY_EN);
346 }
347
348 /* Disable host ATAPI PIO interrupts */
349 ATAPI_SET_INT_MASK(base, ATAPI_GET_INT_MASK(base)
350 & ~(PIO_DONE_MASK | HOST_TERM_XFER_MASK));
351 SSYNC();
352 }
353}
354
355/**
356 * bfin_set_dmamode - Initialize host controller PATA DMA timings
357 * @ap: Port whose timings we are configuring
358 * @adev: um
359 * @udma: udma mode, 0 - 6
360 *
361 * Set UDMA mode for device.
362 *
363 * LOCKING:
364 * None (inherited from caller).
365 */
366
367static void bfin_set_dmamode(struct ata_port *ap, struct ata_device *adev)
368{
369 int mode;
370 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
371 unsigned long fsclk = get_sclk();
372 unsigned short tenv, tack, tcyc_tdvs, tdvs, tmli, tss, trp, tzah;
373 unsigned short tm, td, tkr, tkw, teoc, th;
374 unsigned short n0, nf, tfmin = 5;
375 unsigned short nmin, tcyc;
376
377 mode = adev->dma_mode - XFER_UDMA_0;
378 if (mode >= 0 && mode <= 5) {
9f24e82d 379 dev_dbg(adev->link->ap->dev, "set udmamode: mode=%d\n", mode);
d830d173
SZ		 380 /* the most restrictive timing value is t6 and tc,
381 * the DIOW - data hold. If one SCLK pulse is longer
382 * than this minimum value then register
383 * transfers cannot be supported at this frequency.
384 */
385 while (mode > 0 && udma_fsclk[mode] > fsclk)
386 mode--;
387
388 nmin = num_clocks_min(udma_tmin[mode], fsclk);
389 if (nmin >= 1) {
390 /* calculate the timing values for Ultra DMA. */
391 tdvs = num_clocks_min(udma_tdvsmin[mode], fsclk);
392 tcyc = num_clocks_min(udma_tcycmin[mode], fsclk);
393 tcyc_tdvs = 2;
394
395 /* increase tcyc - tdvs (tcyc_tdvs) until we meed
396 * the minimum cycle length
397 */
398 if (tdvs + tcyc_tdvs < tcyc)
399 tcyc_tdvs = tcyc - tdvs;
400
401 /* Mow assign the values required for the timing
402 * registers
403 */
404 if (tcyc_tdvs < 2)
405 tcyc_tdvs = 2;
406
407 if (tdvs < 2)
408 tdvs = 2;
409
410 tack = num_clocks_min(udma_tackmin, fsclk);
411 tss = num_clocks_min(udma_tssmin, fsclk);
412 tmli = num_clocks_min(udma_tmlimin, fsclk);
413 tzah = num_clocks_min(udma_tzahmin, fsclk);
414 trp = num_clocks_min(udma_trpmin[mode], fsclk);
415 tenv = num_clocks_min(udma_tenvmin, fsclk);
416 if (tenv <= udma_tenvmax[mode]) {
417 ATAPI_SET_ULTRA_TIM_0(base, (tenv<<8 | tack));
418 ATAPI_SET_ULTRA_TIM_1(base,
419 (tcyc_tdvs<<8 | tdvs));
420 ATAPI_SET_ULTRA_TIM_2(base, (tmli<<8 | tss));
421 ATAPI_SET_ULTRA_TIM_3(base, (trp<<8 | tzah));
422
423 /* Enable host ATAPI Untra DMA interrupts */
424 ATAPI_SET_INT_MASK(base,
425 ATAPI_GET_INT_MASK(base)
426 | UDMAIN_DONE_MASK
427 | UDMAOUT_DONE_MASK
428 | UDMAIN_TERM_MASK
429 | UDMAOUT_TERM_MASK);
430 }
431 }
432 }
433
434 mode = adev->dma_mode - XFER_MW_DMA_0;
435 if (mode >= 0 && mode <= 2) {
9f24e82d 436 dev_dbg(adev->link->ap->dev, "set mdmamode: mode=%d\n", mode);
d830d173
SZ		 437 /* the most restrictive timing value is tf, the DMACK to
438 * read data released. If one SCLK pulse is longer than
439 * this maximum value then the MDMA mode
440 * cannot be supported at this frequency.
441 */
442 while (mode > 0 && mdma_fsclk[mode] > fsclk)
443 mode--;
444
445 nf = num_clocks_min(tfmin, fsclk);
446 if (nf >= 1) {
447 /* calculate the timing values for Multi-word DMA. */
448
449 /* DIOR/DIOW asserted pulse width */
450 td = num_clocks_min(mdma_tdmin[mode], fsclk);
451
452 /* DIOR negated pulse width */
453 tkw = num_clocks_min(mdma_tkwmin[mode], fsclk);
454
455 /* Cycle Time */
456 n0 = num_clocks_min(mdma_t0min[mode], fsclk);
457
458 /* increase tk until we meed the minimum cycle length */
459 if (tkw + td < n0)
460 tkw = n0 - td;
461
462 /* DIOR negated pulse width - read */
463 tkr = num_clocks_min(mdma_tkrmin[mode], fsclk);
464 /* CS{1:0] valid to DIOR/DIOW */
465 tm = num_clocks_min(mdma_tmmin[mode], fsclk);
466 /* DIOR/DIOW to DMACK hold */
467 teoc = num_clocks_min(mdma_tjmin[mode], fsclk);
468 /* DIOW Data hold */
469 th = num_clocks_min(mdma_thmin[mode], fsclk);
470
471 ATAPI_SET_MULTI_TIM_0(base, (tm<<8 | td));
472 ATAPI_SET_MULTI_TIM_1(base, (tkr<<8 | tkw));
473 ATAPI_SET_MULTI_TIM_2(base, (teoc<<8 | th));
474
475 /* Enable host ATAPI Multi DMA interrupts */
476 ATAPI_SET_INT_MASK(base, ATAPI_GET_INT_MASK(base)
477 | MULTI_DONE_MASK | MULTI_TERM_MASK);
478 SSYNC();
479 }
480 }
481 return;
482}
483
484/**
485 *
486 * Function: wait_complete
487 *
488 * Description: Waits the interrupt from device
489 *
490 */
491static inline void wait_complete(void __iomem *base, unsigned short mask)
492{
493 unsigned short status;
494 unsigned int i = 0;
495
496#define PATA_BF54X_WAIT_TIMEOUT 10000
497
498 for (i = 0; i < PATA_BF54X_WAIT_TIMEOUT; i++) {
499 status = ATAPI_GET_INT_STATUS(base) & mask;
500 if (status)
501 break;
502 }
503
504 ATAPI_SET_INT_STATUS(base, mask);
505}
506
507/**
508 *
509 * Function: write_atapi_register
510 *
511 * Description: Writes to ATA Device Resgister
512 *
513 */
514
515static void write_atapi_register(void __iomem *base,
516 unsigned long ata_reg, unsigned short value)
517{
518 /* Program the ATA_DEV_TXBUF register with write data (to be
519 * written into the device).
520 */
521 ATAPI_SET_DEV_TXBUF(base, value);
522
523 /* Program the ATA_DEV_ADDR register with address of the
524 * device register (0x01 to 0x0F).
525 */
526 ATAPI_SET_DEV_ADDR(base, ata_reg);
527
528 /* Program the ATA_CTRL register with dir set to write (1)
529 */
530 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR));
531
532 /* ensure PIO DMA is not set */
533 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
534
535 /* and start the transfer */
536 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
537
538 /* Wait for the interrupt to indicate the end of the transfer.
539 * (We need to wait on and clear rhe ATA_DEV_INT interrupt status)
540 */
541 wait_complete(base, PIO_DONE_INT);
542}
543
544/**
545 *
546 * Function: read_atapi_register
547 *
548 *Description: Reads from ATA Device Resgister
549 *
550 */
551
552static unsigned short read_atapi_register(void __iomem *base,
553 unsigned long ata_reg)
554{
555 /* Program the ATA_DEV_ADDR register with address of the
556 * device register (0x01 to 0x0F).
557 */
558 ATAPI_SET_DEV_ADDR(base, ata_reg);
559
560 /* Program the ATA_CTRL register with dir set to read (0) and
561 */
562 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR));
563
564 /* ensure PIO DMA is not set */
565 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
566
567 /* and start the transfer */
568 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
569
570 /* Wait for the interrupt to indicate the end of the transfer.
571 * (PIO_DONE interrupt is set and it doesn't seem to matter
572 * that we don't clear it)
573 */
574 wait_complete(base, PIO_DONE_INT);
575
576 /* Read the ATA_DEV_RXBUF register with write data (to be
577 * written into the device).
578 */
579 return ATAPI_GET_DEV_RXBUF(base);
580}
581
582/**
583 *
584 * Function: write_atapi_register_data
585 *
586 * Description: Writes to ATA Device Resgister
587 *
588 */
589
590static void write_atapi_data(void __iomem *base,
591 int len, unsigned short *buf)
592{
593 int i;
594
595 /* Set transfer length to 1 */
596 ATAPI_SET_XFER_LEN(base, 1);
597
598 /* Program the ATA_DEV_ADDR register with address of the
599 * ATA_REG_DATA
600 */
601 ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);
602
603 /* Program the ATA_CTRL register with dir set to write (1)
604 */
605 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR));
606
607 /* ensure PIO DMA is not set */
608 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
609
610 for (i = 0; i < len; i++) {
611 /* Program the ATA_DEV_TXBUF register with write data (to be
612 * written into the device).
613 */
614 ATAPI_SET_DEV_TXBUF(base, buf[i]);
615
616 /* and start the transfer */
617 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
618
619 /* Wait for the interrupt to indicate the end of the transfer.
620 * (We need to wait on and clear rhe ATA_DEV_INT
621 * interrupt status)
622 */
623 wait_complete(base, PIO_DONE_INT);
624 }
625}
626
627/**
628 *
629 * Function: read_atapi_register_data
630 *
631 * Description: Reads from ATA Device Resgister
632 *
633 */
634
635static void read_atapi_data(void __iomem *base,
636 int len, unsigned short *buf)
637{
638 int i;
639
640 /* Set transfer length to 1 */
641 ATAPI_SET_XFER_LEN(base, 1);
642
643 /* Program the ATA_DEV_ADDR register with address of the
644 * ATA_REG_DATA
645 */
646 ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);
647
648 /* Program the ATA_CTRL register with dir set to read (0) and
649 */
650 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR));
651
652 /* ensure PIO DMA is not set */
653 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
654
655 for (i = 0; i < len; i++) {
656 /* and start the transfer */
657 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
658
659 /* Wait for the interrupt to indicate the end of the transfer.
660 * (PIO_DONE interrupt is set and it doesn't seem to matter
661 * that we don't clear it)
662 */
663 wait_complete(base, PIO_DONE_INT);
664
665 /* Read the ATA_DEV_RXBUF register with write data (to be
666 * written into the device).
667 */
668 buf[i] = ATAPI_GET_DEV_RXBUF(base);
669 }
670}
671
672/**
673 * bfin_tf_load - send taskfile registers to host controller
674 * @ap: Port to which output is sent
675 * @tf: ATA taskfile register set
676 *
9363c382 677 * Note: Original code is ata_sff_tf_load().
d830d173
SZ		 678 */
679
680static void bfin_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
681{
682 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
683 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
684
685 if (tf->ctl != ap->last_ctl) {
686 write_atapi_register(base, ATA_REG_CTRL, tf->ctl);
687 ap->last_ctl = tf->ctl;
688 ata_wait_idle(ap);
689 }
690
691 if (is_addr) {
692 if (tf->flags & ATA_TFLAG_LBA48) {
693 write_atapi_register(base, ATA_REG_FEATURE,
694 tf->hob_feature);
695 write_atapi_register(base, ATA_REG_NSECT,
696 tf->hob_nsect);
697 write_atapi_register(base, ATA_REG_LBAL, tf->hob_lbal);
698 write_atapi_register(base, ATA_REG_LBAM, tf->hob_lbam);
699 write_atapi_register(base, ATA_REG_LBAH, tf->hob_lbah);
f9204112 700 dev_dbg(ap->dev, "hob: feat 0x%X nsect 0x%X, lba 0x%X "
d830d173
SZ		 701 "0x%X 0x%X\n",
702 tf->hob_feature,
703 tf->hob_nsect,
704 tf->hob_lbal,
705 tf->hob_lbam,
706 tf->hob_lbah);
707 }
708
709 write_atapi_register(base, ATA_REG_FEATURE, tf->feature);
710 write_atapi_register(base, ATA_REG_NSECT, tf->nsect);
711 write_atapi_register(base, ATA_REG_LBAL, tf->lbal);
712 write_atapi_register(base, ATA_REG_LBAM, tf->lbam);
713 write_atapi_register(base, ATA_REG_LBAH, tf->lbah);
f9204112 714 dev_dbg(ap->dev, "feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
d830d173
SZ		 715 tf->feature,
716 tf->nsect,
717 tf->lbal,
718 tf->lbam,
719 tf->lbah);
720 }
721
722 if (tf->flags & ATA_TFLAG_DEVICE) {
723 write_atapi_register(base, ATA_REG_DEVICE, tf->device);
f9204112 724 dev_dbg(ap->dev, "device 0x%X\n", tf->device);
d830d173
SZ		 725 }
726
727 ata_wait_idle(ap);
728}
729
730/**
731 * bfin_check_status - Read device status reg & clear interrupt
732 * @ap: port where the device is
733 *
734 * Note: Original code is ata_check_status().
735 */
736
737static u8 bfin_check_status(struct ata_port *ap)
738{
739 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
740 return read_atapi_register(base, ATA_REG_STATUS);
741}
742
743/**
744 * bfin_tf_read - input device's ATA taskfile shadow registers
745 * @ap: Port from which input is read
746 * @tf: ATA taskfile register set for storing input
747 *
9363c382 748 * Note: Original code is ata_sff_tf_read().
d830d173
SZ		 749 */
750
751static void bfin_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
752{
753 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
754
755 tf->command = bfin_check_status(ap);
756 tf->feature = read_atapi_register(base, ATA_REG_ERR);
757 tf->nsect = read_atapi_register(base, ATA_REG_NSECT);
758 tf->lbal = read_atapi_register(base, ATA_REG_LBAL);
759 tf->lbam = read_atapi_register(base, ATA_REG_LBAM);
760 tf->lbah = read_atapi_register(base, ATA_REG_LBAH);
761 tf->device = read_atapi_register(base, ATA_REG_DEVICE);
762
763 if (tf->flags & ATA_TFLAG_LBA48) {
764 write_atapi_register(base, ATA_REG_CTRL, tf->ctl | ATA_HOB);
765 tf->hob_feature = read_atapi_register(base, ATA_REG_ERR);
766 tf->hob_nsect = read_atapi_register(base, ATA_REG_NSECT);
767 tf->hob_lbal = read_atapi_register(base, ATA_REG_LBAL);
768 tf->hob_lbam = read_atapi_register(base, ATA_REG_LBAM);
769 tf->hob_lbah = read_atapi_register(base, ATA_REG_LBAH);
770 }
771}
772
773/**
774 * bfin_exec_command - issue ATA command to host controller
775 * @ap: port to which command is being issued
776 * @tf: ATA taskfile register set
777 *
9363c382 778 * Note: Original code is ata_sff_exec_command().
d830d173
SZ		 779 */
780
781static void bfin_exec_command(struct ata_port *ap,
782 const struct ata_taskfile *tf)
783{
784 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
f9204112 785 dev_dbg(ap->dev, "ata%u: cmd 0x%X\n", ap->print_id, tf->command);
d830d173
SZ		 786
787 write_atapi_register(base, ATA_REG_CMD, tf->command);
9363c382 788 ata_sff_pause(ap);
d830d173
SZ		 789}
790
791/**
792 * bfin_check_altstatus - Read device alternate status reg
793 * @ap: port where the device is
794 */
795
796static u8 bfin_check_altstatus(struct ata_port *ap)
797{
798 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
799 return read_atapi_register(base, ATA_REG_ALTSTATUS);
800}
801
802/**
9363c382 803 * bfin_dev_select - Select device 0/1 on ATA bus
d830d173
SZ		 804 * @ap: ATA channel to manipulate
805 * @device: ATA device (numbered from zero) to select
806 *
9363c382 807 * Note: Original code is ata_sff_dev_select().
d830d173
SZ		 808 */
809
9363c382 810static void bfin_dev_select(struct ata_port *ap, unsigned int device)
d830d173
SZ		 811{
812 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
813 u8 tmp;
814
815 if (device == 0)
816 tmp = ATA_DEVICE_OBS;
817 else
818 tmp = ATA_DEVICE_OBS | ATA_DEV1;
819
820 write_atapi_register(base, ATA_REG_DEVICE, tmp);
9363c382 821 ata_sff_pause(ap);
d830d173
SZ		 822}
823
824/**
825 * bfin_bmdma_setup - Set up IDE DMA transaction
826 * @qc: Info associated with this ATA transaction.
827 *
828 * Note: Original code is ata_bmdma_setup().
829 */
830
831static void bfin_bmdma_setup(struct ata_queued_cmd *qc)
832{
833 unsigned short config = WDSIZE_16;
834 struct scatterlist *sg;
ff2aeb1e 835 unsigned int si;
d830d173 836
f9204112 837 dev_dbg(qc->ap->dev, "in atapi dma setup\n");
d830d173
SZ		 838 /* Program the ATA_CTRL register with dir */
839 if (qc->tf.flags & ATA_TFLAG_WRITE) {
840 /* fill the ATAPI DMA controller */
841 set_dma_config(CH_ATAPI_TX, config);
842 set_dma_x_modify(CH_ATAPI_TX, 2);
ff2aeb1e 843 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d830d173
SZ		 844 set_dma_start_addr(CH_ATAPI_TX, sg_dma_address(sg));
845 set_dma_x_count(CH_ATAPI_TX, sg_dma_len(sg) >> 1);
846 }
847 } else {
848 config |= WNR;
849 /* fill the ATAPI DMA controller */
850 set_dma_config(CH_ATAPI_RX, config);
851 set_dma_x_modify(CH_ATAPI_RX, 2);
ff2aeb1e 852 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d830d173
SZ		 853 set_dma_start_addr(CH_ATAPI_RX, sg_dma_address(sg));
854 set_dma_x_count(CH_ATAPI_RX, sg_dma_len(sg) >> 1);
855 }
856 }
857}
858
859/**
860 * bfin_bmdma_start - Start an IDE DMA transaction
861 * @qc: Info associated with this ATA transaction.
862 *
863 * Note: Original code is ata_bmdma_start().
864 */
865
866static void bfin_bmdma_start(struct ata_queued_cmd *qc)
867{
868 struct ata_port *ap = qc->ap;
869 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
870 struct scatterlist *sg;
ff2aeb1e 871 unsigned int si;
d830d173 872
f9204112 873 dev_dbg(qc->ap->dev, "in atapi dma start\n");
d830d173
SZ		 874 if (!(ap->udma_mask || ap->mwdma_mask))
875 return;
876
877 /* start ATAPI DMA controller*/
878 if (qc->tf.flags & ATA_TFLAG_WRITE) {
879 /*
880 * On blackfin arch, uncacheable memory is not
881 * allocated with flag GFP_DMA. DMA buffer from
882 * common kenel code should be flushed if WB
883 * data cache is enabled. Otherwise, this loop
884 * is an empty loop and optimized out.
885 */
ff2aeb1e 886 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d830d173
SZ		 887 flush_dcache_range(sg_dma_address(sg),
888 sg_dma_address(sg) + sg_dma_len(sg));
889 }
890 enable_dma(CH_ATAPI_TX);
f9204112 891 dev_dbg(qc->ap->dev, "enable udma write\n");
d830d173
SZ		 892
893 /* Send ATA DMA write command */
894 bfin_exec_command(ap, &qc->tf);
895
896 /* set ATA DMA write direction */
897 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base)
898 | XFER_DIR));
899 } else {
900 enable_dma(CH_ATAPI_RX);
f9204112 901 dev_dbg(qc->ap->dev, "enable udma read\n");
d830d173
SZ		 902
903 /* Send ATA DMA read command */
904 bfin_exec_command(ap, &qc->tf);
905
906 /* set ATA DMA read direction */
907 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base)
908 & ~XFER_DIR));
909 }
910
911 /* Reset all transfer count */
912 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | TFRCNT_RST);
913
b6e7b447
SZ		 914 /* Set ATAPI state machine contorl in terminate sequence */
915 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | END_ON_TERM);
916
917 /* Set transfer length to buffer len */
ff2aeb1e 918 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d830d173
SZ		 919 ATAPI_SET_XFER_LEN(base, (sg_dma_len(sg) >> 1));
920 }
921
922 /* Enable ATA DMA operation*/
923 if (ap->udma_mask)
924 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base)
925 | ULTRA_START);
926 else
927 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base)
928 | MULTI_START);
929}
930
931/**
932 * bfin_bmdma_stop - Stop IDE DMA transfer
933 * @qc: Command we are ending DMA for
934 */
935
936static void bfin_bmdma_stop(struct ata_queued_cmd *qc)
937{
938 struct ata_port *ap = qc->ap;
939 struct scatterlist *sg;
ff2aeb1e 940 unsigned int si;
d830d173 941
f9204112 942 dev_dbg(qc->ap->dev, "in atapi dma stop\n");
d830d173
SZ		 943 if (!(ap->udma_mask || ap->mwdma_mask))
944 return;
945
946 /* stop ATAPI DMA controller*/
947 if (qc->tf.flags & ATA_TFLAG_WRITE)
948 disable_dma(CH_ATAPI_TX);
949 else {
950 disable_dma(CH_ATAPI_RX);
951 if (ap->hsm_task_state & HSM_ST_LAST) {
952 /*
953 * On blackfin arch, uncacheable memory is not
954 * allocated with flag GFP_DMA. DMA buffer from
955 * common kenel code should be invalidated if
956 * data cache is enabled. Otherwise, this loop
957 * is an empty loop and optimized out.
958 */
ff2aeb1e 959 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d830d173
SZ		 960 invalidate_dcache_range(
961 sg_dma_address(sg),
962 sg_dma_address(sg)
963 + sg_dma_len(sg));
964 }
965 }
966 }
967}
968
969/**
970 * bfin_devchk - PATA device presence detection
971 * @ap: ATA channel to examine
972 * @device: Device to examine (starting at zero)
973 *
974 * Note: Original code is ata_devchk().
975 */
976
977static unsigned int bfin_devchk(struct ata_port *ap,
978 unsigned int device)
979{
980 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
981 u8 nsect, lbal;
982
9363c382 983 bfin_dev_select(ap, device);
d830d173
SZ		 984
985 write_atapi_register(base, ATA_REG_NSECT, 0x55);
986 write_atapi_register(base, ATA_REG_LBAL, 0xaa);
987
988 write_atapi_register(base, ATA_REG_NSECT, 0xaa);
989 write_atapi_register(base, ATA_REG_LBAL, 0x55);
990
991 write_atapi_register(base, ATA_REG_NSECT, 0x55);
992 write_atapi_register(base, ATA_REG_LBAL, 0xaa);
993
994 nsect = read_atapi_register(base, ATA_REG_NSECT);
995 lbal = read_atapi_register(base, ATA_REG_LBAL);
996
997 if ((nsect == 0x55) && (lbal == 0xaa))
998 return 1; /* we found a device */
999
1000 return 0; /* nothing found */
1001}
1002
1003/**
1004 * bfin_bus_post_reset - PATA device post reset
1005 *
1006 * Note: Original code is ata_bus_post_reset().
1007 */
1008
1009static void bfin_bus_post_reset(struct ata_port *ap, unsigned int devmask)
1010{
1011 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1012 unsigned int dev0 = devmask & (1 << 0);
1013 unsigned int dev1 = devmask & (1 << 1);
341c2c95 1014 unsigned long deadline;
d830d173
SZ		 1015
1016 /* if device 0 was found in ata_devchk, wait for its
1017 * BSY bit to clear
1018 */
1019 if (dev0)
9363c382 1020 ata_sff_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
d830d173
SZ		 1021
1022 /* if device 1 was found in ata_devchk, wait for
1023 * register access, then wait for BSY to clear
1024 */
341c2c95 1025 deadline = ata_deadline(jiffies, ATA_TMOUT_BOOT);
d830d173
SZ		 1026 while (dev1) {
1027 u8 nsect, lbal;
1028
9363c382 1029 bfin_dev_select(ap, 1);
d830d173
SZ		 1030 nsect = read_atapi_register(base, ATA_REG_NSECT);
1031 lbal = read_atapi_register(base, ATA_REG_LBAL);
1032 if ((nsect == 1) && (lbal == 1))
1033 break;
341c2c95 1034 if (time_after(jiffies, deadline)) {
d830d173
SZ		 1035 dev1 = 0;
1036 break;
1037 }
1038 msleep(50); /* give drive a breather */
1039 }
1040 if (dev1)
9363c382 1041 ata_sff_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
d830d173
SZ		 1042
1043 /* is all this really necessary? */
9363c382 1044 bfin_dev_select(ap, 0);
d830d173 1045 if (dev1)
9363c382 1046 bfin_dev_select(ap, 1);
d830d173 1047 if (dev0)
9363c382 1048 bfin_dev_select(ap, 0);
d830d173
SZ		 1049}
1050
1051/**
1052 * bfin_bus_softreset - PATA device software reset
1053 *
1054 * Note: Original code is ata_bus_softreset().
1055 */
1056
1057static unsigned int bfin_bus_softreset(struct ata_port *ap,
1058 unsigned int devmask)
1059{
1060 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1061
1062 /* software reset. causes dev0 to be selected */
1063 write_atapi_register(base, ATA_REG_CTRL, ap->ctl);
1064 udelay(20);
1065 write_atapi_register(base, ATA_REG_CTRL, ap->ctl | ATA_SRST);
1066 udelay(20);
1067 write_atapi_register(base, ATA_REG_CTRL, ap->ctl);
1068
1069 /* spec mandates ">= 2ms" before checking status.
1070 * We wait 150ms, because that was the magic delay used for
1071 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1072 * between when the ATA command register is written, and then
1073 * status is checked. Because waiting for "a while" before
1074 * checking status is fine, post SRST, we perform this magic
1075 * delay here as well.
1076 *
1077 * Old drivers/ide uses the 2mS rule and then waits for ready
1078 */
1079 msleep(150);
1080
1081 /* Before we perform post reset processing we want to see if
1082 * the bus shows 0xFF because the odd clown forgets the D7
1083 * pulldown resistor.
1084 */
1085 if (bfin_check_status(ap) == 0xFF)
1086 return 0;
1087
1088 bfin_bus_post_reset(ap, devmask);
1089
1090 return 0;
1091}
1092
1093/**
9363c382 1094 * bfin_softreset - reset host port via ATA SRST
d830d173
SZ		 1095 * @ap: port to reset
1096 * @classes: resulting classes of attached devices
1097 *
9363c382 1098 * Note: Original code is ata_sff_softreset().
d830d173
SZ		 1099 */
1100
9363c382
TH		 1101static int bfin_softreset(struct ata_link *link, unsigned int *classes,
1102 unsigned long deadline)
d830d173 1103{
858c9c40 1104 struct ata_port *ap = link->ap;
d830d173
SZ		 1105 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
1106 unsigned int devmask = 0, err_mask;
1107 u8 err;
1108
d830d173
SZ		 1109 /* determine if device 0/1 are present */
1110 if (bfin_devchk(ap, 0))
1111 devmask |= (1 << 0);
1112 if (slave_possible && bfin_devchk(ap, 1))
1113 devmask |= (1 << 1);
1114
1115 /* select device 0 again */
9363c382 1116 bfin_dev_select(ap, 0);
d830d173
SZ		 1117
1118 /* issue bus reset */
1119 err_mask = bfin_bus_softreset(ap, devmask);
1120 if (err_mask) {
1121 ata_port_printk(ap, KERN_ERR, "SRST failed (err_mask=0x%x)\n",
1122 err_mask);
1123 return -EIO;
1124 }
1125
1126 /* determine by signature whether we have ATA or ATAPI devices */
9363c382 1127 classes[0] = ata_sff_dev_classify(&ap->link.device[0],
858c9c40 1128 devmask & (1 << 0), &err);
d830d173 1129 if (slave_possible && err != 0x81)
9363c382 1130 classes[1] = ata_sff_dev_classify(&ap->link.device[1],
858c9c40 1131 devmask & (1 << 1), &err);
d830d173 1132
d830d173
SZ		 1133 return 0;
1134}
1135
1136/**
1137 * bfin_bmdma_status - Read IDE DMA status
1138 * @ap: Port associated with this ATA transaction.
1139 */
1140
1141static unsigned char bfin_bmdma_status(struct ata_port *ap)
1142{
1143 unsigned char host_stat = 0;
1144 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1145 unsigned short int_status = ATAPI_GET_INT_STATUS(base);
1146
30d849c9 1147 if (ATAPI_GET_STATUS(base) & (MULTI_XFER_ON|ULTRA_XFER_ON))
dc86f6d4 1148 host_stat |= ATA_DMA_ACTIVE;
30d849c9
SZ		 1149 if (int_status & (MULTI_DONE_INT|UDMAIN_DONE_INT|UDMAOUT_DONE_INT|
1150 ATAPI_DEV_INT))
dc86f6d4 1151 host_stat |= ATA_DMA_INTR;
30d849c9
SZ		 1152 if (int_status & (MULTI_TERM_INT|UDMAIN_TERM_INT|UDMAOUT_TERM_INT))
1153 host_stat |= ATA_DMA_ERR|ATA_DMA_INTR;
d830d173 1154
f9204112
SZ		 1155 dev_dbg(ap->dev, "ATAPI: host_stat=0x%x\n", host_stat);
1156
d830d173
SZ		 1157 return host_stat;
1158}
1159
1160/**
1161 * bfin_data_xfer - Transfer data by PIO
1162 * @adev: device for this I/O
1163 * @buf: data buffer
1164 * @buflen: buffer length
1165 * @write_data: read/write
1166 *
9363c382 1167 * Note: Original code is ata_sff_data_xfer().
d830d173
SZ		 1168 */
1169
55dba312
TH		 1170static unsigned int bfin_data_xfer(struct ata_device *dev, unsigned char *buf,
1171 unsigned int buflen, int rw)
d830d173 1172{
55dba312 1173 struct ata_port *ap = dev->link->ap;
d830d173 1174 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
55dba312
TH		 1175 unsigned int words = buflen >> 1;
1176 unsigned short *buf16 = (u16 *)buf;
d830d173
SZ		 1177
1178 /* Transfer multiple of 2 bytes */
55dba312 1179 if (rw == READ)
d830d173 1180 read_atapi_data(base, words, buf16);
55dba312
TH		 1181 else
1182 write_atapi_data(base, words, buf16);
d830d173
SZ		 1183
1184 /* Transfer trailing 1 byte, if any. */
1185 if (unlikely(buflen & 0x01)) {
1186 unsigned short align_buf[1] = { 0 };
1187 unsigned char *trailing_buf = buf + buflen - 1;
1188
55dba312 1189 if (rw == READ) {
d830d173
SZ		 1190 read_atapi_data(base, 1, align_buf);
1191 memcpy(trailing_buf, align_buf, 1);
55dba312
TH		 1192 } else {
1193 memcpy(align_buf, trailing_buf, 1);
1194 write_atapi_data(base, 1, align_buf);
d830d173 1195 }
55dba312 1196 words++;
d830d173 1197 }
55dba312
TH		 1198
1199 return words << 1;
d830d173
SZ		 1200}
1201
1202/**
1203 * bfin_irq_clear - Clear ATAPI interrupt.
1204 * @ap: Port associated with this ATA transaction.
1205 *
9363c382 1206 * Note: Original code is ata_sff_irq_clear().
d830d173
SZ		 1207 */
1208
1209static void bfin_irq_clear(struct ata_port *ap)
1210{
1211 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1212
f9204112 1213 dev_dbg(ap->dev, "in atapi irq clear\n");
858c9c40
SZ		 1214 ATAPI_SET_INT_STATUS(base, ATAPI_GET_INT_STATUS(base)|ATAPI_DEV_INT
1215 | MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT
1216 | MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT);
d830d173
SZ		 1217}
1218
1219/**
1220 * bfin_irq_on - Enable interrupts on a port.
1221 * @ap: Port on which interrupts are enabled.
1222 *
9363c382 1223 * Note: Original code is ata_sff_irq_on().
d830d173
SZ		 1224 */
1225
1226static unsigned char bfin_irq_on(struct ata_port *ap)
1227{
1228 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1229 u8 tmp;
1230
f9204112 1231 dev_dbg(ap->dev, "in atapi irq on\n");
d830d173
SZ		 1232 ap->ctl &= ~ATA_NIEN;
1233 ap->last_ctl = ap->ctl;
1234
1235 write_atapi_register(base, ATA_REG_CTRL, ap->ctl);
1236 tmp = ata_wait_idle(ap);
1237
1238 bfin_irq_clear(ap);
1239
1240 return tmp;
1241}
1242
d830d173 1243/**
9363c382 1244 * bfin_freeze - Freeze DMA controller port
d830d173
SZ		 1245 * @ap: port to freeze
1246 *
9363c382 1247 * Note: Original code is ata_sff_freeze().
d830d173
SZ		 1248 */
1249
9363c382 1250static void bfin_freeze(struct ata_port *ap)
d830d173
SZ		 1251{
1252 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1253
f9204112 1254 dev_dbg(ap->dev, "in atapi dma freeze\n");
d830d173
SZ		 1255 ap->ctl |= ATA_NIEN;
1256 ap->last_ctl = ap->ctl;
1257
1258 write_atapi_register(base, ATA_REG_CTRL, ap->ctl);
1259
1260 /* Under certain circumstances, some controllers raise IRQ on
1261 * ATA_NIEN manipulation. Also, many controllers fail to mask
1262 * previously pending IRQ on ATA_NIEN assertion. Clear it.
1263 */
5682ed33 1264 ap->ops->sff_check_status(ap);
d830d173
SZ		 1265
1266 bfin_irq_clear(ap);
1267}
1268
1269/**
9363c382 1270 * bfin_thaw - Thaw DMA controller port
d830d173
SZ		 1271 * @ap: port to thaw
1272 *
9363c382 1273 * Note: Original code is ata_sff_thaw().
d830d173
SZ		 1274 */
1275
9363c382 1276void bfin_thaw(struct ata_port *ap)
d830d173 1277{
65c0d4e5 1278 dev_dbg(ap->dev, "in atapi dma thaw\n");
d830d173 1279 bfin_check_status(ap);
d830d173
SZ		 1280 bfin_irq_on(ap);
1281}
1282
1283/**
9363c382 1284 * bfin_postreset - standard postreset callback
d830d173
SZ		 1285 * @ap: the target ata_port
1286 * @classes: classes of attached devices
1287 *
9363c382 1288 * Note: Original code is ata_sff_postreset().
d830d173
SZ		 1289 */
1290
9363c382 1291static void bfin_postreset(struct ata_link *link, unsigned int *classes)
d830d173 1292{
858c9c40 1293 struct ata_port *ap = link->ap;
d830d173
SZ		 1294 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1295
1296 /* re-enable interrupts */
1297 bfin_irq_on(ap);
1298
1299 /* is double-select really necessary? */
1300 if (classes[0] != ATA_DEV_NONE)
9363c382 1301 bfin_dev_select(ap, 1);
d830d173 1302 if (classes[1] != ATA_DEV_NONE)
9363c382 1303 bfin_dev_select(ap, 0);
d830d173
SZ		 1304
1305 /* bail out if no device is present */
1306 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
1307 return;
1308 }
1309
1310 /* set up device control */
1311 write_atapi_register(base, ATA_REG_CTRL, ap->ctl);
1312}
1313
d830d173
SZ		 1314static void bfin_port_stop(struct ata_port *ap)
1315{
f9204112 1316 dev_dbg(ap->dev, "in atapi port stop\n");
d830d173
SZ		 1317 if (ap->udma_mask != 0 || ap->mwdma_mask != 0) {
1318 free_dma(CH_ATAPI_RX);
1319 free_dma(CH_ATAPI_TX);
1320 }
1321}
1322
1323static int bfin_port_start(struct ata_port *ap)
1324{
f9204112 1325 dev_dbg(ap->dev, "in atapi port start\n");
d830d173
SZ		 1326 if (!(ap->udma_mask || ap->mwdma_mask))
1327 return 0;
1328
1329 if (request_dma(CH_ATAPI_RX, "BFIN ATAPI RX DMA") >= 0) {
1330 if (request_dma(CH_ATAPI_TX,
1331 "BFIN ATAPI TX DMA") >= 0)
1332 return 0;
1333
1334 free_dma(CH_ATAPI_RX);
1335 }
1336
1337 ap->udma_mask = 0;
1338 ap->mwdma_mask = 0;
1339 dev_err(ap->dev, "Unable to request ATAPI DMA!"
1340 " Continue in PIO mode.\n");
1341
1342 return 0;
1343}
1344
65c0d4e5
SZ		 1345static unsigned int bfin_ata_host_intr(struct ata_port *ap,
1346 struct ata_queued_cmd *qc)
1347{
1348 struct ata_eh_info *ehi = &ap->link.eh_info;
1349 u8 status, host_stat = 0;
1350
1351 VPRINTK("ata%u: protocol %d task_state %d\n",
1352 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
1353
1354 /* Check whether we are expecting interrupt in this state */
1355 switch (ap->hsm_task_state) {
1356 case HSM_ST_FIRST:
1357 /* Some pre-ATAPI-4 devices assert INTRQ
1358 * at this state when ready to receive CDB.
1359 */
1360
1361 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1362 * The flag was turned on only for atapi devices.
1363 * No need to check is_atapi_taskfile(&qc->tf) again.
1364 */
1365 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1366 goto idle_irq;
1367 break;
1368 case HSM_ST_LAST:
1369 if (qc->tf.protocol == ATA_PROT_DMA ||
1370 qc->tf.protocol == ATAPI_PROT_DMA) {
1371 /* check status of DMA engine */
1372 host_stat = ap->ops->bmdma_status(ap);
1373 VPRINTK("ata%u: host_stat 0x%X\n",
1374 ap->print_id, host_stat);
1375
1376 /* if it's not our irq... */
1377 if (!(host_stat & ATA_DMA_INTR))
1378 goto idle_irq;
1379
1380 /* before we do anything else, clear DMA-Start bit */
1381 ap->ops->bmdma_stop(qc);
1382
1383 if (unlikely(host_stat & ATA_DMA_ERR)) {
1384 /* error when transfering data to/from memory */
1385 qc->err_mask |= AC_ERR_HOST_BUS;
1386 ap->hsm_task_state = HSM_ST_ERR;
1387 }
1388 }
1389 break;
1390 case HSM_ST:
1391 break;
1392 default:
1393 goto idle_irq;
1394 }
1395
1396 /* check altstatus */
1397 status = ap->ops->sff_check_altstatus(ap);
1398 if (status & ATA_BUSY)
1399 goto busy_ata;
1400
1401 /* check main status, clearing INTRQ */
1402 status = ap->ops->sff_check_status(ap);
1403 if (unlikely(status & ATA_BUSY))
1404 goto busy_ata;
1405
1406 /* ack bmdma irq events */
1407 ap->ops->sff_irq_clear(ap);
1408
1409 ata_sff_hsm_move(ap, qc, status, 0);
1410
1411 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
1412 qc->tf.protocol == ATAPI_PROT_DMA))
1413 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
1414
1415busy_ata:
1416 return 1; /* irq handled */
1417
1418idle_irq:
1419 ap->stats.idle_irq++;
1420
1421#ifdef ATA_IRQ_TRAP
1422 if ((ap->stats.idle_irq % 1000) == 0) {
1423 ap->ops->irq_ack(ap, 0); /* debug trap */
1424 ata_port_printk(ap, KERN_WARNING, "irq trap\n");
1425 return 1;
1426 }
1427#endif
1428 return 0; /* irq not handled */
1429}
1430
1431static irqreturn_t bfin_ata_interrupt(int irq, void *dev_instance)
1432{
1433 struct ata_host *host = dev_instance;
1434 unsigned int i;
1435 unsigned int handled = 0;
1436 unsigned long flags;
1437
1438 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1439 spin_lock_irqsave(&host->lock, flags);
1440
1441 for (i = 0; i < host->n_ports; i++) {
1442 struct ata_port *ap;
1443
1444 ap = host->ports[i];
1445 if (ap &&
1446 !(ap->flags & ATA_FLAG_DISABLED)) {
1447 struct ata_queued_cmd *qc;
1448
1449 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1450 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
1451 (qc->flags & ATA_QCFLAG_ACTIVE))
1452 handled |= bfin_ata_host_intr(ap, qc);
1453 }
1454 }
1455
1456 spin_unlock_irqrestore(&host->lock, flags);
1457
1458 return IRQ_RETVAL(handled);
1459}
1460
1461
d830d173 1462static struct scsi_host_template bfin_sht = {
68d1d07b 1463 ATA_BASE_SHT(DRV_NAME),
d830d173 1464 .sg_tablesize = SG_NONE,
d830d173 1465 .dma_boundary = ATA_DMA_BOUNDARY,
d830d173
SZ		 1466};
1467
65c0d4e5 1468static struct ata_port_operations bfin_pata_ops = {
029cfd6b
TH		 1469 .inherits = &ata_sff_port_ops,
1470
d830d173
SZ		 1471 .set_piomode = bfin_set_piomode,
1472 .set_dmamode = bfin_set_dmamode,
1473
5682ed33
TH		 1474 .sff_tf_load = bfin_tf_load,
1475 .sff_tf_read = bfin_tf_read,
1476 .sff_exec_command = bfin_exec_command,
1477 .sff_check_status = bfin_check_status,
1478 .sff_check_altstatus = bfin_check_altstatus,
1479 .sff_dev_select = bfin_dev_select,
d830d173
SZ		 1480
1481 .bmdma_setup = bfin_bmdma_setup,
1482 .bmdma_start = bfin_bmdma_start,
1483 .bmdma_stop = bfin_bmdma_stop,
1484 .bmdma_status = bfin_bmdma_status,
5682ed33 1485 .sff_data_xfer = bfin_data_xfer,
d830d173
SZ		 1486
1487 .qc_prep = ata_noop_qc_prep,
d830d173 1488
9363c382
TH		 1489 .freeze = bfin_freeze,
1490 .thaw = bfin_thaw,
1491 .softreset = bfin_softreset,
1492 .postreset = bfin_postreset,
d830d173 1493
5682ed33
TH		 1494 .sff_irq_clear = bfin_irq_clear,
1495 .sff_irq_on = bfin_irq_on,
d830d173
SZ		 1496
1497 .port_start = bfin_port_start,
1498 .port_stop = bfin_port_stop,
1499};
1500
1501static struct ata_port_info bfin_port_info[] = {
1502 {
d830d173
SZ		 1503 .flags = ATA_FLAG_SLAVE_POSS
1504 | ATA_FLAG_MMIO
1505 | ATA_FLAG_NO_LEGACY,
1506 .pio_mask = 0x1f, /* pio0-4 */
1507 .mwdma_mask = 0,
d830d173 1508 .udma_mask = 0,
d830d173
SZ		 1509 .port_ops = &bfin_pata_ops,
1510 },
1511};
1512
1513/**
1514 * bfin_reset_controller - initialize BF54x ATAPI controller.
1515 */
1516
1517static int bfin_reset_controller(struct ata_host *host)
1518{
1519 void __iomem *base = (void __iomem *)host->ports[0]->ioaddr.ctl_addr;
1520 int count;
1521 unsigned short status;
1522
1523 /* Disable all ATAPI interrupts */
1524 ATAPI_SET_INT_MASK(base, 0);
1525 SSYNC();
1526
1527 /* Assert the RESET signal 25us*/
1528 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | DEV_RST);
1529 udelay(30);
1530
1531 /* Negate the RESET signal for 2ms*/
1532 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) & ~DEV_RST);
1533 msleep(2);
1534
1535 /* Wait on Busy flag to clear */
1536 count = 10000000;
1537 do {
1538 status = read_atapi_register(base, ATA_REG_STATUS);
f9d42491 1539 } while (--count && (status & ATA_BUSY));
d830d173
SZ		 1540
1541 /* Enable only ATAPI Device interrupt */
1542 ATAPI_SET_INT_MASK(base, 1);
1543 SSYNC();
1544
1545 return (!count);
1546}
1547
1548/**
1549 * atapi_io_port - define atapi peripheral port pins.
1550 */
1551static unsigned short atapi_io_port[] = {
1552 P_ATAPI_RESET,
1553 P_ATAPI_DIOR,
1554 P_ATAPI_DIOW,
1555 P_ATAPI_CS0,
1556 P_ATAPI_CS1,
1557 P_ATAPI_DMACK,
1558 P_ATAPI_DMARQ,
1559 P_ATAPI_INTRQ,
1560 P_ATAPI_IORDY,
1561 0
1562};
1563
1564/**
1565 * bfin_atapi_probe - attach a bfin atapi interface
1566 * @pdev: platform device
1567 *
1568 * Register a bfin atapi interface.
1569 *
1570 *
1571 * Platform devices are expected to contain 2 resources per port:
1572 *
1573 * - I/O Base (IORESOURCE_IO)
1574 * - IRQ (IORESOURCE_IRQ)
1575 *
1576 */
1577static int __devinit bfin_atapi_probe(struct platform_device *pdev)
1578{
1579 int board_idx = 0;
1580 struct resource *res;
1581 struct ata_host *host;
f88c480d 1582 unsigned int fsclk = get_sclk();
1583 int udma_mode = 5;
d830d173
SZ		 1584 const struct ata_port_info *ppi[] =
1585 { &bfin_port_info[board_idx], NULL };
1586
1587 /*
1588 * Simple resource validation ..
1589 */
1590 if (unlikely(pdev->num_resources != 2)) {
1591 dev_err(&pdev->dev, "invalid number of resources\n");
1592 return -EINVAL;
1593 }
1594
1595 /*
1596 * Get the register base first
1597 */
1598 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1599 if (res == NULL)
1600 return -EINVAL;
1601
ed722d3d
AM		 1602 while (bfin_port_info[board_idx].udma_mask > 0 &&
1603 udma_fsclk[udma_mode] > fsclk) {
f88c480d 1604 udma_mode--;
1605 bfin_port_info[board_idx].udma_mask >>= 1;
1606 }
1607
d830d173
SZ		 1608 /*
1609 * Now that that's out of the way, wire up the port..
1610 */
1611 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1);
1612 if (!host)
1613 return -ENOMEM;
1614
1615 host->ports[0]->ioaddr.ctl_addr = (void *)res->start;
1616
1617 if (peripheral_request_list(atapi_io_port, "atapi-io-port")) {
1618 dev_err(&pdev->dev, "Requesting Peripherals faild\n");
1619 return -EFAULT;
1620 }
1621
1622 if (bfin_reset_controller(host)) {
1623 peripheral_free_list(atapi_io_port);
1624 dev_err(&pdev->dev, "Fail to reset ATAPI device\n");
1625 return -EFAULT;
1626 }
1627
1628 if (ata_host_activate(host, platform_get_irq(pdev, 0),
65c0d4e5 1629 bfin_ata_interrupt, IRQF_SHARED, &bfin_sht) != 0) {
d830d173
SZ		 1630 peripheral_free_list(atapi_io_port);
1631 dev_err(&pdev->dev, "Fail to attach ATAPI device\n");
1632 return -ENODEV;
1633 }
1634
1635 return 0;
1636}
1637
1638/**
1639 * bfin_atapi_remove - unplug a bfin atapi interface
1640 * @pdev: platform device
1641 *
1642 * A bfin atapi device has been unplugged. Perform the needed
1643 * cleanup. Also called on module unload for any active devices.
1644 */
1645static int __devexit bfin_atapi_remove(struct platform_device *pdev)
1646{
1647 struct device *dev = &pdev->dev;
1648 struct ata_host *host = dev_get_drvdata(dev);
1649
1650 ata_host_detach(host);
1651
1652 peripheral_free_list(atapi_io_port);
1653
1654 return 0;
1655}
1656
1657#ifdef CONFIG_PM
1658int bfin_atapi_suspend(struct platform_device *pdev, pm_message_t state)
1659{
1660 return 0;
1661}
1662
1663int bfin_atapi_resume(struct platform_device *pdev)
1664{
1665 return 0;
1666}
1667#endif
1668
1669static struct platform_driver bfin_atapi_driver = {
1670 .probe = bfin_atapi_probe,
1671 .remove = __devexit_p(bfin_atapi_remove),
1672 .driver = {
1673 .name = DRV_NAME,
1674 .owner = THIS_MODULE,
1675#ifdef CONFIG_PM
1676 .suspend = bfin_atapi_suspend,
1677 .resume = bfin_atapi_resume,
1678#endif
1679 },
1680};
1681
858c9c40
SZ		 1682#define ATAPI_MODE_SIZE 10
1683static char bfin_atapi_mode[ATAPI_MODE_SIZE];
1684
d830d173
SZ		 1685static int __init bfin_atapi_init(void)
1686{
1687 pr_info("register bfin atapi driver\n");
858c9c40
SZ		 1688
1689 switch(bfin_atapi_mode[0]) {
1690 case 'p':
1691 case 'P':
1692 break;
1693 case 'm':
1694 case 'M':
1695 bfin_port_info[0].mwdma_mask = ATA_MWDMA2;
1696 break;
1697 default:
1698 bfin_port_info[0].udma_mask = ATA_UDMA5;
1699 };
1700
d830d173
SZ		 1701 return platform_driver_register(&bfin_atapi_driver);
1702}
1703
1704static void __exit bfin_atapi_exit(void)
1705{
1706 platform_driver_unregister(&bfin_atapi_driver);
1707}
1708
1709module_init(bfin_atapi_init);
1710module_exit(bfin_atapi_exit);
858c9c40
SZ		 1711/*
1712 * ATAPI mode:
1713 * pio/PIO
1714 * udma/UDMA (default)
1715 * mwdma/MWDMA
1716 */
1717module_param_string(bfin_atapi_mode, bfin_atapi_mode, ATAPI_MODE_SIZE, 0);
d830d173
SZ		 1718
1719MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
1720MODULE_DESCRIPTION("PATA driver for blackfin 54x ATAPI controller");
1721MODULE_LICENSE("GPL");
1722MODULE_VERSION(DRV_VERSION);
458622fc 1723MODULE_ALIAS("platform:" DRV_NAME);
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