[linux-2.6-block.git] / drivers / ata / pata_atiixp.c

/*
 * pata_atiixp.c 	- ATI PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  (C) 2009 Bartlomiej Zolnierkiewicz
 *
 * Based on
 *
 *  linux/drivers/ide/pci/atiixp.c	Version 0.01-bart2	Feb. 26, 2004
 *
 *  Copyright (C) 2003 ATI Inc. <hyu@ati.com>
 *  Copyright (C) 2004 Bartlomiej Zolnierkiewicz
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_atiixp"
#define DRV_VERSION "0.4.6"

enum {
	ATIIXP_IDE_PIO_TIMING	= 0x40,
	ATIIXP_IDE_MWDMA_TIMING	= 0x44,
	ATIIXP_IDE_PIO_CONTROL	= 0x48,
	ATIIXP_IDE_PIO_MODE	= 0x4a,
	ATIIXP_IDE_UDMA_CONTROL	= 0x54,
	ATIIXP_IDE_UDMA_MODE 	= 0x56
};

static int atiixp_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 udma;

	/* Hack from drivers/ide/pci. Really we want to know how to do the
	   raw detection not play follow the bios mode guess */
	pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ap->port_no, &udma);
	if ((udma & 0x07) >= 0x04 || (udma & 0x70) >= 0x40)
		return  ATA_CBL_PATA80;
	return ATA_CBL_PATA40;
}

/**
 *	atiixp_set_pio_timing	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called by both the pio and dma setup functions to set the controller
 *	timings for PIO transfers. We must load both the mode number and
 *	timing values into the controller.
 */

static void atiixp_set_pio_timing(struct ata_port *ap, struct ata_device *adev, int pio)
{
	static u8 pio_timings[5] = { 0x5D, 0x47, 0x34, 0x22, 0x20 };

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int dn = 2 * ap->port_no + adev->devno;
	int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1);
	u32 pio_timing_data;
	u16 pio_mode_data;

	pci_read_config_word(pdev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
	pio_mode_data &= ~(0x7 << (4 * dn));
	pio_mode_data |= pio << (4 * dn);
	pci_write_config_word(pdev, ATIIXP_IDE_PIO_MODE, pio_mode_data);

	pci_read_config_dword(pdev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
	pio_timing_data &= ~(0xFF << timing_shift);
	pio_timing_data |= (pio_timings[pio] << timing_shift);
	pci_write_config_dword(pdev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
}

/**
 *	atiixp_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the PIO mode setup. We use a shared helper for this
 *	as the DMA setup must also adjust the PIO timing information.
 */

static void atiixp_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	atiixp_set_pio_timing(ap, adev, adev->pio_mode - XFER_PIO_0);
}

/**
 *	atiixp_set_dmamode	-	set initial DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the DMA mode setup. We use timing tables for most
 *	modes but must tune an appropriate PIO mode to match.
 */

static void atiixp_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	static u8 mwdma_timings[5] = { 0x77, 0x21, 0x20 };

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int dma = adev->dma_mode;
	int dn = 2 * ap->port_no + adev->devno;
	int wanted_pio;

	if (adev->dma_mode >= XFER_UDMA_0) {
		u16 udma_mode_data;

		dma -= XFER_UDMA_0;

		pci_read_config_word(pdev, ATIIXP_IDE_UDMA_MODE, &udma_mode_data);
		udma_mode_data &= ~(0x7 << (4 * dn));
		udma_mode_data |= dma << (4 * dn);
		pci_write_config_word(pdev, ATIIXP_IDE_UDMA_MODE, udma_mode_data);
	} else {
		int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1);
		u32 mwdma_timing_data;

		dma -= XFER_MW_DMA_0;

		pci_read_config_dword(pdev, ATIIXP_IDE_MWDMA_TIMING,
				      &mwdma_timing_data);
		mwdma_timing_data &= ~(0xFF << timing_shift);
		mwdma_timing_data |= (mwdma_timings[dma] << timing_shift);
		pci_write_config_dword(pdev, ATIIXP_IDE_MWDMA_TIMING,
				       mwdma_timing_data);
	}
	/*
	 *	We must now look at the PIO mode situation. We may need to
	 *	adjust the PIO mode to keep the timings acceptable
	 */
	 if (adev->dma_mode >= XFER_MW_DMA_2)
	 	wanted_pio = 4;
	else if (adev->dma_mode == XFER_MW_DMA_1)
		wanted_pio = 3;
	else if (adev->dma_mode == XFER_MW_DMA_0)
		wanted_pio = 0;
	else BUG();

	if (adev->pio_mode != wanted_pio)
		atiixp_set_pio_timing(ap, adev, wanted_pio);
}

/**
 *	atiixp_bmdma_start	-	DMA start callback
 *	@qc: Command in progress
 *
 *	When DMA begins we need to ensure that the UDMA control
 *	register for the channel is correctly set.
 *
 *	Note: The host lock held by the libata layer protects
 *	us from two channels both trying to set DMA bits at once
 */

static void atiixp_bmdma_start(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct ata_device *adev = qc->dev;

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int dn = (2 * ap->port_no) + adev->devno;
	u16 tmp16;

	pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
	if (ata_using_udma(adev))
		tmp16 |= (1 << dn);
	else
		tmp16 &= ~(1 << dn);
	pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
	ata_bmdma_start(qc);
}

/**
 *	atiixp_dma_stop	-	DMA stop callback
 *	@qc: Command in progress
 *
 *	DMA has completed. Clear the UDMA flag as the next operations will
 *	be PIO ones not UDMA data transfer.
 *
 *	Note: The host lock held by the libata layer protects
 *	us from two channels both trying to set DMA bits at once
 */

static void atiixp_bmdma_stop(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int dn = (2 * ap->port_no) + qc->dev->devno;
	u16 tmp16;

	pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
	tmp16 &= ~(1 << dn);
	pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
	ata_bmdma_stop(qc);
}

static struct scsi_host_template atiixp_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
	.sg_tablesize		= LIBATA_DUMB_MAX_PRD,
};

static struct ata_port_operations atiixp_port_ops = {
	.inherits	= &ata_bmdma_port_ops,

	.qc_prep 	= ata_sff_dumb_qc_prep,
	.bmdma_start 	= atiixp_bmdma_start,
	.bmdma_stop	= atiixp_bmdma_stop,

	.cable_detect	= atiixp_cable_detect,
	.set_piomode	= atiixp_set_piomode,
	.set_dmamode	= atiixp_set_dmamode,
};

static int atiixp_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const struct ata_port_info info = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = ATA_PIO4,
		.mwdma_mask = ATA_MWDMA12_ONLY,
		.udma_mask = ATA_UDMA5,
		.port_ops = &atiixp_port_ops
	};
	static const struct pci_bits atiixp_enable_bits[] = {
		{ 0x48, 1, 0x01, 0x00 },
		{ 0x48, 1, 0x08, 0x00 }
	};
	const struct ata_port_info *ppi[] = { &info, &info };
	int i;

	for (i = 0; i < 2; i++)
		if (!pci_test_config_bits(pdev, &atiixp_enable_bits[i]))
			ppi[i] = &ata_dummy_port_info;

	return ata_pci_sff_init_one(pdev, ppi, &atiixp_sht, NULL);
}

static const struct pci_device_id atiixp[] = {
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), },
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), },
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), },
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), },
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP700_IDE), },

	{ },
};

static struct pci_driver atiixp_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= atiixp,
	.probe 		= atiixp_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.resume		= ata_pci_device_resume,
	.suspend	= ata_pci_device_suspend,
#endif
};

static int __init atiixp_init(void)
{
	return pci_register_driver(&atiixp_pci_driver);
}


static void __exit atiixp_exit(void)
{
	pci_unregister_driver(&atiixp_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for ATI IXP200/300/400");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, atiixp);
MODULE_VERSION(DRV_VERSION);

module_init(atiixp_init);
module_exit(atiixp_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_atiixp.c - ATI PATA for new ATA layer
	3	* (C) 2005 Red Hat Inc
1fd4bbec	4	* (C) 2009 Bartlomiej Zolnierkiewicz
669a5db4 JG	5	*
	6	* Based on
	7	*
	8	* linux/drivers/ide/pci/atiixp.c Version 0.01-bart2 Feb. 26, 2004
	9	*
	10	* Copyright (C) 2003 ATI Inc. <hyu@ati.com>
	11	* Copyright (C) 2004 Bartlomiej Zolnierkiewicz
	12	*
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/module.h>
	17	#include <linux/pci.h>
	18	#include <linux/init.h>
	19	#include <linux/blkdev.h>
	20	#include <linux/delay.h>
	21	#include <scsi/scsi_host.h>
	22	#include <linux/libata.h>
	23
	24	#define DRV_NAME "pata_atiixp"
2a3103ce	25	#define DRV_VERSION "0.4.6"
669a5db4 JG	26
	27	enum {
	28	ATIIXP_IDE_PIO_TIMING = 0x40,
	29	ATIIXP_IDE_MWDMA_TIMING = 0x44,
	30	ATIIXP_IDE_PIO_CONTROL = 0x48,
	31	ATIIXP_IDE_PIO_MODE = 0x4a,
	32	ATIIXP_IDE_UDMA_CONTROL = 0x54,
	33	ATIIXP_IDE_UDMA_MODE = 0x56
	34	};
	35
84708606 AC	36	static int atiixp_cable_detect(struct ata_port *ap)
	37	{
	38	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	39	u8 udma;
	40
	41	/* Hack from drivers/ide/pci. Really we want to know how to do the
	42	raw detection not play follow the bios mode guess */
	43	pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ap->port_no, &udma);
	44	if ((udma & 0x07) >= 0x04 \|\| (udma & 0x70) >= 0x40)
	45	return ATA_CBL_PATA80;
	46	return ATA_CBL_PATA40;
	47	}
	48
669a5db4 JG	49	/**
	50	* atiixp_set_pio_timing - set initial PIO mode data
	51	* @ap: ATA interface
	52	* @adev: ATA device
	53	*
	54	* Called by both the pio and dma setup functions to set the controller
	55	* timings for PIO transfers. We must load both the mode number and
	56	* timing values into the controller.
	57	*/
	58
	59	static void atiixp_set_pio_timing(struct ata_port ap, struct ata_device adev, int pio)
	60	{
	61	static u8 pio_timings[5] = { 0x5D, 0x47, 0x34, 0x22, 0x20 };
	62
	63	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	64	int dn = 2 * ap->port_no + adev->devno;
669a5db4	65	int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1);
1fd4bbec BZ	66	u32 pio_timing_data;
1fd4bbec BZ	67	u16 pio_mode_data;
669a5db4 JG	68
	69	pci_read_config_word(pdev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
	70	pio_mode_data &= ~(0x7 << (4 * dn));
	71	pio_mode_data \|= pio << (4 * dn);
	72	pci_write_config_word(pdev, ATIIXP_IDE_PIO_MODE, pio_mode_data);
	73
1fd4bbec	74	pci_read_config_dword(pdev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
d7b5a23f JG	75	pio_timing_data &= ~(0xFF << timing_shift);
d7b5a23f JG	76	pio_timing_data \|= (pio_timings[pio] << timing_shift);
1fd4bbec	77	pci_write_config_dword(pdev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
669a5db4 JG	78	}
	79
	80	/**
	81	* atiixp_set_piomode - set initial PIO mode data
	82	* @ap: ATA interface
	83	* @adev: ATA device
	84	*
	85	* Called to do the PIO mode setup. We use a shared helper for this
	86	* as the DMA setup must also adjust the PIO timing information.
	87	*/
	88
	89	static void atiixp_set_piomode(struct ata_port ap, struct ata_device adev)
	90	{
	91	atiixp_set_pio_timing(ap, adev, adev->pio_mode - XFER_PIO_0);
	92	}
	93
	94	/**
	95	* atiixp_set_dmamode - set initial DMA mode data
	96	* @ap: ATA interface
	97	* @adev: ATA device
	98	*
	99	* Called to do the DMA mode setup. We use timing tables for most
	100	* modes but must tune an appropriate PIO mode to match.
	101	*/
	102
	103	static void atiixp_set_dmamode(struct ata_port ap, struct ata_device adev)
	104	{
	105	static u8 mwdma_timings[5] = { 0x77, 0x21, 0x20 };
	106
	107	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	108	int dma = adev->dma_mode;
	109	int dn = 2 * ap->port_no + adev->devno;
	110	int wanted_pio;
	111
	112	if (adev->dma_mode >= XFER_UDMA_0) {
	113	u16 udma_mode_data;
	114
	115	dma -= XFER_UDMA_0;
	116
	117	pci_read_config_word(pdev, ATIIXP_IDE_UDMA_MODE, &udma_mode_data);
	118	udma_mode_data &= ~(0x7 << (4 * dn));
	119	udma_mode_data \|= dma << (4 * dn);
	120	pci_write_config_word(pdev, ATIIXP_IDE_UDMA_MODE, udma_mode_data);
	121	} else {
669a5db4	122	int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1);
1fd4bbec	123	u32 mwdma_timing_data;
669a5db4 JG	124
	125	dma -= XFER_MW_DMA_0;
	126
1fd4bbec BZ	127	pci_read_config_dword(pdev, ATIIXP_IDE_MWDMA_TIMING,
1fd4bbec BZ	128	&mwdma_timing_data);
669a5db4 JG	129	mwdma_timing_data &= ~(0xFF << timing_shift);
669a5db4 JG	130	mwdma_timing_data \|= (mwdma_timings[dma] << timing_shift);
1fd4bbec BZ	131	pci_write_config_dword(pdev, ATIIXP_IDE_MWDMA_TIMING,
1fd4bbec BZ	132	mwdma_timing_data);
669a5db4 JG	133	}
	134	/*
	135	* We must now look at the PIO mode situation. We may need to
	136	* adjust the PIO mode to keep the timings acceptable
	137	*/
	138	if (adev->dma_mode >= XFER_MW_DMA_2)
	139	wanted_pio = 4;
	140	else if (adev->dma_mode == XFER_MW_DMA_1)
	141	wanted_pio = 3;
	142	else if (adev->dma_mode == XFER_MW_DMA_0)
	143	wanted_pio = 0;
	144	else BUG();
	145
	146	if (adev->pio_mode != wanted_pio)
	147	atiixp_set_pio_timing(ap, adev, wanted_pio);
	148	}
	149
	150	/**
	151	* atiixp_bmdma_start - DMA start callback
	152	* @qc: Command in progress
	153	*
	154	* When DMA begins we need to ensure that the UDMA control
	155	* register for the channel is correctly set.
21d2c925 AC	156	*
	157	* Note: The host lock held by the libata layer protects
	158	* us from two channels both trying to set DMA bits at once
669a5db4 JG	159	*/
	160
	161	static void atiixp_bmdma_start(struct ata_queued_cmd *qc)
	162	{
	163	struct ata_port *ap = qc->ap;
	164	struct ata_device *adev = qc->dev;
	165
	166	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	167	int dn = (2 * ap->port_no) + adev->devno;
	168	u16 tmp16;
	169
	170	pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
b15b3eba	171	if (ata_using_udma(adev))
669a5db4 JG	172	tmp16 \|= (1 << dn);
	173	else
	174	tmp16 &= ~(1 << dn);
	175	pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
	176	ata_bmdma_start(qc);
	177	}
	178
	179	/**
	180	* atiixp_dma_stop - DMA stop callback
	181	* @qc: Command in progress
	182	*
	183	* DMA has completed. Clear the UDMA flag as the next operations will
	184	* be PIO ones not UDMA data transfer.
21d2c925 AC	185	*
	186	* Note: The host lock held by the libata layer protects
	187	* us from two channels both trying to set DMA bits at once
669a5db4 JG	188	*/
	189
	190	static void atiixp_bmdma_stop(struct ata_queued_cmd *qc)
	191	{
	192	struct ata_port *ap = qc->ap;
	193	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	194	int dn = (2 * ap->port_no) + qc->dev->devno;
	195	u16 tmp16;
	196
	197	pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
	198	tmp16 &= ~(1 << dn);
	199	pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
	200	ata_bmdma_stop(qc);
	201	}
	202
	203	static struct scsi_host_template atiixp_sht = {
68d1d07b	204	ATA_BMDMA_SHT(DRV_NAME),
635adc28	205	.sg_tablesize = LIBATA_DUMB_MAX_PRD,
669a5db4 JG	206	};
	207
	208	static struct ata_port_operations atiixp_port_ops = {
029cfd6b	209	.inherits = &ata_bmdma_port_ops,
669a5db4	210
9363c382	211	.qc_prep = ata_sff_dumb_qc_prep,
669a5db4 JG	212	.bmdma_start = atiixp_bmdma_start,
669a5db4 JG	213	.bmdma_stop = atiixp_bmdma_stop,
bda30288	214
029cfd6b TH	215	.cable_detect = atiixp_cable_detect,
	216	.set_piomode = atiixp_set_piomode,
	217	.set_dmamode = atiixp_set_dmamode,
669a5db4 JG	218	};
669a5db4 JG	219
16028232	220	static int atiixp_init_one(struct pci_dev pdev, const struct pci_device_id id)
669a5db4	221	{
1626aeb8	222	static const struct ata_port_info info = {
1d2808fd	223	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	224	.pio_mask = ATA_PIO4,
	225	.mwdma_mask = ATA_MWDMA12_ONLY,
	226	.udma_mask = ATA_UDMA5,
669a5db4 JG	227	.port_ops = &atiixp_port_ops
669a5db4 JG	228	};
16028232 TH	229	static const struct pci_bits atiixp_enable_bits[] = {
	230	{ 0x48, 1, 0x01, 0x00 },
	231	{ 0x48, 1, 0x08, 0x00 }
	232	};
	233	const struct ata_port_info *ppi[] = { &info, &info };
	234	int i;
	235
	236	for (i = 0; i < 2; i++)
	237	if (!pci_test_config_bits(pdev, &atiixp_enable_bits[i]))
	238	ppi[i] = &ata_dummy_port_info;
	239
	240	return ata_pci_sff_init_one(pdev, ppi, &atiixp_sht, NULL);
669a5db4 JG	241	}
669a5db4 JG	242
2d2744fc JG	243	static const struct pci_device_id atiixp[] = {
	244	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), },
	245	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), },
	246	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), },
	247	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), },
1ca972c2	248	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP700_IDE), },
2d2744fc JG	249
2d2744fc JG	250	{ },
669a5db4 JG	251	};
	252
	253	static struct pci_driver atiixp_pci_driver = {
	254	.name = DRV_NAME,
	255	.id_table = atiixp,
	256	.probe = atiixp_init_one,
30ced0f0	257	.remove = ata_pci_remove_one,
438ac6d5	258	#ifdef CONFIG_PM
30ced0f0 A	259	.resume = ata_pci_device_resume,
30ced0f0 A	260	.suspend = ata_pci_device_suspend,
438ac6d5	261	#endif
669a5db4 JG	262	};
	263
	264	static int __init atiixp_init(void)
	265	{
	266	return pci_register_driver(&atiixp_pci_driver);
	267	}
	268
	269
	270	static void __exit atiixp_exit(void)
	271	{
	272	pci_unregister_driver(&atiixp_pci_driver);
	273	}
	274
669a5db4 JG	275	MODULE_AUTHOR("Alan Cox");
	276	MODULE_DESCRIPTION("low-level driver for ATI IXP200/300/400");
	277	MODULE_LICENSE("GPL");
	278	MODULE_DEVICE_TABLE(pci, atiixp);
	279	MODULE_VERSION(DRV_VERSION);
	280
	281	module_init(atiixp_init);
	282	module_exit(atiixp_exit);