[linux-2.6-block.git] / drivers / ata / pata_atiixp.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * pata_atiixp.c 	- ATI PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  (C) 2009-2010 Bartlomiej Zolnierkiewicz
 *
 * Based on
 *
 *  linux/drivers/ide/pci/atiixp.c	Version 0.01-bart2	Feb. 26, 2004
 *
 *  Copyright (C) 2003 ATI Inc. <hyu@ati.com>
 *  Copyright (C) 2004 Bartlomiej Zolnierkiewicz
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include <linux/dmi.h>

#define DRV_NAME "pata_atiixp"
#define DRV_VERSION "0.4.6"

enum {
	ATIIXP_IDE_PIO_TIMING	= 0x40,
	ATIIXP_IDE_MWDMA_TIMING	= 0x44,
	ATIIXP_IDE_PIO_CONTROL	= 0x48,
	ATIIXP_IDE_PIO_MODE	= 0x4a,
	ATIIXP_IDE_UDMA_CONTROL	= 0x54,
	ATIIXP_IDE_UDMA_MODE 	= 0x56
};

static const struct dmi_system_id attixp_cable_override_dmi_table[] = {
	{
		/* Board has onboard PATA<->SATA converters */
		.ident = "MSI E350DM-E33",
		.matches = {
			DMI_MATCH(DMI_BOARD_VENDOR, "MSI"),
			DMI_MATCH(DMI_BOARD_NAME, "E350DM-E33(MS-7720)"),
		},
	},
	{ }
};

static int atiixp_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 udma;

	if (dmi_check_system(attixp_cable_override_dmi_table))
		return ATA_CBL_PATA40_SHORT;

	/* Hack from drivers/ide/pci. Really we want to know how to do the
	   raw detection not play follow the bios mode guess */
	pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ap->port_no, &udma);
	if ((udma & 0x07) >= 0x04 || (udma & 0x70) >= 0x40)
		return  ATA_CBL_PATA80;
	return ATA_CBL_PATA40;
}

static DEFINE_SPINLOCK(atiixp_lock);

/**
 *	atiixp_prereset	-	perform reset handling
 *	@link: ATA link
 *	@deadline: deadline jiffies for the operation
 *
 *	Reset sequence checking enable bits to see which ports are
 *	active.
 */

static int atiixp_prereset(struct ata_link *link, unsigned long deadline)
{
	static const struct pci_bits atiixp_enable_bits[] = {
		{ 0x48, 1, 0x01, 0x00 },
		{ 0x48, 1, 0x08, 0x00 }
	};

	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	if (!pci_test_config_bits(pdev, &atiixp_enable_bits[ap->port_no]))
		return -ENOENT;

	return ata_sff_prereset(link, deadline);
}

/**
 *	atiixp_set_pio_timing	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *	@pio: Requested PIO
 *
 *	Called by both the pio and dma setup functions to set the controller
 *	timings for PIO transfers. We must load both the mode number and
 *	timing values into the controller.
 */

static void atiixp_set_pio_timing(struct ata_port *ap, struct ata_device *adev, int pio)
{
	static const u8 pio_timings[5] = { 0x5D, 0x47, 0x34, 0x22, 0x20 };

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int dn = 2 * ap->port_no + adev->devno;
	int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1);
	u32 pio_timing_data;
	u16 pio_mode_data;

	pci_read_config_word(pdev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
	pio_mode_data &= ~(0x7 << (4 * dn));
	pio_mode_data |= pio << (4 * dn);
	pci_write_config_word(pdev, ATIIXP_IDE_PIO_MODE, pio_mode_data);

	pci_read_config_dword(pdev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
	pio_timing_data &= ~(0xFF << timing_shift);
	pio_timing_data |= (pio_timings[pio] << timing_shift);
	pci_write_config_dword(pdev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
}

/**
 *	atiixp_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the PIO mode setup. We use a shared helper for this
 *	as the DMA setup must also adjust the PIO timing information.
 */

static void atiixp_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	unsigned long flags;
	spin_lock_irqsave(&atiixp_lock, flags);
	atiixp_set_pio_timing(ap, adev, adev->pio_mode - XFER_PIO_0);
	spin_unlock_irqrestore(&atiixp_lock, flags);
}

/**
 *	atiixp_set_dmamode	-	set initial DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the DMA mode setup. We use timing tables for most
 *	modes but must tune an appropriate PIO mode to match.
 */

static void atiixp_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	static const u8 mwdma_timings[5] = { 0x77, 0x21, 0x20 };

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int dma = adev->dma_mode;
	int dn = 2 * ap->port_no + adev->devno;
	int wanted_pio;
	unsigned long flags;

	spin_lock_irqsave(&atiixp_lock, flags);

	if (adev->dma_mode >= XFER_UDMA_0) {
		u16 udma_mode_data;

		dma -= XFER_UDMA_0;

		pci_read_config_word(pdev, ATIIXP_IDE_UDMA_MODE, &udma_mode_data);
		udma_mode_data &= ~(0x7 << (4 * dn));
		udma_mode_data |= dma << (4 * dn);
		pci_write_config_word(pdev, ATIIXP_IDE_UDMA_MODE, udma_mode_data);
	} else {
		int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1);
		u32 mwdma_timing_data;

		dma -= XFER_MW_DMA_0;

		pci_read_config_dword(pdev, ATIIXP_IDE_MWDMA_TIMING,
				      &mwdma_timing_data);
		mwdma_timing_data &= ~(0xFF << timing_shift);
		mwdma_timing_data |= (mwdma_timings[dma] << timing_shift);
		pci_write_config_dword(pdev, ATIIXP_IDE_MWDMA_TIMING,
				       mwdma_timing_data);
	}
	/*
	 *	We must now look at the PIO mode situation. We may need to
	 *	adjust the PIO mode to keep the timings acceptable
	 */
	if (adev->dma_mode >= XFER_MW_DMA_2)
		wanted_pio = 4;
	else if (adev->dma_mode == XFER_MW_DMA_1)
		wanted_pio = 3;
	else if (adev->dma_mode == XFER_MW_DMA_0)
		wanted_pio = 0;
	else BUG();

	if (adev->pio_mode != wanted_pio)
		atiixp_set_pio_timing(ap, adev, wanted_pio);
	spin_unlock_irqrestore(&atiixp_lock, flags);
}

/**
 *	atiixp_bmdma_start	-	DMA start callback
 *	@qc: Command in progress
 *
 *	When DMA begins we need to ensure that the UDMA control
 *	register for the channel is correctly set.
 *
 *	Note: The host lock held by the libata layer protects
 *	us from two channels both trying to set DMA bits at once
 */

static void atiixp_bmdma_start(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct ata_device *adev = qc->dev;

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int dn = (2 * ap->port_no) + adev->devno;
	u16 tmp16;

	pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
	if (ata_using_udma(adev))
		tmp16 |= (1 << dn);
	else
		tmp16 &= ~(1 << dn);
	pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
	ata_bmdma_start(qc);
}

/**
 *	atiixp_bmdma_stop	-	DMA stop callback
 *	@qc: Command in progress
 *
 *	DMA has completed. Clear the UDMA flag as the next operations will
 *	be PIO ones not UDMA data transfer.
 *
 *	Note: The host lock held by the libata layer protects
 *	us from two channels both trying to set DMA bits at once
 */

static void atiixp_bmdma_stop(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int dn = (2 * ap->port_no) + qc->dev->devno;
	u16 tmp16;

	pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
	tmp16 &= ~(1 << dn);
	pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
	ata_bmdma_stop(qc);
}

static const struct scsi_host_template atiixp_sht = {
	ATA_BASE_SHT(DRV_NAME),
	.sg_tablesize		= LIBATA_DUMB_MAX_PRD,
	.dma_boundary		= ATA_DMA_BOUNDARY,
};

static struct ata_port_operations atiixp_port_ops = {
	.inherits	= &ata_bmdma_port_ops,

	.qc_prep 	= ata_bmdma_dumb_qc_prep,
	.bmdma_start 	= atiixp_bmdma_start,
	.bmdma_stop	= atiixp_bmdma_stop,

	.prereset	= atiixp_prereset,
	.cable_detect	= atiixp_cable_detect,
	.set_piomode	= atiixp_set_piomode,
	.set_dmamode	= atiixp_set_dmamode,
};

static int atiixp_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const struct ata_port_info info = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = ATA_PIO4,
		.mwdma_mask = ATA_MWDMA12_ONLY,
		.udma_mask = ATA_UDMA5,
		.port_ops = &atiixp_port_ops
	};
	const struct ata_port_info *ppi[] = { &info, &info };

	/* SB600 doesn't have secondary port wired */
	if (pdev->device == PCI_DEVICE_ID_ATI_IXP600_IDE)
		ppi[1] = &ata_dummy_port_info;

	return ata_pci_bmdma_init_one(pdev, ppi, &atiixp_sht, NULL,
				      ATA_HOST_PARALLEL_SCAN);
}

static const struct pci_device_id atiixp[] = {
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), },
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), },
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), },
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), },
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP700_IDE), },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_HUDSON2_IDE), },

	{ },
};

static struct pci_driver atiixp_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= atiixp,
	.probe 		= atiixp_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM_SLEEP
	.resume		= ata_pci_device_resume,
	.suspend	= ata_pci_device_suspend,
#endif
};

module_pci_driver(atiixp_pci_driver);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for ATI IXP200/300/400");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, atiixp);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
09c434b8	1	// SPDX-License-Identifier: GPL-2.0-only
669a5db4 JG	2	/*
	3	* pata_atiixp.c - ATI PATA for new ATA layer
	4	* (C) 2005 Red Hat Inc
e99846f1	5	* (C) 2009-2010 Bartlomiej Zolnierkiewicz
669a5db4 JG	6	*
	7	* Based on
	8	*
	9	* linux/drivers/ide/pci/atiixp.c Version 0.01-bart2 Feb. 26, 2004
	10	*
	11	* Copyright (C) 2003 ATI Inc. <hyu@ati.com>
	12	* Copyright (C) 2004 Bartlomiej Zolnierkiewicz
	13	*
	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/module.h>
	18	#include <linux/pci.h>
669a5db4 JG	19	#include <linux/blkdev.h>
	20	#include <linux/delay.h>
	21	#include <scsi/scsi_host.h>
	22	#include <linux/libata.h>
1117c811	23	#include <linux/dmi.h>
669a5db4 JG	24
669a5db4 JG	25	#define DRV_NAME "pata_atiixp"
2a3103ce	26	#define DRV_VERSION "0.4.6"
669a5db4 JG	27
	28	enum {
	29	ATIIXP_IDE_PIO_TIMING = 0x40,
	30	ATIIXP_IDE_MWDMA_TIMING = 0x44,
	31	ATIIXP_IDE_PIO_CONTROL = 0x48,
	32	ATIIXP_IDE_PIO_MODE = 0x4a,
	33	ATIIXP_IDE_UDMA_CONTROL = 0x54,
	34	ATIIXP_IDE_UDMA_MODE = 0x56
	35	};
	36
1117c811 AH	37	static const struct dmi_system_id attixp_cable_override_dmi_table[] = {
	38	{
	39	/* Board has onboard PATA<->SATA converters */
	40	.ident = "MSI E350DM-E33",
	41	.matches = {
	42	DMI_MATCH(DMI_BOARD_VENDOR, "MSI"),
	43	DMI_MATCH(DMI_BOARD_NAME, "E350DM-E33(MS-7720)"),
	44	},
	45	},
	46	{ }
	47	};
	48
84708606 AC	49	static int atiixp_cable_detect(struct ata_port *ap)
	50	{
	51	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	52	u8 udma;
	53
1117c811 AH	54	if (dmi_check_system(attixp_cable_override_dmi_table))
	55	return ATA_CBL_PATA40_SHORT;
	56
84708606 AC	57	/* Hack from drivers/ide/pci. Really we want to know how to do the
	58	raw detection not play follow the bios mode guess */
	59	pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ap->port_no, &udma);
	60	if ((udma & 0x07) >= 0x04 \|\| (udma & 0x70) >= 0x40)
	61	return ATA_CBL_PATA80;
	62	return ATA_CBL_PATA40;
	63	}
	64
e99846f1 BZ	65	static DEFINE_SPINLOCK(atiixp_lock);
e99846f1 BZ	66
46b9e770 BZ	67	/**
	68	* atiixp_prereset - perform reset handling
	69	* @link: ATA link
	70	* @deadline: deadline jiffies for the operation
	71	*
	72	* Reset sequence checking enable bits to see which ports are
	73	* active.
	74	*/
	75
	76	static int atiixp_prereset(struct ata_link *link, unsigned long deadline)
	77	{
	78	static const struct pci_bits atiixp_enable_bits[] = {
	79	{ 0x48, 1, 0x01, 0x00 },
	80	{ 0x48, 1, 0x08, 0x00 }
	81	};
	82
	83	struct ata_port *ap = link->ap;
	84	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	85
	86	if (!pci_test_config_bits(pdev, &atiixp_enable_bits[ap->port_no]))
	87	return -ENOENT;
	88
	89	return ata_sff_prereset(link, deadline);
	90	}
	91
669a5db4 JG	92	/**
	93	* atiixp_set_pio_timing - set initial PIO mode data
	94	* @ap: ATA interface
	95	* @adev: ATA device
2d35ba9e	96	* @pio: Requested PIO
669a5db4 JG	97	*
	98	* Called by both the pio and dma setup functions to set the controller
	99	* timings for PIO transfers. We must load both the mode number and
	100	* timing values into the controller.
	101	*/
	102
	103	static void atiixp_set_pio_timing(struct ata_port ap, struct ata_device adev, int pio)
	104	{
9ab84425	105	static const u8 pio_timings[5] = { 0x5D, 0x47, 0x34, 0x22, 0x20 };
669a5db4 JG	106
	107	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	108	int dn = 2 * ap->port_no + adev->devno;
669a5db4	109	int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1);
1fd4bbec BZ	110	u32 pio_timing_data;
1fd4bbec BZ	111	u16 pio_mode_data;
669a5db4 JG	112
	113	pci_read_config_word(pdev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
	114	pio_mode_data &= ~(0x7 << (4 * dn));
	115	pio_mode_data \|= pio << (4 * dn);
	116	pci_write_config_word(pdev, ATIIXP_IDE_PIO_MODE, pio_mode_data);
	117
1fd4bbec	118	pci_read_config_dword(pdev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
d7b5a23f JG	119	pio_timing_data &= ~(0xFF << timing_shift);
d7b5a23f JG	120	pio_timing_data \|= (pio_timings[pio] << timing_shift);
1fd4bbec	121	pci_write_config_dword(pdev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
669a5db4 JG	122	}
	123
	124	/**
	125	* atiixp_set_piomode - set initial PIO mode data
	126	* @ap: ATA interface
	127	* @adev: ATA device
	128	*
	129	* Called to do the PIO mode setup. We use a shared helper for this
	130	* as the DMA setup must also adjust the PIO timing information.
	131	*/
	132
	133	static void atiixp_set_piomode(struct ata_port ap, struct ata_device adev)
	134	{
e99846f1 BZ	135	unsigned long flags;
e99846f1 BZ	136	spin_lock_irqsave(&atiixp_lock, flags);
669a5db4	137	atiixp_set_pio_timing(ap, adev, adev->pio_mode - XFER_PIO_0);
e99846f1	138	spin_unlock_irqrestore(&atiixp_lock, flags);
669a5db4 JG	139	}
	140
	141	/**
	142	* atiixp_set_dmamode - set initial DMA mode data
	143	* @ap: ATA interface
	144	* @adev: ATA device
	145	*
	146	* Called to do the DMA mode setup. We use timing tables for most
	147	* modes but must tune an appropriate PIO mode to match.
	148	*/
	149
	150	static void atiixp_set_dmamode(struct ata_port ap, struct ata_device adev)
	151	{
9ab84425	152	static const u8 mwdma_timings[5] = { 0x77, 0x21, 0x20 };
669a5db4 JG	153
	154	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	155	int dma = adev->dma_mode;
	156	int dn = 2 * ap->port_no + adev->devno;
	157	int wanted_pio;
e99846f1 BZ	158	unsigned long flags;
	159
	160	spin_lock_irqsave(&atiixp_lock, flags);
669a5db4 JG	161
	162	if (adev->dma_mode >= XFER_UDMA_0) {
	163	u16 udma_mode_data;
	164
	165	dma -= XFER_UDMA_0;
	166
	167	pci_read_config_word(pdev, ATIIXP_IDE_UDMA_MODE, &udma_mode_data);
	168	udma_mode_data &= ~(0x7 << (4 * dn));
	169	udma_mode_data \|= dma << (4 * dn);
	170	pci_write_config_word(pdev, ATIIXP_IDE_UDMA_MODE, udma_mode_data);
	171	} else {
669a5db4	172	int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1);
1fd4bbec	173	u32 mwdma_timing_data;
669a5db4 JG	174
	175	dma -= XFER_MW_DMA_0;
	176
1fd4bbec BZ	177	pci_read_config_dword(pdev, ATIIXP_IDE_MWDMA_TIMING,
1fd4bbec BZ	178	&mwdma_timing_data);
669a5db4 JG	179	mwdma_timing_data &= ~(0xFF << timing_shift);
669a5db4 JG	180	mwdma_timing_data \|= (mwdma_timings[dma] << timing_shift);
1fd4bbec BZ	181	pci_write_config_dword(pdev, ATIIXP_IDE_MWDMA_TIMING,
1fd4bbec BZ	182	mwdma_timing_data);
669a5db4 JG	183	}
	184	/*
	185	* We must now look at the PIO mode situation. We may need to
	186	* adjust the PIO mode to keep the timings acceptable
	187	*/
273b542e CIK	188	if (adev->dma_mode >= XFER_MW_DMA_2)
273b542e CIK	189	wanted_pio = 4;
669a5db4 JG	190	else if (adev->dma_mode == XFER_MW_DMA_1)
	191	wanted_pio = 3;
	192	else if (adev->dma_mode == XFER_MW_DMA_0)
	193	wanted_pio = 0;
	194	else BUG();
	195
	196	if (adev->pio_mode != wanted_pio)
	197	atiixp_set_pio_timing(ap, adev, wanted_pio);
e99846f1	198	spin_unlock_irqrestore(&atiixp_lock, flags);
669a5db4 JG	199	}
	200
	201	/**
	202	* atiixp_bmdma_start - DMA start callback
	203	* @qc: Command in progress
	204	*
	205	* When DMA begins we need to ensure that the UDMA control
	206	* register for the channel is correctly set.
21d2c925 AC	207	*
	208	* Note: The host lock held by the libata layer protects
	209	* us from two channels both trying to set DMA bits at once
669a5db4 JG	210	*/
	211
	212	static void atiixp_bmdma_start(struct ata_queued_cmd *qc)
	213	{
	214	struct ata_port *ap = qc->ap;
	215	struct ata_device *adev = qc->dev;
	216
	217	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	218	int dn = (2 * ap->port_no) + adev->devno;
	219	u16 tmp16;
	220
	221	pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
b15b3eba	222	if (ata_using_udma(adev))
669a5db4 JG	223	tmp16 \|= (1 << dn);
	224	else
	225	tmp16 &= ~(1 << dn);
	226	pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
	227	ata_bmdma_start(qc);
	228	}
	229
	230	/**
2d35ba9e	231	* atiixp_bmdma_stop - DMA stop callback
669a5db4 JG	232	* @qc: Command in progress
	233	*
	234	* DMA has completed. Clear the UDMA flag as the next operations will
	235	* be PIO ones not UDMA data transfer.
21d2c925 AC	236	*
	237	* Note: The host lock held by the libata layer protects
	238	* us from two channels both trying to set DMA bits at once
669a5db4 JG	239	*/
	240
	241	static void atiixp_bmdma_stop(struct ata_queued_cmd *qc)
	242	{
	243	struct ata_port *ap = qc->ap;
	244	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	245	int dn = (2 * ap->port_no) + qc->dev->devno;
	246	u16 tmp16;
	247
	248	pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
	249	tmp16 &= ~(1 << dn);
	250	pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
	251	ata_bmdma_stop(qc);
	252	}
	253
25df73d9	254	static const struct scsi_host_template atiixp_sht = {
76115de6	255	ATA_BASE_SHT(DRV_NAME),
635adc28	256	.sg_tablesize = LIBATA_DUMB_MAX_PRD,
76115de6	257	.dma_boundary = ATA_DMA_BOUNDARY,
669a5db4 JG	258	};
	259
	260	static struct ata_port_operations atiixp_port_ops = {
029cfd6b	261	.inherits = &ata_bmdma_port_ops,
669a5db4	262
f47451c4	263	.qc_prep = ata_bmdma_dumb_qc_prep,
669a5db4 JG	264	.bmdma_start = atiixp_bmdma_start,
669a5db4 JG	265	.bmdma_stop = atiixp_bmdma_stop,
bda30288	266
46b9e770	267	.prereset = atiixp_prereset,
029cfd6b TH	268	.cable_detect = atiixp_cable_detect,
	269	.set_piomode = atiixp_set_piomode,
	270	.set_dmamode = atiixp_set_dmamode,
669a5db4 JG	271	};
669a5db4 JG	272
16028232	273	static int atiixp_init_one(struct pci_dev pdev, const struct pci_device_id id)
669a5db4	274	{
1626aeb8	275	static const struct ata_port_info info = {
1d2808fd	276	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	277	.pio_mask = ATA_PIO4,
	278	.mwdma_mask = ATA_MWDMA12_ONLY,
	279	.udma_mask = ATA_UDMA5,
669a5db4 JG	280	.port_ops = &atiixp_port_ops
669a5db4 JG	281	};
16028232	282	const struct ata_port_info *ppi[] = { &info, &info };
16028232	283
e47ecd4e	284	/* SB600 doesn't have secondary port wired */
ce42c176	285	if (pdev->device == PCI_DEVICE_ID_ATI_IXP600_IDE)
e47ecd4e DS	286	ppi[1] = &ata_dummy_port_info;
e47ecd4e DS	287
1c5afdf7 TH	288	return ata_pci_bmdma_init_one(pdev, ppi, &atiixp_sht, NULL,
1c5afdf7 TH	289	ATA_HOST_PARALLEL_SCAN);
669a5db4 JG	290	}
669a5db4 JG	291
2d2744fc JG	292	static const struct pci_device_id atiixp[] = {
	293	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), },
	294	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), },
	295	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), },
	296	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), },
1ca972c2	297	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP700_IDE), },
5deab536	298	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_HUDSON2_IDE), },
2d2744fc JG	299
2d2744fc JG	300	{ },
669a5db4 JG	301	};
	302
	303	static struct pci_driver atiixp_pci_driver = {
	304	.name = DRV_NAME,
	305	.id_table = atiixp,
	306	.probe = atiixp_init_one,
30ced0f0	307	.remove = ata_pci_remove_one,
58eb8cd5	308	#ifdef CONFIG_PM_SLEEP
30ced0f0 A	309	.resume = ata_pci_device_resume,
30ced0f0 A	310	.suspend = ata_pci_device_suspend,
438ac6d5	311	#endif
669a5db4 JG	312	};
669a5db4 JG	313
2fc75da0	314	module_pci_driver(atiixp_pci_driver);
669a5db4	315
669a5db4 JG	316	MODULE_AUTHOR("Alan Cox");
	317	MODULE_DESCRIPTION("low-level driver for ATI IXP200/300/400");
	318	MODULE_LICENSE("GPL");
	319	MODULE_DEVICE_TABLE(pci, atiixp);
	320	MODULE_VERSION(DRV_VERSION);