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918d7b7c SM |
1 | /* |
2 | * PATA driver for AT91SAM9260 Static Memory Controller | |
3 | * with CompactFlash interface in True IDE mode | |
4 | * | |
5 | * Copyright (C) 2009 Matyukevich Sergey | |
6 | * | |
7 | * Based on: | |
8 | * * generic platform driver by Paul Mundt: drivers/ata/pata_platform.c | |
9 | * * pata_at32 driver by Kristoffer Nyborg Gregertsen | |
10 | * * at91_ide driver by Stanislaw Gruszka | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify it | |
13 | * under the terms of the GNU General Public License version 2 | |
14 | * as published by the Free Software Foundation. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/blkdev.h> | |
5a0e3ad6 | 22 | #include <linux/gfp.h> |
918d7b7c SM |
23 | #include <scsi/scsi_host.h> |
24 | #include <linux/ata.h> | |
25 | #include <linux/clk.h> | |
26 | #include <linux/libata.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/ata_platform.h> | |
29 | ||
918d7b7c | 30 | #include <mach/at91sam9_smc.h> |
918d7b7c SM |
31 | #include <mach/board.h> |
32 | #include <mach/gpio.h> | |
33 | ||
34 | ||
35 | #define DRV_NAME "pata_at91" | |
9719b8f5 | 36 | #define DRV_VERSION "0.2" |
918d7b7c SM |
37 | |
38 | #define CF_IDE_OFFSET 0x00c00000 | |
39 | #define CF_ALT_IDE_OFFSET 0x00e00000 | |
40 | #define CF_IDE_RES_SIZE 0x08 | |
9719b8f5 | 41 | #define NCS_RD_PULSE_LIMIT 0x3f /* maximal value for pulse bitfields */ |
918d7b7c SM |
42 | |
43 | struct at91_ide_info { | |
44 | unsigned long mode; | |
45 | unsigned int cs; | |
46 | ||
7d084d96 SM |
47 | struct clk *mck; |
48 | ||
918d7b7c SM |
49 | void __iomem *ide_addr; |
50 | void __iomem *alt_addr; | |
51 | }; | |
52 | ||
792d37af IP |
53 | static const struct ata_timing initial_timing = { |
54 | .mode = XFER_PIO_0, | |
55 | .setup = 70, | |
56 | .act8b = 290, | |
57 | .rec8b = 240, | |
58 | .cyc8b = 600, | |
59 | .active = 165, | |
60 | .recover = 150, | |
61 | .dmack_hold = 0, | |
62 | .cycle = 600, | |
63 | .udma = 0 | |
64 | }; | |
918d7b7c | 65 | |
7d084d96 | 66 | static unsigned long calc_mck_cycles(unsigned long ns, unsigned long mck_hz) |
918d7b7c SM |
67 | { |
68 | unsigned long mul; | |
69 | ||
7d084d96 SM |
70 | /* |
71 | * cycles = x [nsec] * f [Hz] / 10^9 [ns in sec] = | |
72 | * x * (f / 1_000_000_000) = | |
73 | * x * ((f * 65536) / 1_000_000_000) / 65536 = | |
74 | * x * (((f / 10_000) * 65536) / 100_000) / 65536 = | |
75 | */ | |
918d7b7c | 76 | |
7d084d96 SM |
77 | mul = (mck_hz / 10000) << 16; |
78 | mul /= 100000; | |
918d7b7c | 79 | |
7d084d96 | 80 | return (ns * mul + 65536) >> 16; /* rounding */ |
918d7b7c SM |
81 | } |
82 | ||
83 | static void set_smc_mode(struct at91_ide_info *info) | |
84 | { | |
7d084d96 SM |
85 | at91_sys_write(AT91_SMC_MODE(info->cs), info->mode); |
86 | return; | |
918d7b7c SM |
87 | } |
88 | ||
89 | static void set_smc_timing(struct device *dev, | |
90 | struct at91_ide_info *info, const struct ata_timing *ata) | |
91 | { | |
7d084d96 SM |
92 | unsigned long read_cycle, write_cycle, active, recover; |
93 | unsigned long nrd_setup, nrd_pulse, nrd_recover; | |
94 | unsigned long nwe_setup, nwe_pulse; | |
918d7b7c | 95 | |
7d084d96 SM |
96 | unsigned long ncs_write_setup, ncs_write_pulse; |
97 | unsigned long ncs_read_setup, ncs_read_pulse; | |
918d7b7c | 98 | |
7d084d96 | 99 | unsigned long mck_hz; |
918d7b7c SM |
100 | |
101 | read_cycle = ata->cyc8b; | |
102 | nrd_setup = ata->setup; | |
103 | nrd_pulse = ata->act8b; | |
104 | nrd_recover = ata->rec8b; | |
105 | ||
7d084d96 | 106 | mck_hz = clk_get_rate(info->mck); |
918d7b7c SM |
107 | |
108 | read_cycle = calc_mck_cycles(read_cycle, mck_hz); | |
109 | nrd_setup = calc_mck_cycles(nrd_setup, mck_hz); | |
110 | nrd_pulse = calc_mck_cycles(nrd_pulse, mck_hz); | |
111 | nrd_recover = calc_mck_cycles(nrd_recover, mck_hz); | |
112 | ||
918d7b7c SM |
113 | active = nrd_setup + nrd_pulse; |
114 | recover = read_cycle - active; | |
115 | ||
116 | /* Need at least two cycles recovery */ | |
117 | if (recover < 2) | |
118 | read_cycle = active + 2; | |
119 | ||
120 | /* (CS0, CS1, DIR, OE) <= (CFCE1, CFCE2, CFRNW, NCSX) timings */ | |
121 | ncs_read_setup = 1; | |
122 | ncs_read_pulse = read_cycle - 2; | |
9719b8f5 IP |
123 | if (ncs_read_pulse > NCS_RD_PULSE_LIMIT) { |
124 | ncs_read_pulse = NCS_RD_PULSE_LIMIT; | |
125 | dev_warn(dev, "ncs_read_pulse limited to maximal value %lu\n", | |
126 | ncs_read_pulse); | |
127 | } | |
918d7b7c SM |
128 | |
129 | /* Write timings same as read timings */ | |
130 | write_cycle = read_cycle; | |
131 | nwe_setup = nrd_setup; | |
132 | nwe_pulse = nrd_pulse; | |
133 | ncs_write_setup = ncs_read_setup; | |
134 | ncs_write_pulse = ncs_read_pulse; | |
135 | ||
7d084d96 | 136 | dev_dbg(dev, "ATA timings: nrd_setup = %lu nrd_pulse = %lu nrd_cycle = %lu\n", |
918d7b7c | 137 | nrd_setup, nrd_pulse, read_cycle); |
7d084d96 | 138 | dev_dbg(dev, "ATA timings: nwe_setup = %lu nwe_pulse = %lu nwe_cycle = %lu\n", |
918d7b7c | 139 | nwe_setup, nwe_pulse, write_cycle); |
7d084d96 | 140 | dev_dbg(dev, "ATA timings: ncs_read_setup = %lu ncs_read_pulse = %lu\n", |
918d7b7c | 141 | ncs_read_setup, ncs_read_pulse); |
7d084d96 | 142 | dev_dbg(dev, "ATA timings: ncs_write_setup = %lu ncs_write_pulse = %lu\n", |
918d7b7c SM |
143 | ncs_write_setup, ncs_write_pulse); |
144 | ||
145 | at91_sys_write(AT91_SMC_SETUP(info->cs), | |
146 | AT91_SMC_NWESETUP_(nwe_setup) | | |
147 | AT91_SMC_NRDSETUP_(nrd_setup) | | |
148 | AT91_SMC_NCS_WRSETUP_(ncs_write_setup) | | |
149 | AT91_SMC_NCS_RDSETUP_(ncs_read_setup)); | |
150 | ||
151 | at91_sys_write(AT91_SMC_PULSE(info->cs), | |
152 | AT91_SMC_NWEPULSE_(nwe_pulse) | | |
153 | AT91_SMC_NRDPULSE_(nrd_pulse) | | |
154 | AT91_SMC_NCS_WRPULSE_(ncs_write_pulse) | | |
155 | AT91_SMC_NCS_RDPULSE_(ncs_read_pulse)); | |
156 | ||
157 | at91_sys_write(AT91_SMC_CYCLE(info->cs), | |
158 | AT91_SMC_NWECYCLE_(write_cycle) | | |
159 | AT91_SMC_NRDCYCLE_(read_cycle)); | |
160 | ||
161 | return; | |
162 | } | |
163 | ||
164 | static void pata_at91_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
165 | { | |
166 | struct at91_ide_info *info = ap->host->private_data; | |
167 | struct ata_timing timing; | |
168 | int ret; | |
169 | ||
170 | /* Compute ATA timing and set it to SMC */ | |
171 | ret = ata_timing_compute(adev, adev->pio_mode, &timing, 1000, 0); | |
172 | if (ret) { | |
429e3861 JG |
173 | dev_warn(ap->dev, "Failed to compute ATA timing %d, " |
174 | "set PIO_0 timing\n", ret); | |
918d7b7c SM |
175 | set_smc_timing(ap->dev, info, &initial_timing); |
176 | } else { | |
177 | set_smc_timing(ap->dev, info, &timing); | |
178 | } | |
179 | ||
180 | /* Setup SMC mode */ | |
181 | set_smc_mode(info); | |
182 | ||
183 | return; | |
184 | } | |
185 | ||
186 | static unsigned int pata_at91_data_xfer_noirq(struct ata_device *dev, | |
187 | unsigned char *buf, unsigned int buflen, int rw) | |
188 | { | |
189 | struct at91_ide_info *info = dev->link->ap->host->private_data; | |
190 | unsigned int consumed; | |
191 | unsigned long flags; | |
192 | unsigned int mode; | |
193 | ||
194 | local_irq_save(flags); | |
195 | mode = at91_sys_read(AT91_SMC_MODE(info->cs)); | |
196 | ||
197 | /* set 16bit mode before writing data */ | |
198 | at91_sys_write(AT91_SMC_MODE(info->cs), | |
199 | (mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_16); | |
200 | ||
201 | consumed = ata_sff_data_xfer(dev, buf, buflen, rw); | |
202 | ||
203 | /* restore 8bit mode after data is written */ | |
204 | at91_sys_write(AT91_SMC_MODE(info->cs), | |
205 | (mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_8); | |
206 | ||
207 | local_irq_restore(flags); | |
208 | return consumed; | |
209 | } | |
210 | ||
211 | static struct scsi_host_template pata_at91_sht = { | |
212 | ATA_PIO_SHT(DRV_NAME), | |
213 | }; | |
214 | ||
215 | static struct ata_port_operations pata_at91_port_ops = { | |
216 | .inherits = &ata_sff_port_ops, | |
217 | ||
218 | .sff_data_xfer = pata_at91_data_xfer_noirq, | |
219 | .set_piomode = pata_at91_set_piomode, | |
220 | .cable_detect = ata_cable_40wire, | |
918d7b7c SM |
221 | }; |
222 | ||
223 | static int __devinit pata_at91_probe(struct platform_device *pdev) | |
224 | { | |
225 | struct at91_cf_data *board = pdev->dev.platform_data; | |
226 | struct device *dev = &pdev->dev; | |
227 | struct at91_ide_info *info; | |
228 | struct resource *mem_res; | |
229 | struct ata_host *host; | |
230 | struct ata_port *ap; | |
7d084d96 | 231 | |
918d7b7c SM |
232 | int irq_flags = 0; |
233 | int irq = 0; | |
234 | int ret; | |
235 | ||
236 | /* get platform resources: IO/CTL memories and irq/rst pins */ | |
237 | ||
238 | if (pdev->num_resources != 1) { | |
239 | dev_err(&pdev->dev, "invalid number of resources\n"); | |
240 | return -EINVAL; | |
241 | } | |
242 | ||
243 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
244 | ||
245 | if (!mem_res) { | |
246 | dev_err(dev, "failed to get mem resource\n"); | |
247 | return -EINVAL; | |
248 | } | |
249 | ||
250 | irq = board->irq_pin; | |
251 | ||
252 | /* init ata host */ | |
253 | ||
254 | host = ata_host_alloc(dev, 1); | |
255 | ||
256 | if (!host) | |
257 | return -ENOMEM; | |
258 | ||
259 | ap = host->ports[0]; | |
260 | ap->ops = &pata_at91_port_ops; | |
261 | ap->flags |= ATA_FLAG_SLAVE_POSS; | |
262 | ap->pio_mask = ATA_PIO4; | |
263 | ||
264 | if (!irq) { | |
265 | ap->flags |= ATA_FLAG_PIO_POLLING; | |
266 | ata_port_desc(ap, "no IRQ, using PIO polling"); | |
267 | } | |
268 | ||
df9eba8c | 269 | info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); |
918d7b7c SM |
270 | |
271 | if (!info) { | |
272 | dev_err(dev, "failed to allocate memory for private data\n"); | |
273 | return -ENOMEM; | |
274 | } | |
275 | ||
7d084d96 SM |
276 | info->mck = clk_get(NULL, "mck"); |
277 | ||
278 | if (IS_ERR(info->mck)) { | |
279 | dev_err(dev, "failed to get access to mck clock\n"); | |
280 | return -ENODEV; | |
281 | } | |
282 | ||
918d7b7c SM |
283 | info->cs = board->chipselect; |
284 | info->mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | | |
285 | AT91_SMC_EXNWMODE_READY | AT91_SMC_BAT_SELECT | | |
286 | AT91_SMC_DBW_8 | AT91_SMC_TDF_(0); | |
287 | ||
288 | info->ide_addr = devm_ioremap(dev, | |
289 | mem_res->start + CF_IDE_OFFSET, CF_IDE_RES_SIZE); | |
290 | ||
291 | if (!info->ide_addr) { | |
292 | dev_err(dev, "failed to map IO base\n"); | |
293 | ret = -ENOMEM; | |
df9eba8c | 294 | goto err_put; |
918d7b7c SM |
295 | } |
296 | ||
297 | info->alt_addr = devm_ioremap(dev, | |
298 | mem_res->start + CF_ALT_IDE_OFFSET, CF_IDE_RES_SIZE); | |
299 | ||
300 | if (!info->alt_addr) { | |
301 | dev_err(dev, "failed to map CTL base\n"); | |
302 | ret = -ENOMEM; | |
df9eba8c | 303 | goto err_put; |
918d7b7c SM |
304 | } |
305 | ||
306 | ap->ioaddr.cmd_addr = info->ide_addr; | |
307 | ap->ioaddr.ctl_addr = info->alt_addr + 0x06; | |
308 | ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr; | |
309 | ||
310 | ata_sff_std_ports(&ap->ioaddr); | |
311 | ||
312 | ata_port_desc(ap, "mmio cmd 0x%llx ctl 0x%llx", | |
313 | (unsigned long long)mem_res->start + CF_IDE_OFFSET, | |
314 | (unsigned long long)mem_res->start + CF_ALT_IDE_OFFSET); | |
315 | ||
316 | host->private_data = info; | |
317 | ||
318 | return ata_host_activate(host, irq ? gpio_to_irq(irq) : 0, | |
319 | irq ? ata_sff_interrupt : NULL, | |
320 | irq_flags, &pata_at91_sht); | |
321 | ||
df9eba8c | 322 | err_put: |
7d084d96 | 323 | clk_put(info->mck); |
918d7b7c SM |
324 | return ret; |
325 | } | |
326 | ||
327 | static int __devexit pata_at91_remove(struct platform_device *pdev) | |
328 | { | |
329 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
1e1f421a | 330 | struct at91_ide_info *info; |
918d7b7c SM |
331 | |
332 | if (!host) | |
333 | return 0; | |
1e1f421a | 334 | info = host->private_data; |
918d7b7c SM |
335 | |
336 | ata_host_detach(host); | |
337 | ||
338 | if (!info) | |
339 | return 0; | |
340 | ||
7d084d96 | 341 | clk_put(info->mck); |
918d7b7c | 342 | |
918d7b7c SM |
343 | return 0; |
344 | } | |
345 | ||
346 | static struct platform_driver pata_at91_driver = { | |
347 | .probe = pata_at91_probe, | |
348 | .remove = __devexit_p(pata_at91_remove), | |
349 | .driver = { | |
350 | .name = DRV_NAME, | |
351 | .owner = THIS_MODULE, | |
352 | }, | |
353 | }; | |
354 | ||
355 | static int __init pata_at91_init(void) | |
356 | { | |
357 | return platform_driver_register(&pata_at91_driver); | |
358 | } | |
359 | ||
360 | static void __exit pata_at91_exit(void) | |
361 | { | |
362 | platform_driver_unregister(&pata_at91_driver); | |
363 | } | |
364 | ||
365 | ||
366 | module_init(pata_at91_init); | |
367 | module_exit(pata_at91_exit); | |
368 | ||
369 | ||
370 | MODULE_LICENSE("GPL"); | |
371 | MODULE_DESCRIPTION("Driver for CF in True IDE mode on AT91SAM9260 SoC"); | |
372 | MODULE_AUTHOR("Matyukevich Sergey"); | |
373 | MODULE_VERSION(DRV_VERSION); | |
374 |