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7c9ef8e4 KNG |
1 | /* |
2 | * AVR32 SMC/CFC PATA Driver | |
3 | * | |
4 | * Copyright (C) 2007 Atmel Norway | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License version | |
8 | * 2 as published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #define DEBUG | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/irq.h> | |
21 | #include <scsi/scsi_host.h> | |
22 | #include <linux/ata.h> | |
23 | #include <linux/libata.h> | |
24 | #include <linux/err.h> | |
25 | #include <linux/io.h> | |
26 | ||
27 | #include <asm/arch/board.h> | |
28 | #include <asm/arch/smc.h> | |
29 | ||
30 | #define DRV_NAME "pata_at32" | |
1c20a493 | 31 | #define DRV_VERSION "0.0.3" |
7c9ef8e4 KNG |
32 | |
33 | /* | |
34 | * CompactFlash controller memory layout relative to the base address: | |
35 | * | |
36 | * Attribute memory: 0000 0000 -> 003f ffff | |
37 | * Common memory: 0040 0000 -> 007f ffff | |
38 | * I/O memory: 0080 0000 -> 00bf ffff | |
39 | * True IDE Mode: 00c0 0000 -> 00df ffff | |
40 | * Alt IDE Mode: 00e0 0000 -> 00ff ffff | |
41 | * | |
42 | * Only True IDE and Alt True IDE mode are needed for this driver. | |
43 | * | |
44 | * True IDE mode => CS0 = 0, CS1 = 1 (cmd, error, stat, etc) | |
45 | * Alt True IDE mode => CS0 = 1, CS1 = 0 (ctl, alt_stat) | |
46 | */ | |
47 | #define CF_IDE_OFFSET 0x00c00000 | |
48 | #define CF_ALT_IDE_OFFSET 0x00e00000 | |
49 | #define CF_RES_SIZE 2048 | |
50 | ||
51 | /* | |
52 | * Define DEBUG_BUS if you are doing debugging of your own EBI -> PATA | |
53 | * adaptor with a logic analyzer or similar. | |
54 | */ | |
55 | #undef DEBUG_BUS | |
56 | ||
57 | /* | |
58 | * ATA PIO modes | |
59 | * | |
60 | * Name | Mb/s | Min cycle time | Mask | |
61 | * --------+-------+----------------+-------- | |
62 | * Mode 0 | 3.3 | 600 ns | 0x01 | |
63 | * Mode 1 | 5.2 | 383 ns | 0x03 | |
64 | * Mode 2 | 8.3 | 240 ns | 0x07 | |
65 | * Mode 3 | 11.1 | 180 ns | 0x0f | |
66 | * Mode 4 | 16.7 | 120 ns | 0x1f | |
1c20a493 KNG |
67 | * |
68 | * Alter PIO_MASK below according to table to set maximal PIO mode. | |
7c9ef8e4 KNG |
69 | */ |
70 | #define PIO_MASK (0x1f) | |
71 | ||
72 | /* | |
73 | * Struct containing private information about device. | |
74 | */ | |
75 | struct at32_ide_info { | |
76 | unsigned int irq; | |
77 | struct resource res_ide; | |
78 | struct resource res_alt; | |
79 | void __iomem *ide_addr; | |
80 | void __iomem *alt_addr; | |
81 | unsigned int cs; | |
82 | struct smc_config smc; | |
83 | }; | |
84 | ||
85 | /* | |
86 | * Setup SMC for the given ATA timing. | |
87 | */ | |
88 | static int pata_at32_setup_timing(struct device *dev, | |
89 | struct at32_ide_info *info, | |
1c20a493 | 90 | const struct ata_timing *ata) |
7c9ef8e4 | 91 | { |
7c9ef8e4 | 92 | struct smc_config *smc = &info->smc; |
1c20a493 | 93 | struct smc_timing timing; |
7c9ef8e4 KNG |
94 | |
95 | int active; | |
96 | int recover; | |
97 | ||
1c20a493 KNG |
98 | memset(&timing, 0, sizeof(struct smc_timing)); |
99 | ||
7c9ef8e4 | 100 | /* Total cycle time */ |
1c20a493 | 101 | timing.read_cycle = ata->cyc8b; |
7c9ef8e4 KNG |
102 | |
103 | /* DIOR <= CFIOR timings */ | |
1c20a493 KNG |
104 | timing.nrd_setup = ata->setup; |
105 | timing.nrd_pulse = ata->act8b; | |
106 | timing.nrd_recover = ata->rec8b; | |
107 | ||
108 | /* Convert nanosecond timing to clock cycles */ | |
109 | smc_set_timing(smc, &timing); | |
7c9ef8e4 | 110 | |
1c20a493 KNG |
111 | /* Add one extra cycle setup due to signal ring */ |
112 | smc->nrd_setup = smc->nrd_setup + 1; | |
113 | ||
114 | active = smc->nrd_setup + smc->nrd_pulse; | |
7c9ef8e4 KNG |
115 | recover = smc->read_cycle - active; |
116 | ||
1c20a493 KNG |
117 | /* Need at least two cycles recovery */ |
118 | if (recover < 2) | |
119 | smc->read_cycle = active + 2; | |
7c9ef8e4 KNG |
120 | |
121 | /* (CS0, CS1, DIR, OE) <= (CFCE1, CFCE2, CFRNW, NCSX) timings */ | |
1c20a493 KNG |
122 | smc->ncs_read_setup = 1; |
123 | smc->ncs_read_pulse = smc->read_cycle - 2; | |
7c9ef8e4 KNG |
124 | |
125 | /* Write timings same as read timings */ | |
126 | smc->write_cycle = smc->read_cycle; | |
127 | smc->nwe_setup = smc->nrd_setup; | |
128 | smc->nwe_pulse = smc->nrd_pulse; | |
129 | smc->ncs_write_setup = smc->ncs_read_setup; | |
130 | smc->ncs_write_pulse = smc->ncs_read_pulse; | |
131 | ||
1c20a493 KNG |
132 | /* Do some debugging output of ATA and SMC timings */ |
133 | dev_dbg(dev, "ATA: C=%d S=%d P=%d R=%d\n", | |
134 | ata->cyc8b, ata->setup, ata->act8b, ata->rec8b); | |
135 | ||
136 | dev_dbg(dev, "SMC: C=%d S=%d P=%d NS=%d NP=%d\n", | |
7c9ef8e4 | 137 | smc->read_cycle, smc->nrd_setup, smc->nrd_pulse, |
1c20a493 | 138 | smc->ncs_read_setup, smc->ncs_read_pulse); |
7c9ef8e4 KNG |
139 | |
140 | /* Finally, configure the SMC */ | |
141 | return smc_set_configuration(info->cs, smc); | |
142 | } | |
143 | ||
144 | /* | |
145 | * Procedures for libATA. | |
146 | */ | |
147 | static void pata_at32_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
148 | { | |
149 | struct ata_timing timing; | |
150 | struct at32_ide_info *info = ap->host->private_data; | |
151 | ||
152 | int ret; | |
153 | ||
154 | /* Compute ATA timing */ | |
155 | ret = ata_timing_compute(adev, adev->pio_mode, &timing, 1000, 0); | |
156 | if (ret) { | |
157 | dev_warn(ap->dev, "Failed to compute ATA timing %d\n", ret); | |
158 | return; | |
159 | } | |
160 | ||
161 | /* Setup SMC to ATA timing */ | |
162 | ret = pata_at32_setup_timing(ap->dev, info, &timing); | |
163 | if (ret) { | |
164 | dev_warn(ap->dev, "Failed to setup ATA timing %d\n", ret); | |
165 | return; | |
166 | } | |
167 | } | |
168 | ||
169 | static void pata_at32_irq_clear(struct ata_port *ap) | |
170 | { | |
171 | /* No DMA controller yet */ | |
172 | } | |
173 | ||
174 | static struct scsi_host_template at32_sht = { | |
175 | .module = THIS_MODULE, | |
176 | .name = DRV_NAME, | |
177 | .ioctl = ata_scsi_ioctl, | |
178 | .queuecommand = ata_scsi_queuecmd, | |
179 | .can_queue = ATA_DEF_QUEUE, | |
180 | .this_id = ATA_SHT_THIS_ID, | |
181 | .sg_tablesize = LIBATA_MAX_PRD, | |
182 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, | |
183 | .emulated = ATA_SHT_EMULATED, | |
184 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
185 | .proc_name = DRV_NAME, | |
186 | .dma_boundary = ATA_DMA_BOUNDARY, | |
187 | .slave_configure = ata_scsi_slave_config, | |
188 | .slave_destroy = ata_scsi_slave_destroy, | |
189 | .bios_param = ata_std_bios_param, | |
190 | }; | |
191 | ||
192 | static struct ata_port_operations at32_port_ops = { | |
7c9ef8e4 KNG |
193 | .set_piomode = pata_at32_set_piomode, |
194 | .tf_load = ata_tf_load, | |
195 | .tf_read = ata_tf_read, | |
196 | .exec_command = ata_exec_command, | |
197 | .check_status = ata_check_status, | |
198 | .dev_select = ata_std_dev_select, | |
199 | ||
200 | .freeze = ata_bmdma_freeze, | |
201 | .thaw = ata_bmdma_thaw, | |
202 | .error_handler = ata_bmdma_error_handler, | |
203 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
204 | .cable_detect = ata_cable_40wire, | |
205 | ||
206 | .qc_prep = ata_qc_prep, | |
207 | .qc_issue = ata_qc_issue_prot, | |
208 | ||
209 | .data_xfer = ata_data_xfer, | |
210 | ||
211 | .irq_clear = pata_at32_irq_clear, | |
212 | .irq_on = ata_irq_on, | |
7c9ef8e4 KNG |
213 | |
214 | .port_start = ata_sff_port_start, | |
215 | }; | |
216 | ||
217 | static int __init pata_at32_init_one(struct device *dev, | |
218 | struct at32_ide_info *info) | |
219 | { | |
220 | struct ata_host *host; | |
221 | struct ata_port *ap; | |
222 | ||
223 | host = ata_host_alloc(dev, 1); | |
224 | if (!host) | |
225 | return -ENOMEM; | |
226 | ||
227 | ap = host->ports[0]; | |
228 | ||
229 | /* Setup ATA bindings */ | |
230 | ap->ops = &at32_port_ops; | |
231 | ap->pio_mask = PIO_MASK; | |
1c20a493 | 232 | ap->flags |= ATA_FLAG_MMIO | ATA_FLAG_SLAVE_POSS; |
7c9ef8e4 KNG |
233 | |
234 | /* | |
235 | * Since all 8-bit taskfile transfers has to go on the lower | |
236 | * byte of the data bus and there is a bug in the SMC that | |
237 | * makes it impossible to alter the bus width during runtime, | |
238 | * we need to hardwire the address signals as follows: | |
239 | * | |
240 | * A_IDE(2:0) <= A_EBI(3:1) | |
241 | * | |
242 | * This makes all addresses on the EBI even, thus all data | |
243 | * will be on the lower byte of the data bus. All addresses | |
244 | * used by libATA need to be altered according to this. | |
245 | */ | |
246 | ap->ioaddr.altstatus_addr = info->alt_addr + (0x06 << 1); | |
247 | ap->ioaddr.ctl_addr = info->alt_addr + (0x06 << 1); | |
248 | ||
249 | ap->ioaddr.data_addr = info->ide_addr + (ATA_REG_DATA << 1); | |
250 | ap->ioaddr.error_addr = info->ide_addr + (ATA_REG_ERR << 1); | |
251 | ap->ioaddr.feature_addr = info->ide_addr + (ATA_REG_FEATURE << 1); | |
252 | ap->ioaddr.nsect_addr = info->ide_addr + (ATA_REG_NSECT << 1); | |
253 | ap->ioaddr.lbal_addr = info->ide_addr + (ATA_REG_LBAL << 1); | |
254 | ap->ioaddr.lbam_addr = info->ide_addr + (ATA_REG_LBAM << 1); | |
255 | ap->ioaddr.lbah_addr = info->ide_addr + (ATA_REG_LBAH << 1); | |
256 | ap->ioaddr.device_addr = info->ide_addr + (ATA_REG_DEVICE << 1); | |
257 | ap->ioaddr.status_addr = info->ide_addr + (ATA_REG_STATUS << 1); | |
258 | ap->ioaddr.command_addr = info->ide_addr + (ATA_REG_CMD << 1); | |
259 | ||
260 | /* Set info as private data of ATA host */ | |
261 | host->private_data = info; | |
262 | ||
263 | /* Register ATA device and return */ | |
264 | return ata_host_activate(host, info->irq, ata_interrupt, | |
265 | IRQF_SHARED | IRQF_TRIGGER_RISING, | |
266 | &at32_sht); | |
267 | } | |
268 | ||
269 | /* | |
270 | * This function may come in handy for people analyzing their own | |
271 | * EBI -> PATA adaptors. | |
272 | */ | |
273 | #ifdef DEBUG_BUS | |
274 | ||
275 | static void __init pata_at32_debug_bus(struct device *dev, | |
276 | struct at32_ide_info *info) | |
277 | { | |
278 | const int d1 = 0xff; | |
279 | const int d2 = 0x00; | |
280 | ||
281 | int i; | |
282 | ||
283 | /* Write 8-bit values (registers) */ | |
284 | iowrite8(d1, info->alt_addr + (0x06 << 1)); | |
285 | iowrite8(d2, info->alt_addr + (0x06 << 1)); | |
286 | ||
287 | for (i = 0; i < 8; i++) { | |
288 | iowrite8(d1, info->ide_addr + (i << 1)); | |
289 | iowrite8(d2, info->ide_addr + (i << 1)); | |
290 | } | |
291 | ||
292 | /* Write 16 bit values (data) */ | |
293 | iowrite16(d1, info->ide_addr); | |
294 | iowrite16(d1 << 8, info->ide_addr); | |
295 | ||
296 | iowrite16(d1, info->ide_addr); | |
297 | iowrite16(d1 << 8, info->ide_addr); | |
298 | } | |
299 | ||
300 | #endif | |
301 | ||
302 | static int __init pata_at32_probe(struct platform_device *pdev) | |
303 | { | |
304 | const struct ata_timing initial_timing = | |
305 | {XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0}; | |
306 | ||
307 | struct device *dev = &pdev->dev; | |
308 | struct at32_ide_info *info; | |
309 | struct ide_platform_data *board = pdev->dev.platform_data; | |
310 | struct resource *res; | |
311 | ||
312 | int irq; | |
313 | int ret; | |
314 | ||
315 | if (!board) | |
316 | return -ENXIO; | |
317 | ||
318 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
319 | if (!res) | |
320 | return -ENXIO; | |
321 | ||
322 | /* Retrive IRQ */ | |
323 | irq = platform_get_irq(pdev, 0); | |
324 | if (irq < 0) | |
325 | return irq; | |
326 | ||
327 | /* Setup struct containing private infomation */ | |
328 | info = kzalloc(sizeof(struct at32_ide_info), GFP_KERNEL); | |
329 | if (!info) | |
330 | return -ENOMEM; | |
331 | ||
332 | memset(info, 0, sizeof(struct at32_ide_info)); | |
333 | ||
334 | info->irq = irq; | |
335 | info->cs = board->cs; | |
336 | ||
337 | /* Request memory resources */ | |
338 | info->res_ide.start = res->start + CF_IDE_OFFSET; | |
339 | info->res_ide.end = info->res_ide.start + CF_RES_SIZE - 1; | |
340 | info->res_ide.name = "ide"; | |
341 | info->res_ide.flags = IORESOURCE_MEM; | |
342 | ||
343 | ret = request_resource(res, &info->res_ide); | |
344 | if (ret) | |
345 | goto err_req_res_ide; | |
346 | ||
347 | info->res_alt.start = res->start + CF_ALT_IDE_OFFSET; | |
348 | info->res_alt.end = info->res_alt.start + CF_RES_SIZE - 1; | |
349 | info->res_alt.name = "alt"; | |
350 | info->res_alt.flags = IORESOURCE_MEM; | |
351 | ||
352 | ret = request_resource(res, &info->res_alt); | |
353 | if (ret) | |
354 | goto err_req_res_alt; | |
355 | ||
356 | /* Setup non-timing elements of SMC */ | |
357 | info->smc.bus_width = 2; /* 16 bit data bus */ | |
358 | info->smc.nrd_controlled = 1; /* Sample data on rising edge of NRD */ | |
359 | info->smc.nwe_controlled = 0; /* Drive data on falling edge of NCS */ | |
360 | info->smc.nwait_mode = 3; /* NWAIT is in READY mode */ | |
361 | info->smc.byte_write = 0; /* Byte select access type */ | |
362 | info->smc.tdf_mode = 0; /* TDF optimization disabled */ | |
363 | info->smc.tdf_cycles = 0; /* No TDF wait cycles */ | |
364 | ||
1c20a493 | 365 | /* Setup SMC to ATA timing */ |
7c9ef8e4 KNG |
366 | ret = pata_at32_setup_timing(dev, info, &initial_timing); |
367 | if (ret) | |
368 | goto err_setup_timing; | |
369 | ||
1c20a493 | 370 | /* Map ATA address space */ |
7c9ef8e4 KNG |
371 | ret = -ENOMEM; |
372 | info->ide_addr = devm_ioremap(dev, info->res_ide.start, 16); | |
373 | info->alt_addr = devm_ioremap(dev, info->res_alt.start, 16); | |
374 | if (!info->ide_addr || !info->alt_addr) | |
375 | goto err_ioremap; | |
376 | ||
377 | #ifdef DEBUG_BUS | |
378 | pata_at32_debug_bus(dev, info); | |
379 | #endif | |
380 | ||
1c20a493 | 381 | /* Setup and register ATA device */ |
7c9ef8e4 KNG |
382 | ret = pata_at32_init_one(dev, info); |
383 | if (ret) | |
384 | goto err_ata_device; | |
385 | ||
386 | return 0; | |
387 | ||
388 | err_ata_device: | |
389 | err_ioremap: | |
390 | err_setup_timing: | |
391 | release_resource(&info->res_alt); | |
392 | err_req_res_alt: | |
393 | release_resource(&info->res_ide); | |
394 | err_req_res_ide: | |
395 | kfree(info); | |
396 | ||
397 | return ret; | |
398 | } | |
399 | ||
400 | static int __exit pata_at32_remove(struct platform_device *pdev) | |
401 | { | |
402 | struct ata_host *host = platform_get_drvdata(pdev); | |
403 | struct at32_ide_info *info; | |
404 | ||
405 | if (!host) | |
406 | return 0; | |
407 | ||
408 | info = host->private_data; | |
409 | ata_host_detach(host); | |
410 | ||
411 | if (!info) | |
412 | return 0; | |
413 | ||
414 | release_resource(&info->res_ide); | |
415 | release_resource(&info->res_alt); | |
416 | ||
417 | kfree(info); | |
418 | ||
419 | return 0; | |
420 | } | |
421 | ||
422 | static struct platform_driver pata_at32_driver = { | |
423 | .remove = __exit_p(pata_at32_remove), | |
424 | .driver = { | |
425 | .name = "at32_ide", | |
426 | .owner = THIS_MODULE, | |
427 | }, | |
428 | }; | |
429 | ||
430 | static int __init pata_at32_init(void) | |
431 | { | |
432 | return platform_driver_probe(&pata_at32_driver, pata_at32_probe); | |
433 | } | |
434 | ||
435 | static void __exit pata_at32_exit(void) | |
436 | { | |
437 | platform_driver_unregister(&pata_at32_driver); | |
438 | } | |
439 | ||
440 | module_init(pata_at32_init); | |
441 | module_exit(pata_at32_exit); | |
442 | ||
443 | MODULE_LICENSE("GPL"); | |
444 | MODULE_DESCRIPTION("AVR32 SMC/CFC PATA Driver"); | |
445 | MODULE_AUTHOR("Kristoffer Nyborg Gregertsen <kngregertsen@norway.atmel.com>"); | |
446 | MODULE_VERSION(DRV_VERSION); |