[linux-2.6-block.git] / drivers / ata / pata_artop.c

/*
 *    pata_artop.c - ARTOP ATA controller driver
 *
 *	(C) 2006 Red Hat
 *	(C) 2007,2011 Bartlomiej Zolnierkiewicz
 *
 *    Based in part on drivers/ide/pci/aec62xx.c
 *	Copyright (C) 1999-2002	Andre Hedrick <andre@linux-ide.org>
 *	865/865R fixes for Macintosh card version from a patch to the old
 *		driver by Thibaut VARENE <varenet@parisc-linux.org>
 *	When setting the PCI latency we must set 0x80 or higher for burst
 *		performance Alessandro Zummo <alessandro.zummo@towertech.it>
 *
 *	TODO
 *	Investigate no_dsc on 850R
 *	Clock detect
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include <linux/ata.h>

#define DRV_NAME	"pata_artop"
#define DRV_VERSION	"0.4.6"

/*
 *	The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
 *	get PCI bus speed functionality we leave this as 0. Its a variable
 *	for when we get the functionality and also for folks wanting to
 *	test stuff.
 */

static int clock = 0;

/**
 *	artop62x0_pre_reset	-	probe begin
 *	@link: link
 *	@deadline: deadline jiffies for the operation
 *
 *	Nothing complicated needed here.
 */

static int artop62x0_pre_reset(struct ata_link *link, unsigned long deadline)
{
	static const struct pci_bits artop_enable_bits[] = {
		{ 0x4AU, 1U, 0x02UL, 0x02UL },	/* port 0 */
		{ 0x4AU, 1U, 0x04UL, 0x04UL },	/* port 1 */
	};

	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	/* Odd numbered device ids are the units with enable bits. */
	if ((pdev->device & 1) &&
	    !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
		return -ENOENT;

	return ata_sff_prereset(link, deadline);
}

/**
 *	artop6260_cable_detect	-	identify cable type
 *	@ap: Port
 *
 *	Identify the cable type for the ARTOP interface in question
 */

static int artop6260_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 tmp;
	pci_read_config_byte(pdev, 0x49, &tmp);
	if (tmp & (1 << ap->port_no))
		return ATA_CBL_PATA40;
	return ATA_CBL_PATA80;
}

/**
 *	artop6210_load_piomode - Load a set of PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device
 *	@pio: PIO mode
 *
 *	Set PIO mode for device, in host controller PCI config space. This
 *	is used both to set PIO timings in PIO mode and also to set the
 *	matching PIO clocking for UDMA, as well as the MWDMA timings.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6210_load_piomode(struct ata_port *ap, struct ata_device *adev, unsigned int pio)
{
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	int dn = adev->devno + 2 * ap->port_no;
	const u16 timing[2][5] = {
		{ 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 },
		{ 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 }

	};
	/* Load the PIO timing active/recovery bits */
	pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]);
}

/**
 *	artop6210_set_piomode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device we are configuring
 *
 *	Set PIO mode for device, in host controller PCI config space. For
 *	ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
 *	the event UDMA is used the later call to set_dmamode will set the
 *	bits as required.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6210_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	int dn = adev->devno + 2 * ap->port_no;
	u8 ultra;

	artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);

	/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
	pci_read_config_byte(pdev, 0x54, &ultra);
	ultra &= ~(3 << (2 * dn));
	pci_write_config_byte(pdev, 0x54, ultra);
}

/**
 *	artop6260_load_piomode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device we are configuring
 *	@pio: PIO mode
 *
 *	Set PIO mode for device, in host controller PCI config space. The
 *	ARTOP6260 and relatives store the timing data differently.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6260_load_piomode (struct ata_port *ap, struct ata_device *adev, unsigned int pio)
{
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	int dn = adev->devno + 2 * ap->port_no;
	const u8 timing[2][5] = {
		{ 0x00, 0x0A, 0x08, 0x33, 0x31 },
		{ 0x70, 0x7A, 0x78, 0x43, 0x41 }

	};
	/* Load the PIO timing active/recovery bits */
	pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]);
}

/**
 *	artop6260_set_piomode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device we are configuring
 *
 *	Set PIO mode for device, in host controller PCI config space. For
 *	ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
 *	the event UDMA is used the later call to set_dmamode will set the
 *	bits as required.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6260_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	u8 ultra;

	artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);

	/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
	pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
	ultra &= ~(7 << (4  * adev->devno));	/* One nibble per drive */
	pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
}

/**
 *	artop6210_set_dmamode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device whose timings we are configuring
 *
 *	Set DMA mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6210_set_dmamode (struct ata_port *ap, struct ata_device *adev)
{
	unsigned int pio;
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	int dn = adev->devno + 2 * ap->port_no;
	u8 ultra;

	if (adev->dma_mode == XFER_MW_DMA_0)
		pio = 1;
	else
		pio = 4;

	/* Load the PIO timing active/recovery bits */
	artop6210_load_piomode(ap, adev, pio);

	pci_read_config_byte(pdev, 0x54, &ultra);
	ultra &= ~(3 << (2 * dn));

	/* Add ultra DMA bits if in UDMA mode */
	if (adev->dma_mode >= XFER_UDMA_0) {
		u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock;
		if (mode == 0)
			mode = 1;
		ultra |= (mode << (2 * dn));
	}
	pci_write_config_byte(pdev, 0x54, ultra);
}

/**
 *	artop6260_set_dmamode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device we are configuring
 *
 *	Set DMA mode for device, in host controller PCI config space. The
 *	ARTOP6260 and relatives store the timing data differently.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6260_set_dmamode (struct ata_port *ap, struct ata_device *adev)
{
	unsigned int pio	= adev->pio_mode - XFER_PIO_0;
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	u8 ultra;

	if (adev->dma_mode == XFER_MW_DMA_0)
		pio = 1;
	else
		pio = 4;

	/* Load the PIO timing active/recovery bits */
	artop6260_load_piomode(ap, adev, pio);

	/* Add ultra DMA bits if in UDMA mode */
	pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
	ultra &= ~(7 << (4  * adev->devno));	/* One nibble per drive */
	if (adev->dma_mode >= XFER_UDMA_0) {
		u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock;
		if (mode == 0)
			mode = 1;
		ultra |= (mode << (4 * adev->devno));
	}
	pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
}

/**
 *	artop_6210_qc_defer	-	implement serialization
 *	@qc: command
 *
 *	Issue commands per host on this chip.
 */

static int artop6210_qc_defer(struct ata_queued_cmd *qc)
{
	struct ata_host *host = qc->ap->host;
	struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
	int rc;

	/* First apply the usual rules */
	rc = ata_std_qc_defer(qc);
	if (rc != 0)
		return rc;

	/* Now apply serialization rules. Only allow a command if the
	   other channel state machine is idle */
	if (alt && alt->qc_active)
		return	ATA_DEFER_PORT;
	return 0;
}

static struct scsi_host_template artop_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations artop6210_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.cable_detect		= ata_cable_40wire,
	.set_piomode		= artop6210_set_piomode,
	.set_dmamode		= artop6210_set_dmamode,
	.prereset		= artop62x0_pre_reset,
	.qc_defer		= artop6210_qc_defer,
};

static struct ata_port_operations artop6260_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.cable_detect		= artop6260_cable_detect,
	.set_piomode		= artop6260_set_piomode,
	.set_dmamode		= artop6260_set_dmamode,
	.prereset		= artop62x0_pre_reset,
};

static void atp8xx_fixup(struct pci_dev *pdev)
{
	if (pdev->device == 0x0005)
		/* BIOS may have left us in UDMA, clear it before libata probe */
		pci_write_config_byte(pdev, 0x54, 0);
	else if (pdev->device == 0x0008 || pdev->device == 0x0009) {
		u8 reg;

		/* Mac systems come up with some registers not set as we
		   will need them */

		/* Clear reset & test bits */
		pci_read_config_byte(pdev, 0x49, &reg);
		pci_write_config_byte(pdev, 0x49, reg & ~0x30);

		/* PCI latency must be > 0x80 for burst mode, tweak it
		 * if required.
		 */
		pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &reg);
		if (reg <= 0x80)
			pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90);

		/* Enable IRQ output and burst mode */
		pci_read_config_byte(pdev, 0x4a, &reg);
		pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80);
	}
}

/**
 *	artop_init_one - Register ARTOP ATA PCI device with kernel services
 *	@pdev: PCI device to register
 *	@ent: Entry in artop_pci_tbl matching with @pdev
 *
 *	Called from kernel PCI layer.
 *
 *	LOCKING:
 *	Inherited from PCI layer (may sleep).
 *
 *	RETURNS:
 *	Zero on success, or -ERRNO value.
 */

static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const struct ata_port_info info_6210 = {
		.flags		= ATA_FLAG_SLAVE_POSS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask 	= ATA_UDMA2,
		.port_ops	= &artop6210_ops,
	};
	static const struct ata_port_info info_626x = {
		.flags		= ATA_FLAG_SLAVE_POSS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask 	= ATA_UDMA4,
		.port_ops	= &artop6260_ops,
	};
	static const struct ata_port_info info_628x = {
		.flags		= ATA_FLAG_SLAVE_POSS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask 	= ATA_UDMA5,
		.port_ops	= &artop6260_ops,
	};
	static const struct ata_port_info info_628x_fast = {
		.flags		= ATA_FLAG_SLAVE_POSS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask 	= ATA_UDMA6,
		.port_ops	= &artop6260_ops,
	};
	const struct ata_port_info *ppi[] = { NULL, NULL };
	int rc;

	ata_print_version_once(&pdev->dev, DRV_VERSION);

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	if (id->driver_data == 0)	/* 6210 variant */
		ppi[0] = &info_6210;
	else if (id->driver_data == 1)	/* 6260 */
		ppi[0] = &info_626x;
	else if (id->driver_data == 2)	{ /* 6280 or 6280 + fast */
		unsigned long io = pci_resource_start(pdev, 4);

		ppi[0] = &info_628x;
		if (inb(io) & 0x10)
			ppi[0] = &info_628x_fast;
	}

	BUG_ON(ppi[0] == NULL);

	atp8xx_fixup(pdev);

	return ata_pci_bmdma_init_one(pdev, ppi, &artop_sht, NULL, 0);
}

static const struct pci_device_id artop_pci_tbl[] = {
	{ PCI_VDEVICE(ARTOP, 0x0005), 0 },
	{ PCI_VDEVICE(ARTOP, 0x0006), 1 },
	{ PCI_VDEVICE(ARTOP, 0x0007), 1 },
	{ PCI_VDEVICE(ARTOP, 0x0008), 2 },
	{ PCI_VDEVICE(ARTOP, 0x0009), 2 },

	{ }	/* terminate list */
};

#ifdef CONFIG_PM
static int atp8xx_reinit_one(struct pci_dev *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	int rc;

	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;

	atp8xx_fixup(pdev);

	ata_host_resume(host);
	return 0;
}
#endif

static struct pci_driver artop_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= artop_pci_tbl,
	.probe			= artop_init_one,
	.remove			= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend		= ata_pci_device_suspend,
	.resume			= atp8xx_reinit_one,
#endif
};

module_pci_driver(artop_pci_driver);

MODULE_AUTHOR("Alan Cox, Bartlomiej Zolnierkiewicz");
MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, artop_pci_tbl);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_artop.c - ARTOP ATA controller driver
	3	*
ab771630	4	* (C) 2006 Red Hat
067f8c7b	5	* (C) 2007,2011 Bartlomiej Zolnierkiewicz
669a5db4 JG	6	*
	7	* Based in part on drivers/ide/pci/aec62xx.c
	8	* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
	9	* 865/865R fixes for Macintosh card version from a patch to the old
	10	* driver by Thibaut VARENE <varenet@parisc-linux.org>
	11	* When setting the PCI latency we must set 0x80 or higher for burst
	12	* performance Alessandro Zummo <alessandro.zummo@towertech.it>
	13	*
	14	* TODO
669a5db4 JG	15	* Investigate no_dsc on 850R
	16	* Clock detect
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/pci.h>
	22	#include <linux/init.h>
	23	#include <linux/blkdev.h>
	24	#include <linux/delay.h>
	25	#include <linux/device.h>
	26	#include <scsi/scsi_host.h>
	27	#include <linux/libata.h>
	28	#include <linux/ata.h>
	29
	30	#define DRV_NAME "pata_artop"
067f8c7b	31	#define DRV_VERSION "0.4.6"
669a5db4 JG	32
	33	/*
	34	* The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
	35	* get PCI bus speed functionality we leave this as 0. Its a variable
	36	* for when we get the functionality and also for folks wanting to
	37	* test stuff.
	38	*/
	39
	40	static int clock = 0;
	41
669a5db4	42	/**
f6b56696	43	* artop62x0_pre_reset - probe begin
cc0680a5	44	* @link: link
d4b2bab4	45	* @deadline: deadline jiffies for the operation
669a5db4	46	*
669a5db4 JG	47	* Nothing complicated needed here.
	48	*/
	49
f6b56696	50	static int artop62x0_pre_reset(struct ata_link *link, unsigned long deadline)
669a5db4 JG	51	{
	52	static const struct pci_bits artop_enable_bits[] = {
	53	{ 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */
	54	{ 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */
	55	};
	56
cc0680a5	57	struct ata_port *ap = link->ap;
669a5db4	58	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
669a5db4	59
f6b56696	60	/* Odd numbered device ids are the units with enable bits. */
673424c0 JD	61	if ((pdev->device & 1) &&
673424c0 JD	62	!pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
c961922b	63	return -ENOENT;
27c78b37	64
9363c382	65	return ata_sff_prereset(link, deadline);
a73984a0	66	}
c961922b	67
a73984a0 JG	68	/**
	69	* artop6260_cable_detect - identify cable type
	70	* @ap: Port
	71	*
c343a839	72	* Identify the cable type for the ARTOP interface in question
a73984a0	73	*/
a617c09f	74
a73984a0 JG	75	static int artop6260_cable_detect(struct ata_port *ap)
	76	{
	77	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	78	u8 tmp;
669a5db4	79	pci_read_config_byte(pdev, 0x49, &tmp);
3f9dd27a	80	if (tmp & (1 << ap->port_no))
a73984a0 JG	81	return ATA_CBL_PATA40;
a73984a0 JG	82	return ATA_CBL_PATA80;
669a5db4 JG	83	}
669a5db4 JG	84
669a5db4 JG	85	/**
	86	* artop6210_load_piomode - Load a set of PATA PIO timings
	87	* @ap: Port whose timings we are configuring
	88	* @adev: Device
	89	* @pio: PIO mode
	90	*
	91	* Set PIO mode for device, in host controller PCI config space. This
	92	* is used both to set PIO timings in PIO mode and also to set the
	93	* matching PIO clocking for UDMA, as well as the MWDMA timings.
	94	*
	95	* LOCKING:
	96	* None (inherited from caller).
	97	*/
	98
	99	static void artop6210_load_piomode(struct ata_port ap, struct ata_device adev, unsigned int pio)
	100	{
	101	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	102	int dn = adev->devno + 2 * ap->port_no;
	103	const u16 timing[2][5] = {
	104	{ 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 },
	105	{ 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 }
	106
	107	};
	108	/* Load the PIO timing active/recovery bits */
	109	pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]);
	110	}
	111
	112	/**
	113	* artop6210_set_piomode - Initialize host controller PATA PIO timings
	114	* @ap: Port whose timings we are configuring
	115	* @adev: Device we are configuring
	116	*
	117	* Set PIO mode for device, in host controller PCI config space. For
	118	* ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
	119	* the event UDMA is used the later call to set_dmamode will set the
	120	* bits as required.
	121	*
	122	* LOCKING:
	123	* None (inherited from caller).
	124	*/
	125
	126	static void artop6210_set_piomode(struct ata_port ap, struct ata_device adev)
	127	{
	128	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	129	int dn = adev->devno + 2 * ap->port_no;
	130	u8 ultra;
	131
	132	artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
	133
	134	/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
	135	pci_read_config_byte(pdev, 0x54, &ultra);
	136	ultra &= ~(3 << (2 * dn));
	137	pci_write_config_byte(pdev, 0x54, ultra);
	138	}
	139
	140	/**
	141	* artop6260_load_piomode - Initialize host controller PATA PIO timings
	142	* @ap: Port whose timings we are configuring
	143	* @adev: Device we are configuring
	144	* @pio: PIO mode
	145	*
	146	* Set PIO mode for device, in host controller PCI config space. The
	147	* ARTOP6260 and relatives store the timing data differently.
	148	*
149	* LOCKING:
150	* None (inherited from caller).
151	*/
152
153	static void artop6260_load_piomode (struct ata_port ap, struct ata_device adev, unsigned int pio)
154	{
155	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
156	int dn = adev->devno + 2 * ap->port_no;
157	const u8 timing[2][5] = {
158	{ 0x00, 0x0A, 0x08, 0x33, 0x31 },
159	{ 0x70, 0x7A, 0x78, 0x43, 0x41 }
160
161	};
162	/* Load the PIO timing active/recovery bits */
163	pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]);
164	}
165
166	/**
167	* artop6260_set_piomode - Initialize host controller PATA PIO timings
168	* @ap: Port whose timings we are configuring
169	* @adev: Device we are configuring
170	*
171	* Set PIO mode for device, in host controller PCI config space. For
172	* ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
173	* the event UDMA is used the later call to set_dmamode will set the
174	* bits as required.
175	*
176	* LOCKING:
177	* None (inherited from caller).
178	*/
179
180	static void artop6260_set_piomode(struct ata_port ap, struct ata_device adev)
181	{
182	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
183	u8 ultra;
184
185	artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
186
187	/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
188	pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
189	ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
190	pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
191	}
192
193	/**
194	* artop6210_set_dmamode - Initialize host controller PATA PIO timings
195	* @ap: Port whose timings we are configuring
a73984a0	196	* @adev: Device whose timings we are configuring
669a5db4 JG	197	*
	198	* Set DMA mode for device, in host controller PCI config space.
	199	*
	200	* LOCKING:
	201	* None (inherited from caller).
	202	*/
	203
	204	static void artop6210_set_dmamode (struct ata_port ap, struct ata_device adev)
	205	{
	206	unsigned int pio;
	207	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	208	int dn = adev->devno + 2 * ap->port_no;
	209	u8 ultra;
	210
	211	if (adev->dma_mode == XFER_MW_DMA_0)
	212	pio = 1;
	213	else
	214	pio = 4;
	215
	216	/* Load the PIO timing active/recovery bits */
	217	artop6210_load_piomode(ap, adev, pio);
	218
	219	pci_read_config_byte(pdev, 0x54, &ultra);
	220	ultra &= ~(3 << (2 * dn));
	221
	222	/* Add ultra DMA bits if in UDMA mode */
	223	if (adev->dma_mode >= XFER_UDMA_0) {
	224	u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock;
	225	if (mode == 0)
	226	mode = 1;
	227	ultra \|= (mode << (2 * dn));
	228	}
	229	pci_write_config_byte(pdev, 0x54, ultra);
	230	}
	231
	232	/**
	233	* artop6260_set_dmamode - Initialize host controller PATA PIO timings
	234	* @ap: Port whose timings we are configuring
	235	* @adev: Device we are configuring
	236	*
	237	* Set DMA mode for device, in host controller PCI config space. The
	238	* ARTOP6260 and relatives store the timing data differently.
	239	*
	240	* LOCKING:
	241	* None (inherited from caller).
	242	*/
	243
	244	static void artop6260_set_dmamode (struct ata_port ap, struct ata_device adev)
	245	{
	246	unsigned int pio = adev->pio_mode - XFER_PIO_0;
	247	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	248	u8 ultra;
	249
	250	if (adev->dma_mode == XFER_MW_DMA_0)
	251	pio = 1;
	252	else
	253	pio = 4;
	254
	255	/* Load the PIO timing active/recovery bits */
	256	artop6260_load_piomode(ap, adev, pio);
	257
	258	/* Add ultra DMA bits if in UDMA mode */
	259	pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
	260	ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
261	if (adev->dma_mode >= XFER_UDMA_0) {
262	u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock;
263	if (mode == 0)
264	mode = 1;
265	ultra \|= (mode << (4 * adev->devno));
266	}
267	pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
268	}
269
140d6fed AC	270	/**
	271	* artop_6210_qc_defer - implement serialization
	272	* @qc: command
	273	*
	274	* Issue commands per host on this chip.
	275	*/
	276
	277	static int artop6210_qc_defer(struct ata_queued_cmd *qc)
	278	{
	279	struct ata_host *host = qc->ap->host;
	280	struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
	281	int rc;
	282
	283	/* First apply the usual rules */
	284	rc = ata_std_qc_defer(qc);
	285	if (rc != 0)
	286	return rc;
	287
	288	/* Now apply serialization rules. Only allow a command if the
	289	other channel state machine is idle */
	290	if (alt && alt->qc_active)
	291	return ATA_DEFER_PORT;
	292	return 0;
	293	}
	294
669a5db4	295	static struct scsi_host_template artop_sht = {
68d1d07b	296	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	297	};
669a5db4 JG	298
029cfd6b TH	299	static struct ata_port_operations artop6210_ops = {
	300	.inherits = &ata_bmdma_port_ops,
	301	.cable_detect = ata_cable_40wire,
669a5db4 JG	302	.set_piomode = artop6210_set_piomode,
669a5db4 JG	303	.set_dmamode = artop6210_set_dmamode,
f6b56696	304	.prereset = artop62x0_pre_reset,
140d6fed	305	.qc_defer = artop6210_qc_defer,
669a5db4 JG	306	};
669a5db4 JG	307
029cfd6b TH	308	static struct ata_port_operations artop6260_ops = {
	309	.inherits = &ata_bmdma_port_ops,
	310	.cable_detect = artop6260_cable_detect,
669a5db4 JG	311	.set_piomode = artop6260_set_piomode,
669a5db4 JG	312	.set_dmamode = artop6260_set_dmamode,
f6b56696	313	.prereset = artop62x0_pre_reset,
669a5db4 JG	314	};
669a5db4 JG	315
067f8c7b BZ	316	static void atp8xx_fixup(struct pci_dev *pdev)
	317	{
	318	if (pdev->device == 0x0005)
	319	/* BIOS may have left us in UDMA, clear it before libata probe */
	320	pci_write_config_byte(pdev, 0x54, 0);
	321	else if (pdev->device == 0x0008 \|\| pdev->device == 0x0009) {
	322	u8 reg;
	323
	324	/* Mac systems come up with some registers not set as we
	325	will need them */
	326
	327	/* Clear reset & test bits */
	328	pci_read_config_byte(pdev, 0x49, &reg);
	329	pci_write_config_byte(pdev, 0x49, reg & ~0x30);
	330
	331	/* PCI latency must be > 0x80 for burst mode, tweak it
	332	* if required.
	333	*/
	334	pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &reg);
	335	if (reg <= 0x80)
	336	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90);
	337
	338	/* Enable IRQ output and burst mode */
	339	pci_read_config_byte(pdev, 0x4a, &reg);
	340	pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) \| 0x80);
	341	}
	342	}
669a5db4 JG	343
	344	/**
	345	* artop_init_one - Register ARTOP ATA PCI device with kernel services
	346	* @pdev: PCI device to register
	347	* @ent: Entry in artop_pci_tbl matching with @pdev
	348	*
	349	* Called from kernel PCI layer.
	350	*
	351	* LOCKING:
	352	* Inherited from PCI layer (may sleep).
	353	*
	354	* RETURNS:
	355	* Zero on success, or -ERRNO value.
	356	*/
	357
	358	static int artop_init_one (struct pci_dev pdev, const struct pci_device_id id)
	359	{
1626aeb8	360	static const struct ata_port_info info_6210 = {
1d2808fd	361	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	362	.pio_mask = ATA_PIO4,
14bdef98 EIB	363	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	364	.udma_mask = ATA_UDMA2,
	365	.port_ops = &artop6210_ops,
	366	};
1626aeb8	367	static const struct ata_port_info info_626x = {
1d2808fd	368	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	369	.pio_mask = ATA_PIO4,
14bdef98 EIB	370	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	371	.udma_mask = ATA_UDMA4,
	372	.port_ops = &artop6260_ops,
	373	};
be456b77	374	static const struct ata_port_info info_628x = {
1d2808fd	375	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	376	.pio_mask = ATA_PIO4,
14bdef98 EIB	377	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	378	.udma_mask = ATA_UDMA5,
	379	.port_ops = &artop6260_ops,
	380	};
be456b77	381	static const struct ata_port_info info_628x_fast = {
be456b77	382	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	383	.pio_mask = ATA_PIO4,
14bdef98 EIB	384	.mwdma_mask = ATA_MWDMA2,
be456b77 BZ	385	.udma_mask = ATA_UDMA6,
	386	.port_ops = &artop6260_ops,
	387	};
1626aeb8	388	const struct ata_port_info *ppi[] = { NULL, NULL };
f08048e9	389	int rc;
669a5db4	390
06296a1e	391	ata_print_version_once(&pdev->dev, DRV_VERSION);
669a5db4	392
f08048e9 TH	393	rc = pcim_enable_device(pdev);
	394	if (rc)
	395	return rc;
	396
067f8c7b	397	if (id->driver_data == 0) /* 6210 variant */
1626aeb8	398	ppi[0] = &info_6210;
669a5db4	399	else if (id->driver_data == 1) /* 6260 */
1626aeb8	400	ppi[0] = &info_626x;
be456b77	401	else if (id->driver_data == 2) { /* 6280 or 6280 + fast */
669a5db4	402	unsigned long io = pci_resource_start(pdev, 4);
669a5db4	403
be456b77	404	ppi[0] = &info_628x;
669a5db4	405	if (inb(io) & 0x10)
be456b77	406	ppi[0] = &info_628x_fast;
669a5db4	407	}
15a7c3bb	408
1626aeb8	409	BUG_ON(ppi[0] == NULL);
15a7c3bb	410
067f8c7b BZ	411	atp8xx_fixup(pdev);
067f8c7b BZ	412
1c5afdf7	413	return ata_pci_bmdma_init_one(pdev, ppi, &artop_sht, NULL, 0);
669a5db4 JG	414	}
	415
	416	static const struct pci_device_id artop_pci_tbl[] = {
2d2744fc JG	417	{ PCI_VDEVICE(ARTOP, 0x0005), 0 },
	418	{ PCI_VDEVICE(ARTOP, 0x0006), 1 },
	419	{ PCI_VDEVICE(ARTOP, 0x0007), 1 },
	420	{ PCI_VDEVICE(ARTOP, 0x0008), 2 },
	421	{ PCI_VDEVICE(ARTOP, 0x0009), 2 },
	422
669a5db4 JG	423	{ } /* terminate list */
	424	};
	425
067f8c7b BZ	426	#ifdef CONFIG_PM
	427	static int atp8xx_reinit_one(struct pci_dev *pdev)
	428	{
	429	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	430	int rc;
	431
	432	rc = ata_pci_device_do_resume(pdev);
	433	if (rc)
	434	return rc;
	435
	436	atp8xx_fixup(pdev);
	437
	438	ata_host_resume(host);
	439	return 0;
	440	}
	441	#endif
	442
669a5db4 JG	443	static struct pci_driver artop_pci_driver = {
	444	.name = DRV_NAME,
	445	.id_table = artop_pci_tbl,
	446	.probe = artop_init_one,
	447	.remove = ata_pci_remove_one,
067f8c7b BZ	448	#ifdef CONFIG_PM
	449	.suspend = ata_pci_device_suspend,
	450	.resume = atp8xx_reinit_one,
	451	#endif
669a5db4 JG	452	};
669a5db4 JG	453
2fc75da0	454	module_pci_driver(artop_pci_driver);
669a5db4	455
067f8c7b	456	MODULE_AUTHOR("Alan Cox, Bartlomiej Zolnierkiewicz");
669a5db4 JG	457	MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA");
	458	MODULE_LICENSE("GPL");
	459	MODULE_DEVICE_TABLE(pci, artop_pci_tbl);
	460	MODULE_VERSION(DRV_VERSION);