Commit | Line | Data |
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09c434b8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
669a5db4 JG |
2 | /* |
3 | * pata_artop.c - ARTOP ATA controller driver | |
4 | * | |
ab771630 | 5 | * (C) 2006 Red Hat |
067f8c7b | 6 | * (C) 2007,2011 Bartlomiej Zolnierkiewicz |
669a5db4 JG |
7 | * |
8 | * Based in part on drivers/ide/pci/aec62xx.c | |
9 | * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> | |
10 | * 865/865R fixes for Macintosh card version from a patch to the old | |
11 | * driver by Thibaut VARENE <varenet@parisc-linux.org> | |
12 | * When setting the PCI latency we must set 0x80 or higher for burst | |
13 | * performance Alessandro Zummo <alessandro.zummo@towertech.it> | |
14 | * | |
15 | * TODO | |
669a5db4 JG |
16 | * Investigate no_dsc on 850R |
17 | * Clock detect | |
18 | */ | |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/pci.h> | |
669a5db4 JG |
23 | #include <linux/blkdev.h> |
24 | #include <linux/delay.h> | |
25 | #include <linux/device.h> | |
26 | #include <scsi/scsi_host.h> | |
27 | #include <linux/libata.h> | |
28 | #include <linux/ata.h> | |
29 | ||
30 | #define DRV_NAME "pata_artop" | |
7ad3128e | 31 | #define DRV_VERSION "0.4.8" |
669a5db4 JG |
32 | |
33 | /* | |
34 | * The ARTOP has 33 Mhz and "over clocked" timing tables. Until we | |
35 | * get PCI bus speed functionality we leave this as 0. Its a variable | |
36 | * for when we get the functionality and also for folks wanting to | |
37 | * test stuff. | |
38 | */ | |
39 | ||
40 | static int clock = 0; | |
41 | ||
669a5db4 | 42 | /** |
f6b56696 | 43 | * artop62x0_pre_reset - probe begin |
cc0680a5 | 44 | * @link: link |
d4b2bab4 | 45 | * @deadline: deadline jiffies for the operation |
669a5db4 | 46 | * |
669a5db4 JG |
47 | * Nothing complicated needed here. |
48 | */ | |
49 | ||
f6b56696 | 50 | static int artop62x0_pre_reset(struct ata_link *link, unsigned long deadline) |
669a5db4 JG |
51 | { |
52 | static const struct pci_bits artop_enable_bits[] = { | |
53 | { 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */ | |
54 | { 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */ | |
55 | }; | |
56 | ||
cc0680a5 | 57 | struct ata_port *ap = link->ap; |
669a5db4 | 58 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
669a5db4 | 59 | |
f6b56696 | 60 | /* Odd numbered device ids are the units with enable bits. */ |
673424c0 JD |
61 | if ((pdev->device & 1) && |
62 | !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no])) | |
c961922b | 63 | return -ENOENT; |
27c78b37 | 64 | |
9363c382 | 65 | return ata_sff_prereset(link, deadline); |
a73984a0 | 66 | } |
c961922b | 67 | |
a73984a0 JG |
68 | /** |
69 | * artop6260_cable_detect - identify cable type | |
70 | * @ap: Port | |
71 | * | |
c343a839 | 72 | * Identify the cable type for the ARTOP interface in question |
a73984a0 | 73 | */ |
a617c09f | 74 | |
a73984a0 JG |
75 | static int artop6260_cable_detect(struct ata_port *ap) |
76 | { | |
77 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
78 | u8 tmp; | |
669a5db4 | 79 | pci_read_config_byte(pdev, 0x49, &tmp); |
3f9dd27a | 80 | if (tmp & (1 << ap->port_no)) |
a73984a0 JG |
81 | return ATA_CBL_PATA40; |
82 | return ATA_CBL_PATA80; | |
669a5db4 JG |
83 | } |
84 | ||
669a5db4 JG |
85 | /** |
86 | * artop6210_load_piomode - Load a set of PATA PIO timings | |
87 | * @ap: Port whose timings we are configuring | |
88 | * @adev: Device | |
89 | * @pio: PIO mode | |
90 | * | |
91 | * Set PIO mode for device, in host controller PCI config space. This | |
92 | * is used both to set PIO timings in PIO mode and also to set the | |
93 | * matching PIO clocking for UDMA, as well as the MWDMA timings. | |
94 | * | |
95 | * LOCKING: | |
96 | * None (inherited from caller). | |
97 | */ | |
98 | ||
99 | static void artop6210_load_piomode(struct ata_port *ap, struct ata_device *adev, unsigned int pio) | |
100 | { | |
101 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
102 | int dn = adev->devno + 2 * ap->port_no; | |
44bdc2fb | 103 | static const u16 timing[2][5] = { |
669a5db4 JG |
104 | { 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 }, |
105 | { 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 } | |
106 | ||
107 | }; | |
108 | /* Load the PIO timing active/recovery bits */ | |
109 | pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]); | |
110 | } | |
111 | ||
112 | /** | |
113 | * artop6210_set_piomode - Initialize host controller PATA PIO timings | |
114 | * @ap: Port whose timings we are configuring | |
115 | * @adev: Device we are configuring | |
116 | * | |
117 | * Set PIO mode for device, in host controller PCI config space. For | |
118 | * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In | |
119 | * the event UDMA is used the later call to set_dmamode will set the | |
120 | * bits as required. | |
121 | * | |
122 | * LOCKING: | |
123 | * None (inherited from caller). | |
124 | */ | |
125 | ||
126 | static void artop6210_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
127 | { | |
128 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
129 | int dn = adev->devno + 2 * ap->port_no; | |
130 | u8 ultra; | |
131 | ||
132 | artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0); | |
133 | ||
134 | /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */ | |
135 | pci_read_config_byte(pdev, 0x54, &ultra); | |
136 | ultra &= ~(3 << (2 * dn)); | |
137 | pci_write_config_byte(pdev, 0x54, ultra); | |
138 | } | |
139 | ||
140 | /** | |
141 | * artop6260_load_piomode - Initialize host controller PATA PIO timings | |
142 | * @ap: Port whose timings we are configuring | |
143 | * @adev: Device we are configuring | |
144 | * @pio: PIO mode | |
145 | * | |
146 | * Set PIO mode for device, in host controller PCI config space. The | |
147 | * ARTOP6260 and relatives store the timing data differently. | |
148 | * | |
149 | * LOCKING: | |
150 | * None (inherited from caller). | |
151 | */ | |
152 | ||
153 | static void artop6260_load_piomode (struct ata_port *ap, struct ata_device *adev, unsigned int pio) | |
154 | { | |
155 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
156 | int dn = adev->devno + 2 * ap->port_no; | |
44bdc2fb | 157 | static const u8 timing[2][5] = { |
669a5db4 JG |
158 | { 0x00, 0x0A, 0x08, 0x33, 0x31 }, |
159 | { 0x70, 0x7A, 0x78, 0x43, 0x41 } | |
160 | ||
161 | }; | |
162 | /* Load the PIO timing active/recovery bits */ | |
163 | pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]); | |
164 | } | |
165 | ||
166 | /** | |
167 | * artop6260_set_piomode - Initialize host controller PATA PIO timings | |
168 | * @ap: Port whose timings we are configuring | |
169 | * @adev: Device we are configuring | |
170 | * | |
171 | * Set PIO mode for device, in host controller PCI config space. For | |
172 | * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In | |
173 | * the event UDMA is used the later call to set_dmamode will set the | |
174 | * bits as required. | |
175 | * | |
176 | * LOCKING: | |
177 | * None (inherited from caller). | |
178 | */ | |
179 | ||
180 | static void artop6260_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
181 | { | |
182 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
183 | u8 ultra; | |
184 | ||
185 | artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0); | |
186 | ||
187 | /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */ | |
188 | pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra); | |
189 | ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */ | |
190 | pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra); | |
191 | } | |
192 | ||
193 | /** | |
194 | * artop6210_set_dmamode - Initialize host controller PATA PIO timings | |
195 | * @ap: Port whose timings we are configuring | |
a73984a0 | 196 | * @adev: Device whose timings we are configuring |
669a5db4 JG |
197 | * |
198 | * Set DMA mode for device, in host controller PCI config space. | |
199 | * | |
200 | * LOCKING: | |
201 | * None (inherited from caller). | |
202 | */ | |
203 | ||
204 | static void artop6210_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
205 | { | |
206 | unsigned int pio; | |
207 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
208 | int dn = adev->devno + 2 * ap->port_no; | |
209 | u8 ultra; | |
210 | ||
211 | if (adev->dma_mode == XFER_MW_DMA_0) | |
212 | pio = 1; | |
213 | else | |
214 | pio = 4; | |
215 | ||
216 | /* Load the PIO timing active/recovery bits */ | |
217 | artop6210_load_piomode(ap, adev, pio); | |
218 | ||
219 | pci_read_config_byte(pdev, 0x54, &ultra); | |
220 | ultra &= ~(3 << (2 * dn)); | |
221 | ||
222 | /* Add ultra DMA bits if in UDMA mode */ | |
223 | if (adev->dma_mode >= XFER_UDMA_0) { | |
224 | u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock; | |
225 | if (mode == 0) | |
226 | mode = 1; | |
227 | ultra |= (mode << (2 * dn)); | |
228 | } | |
229 | pci_write_config_byte(pdev, 0x54, ultra); | |
230 | } | |
231 | ||
232 | /** | |
233 | * artop6260_set_dmamode - Initialize host controller PATA PIO timings | |
234 | * @ap: Port whose timings we are configuring | |
235 | * @adev: Device we are configuring | |
236 | * | |
237 | * Set DMA mode for device, in host controller PCI config space. The | |
238 | * ARTOP6260 and relatives store the timing data differently. | |
239 | * | |
240 | * LOCKING: | |
241 | * None (inherited from caller). | |
242 | */ | |
243 | ||
244 | static void artop6260_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
245 | { | |
01bb12e4 | 246 | unsigned int pio; |
669a5db4 JG |
247 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
248 | u8 ultra; | |
249 | ||
250 | if (adev->dma_mode == XFER_MW_DMA_0) | |
251 | pio = 1; | |
252 | else | |
253 | pio = 4; | |
254 | ||
255 | /* Load the PIO timing active/recovery bits */ | |
256 | artop6260_load_piomode(ap, adev, pio); | |
257 | ||
258 | /* Add ultra DMA bits if in UDMA mode */ | |
259 | pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra); | |
260 | ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */ | |
261 | if (adev->dma_mode >= XFER_UDMA_0) { | |
262 | u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock; | |
263 | if (mode == 0) | |
264 | mode = 1; | |
265 | ultra |= (mode << (4 * adev->devno)); | |
266 | } | |
267 | pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra); | |
268 | } | |
269 | ||
140d6fed | 270 | /** |
9c7d0b2a | 271 | * artop6210_qc_defer - implement serialization |
140d6fed AC |
272 | * @qc: command |
273 | * | |
274 | * Issue commands per host on this chip. | |
275 | */ | |
276 | ||
277 | static int artop6210_qc_defer(struct ata_queued_cmd *qc) | |
278 | { | |
279 | struct ata_host *host = qc->ap->host; | |
280 | struct ata_port *alt = host->ports[1 ^ qc->ap->port_no]; | |
281 | int rc; | |
282 | ||
283 | /* First apply the usual rules */ | |
284 | rc = ata_std_qc_defer(qc); | |
285 | if (rc != 0) | |
286 | return rc; | |
287 | ||
288 | /* Now apply serialization rules. Only allow a command if the | |
289 | other channel state machine is idle */ | |
290 | if (alt && alt->qc_active) | |
291 | return ATA_DEFER_PORT; | |
292 | return 0; | |
293 | } | |
294 | ||
25df73d9 | 295 | static const struct scsi_host_template artop_sht = { |
68d1d07b | 296 | ATA_BMDMA_SHT(DRV_NAME), |
669a5db4 JG |
297 | }; |
298 | ||
029cfd6b TH |
299 | static struct ata_port_operations artop6210_ops = { |
300 | .inherits = &ata_bmdma_port_ops, | |
301 | .cable_detect = ata_cable_40wire, | |
669a5db4 JG |
302 | .set_piomode = artop6210_set_piomode, |
303 | .set_dmamode = artop6210_set_dmamode, | |
f6b56696 | 304 | .prereset = artop62x0_pre_reset, |
140d6fed | 305 | .qc_defer = artop6210_qc_defer, |
669a5db4 JG |
306 | }; |
307 | ||
029cfd6b TH |
308 | static struct ata_port_operations artop6260_ops = { |
309 | .inherits = &ata_bmdma_port_ops, | |
310 | .cable_detect = artop6260_cable_detect, | |
669a5db4 JG |
311 | .set_piomode = artop6260_set_piomode, |
312 | .set_dmamode = artop6260_set_dmamode, | |
f6b56696 | 313 | .prereset = artop62x0_pre_reset, |
669a5db4 JG |
314 | }; |
315 | ||
067f8c7b BZ |
316 | static void atp8xx_fixup(struct pci_dev *pdev) |
317 | { | |
7ad3128e SS |
318 | u8 reg; |
319 | ||
320 | switch (pdev->device) { | |
321 | case 0x0005: | |
067f8c7b BZ |
322 | /* BIOS may have left us in UDMA, clear it before libata probe */ |
323 | pci_write_config_byte(pdev, 0x54, 0); | |
7ad3128e SS |
324 | break; |
325 | case 0x0008: | |
326 | case 0x0009: | |
067f8c7b BZ |
327 | /* Mac systems come up with some registers not set as we |
328 | will need them */ | |
329 | ||
330 | /* Clear reset & test bits */ | |
331 | pci_read_config_byte(pdev, 0x49, ®); | |
332 | pci_write_config_byte(pdev, 0x49, reg & ~0x30); | |
333 | ||
334 | /* PCI latency must be > 0x80 for burst mode, tweak it | |
335 | * if required. | |
336 | */ | |
337 | pci_read_config_byte(pdev, PCI_LATENCY_TIMER, ®); | |
338 | if (reg <= 0x80) | |
339 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90); | |
340 | ||
341 | /* Enable IRQ output and burst mode */ | |
342 | pci_read_config_byte(pdev, 0x4a, ®); | |
343 | pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80); | |
7ad3128e | 344 | break; |
067f8c7b BZ |
345 | } |
346 | } | |
669a5db4 JG |
347 | |
348 | /** | |
349 | * artop_init_one - Register ARTOP ATA PCI device with kernel services | |
350 | * @pdev: PCI device to register | |
5c16c0ce | 351 | * @id: PCI device ID |
669a5db4 JG |
352 | * |
353 | * Called from kernel PCI layer. | |
354 | * | |
355 | * LOCKING: | |
356 | * Inherited from PCI layer (may sleep). | |
357 | * | |
358 | * RETURNS: | |
359 | * Zero on success, or -ERRNO value. | |
360 | */ | |
361 | ||
362 | static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id) | |
363 | { | |
1626aeb8 | 364 | static const struct ata_port_info info_6210 = { |
1d2808fd | 365 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
366 | .pio_mask = ATA_PIO4, |
367 | .mwdma_mask = ATA_MWDMA2, | |
669a5db4 JG |
368 | .udma_mask = ATA_UDMA2, |
369 | .port_ops = &artop6210_ops, | |
370 | }; | |
1626aeb8 | 371 | static const struct ata_port_info info_626x = { |
1d2808fd | 372 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
373 | .pio_mask = ATA_PIO4, |
374 | .mwdma_mask = ATA_MWDMA2, | |
669a5db4 JG |
375 | .udma_mask = ATA_UDMA4, |
376 | .port_ops = &artop6260_ops, | |
377 | }; | |
be456b77 | 378 | static const struct ata_port_info info_628x = { |
1d2808fd | 379 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
380 | .pio_mask = ATA_PIO4, |
381 | .mwdma_mask = ATA_MWDMA2, | |
669a5db4 JG |
382 | .udma_mask = ATA_UDMA5, |
383 | .port_ops = &artop6260_ops, | |
384 | }; | |
be456b77 | 385 | static const struct ata_port_info info_628x_fast = { |
be456b77 | 386 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
387 | .pio_mask = ATA_PIO4, |
388 | .mwdma_mask = ATA_MWDMA2, | |
be456b77 BZ |
389 | .udma_mask = ATA_UDMA6, |
390 | .port_ops = &artop6260_ops, | |
391 | }; | |
1626aeb8 | 392 | const struct ata_port_info *ppi[] = { NULL, NULL }; |
f08048e9 | 393 | int rc; |
669a5db4 | 394 | |
06296a1e | 395 | ata_print_version_once(&pdev->dev, DRV_VERSION); |
669a5db4 | 396 | |
f08048e9 TH |
397 | rc = pcim_enable_device(pdev); |
398 | if (rc) | |
399 | return rc; | |
400 | ||
183a4bfb SS |
401 | switch (id->driver_data) { |
402 | case 0: /* 6210 variant */ | |
1626aeb8 | 403 | ppi[0] = &info_6210; |
183a4bfb SS |
404 | break; |
405 | case 1: /* 6260 */ | |
1626aeb8 | 406 | ppi[0] = &info_626x; |
183a4bfb SS |
407 | break; |
408 | case 2: /* 6280 or 6280 + fast */ | |
409 | if (inb(pci_resource_start(pdev, 4)) & 0x10) | |
be456b77 | 410 | ppi[0] = &info_628x_fast; |
183a4bfb SS |
411 | else |
412 | ppi[0] = &info_628x; | |
413 | break; | |
669a5db4 | 414 | } |
15a7c3bb | 415 | |
1626aeb8 | 416 | BUG_ON(ppi[0] == NULL); |
15a7c3bb | 417 | |
067f8c7b BZ |
418 | atp8xx_fixup(pdev); |
419 | ||
1c5afdf7 | 420 | return ata_pci_bmdma_init_one(pdev, ppi, &artop_sht, NULL, 0); |
669a5db4 JG |
421 | } |
422 | ||
423 | static const struct pci_device_id artop_pci_tbl[] = { | |
2d2744fc JG |
424 | { PCI_VDEVICE(ARTOP, 0x0005), 0 }, |
425 | { PCI_VDEVICE(ARTOP, 0x0006), 1 }, | |
426 | { PCI_VDEVICE(ARTOP, 0x0007), 1 }, | |
427 | { PCI_VDEVICE(ARTOP, 0x0008), 2 }, | |
428 | { PCI_VDEVICE(ARTOP, 0x0009), 2 }, | |
429 | ||
669a5db4 JG |
430 | { } /* terminate list */ |
431 | }; | |
432 | ||
58eb8cd5 | 433 | #ifdef CONFIG_PM_SLEEP |
067f8c7b BZ |
434 | static int atp8xx_reinit_one(struct pci_dev *pdev) |
435 | { | |
0a86e1c8 | 436 | struct ata_host *host = pci_get_drvdata(pdev); |
067f8c7b BZ |
437 | int rc; |
438 | ||
439 | rc = ata_pci_device_do_resume(pdev); | |
440 | if (rc) | |
441 | return rc; | |
442 | ||
443 | atp8xx_fixup(pdev); | |
444 | ||
445 | ata_host_resume(host); | |
446 | return 0; | |
447 | } | |
448 | #endif | |
449 | ||
669a5db4 JG |
450 | static struct pci_driver artop_pci_driver = { |
451 | .name = DRV_NAME, | |
452 | .id_table = artop_pci_tbl, | |
453 | .probe = artop_init_one, | |
454 | .remove = ata_pci_remove_one, | |
58eb8cd5 | 455 | #ifdef CONFIG_PM_SLEEP |
067f8c7b BZ |
456 | .suspend = ata_pci_device_suspend, |
457 | .resume = atp8xx_reinit_one, | |
458 | #endif | |
669a5db4 JG |
459 | }; |
460 | ||
2fc75da0 | 461 | module_pci_driver(artop_pci_driver); |
669a5db4 | 462 | |
067f8c7b | 463 | MODULE_AUTHOR("Alan Cox, Bartlomiej Zolnierkiewicz"); |
669a5db4 JG |
464 | MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA"); |
465 | MODULE_LICENSE("GPL"); | |
466 | MODULE_DEVICE_TABLE(pci, artop_pci_tbl); | |
467 | MODULE_VERSION(DRV_VERSION); |