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pata_arasan: Add clk_{un}prepare() support
[linux-2.6-block.git] / drivers / ata / pata_arasan_cf.c
CommitLineData
a480167b
VK		 1/*
2 * drivers/ata/pata_arasan_cf.c
3 *
4 * Arasan Compact Flash host controller source file
5 *
6 * Copyright (C) 2011 ST Microelectronics
10d8935f 7 * Viresh Kumar <viresh.linux@gmail.com>
a480167b
VK		 8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14/*
15 * The Arasan CompactFlash Device Controller IP core has three basic modes of
16 * operation: PC card ATA using I/O mode, PC card ATA using memory mode, PC card
17 * ATA using true IDE modes. This driver supports only True IDE mode currently.
18 *
19 * Arasan CF Controller shares global irq register with Arasan XD Controller.
20 *
21 * Tested on arch/arm/mach-spear13xx
22 */
23
24#include <linux/ata.h>
25#include <linux/clk.h>
26#include <linux/completion.h>
27#include <linux/delay.h>
28#include <linux/dmaengine.h>
29#include <linux/io.h>
30#include <linux/irq.h>
31#include <linux/kernel.h>
32#include <linux/libata.h>
33#include <linux/module.h>
34#include <linux/pata_arasan_cf_data.h>
35#include <linux/platform_device.h>
36#include <linux/pm.h>
37#include <linux/slab.h>
38#include <linux/spinlock.h>
39#include <linux/types.h>
40#include <linux/workqueue.h>
41
42#define DRIVER_NAME "arasan_cf"
43#define TIMEOUT msecs_to_jiffies(3000)
44
45/* Registers */
46/* CompactFlash Interface Status */
47#define CFI_STS 0x000
48 #define STS_CHG (1)
49 #define BIN_AUDIO_OUT (1 << 1)
50 #define CARD_DETECT1 (1 << 2)
51 #define CARD_DETECT2 (1 << 3)
52 #define INP_ACK (1 << 4)
53 #define CARD_READY (1 << 5)
54 #define IO_READY (1 << 6)
55 #define B16_IO_PORT_SEL (1 << 7)
56/* IRQ */
57#define IRQ_STS 0x004
58/* Interrupt Enable */
59#define IRQ_EN 0x008
60 #define CARD_DETECT_IRQ (1)
61 #define STATUS_CHNG_IRQ (1 << 1)
62 #define MEM_MODE_IRQ (1 << 2)
63 #define IO_MODE_IRQ (1 << 3)
64 #define TRUE_IDE_MODE_IRQ (1 << 8)
65 #define PIO_XFER_ERR_IRQ (1 << 9)
66 #define BUF_AVAIL_IRQ (1 << 10)
67 #define XFER_DONE_IRQ (1 << 11)
68 #define IGNORED_IRQS (STATUS_CHNG_IRQ | MEM_MODE_IRQ | IO_MODE_IRQ |\
69 TRUE_IDE_MODE_IRQ)
70 #define TRUE_IDE_IRQS (CARD_DETECT_IRQ | PIO_XFER_ERR_IRQ |\
71 BUF_AVAIL_IRQ | XFER_DONE_IRQ)
72/* Operation Mode */
73#define OP_MODE 0x00C
74 #define CARD_MODE_MASK (0x3)
75 #define MEM_MODE (0x0)
76 #define IO_MODE (0x1)
77 #define TRUE_IDE_MODE (0x2)
78
79 #define CARD_TYPE_MASK (1 << 2)
80 #define CF_CARD (0)
81 #define CF_PLUS_CARD (1 << 2)
82
83 #define CARD_RESET (1 << 3)
84 #define CFHOST_ENB (1 << 4)
85 #define OUTPUTS_TRISTATE (1 << 5)
86 #define ULTRA_DMA_ENB (1 << 8)
87 #define MULTI_WORD_DMA_ENB (1 << 9)
88 #define DRQ_BLOCK_SIZE_MASK (0x3 << 11)
89 #define DRQ_BLOCK_SIZE_512 (0)
90 #define DRQ_BLOCK_SIZE_1024 (1 << 11)
91 #define DRQ_BLOCK_SIZE_2048 (2 << 11)
92 #define DRQ_BLOCK_SIZE_4096 (3 << 11)
93/* CF Interface Clock Configuration */
94#define CLK_CFG 0x010
95 #define CF_IF_CLK_MASK (0XF)
96/* CF Timing Mode Configuration */
97#define TM_CFG 0x014
98 #define MEM_MODE_TIMING_MASK (0x3)
99 #define MEM_MODE_TIMING_250NS (0x0)
100 #define MEM_MODE_TIMING_120NS (0x1)
101 #define MEM_MODE_TIMING_100NS (0x2)
102 #define MEM_MODE_TIMING_80NS (0x3)
103
104 #define IO_MODE_TIMING_MASK (0x3 << 2)
105 #define IO_MODE_TIMING_250NS (0x0 << 2)
106 #define IO_MODE_TIMING_120NS (0x1 << 2)
107 #define IO_MODE_TIMING_100NS (0x2 << 2)
108 #define IO_MODE_TIMING_80NS (0x3 << 2)
109
110 #define TRUEIDE_PIO_TIMING_MASK (0x7 << 4)
111 #define TRUEIDE_PIO_TIMING_SHIFT 4
112
113 #define TRUEIDE_MWORD_DMA_TIMING_MASK (0x7 << 7)
114 #define TRUEIDE_MWORD_DMA_TIMING_SHIFT 7
115
116 #define ULTRA_DMA_TIMING_MASK (0x7 << 10)
117 #define ULTRA_DMA_TIMING_SHIFT 10
118/* CF Transfer Address */
119#define XFER_ADDR 0x014
120 #define XFER_ADDR_MASK (0x7FF)
121 #define MAX_XFER_COUNT 0x20000u
122/* Transfer Control */
123#define XFER_CTR 0x01C
124 #define XFER_COUNT_MASK (0x3FFFF)
125 #define ADDR_INC_DISABLE (1 << 24)
126 #define XFER_WIDTH_MASK (1 << 25)
127 #define XFER_WIDTH_8B (0)
128 #define XFER_WIDTH_16B (1 << 25)
129
130 #define MEM_TYPE_MASK (1 << 26)
131 #define MEM_TYPE_COMMON (0)
132 #define MEM_TYPE_ATTRIBUTE (1 << 26)
133
134 #define MEM_IO_XFER_MASK (1 << 27)
135 #define MEM_XFER (0)
136 #define IO_XFER (1 << 27)
137
138 #define DMA_XFER_MODE (1 << 28)
139
140 #define AHB_BUS_NORMAL_PIO_OPRTN (~(1 << 29))
141 #define XFER_DIR_MASK (1 << 30)
142 #define XFER_READ (0)
143 #define XFER_WRITE (1 << 30)
144
145 #define XFER_START (1 << 31)
146/* Write Data Port */
147#define WRITE_PORT 0x024
148/* Read Data Port */
149#define READ_PORT 0x028
150/* ATA Data Port */
151#define ATA_DATA_PORT 0x030
152 #define ATA_DATA_PORT_MASK (0xFFFF)
153/* ATA Error/Features */
154#define ATA_ERR_FTR 0x034
155/* ATA Sector Count */
156#define ATA_SC 0x038
157/* ATA Sector Number */
158#define ATA_SN 0x03C
159/* ATA Cylinder Low */
160#define ATA_CL 0x040
161/* ATA Cylinder High */
162#define ATA_CH 0x044
163/* ATA Select Card/Head */
164#define ATA_SH 0x048
165/* ATA Status-Command */
166#define ATA_STS_CMD 0x04C
167/* ATA Alternate Status/Device Control */
168#define ATA_ASTS_DCTR 0x050
169/* Extended Write Data Port 0x200-0x3FC */
170#define EXT_WRITE_PORT 0x200
171/* Extended Read Data Port 0x400-0x5FC */
172#define EXT_READ_PORT 0x400
173 #define FIFO_SIZE 0x200u
174/* Global Interrupt Status */
175#define GIRQ_STS 0x800
176/* Global Interrupt Status enable */
177#define GIRQ_STS_EN 0x804
178/* Global Interrupt Signal enable */
179#define GIRQ_SGN_EN 0x808
180 #define GIRQ_CF (1)
181 #define GIRQ_XD (1 << 1)
182
183/* Compact Flash Controller Dev Structure */
184struct arasan_cf_dev {
185 /* pointer to ata_host structure */
186 struct ata_host *host;
d14fb1e9 187 /* clk structure */
a480167b 188 struct clk *clk;
a480167b
VK		 189
190 /* physical base address of controller */
191 dma_addr_t pbase;
192 /* virtual base address of controller */
193 void __iomem *vbase;
194 /* irq number*/
195 int irq;
196
197 /* status to be updated to framework regarding DMA transfer */
198 u8 dma_status;
199 /* Card is present or Not */
200 u8 card_present;
201
202 /* dma specific */
203 /* Completion for transfer complete interrupt from controller */
204 struct completion cf_completion;
205 /* Completion for DMA transfer complete. */
206 struct completion dma_completion;
207 /* Dma channel allocated */
208 struct dma_chan *dma_chan;
209 /* Mask for DMA transfers */
210 dma_cap_mask_t mask;
60a230e4
VK		 211 /* dma channel private data */
212 void *dma_priv;
a480167b
VK		 213 /* DMA transfer work */
214 struct work_struct work;
215 /* DMA delayed finish work */
216 struct delayed_work dwork;
217 /* qc to be transferred using DMA */
218 struct ata_queued_cmd *qc;
219};
220
221static struct scsi_host_template arasan_cf_sht = {
222 ATA_BASE_SHT(DRIVER_NAME),
223 .sg_tablesize = SG_NONE,
224 .dma_boundary = 0xFFFFFFFFUL,
225};
226
227static void cf_dumpregs(struct arasan_cf_dev *acdev)
228{
229 struct device *dev = acdev->host->dev;
230
231 dev_dbg(dev, ": =========== REGISTER DUMP ===========");
232 dev_dbg(dev, ": CFI_STS: %x", readl(acdev->vbase + CFI_STS));
233 dev_dbg(dev, ": IRQ_STS: %x", readl(acdev->vbase + IRQ_STS));
234 dev_dbg(dev, ": IRQ_EN: %x", readl(acdev->vbase + IRQ_EN));
235 dev_dbg(dev, ": OP_MODE: %x", readl(acdev->vbase + OP_MODE));
236 dev_dbg(dev, ": CLK_CFG: %x", readl(acdev->vbase + CLK_CFG));
237 dev_dbg(dev, ": TM_CFG: %x", readl(acdev->vbase + TM_CFG));
238 dev_dbg(dev, ": XFER_CTR: %x", readl(acdev->vbase + XFER_CTR));
239 dev_dbg(dev, ": GIRQ_STS: %x", readl(acdev->vbase + GIRQ_STS));
240 dev_dbg(dev, ": GIRQ_STS_EN: %x", readl(acdev->vbase + GIRQ_STS_EN));
241 dev_dbg(dev, ": GIRQ_SGN_EN: %x", readl(acdev->vbase + GIRQ_SGN_EN));
242 dev_dbg(dev, ": =====================================");
243}
244
245/* Enable/Disable global interrupts shared between CF and XD ctrlr. */
246static void cf_ginterrupt_enable(struct arasan_cf_dev *acdev, bool enable)
247{
248 /* enable should be 0 or 1 */
249 writel(enable, acdev->vbase + GIRQ_STS_EN);
250 writel(enable, acdev->vbase + GIRQ_SGN_EN);
251}
252
253/* Enable/Disable CF interrupts */
254static inline void
255cf_interrupt_enable(struct arasan_cf_dev *acdev, u32 mask, bool enable)
256{
257 u32 val = readl(acdev->vbase + IRQ_EN);
258 /* clear & enable/disable irqs */
259 if (enable) {
260 writel(mask, acdev->vbase + IRQ_STS);
261 writel(val | mask, acdev->vbase + IRQ_EN);
262 } else
263 writel(val & ~mask, acdev->vbase + IRQ_EN);
264}
265
266static inline void cf_card_reset(struct arasan_cf_dev *acdev)
267{
268 u32 val = readl(acdev->vbase + OP_MODE);
269
270 writel(val | CARD_RESET, acdev->vbase + OP_MODE);
271 udelay(200);
272 writel(val & ~CARD_RESET, acdev->vbase + OP_MODE);
273}
274
275static inline void cf_ctrl_reset(struct arasan_cf_dev *acdev)
276{
277 writel(readl(acdev->vbase + OP_MODE) & ~CFHOST_ENB,
278 acdev->vbase + OP_MODE);
279 writel(readl(acdev->vbase + OP_MODE) | CFHOST_ENB,
280 acdev->vbase + OP_MODE);
281}
282
283static void cf_card_detect(struct arasan_cf_dev *acdev, bool hotplugged)
284{
285 struct ata_port *ap = acdev->host->ports[0];
286 struct ata_eh_info *ehi = &ap->link.eh_info;
287 u32 val = readl(acdev->vbase + CFI_STS);
288
289 /* Both CD1 & CD2 should be low if card inserted completely */
290 if (!(val & (CARD_DETECT1 | CARD_DETECT2))) {
291 if (acdev->card_present)
292 return;
293 acdev->card_present = 1;
294 cf_card_reset(acdev);
295 } else {
296 if (!acdev->card_present)
297 return;
298 acdev->card_present = 0;
299 }
300
301 if (hotplugged) {
302 ata_ehi_hotplugged(ehi);
303 ata_port_freeze(ap);
304 }
305}
306
307static int cf_init(struct arasan_cf_dev *acdev)
308{
309 struct arasan_cf_pdata *pdata = dev_get_platdata(acdev->host->dev);
310 unsigned long flags;
311 int ret = 0;
312
3f09e6c0 313 ret = clk_prepare_enable(acdev->clk);
a480167b
VK		 314 if (ret) {
315 dev_dbg(acdev->host->dev, "clock enable failed");
316 return ret;
317 }
a480167b
VK		 318
319 spin_lock_irqsave(&acdev->host->lock, flags);
320 /* configure CF interface clock */
321 writel((pdata->cf_if_clk <= CF_IF_CLK_200M) ? pdata->cf_if_clk :
322 CF_IF_CLK_166M, acdev->vbase + CLK_CFG);
323
324 writel(TRUE_IDE_MODE | CFHOST_ENB, acdev->vbase + OP_MODE);
325 cf_interrupt_enable(acdev, CARD_DETECT_IRQ, 1);
326 cf_ginterrupt_enable(acdev, 1);
327 spin_unlock_irqrestore(&acdev->host->lock, flags);
328
329 return ret;
330}
331
332static void cf_exit(struct arasan_cf_dev *acdev)
333{
334 unsigned long flags;
335
336 spin_lock_irqsave(&acdev->host->lock, flags);
337 cf_ginterrupt_enable(acdev, 0);
338 cf_interrupt_enable(acdev, TRUE_IDE_IRQS, 0);
339 cf_card_reset(acdev);
340 writel(readl(acdev->vbase + OP_MODE) & ~CFHOST_ENB,
341 acdev->vbase + OP_MODE);
342 spin_unlock_irqrestore(&acdev->host->lock, flags);
3f09e6c0 343 clk_disable_unprepare(acdev->clk);
a480167b
VK		 344}
345
346static void dma_callback(void *dev)
347{
348 struct arasan_cf_dev *acdev = (struct arasan_cf_dev *) dev;
349
350 complete(&acdev->dma_completion);
351}
352
353static bool filter(struct dma_chan *chan, void *slave)
354{
60a230e4 355 chan->private = slave;
a480167b
VK		 356 return true;
357}
358
359static inline void dma_complete(struct arasan_cf_dev *acdev)
360{
361 struct ata_queued_cmd *qc = acdev->qc;
362 unsigned long flags;
363
364 acdev->qc = NULL;
365 ata_sff_interrupt(acdev->irq, acdev->host);
366
367 spin_lock_irqsave(&acdev->host->lock, flags);
368 if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
369 ata_ehi_push_desc(&qc->ap->link.eh_info, "DMA Failed: Timeout");
370 spin_unlock_irqrestore(&acdev->host->lock, flags);
371}
372
373static inline int wait4buf(struct arasan_cf_dev *acdev)
374{
375 if (!wait_for_completion_timeout(&acdev->cf_completion, TIMEOUT)) {
376 u32 rw = acdev->qc->tf.flags & ATA_TFLAG_WRITE;
377
378 dev_err(acdev->host->dev, "%s TimeOut", rw ? "write" : "read");
379 return -ETIMEDOUT;
380 }
381
25985edc 382 /* Check if PIO Error interrupt has occurred */
a480167b
VK		 383 if (acdev->dma_status & ATA_DMA_ERR)
384 return -EAGAIN;
385
386 return 0;
387}
388
389static int
390dma_xfer(struct arasan_cf_dev *acdev, dma_addr_t src, dma_addr_t dest, u32 len)
391{
392 struct dma_async_tx_descriptor *tx;
393 struct dma_chan *chan = acdev->dma_chan;
394 dma_cookie_t cookie;
395 unsigned long flags = DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_SRC_UNMAP |
396 DMA_COMPL_SKIP_DEST_UNMAP;
397 int ret = 0;
398
399 tx = chan->device->device_prep_dma_memcpy(chan, dest, src, len, flags);
400 if (!tx) {
401 dev_err(acdev->host->dev, "device_prep_dma_memcpy failed\n");
402 return -EAGAIN;
403 }
404
405 tx->callback = dma_callback;
406 tx->callback_param = acdev;
407 cookie = tx->tx_submit(tx);
408
409 ret = dma_submit_error(cookie);
410 if (ret) {
411 dev_err(acdev->host->dev, "dma_submit_error\n");
412 return ret;
413 }
414
415 chan->device->device_issue_pending(chan);
416
417 /* Wait for DMA to complete */
418 if (!wait_for_completion_timeout(&acdev->dma_completion, TIMEOUT)) {
419 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
420 dev_err(acdev->host->dev, "wait_for_completion_timeout\n");
421 return -ETIMEDOUT;
422 }
423
424 return ret;
425}
426
427static int sg_xfer(struct arasan_cf_dev *acdev, struct scatterlist *sg)
428{
429 dma_addr_t dest = 0, src = 0;
430 u32 xfer_cnt, sglen, dma_len, xfer_ctr;
431 u32 write = acdev->qc->tf.flags & ATA_TFLAG_WRITE;
432 unsigned long flags;
433 int ret = 0;
434
435 sglen = sg_dma_len(sg);
436 if (write) {
437 src = sg_dma_address(sg);
438 dest = acdev->pbase + EXT_WRITE_PORT;
439 } else {
440 dest = sg_dma_address(sg);
441 src = acdev->pbase + EXT_READ_PORT;
442 }
443
444 /*
445 * For each sg:
446 * MAX_XFER_COUNT data will be transferred before we get transfer
25985edc 447 * complete interrupt. Between after FIFO_SIZE data
a480167b
VK		 448 * buffer available interrupt will be generated. At this time we will
449 * fill FIFO again: max FIFO_SIZE data.
450 */
451 while (sglen) {
452 xfer_cnt = min(sglen, MAX_XFER_COUNT);
453 spin_lock_irqsave(&acdev->host->lock, flags);
454 xfer_ctr = readl(acdev->vbase + XFER_CTR) &
455 ~XFER_COUNT_MASK;
456 writel(xfer_ctr | xfer_cnt | XFER_START,
457 acdev->vbase + XFER_CTR);
458 spin_unlock_irqrestore(&acdev->host->lock, flags);
459
25985edc 460 /* continue dma xfers until current sg is completed */
a480167b
VK		 461 while (xfer_cnt) {
462 /* wait for read to complete */
463 if (!write) {
464 ret = wait4buf(acdev);
465 if (ret)
466 goto fail;
467 }
468
469 /* read/write FIFO in chunk of FIFO_SIZE */
470 dma_len = min(xfer_cnt, FIFO_SIZE);
471 ret = dma_xfer(acdev, src, dest, dma_len);
472 if (ret) {
473 dev_err(acdev->host->dev, "dma failed");
474 goto fail;
475 }
476
477 if (write)
478 src += dma_len;
479 else
480 dest += dma_len;
481
482 sglen -= dma_len;
483 xfer_cnt -= dma_len;
484
485 /* wait for write to complete */
486 if (write) {
487 ret = wait4buf(acdev);
488 if (ret)
489 goto fail;
490 }
491 }
492 }
493
494fail:
495 spin_lock_irqsave(&acdev->host->lock, flags);
496 writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
497 acdev->vbase + XFER_CTR);
498 spin_unlock_irqrestore(&acdev->host->lock, flags);
499
500 return ret;
501}
502
503/*
504 * This routine uses External DMA controller to read/write data to FIFO of CF
505 * controller. There are two xfer related interrupt supported by CF controller:
506 * - buf_avail: This interrupt is generated as soon as we have buffer of 512
507 * bytes available for reading or empty buffer available for writing.
508 * - xfer_done: This interrupt is generated on transfer of "xfer_size" amount of
509 * data to/from FIFO. xfer_size is programmed in XFER_CTR register.
510 *
511 * Max buffer size = FIFO_SIZE = 512 Bytes.
512 * Max xfer_size = MAX_XFER_COUNT = 256 KB.
513 */
514static void data_xfer(struct work_struct *work)
515{
516 struct arasan_cf_dev *acdev = container_of(work, struct arasan_cf_dev,
517 work);
518 struct ata_queued_cmd *qc = acdev->qc;
519 struct scatterlist *sg;
520 unsigned long flags;
521 u32 temp;
522 int ret = 0;
523
524 /* request dma channels */
525 /* dma_request_channel may sleep, so calling from process context */
60a230e4
VK		 526 acdev->dma_chan = dma_request_channel(acdev->mask, filter,
527 acdev->dma_priv);
a480167b
VK		 528 if (!acdev->dma_chan) {
529 dev_err(acdev->host->dev, "Unable to get dma_chan\n");
530 goto chan_request_fail;
531 }
532
533 for_each_sg(qc->sg, sg, qc->n_elem, temp) {
534 ret = sg_xfer(acdev, sg);
535 if (ret)
536 break;
537 }
538
539 dma_release_channel(acdev->dma_chan);
540
541 /* data xferred successfully */
542 if (!ret) {
543 u32 status;
544
545 spin_lock_irqsave(&acdev->host->lock, flags);
546 status = ioread8(qc->ap->ioaddr.altstatus_addr);
547 spin_unlock_irqrestore(&acdev->host->lock, flags);
548 if (status & (ATA_BUSY | ATA_DRQ)) {
549 ata_sff_queue_delayed_work(&acdev->dwork, 1);
550 return;
551 }
552
553 goto sff_intr;
554 }
555
556 cf_dumpregs(acdev);
557
558chan_request_fail:
559 spin_lock_irqsave(&acdev->host->lock, flags);
25985edc 560 /* error when transferring data to/from memory */
a480167b
VK		 561 qc->err_mask |= AC_ERR_HOST_BUS;
562 qc->ap->hsm_task_state = HSM_ST_ERR;
563
564 cf_ctrl_reset(acdev);
565 spin_unlock_irqrestore(qc->ap->lock, flags);
566sff_intr:
567 dma_complete(acdev);
568}
569
570static void delayed_finish(struct work_struct *work)
571{
572 struct arasan_cf_dev *acdev = container_of(work, struct arasan_cf_dev,
573 dwork.work);
574 struct ata_queued_cmd *qc = acdev->qc;
575 unsigned long flags;
576 u8 status;
577
578 spin_lock_irqsave(&acdev->host->lock, flags);
579 status = ioread8(qc->ap->ioaddr.altstatus_addr);
580 spin_unlock_irqrestore(&acdev->host->lock, flags);
581
582 if (status & (ATA_BUSY | ATA_DRQ))
583 ata_sff_queue_delayed_work(&acdev->dwork, 1);
584 else
585 dma_complete(acdev);
586}
587
588static irqreturn_t arasan_cf_interrupt(int irq, void *dev)
589{
590 struct arasan_cf_dev *acdev = ((struct ata_host *)dev)->private_data;
591 unsigned long flags;
592 u32 irqsts;
593
594 irqsts = readl(acdev->vbase + GIRQ_STS);
595 if (!(irqsts & GIRQ_CF))
596 return IRQ_NONE;
597
598 spin_lock_irqsave(&acdev->host->lock, flags);
599 irqsts = readl(acdev->vbase + IRQ_STS);
600 writel(irqsts, acdev->vbase + IRQ_STS); /* clear irqs */
601 writel(GIRQ_CF, acdev->vbase + GIRQ_STS); /* clear girqs */
602
603 /* handle only relevant interrupts */
604 irqsts &= ~IGNORED_IRQS;
605
606 if (irqsts & CARD_DETECT_IRQ) {
607 cf_card_detect(acdev, 1);
608 spin_unlock_irqrestore(&acdev->host->lock, flags);
609 return IRQ_HANDLED;
610 }
611
612 if (irqsts & PIO_XFER_ERR_IRQ) {
613 acdev->dma_status = ATA_DMA_ERR;
614 writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
615 acdev->vbase + XFER_CTR);
616 spin_unlock_irqrestore(&acdev->host->lock, flags);
617 complete(&acdev->cf_completion);
618 dev_err(acdev->host->dev, "pio xfer err irq\n");
619 return IRQ_HANDLED;
620 }
621
622 spin_unlock_irqrestore(&acdev->host->lock, flags);
623
624 if (irqsts & BUF_AVAIL_IRQ) {
625 complete(&acdev->cf_completion);
626 return IRQ_HANDLED;
627 }
628
629 if (irqsts & XFER_DONE_IRQ) {
630 struct ata_queued_cmd *qc = acdev->qc;
631
632 /* Send Complete only for write */
633 if (qc->tf.flags & ATA_TFLAG_WRITE)
634 complete(&acdev->cf_completion);
635 }
636
637 return IRQ_HANDLED;
638}
639
640static void arasan_cf_freeze(struct ata_port *ap)
641{
642 struct arasan_cf_dev *acdev = ap->host->private_data;
643
644 /* stop transfer and reset controller */
645 writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
646 acdev->vbase + XFER_CTR);
647 cf_ctrl_reset(acdev);
648 acdev->dma_status = ATA_DMA_ERR;
649
650 ata_sff_dma_pause(ap);
651 ata_sff_freeze(ap);
652}
653
654void arasan_cf_error_handler(struct ata_port *ap)
655{
656 struct arasan_cf_dev *acdev = ap->host->private_data;
657
658 /*
659 * DMA transfers using an external DMA controller may be scheduled.
660 * Abort them before handling error. Refer data_xfer() for further
661 * details.
662 */
663 cancel_work_sync(&acdev->work);
664 cancel_delayed_work_sync(&acdev->dwork);
665 return ata_sff_error_handler(ap);
666}
667
668static void arasan_cf_dma_start(struct arasan_cf_dev *acdev)
669{
670 u32 xfer_ctr = readl(acdev->vbase + XFER_CTR) & ~XFER_DIR_MASK;
671 u32 write = acdev->qc->tf.flags & ATA_TFLAG_WRITE;
672
673 xfer_ctr |= write ? XFER_WRITE : XFER_READ;
674 writel(xfer_ctr, acdev->vbase + XFER_CTR);
675
676 acdev->qc->ap->ops->sff_exec_command(acdev->qc->ap, &acdev->qc->tf);
677 ata_sff_queue_work(&acdev->work);
678}
679
680unsigned int arasan_cf_qc_issue(struct ata_queued_cmd *qc)
681{
682 struct ata_port *ap = qc->ap;
683 struct arasan_cf_dev *acdev = ap->host->private_data;
684
685 /* defer PIO handling to sff_qc_issue */
686 if (!ata_is_dma(qc->tf.protocol))
687 return ata_sff_qc_issue(qc);
688
689 /* select the device */
690 ata_wait_idle(ap);
691 ata_sff_dev_select(ap, qc->dev->devno);
692 ata_wait_idle(ap);
693
694 /* start the command */
695 switch (qc->tf.protocol) {
696 case ATA_PROT_DMA:
697 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
698
699 ap->ops->sff_tf_load(ap, &qc->tf);
700 acdev->dma_status = 0;
701 acdev->qc = qc;
702 arasan_cf_dma_start(acdev);
703 ap->hsm_task_state = HSM_ST_LAST;
704 break;
705
706 default:
707 WARN_ON(1);
708 return AC_ERR_SYSTEM;
709 }
710
711 return 0;
712}
713
714static void arasan_cf_set_piomode(struct ata_port *ap, struct ata_device *adev)
715{
716 struct arasan_cf_dev *acdev = ap->host->private_data;
717 u8 pio = adev->pio_mode - XFER_PIO_0;
718 unsigned long flags;
719 u32 val;
720
721 /* Arasan ctrl supports Mode0 -> Mode6 */
722 if (pio > 6) {
723 dev_err(ap->dev, "Unknown PIO mode\n");
724 return;
725 }
726
727 spin_lock_irqsave(&acdev->host->lock, flags);
728 val = readl(acdev->vbase + OP_MODE) &
729 ~(ULTRA_DMA_ENB | MULTI_WORD_DMA_ENB | DRQ_BLOCK_SIZE_MASK);
730 writel(val, acdev->vbase + OP_MODE);
731 val = readl(acdev->vbase + TM_CFG) & ~TRUEIDE_PIO_TIMING_MASK;
732 val |= pio << TRUEIDE_PIO_TIMING_SHIFT;
733 writel(val, acdev->vbase + TM_CFG);
734
735 cf_interrupt_enable(acdev, BUF_AVAIL_IRQ | XFER_DONE_IRQ, 0);
736 cf_interrupt_enable(acdev, PIO_XFER_ERR_IRQ, 1);
737 spin_unlock_irqrestore(&acdev->host->lock, flags);
738}
739
740static void arasan_cf_set_dmamode(struct ata_port *ap, struct ata_device *adev)
741{
742 struct arasan_cf_dev *acdev = ap->host->private_data;
743 u32 opmode, tmcfg, dma_mode = adev->dma_mode;
744 unsigned long flags;
745
746 spin_lock_irqsave(&acdev->host->lock, flags);
747 opmode = readl(acdev->vbase + OP_MODE) &
748 ~(MULTI_WORD_DMA_ENB | ULTRA_DMA_ENB);
749 tmcfg = readl(acdev->vbase + TM_CFG);
750
751 if ((dma_mode >= XFER_UDMA_0) && (dma_mode <= XFER_UDMA_6)) {
752 opmode |= ULTRA_DMA_ENB;
753 tmcfg &= ~ULTRA_DMA_TIMING_MASK;
754 tmcfg |= (dma_mode - XFER_UDMA_0) << ULTRA_DMA_TIMING_SHIFT;
755 } else if ((dma_mode >= XFER_MW_DMA_0) && (dma_mode <= XFER_MW_DMA_4)) {
756 opmode |= MULTI_WORD_DMA_ENB;
757 tmcfg &= ~TRUEIDE_MWORD_DMA_TIMING_MASK;
758 tmcfg |= (dma_mode - XFER_MW_DMA_0) <<
759 TRUEIDE_MWORD_DMA_TIMING_SHIFT;
760 } else {
761 dev_err(ap->dev, "Unknown DMA mode\n");
762 spin_unlock_irqrestore(&acdev->host->lock, flags);
763 return;
764 }
765
766 writel(opmode, acdev->vbase + OP_MODE);
767 writel(tmcfg, acdev->vbase + TM_CFG);
768 writel(DMA_XFER_MODE, acdev->vbase + XFER_CTR);
769
770 cf_interrupt_enable(acdev, PIO_XFER_ERR_IRQ, 0);
771 cf_interrupt_enable(acdev, BUF_AVAIL_IRQ | XFER_DONE_IRQ, 1);
772 spin_unlock_irqrestore(&acdev->host->lock, flags);
773}
774
775static struct ata_port_operations arasan_cf_ops = {
776 .inherits = &ata_sff_port_ops,
777 .freeze = arasan_cf_freeze,
778 .error_handler = arasan_cf_error_handler,
779 .qc_issue = arasan_cf_qc_issue,
780 .set_piomode = arasan_cf_set_piomode,
781 .set_dmamode = arasan_cf_set_dmamode,
782};
783
784static int __devinit arasan_cf_probe(struct platform_device *pdev)
785{
786 struct arasan_cf_dev *acdev;
787 struct arasan_cf_pdata *pdata = dev_get_platdata(&pdev->dev);
788 struct ata_host *host;
789 struct ata_port *ap;
790 struct resource *res;
791 irq_handler_t irq_handler = NULL;
792 int ret = 0;
793
794 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
795 if (!res)
796 return -EINVAL;
797
798 if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
799 DRIVER_NAME)) {
800 dev_warn(&pdev->dev, "Failed to get memory region resource\n");
801 return -ENOENT;
802 }
803
804 acdev = devm_kzalloc(&pdev->dev, sizeof(*acdev), GFP_KERNEL);
805 if (!acdev) {
806 dev_warn(&pdev->dev, "kzalloc fail\n");
807 return -ENOMEM;
808 }
809
810 /* if irq is 0, support only PIO */
811 acdev->irq = platform_get_irq(pdev, 0);
812 if (acdev->irq)
813 irq_handler = arasan_cf_interrupt;
814 else
815 pdata->quirk |= CF_BROKEN_MWDMA | CF_BROKEN_UDMA;
816
817 acdev->pbase = res->start;
818 acdev->vbase = devm_ioremap_nocache(&pdev->dev, res->start,
819 resource_size(res));
820 if (!acdev->vbase) {
821 dev_warn(&pdev->dev, "ioremap fail\n");
822 return -ENOMEM;
823 }
824
a480167b
VK		 825 acdev->clk = clk_get(&pdev->dev, NULL);
826 if (IS_ERR(acdev->clk)) {
827 dev_warn(&pdev->dev, "Clock not found\n");
828 return PTR_ERR(acdev->clk);
829 }
a480167b
VK		 830
831 /* allocate host */
832 host = ata_host_alloc(&pdev->dev, 1);
833 if (!host) {
834 ret = -ENOMEM;
835 dev_warn(&pdev->dev, "alloc host fail\n");
836 goto free_clk;
837 }
838
839 ap = host->ports[0];
840 host->private_data = acdev;
841 acdev->host = host;
842 ap->ops = &arasan_cf_ops;
843 ap->pio_mask = ATA_PIO6;
844 ap->mwdma_mask = ATA_MWDMA4;
845 ap->udma_mask = ATA_UDMA6;
846
847 init_completion(&acdev->cf_completion);
848 init_completion(&acdev->dma_completion);
849 INIT_WORK(&acdev->work, data_xfer);
850 INIT_DELAYED_WORK(&acdev->dwork, delayed_finish);
851 dma_cap_set(DMA_MEMCPY, acdev->mask);
60a230e4 852 acdev->dma_priv = pdata->dma_priv;
a480167b
VK		 853
854 /* Handle platform specific quirks */
855 if (pdata->quirk) {
856 if (pdata->quirk & CF_BROKEN_PIO) {
857 ap->ops->set_piomode = NULL;
858 ap->pio_mask = 0;
859 }
860 if (pdata->quirk & CF_BROKEN_MWDMA)
861 ap->mwdma_mask = 0;
862 if (pdata->quirk & CF_BROKEN_UDMA)
863 ap->udma_mask = 0;
864 }
865 ap->flags |= ATA_FLAG_PIO_POLLING | ATA_FLAG_NO_ATAPI;
866
867 ap->ioaddr.cmd_addr = acdev->vbase + ATA_DATA_PORT;
868 ap->ioaddr.data_addr = acdev->vbase + ATA_DATA_PORT;
869 ap->ioaddr.error_addr = acdev->vbase + ATA_ERR_FTR;
870 ap->ioaddr.feature_addr = acdev->vbase + ATA_ERR_FTR;
871 ap->ioaddr.nsect_addr = acdev->vbase + ATA_SC;
872 ap->ioaddr.lbal_addr = acdev->vbase + ATA_SN;
873 ap->ioaddr.lbam_addr = acdev->vbase + ATA_CL;
874 ap->ioaddr.lbah_addr = acdev->vbase + ATA_CH;
875 ap->ioaddr.device_addr = acdev->vbase + ATA_SH;
876 ap->ioaddr.status_addr = acdev->vbase + ATA_STS_CMD;
877 ap->ioaddr.command_addr = acdev->vbase + ATA_STS_CMD;
878 ap->ioaddr.altstatus_addr = acdev->vbase + ATA_ASTS_DCTR;
879 ap->ioaddr.ctl_addr = acdev->vbase + ATA_ASTS_DCTR;
880
a17139b6
JG		 881 ata_port_desc(ap, "phy_addr %llx virt_addr %p",
882 (unsigned long long) res->start, acdev->vbase);
a480167b
VK		 883
884 ret = cf_init(acdev);
885 if (ret)
886 goto free_clk;
887
888 cf_card_detect(acdev, 0);
889
890 return ata_host_activate(host, acdev->irq, irq_handler, 0,
891 &arasan_cf_sht);
892
893free_clk:
a480167b 894 clk_put(acdev->clk);
a480167b
VK		 895 return ret;
896}
897
898static int __devexit arasan_cf_remove(struct platform_device *pdev)
899{
900 struct ata_host *host = dev_get_drvdata(&pdev->dev);
901 struct arasan_cf_dev *acdev = host->ports[0]->private_data;
902
903 ata_host_detach(host);
904 cf_exit(acdev);
a480167b 905 clk_put(acdev->clk);
a480167b
VK		 906
907 return 0;
908}
909
910#ifdef CONFIG_PM
911static int arasan_cf_suspend(struct device *dev)
912{
90f0adf0 913 struct ata_host *host = dev_get_drvdata(dev);
a480167b
VK		 914 struct arasan_cf_dev *acdev = host->ports[0]->private_data;
915
40679b3c 916 if (acdev->dma_chan)
a480167b
VK		 917 acdev->dma_chan->device->device_control(acdev->dma_chan,
918 DMA_TERMINATE_ALL, 0);
40679b3c 919
a480167b
VK		 920 cf_exit(acdev);
921 return ata_host_suspend(host, PMSG_SUSPEND);
922}
923
924static int arasan_cf_resume(struct device *dev)
925{
90f0adf0 926 struct ata_host *host = dev_get_drvdata(dev);
a480167b
VK		 927 struct arasan_cf_dev *acdev = host->ports[0]->private_data;
928
929 cf_init(acdev);
930 ata_host_resume(host);
931
932 return 0;
933}
fb9751d4 934#endif
a480167b 935
40679b3c 936static SIMPLE_DEV_PM_OPS(arasan_cf_pm_ops, arasan_cf_suspend, arasan_cf_resume);
a480167b
VK		 937
938static struct platform_driver arasan_cf_driver = {
939 .probe = arasan_cf_probe,
940 .remove = __devexit_p(arasan_cf_remove),
941 .driver = {
942 .name = DRIVER_NAME,
943 .owner = THIS_MODULE,
40679b3c 944 .pm = &arasan_cf_pm_ops,
a480167b
VK		 945 },
946};
947
99c8ea3e 948module_platform_driver(arasan_cf_driver);
a480167b 949
10d8935f 950MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");
a480167b
VK		 951MODULE_DESCRIPTION("Arasan ATA Compact Flash driver");
952MODULE_LICENSE("GPL");
953MODULE_ALIAS("platform:" DRIVER_NAME);
Linux 6.x block layer and io_uring tree(s)