[linux-2.6-block.git] / drivers / ata / pata_amd.c

/*
 * pata_amd.c 	- AMD PATA for new ATA layer
 *			  (C) 2005-2006 Red Hat Inc
 *
 *  Based on pata-sil680. Errata information is taken from data sheets
 *  and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
 *  claimed by sata-nv.c.
 *
 *  TODO:
 *	Variable system clock when/if it makes sense
 *	Power management on ports
 *
 *
 *  Documentation publically available.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_amd"
#define DRV_VERSION "0.3.11"

/**
 *	timing_setup		-	shared timing computation and load
 *	@ap: ATA port being set up
 *	@adev: drive being configured
 *	@offset: port offset
 *	@speed: target speed
 *	@clock: clock multiplier (number of times 33MHz for this part)
 *
 *	Perform the actual timing set up for Nvidia or AMD PATA devices.
 *	The actual devices vary so they all call into this helper function
 *	providing the clock multipler and offset (because AMD and Nvidia put
 *	the ports at different locations).
 */

static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock)
{
	static const unsigned char amd_cyc2udma[] = {
		6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
	};

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	struct ata_device *peer = ata_dev_pair(adev);
	int dn = ap->port_no * 2 + adev->devno;
	struct ata_timing at, apeer;
	int T, UT;
	const int amd_clock = 33333;	/* KHz. */
	u8 t;

	T = 1000000000 / amd_clock;
	UT = T;
	if (clock >= 2)
		UT = T / 2;

	if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
		dev_printk(KERN_ERR, &pdev->dev, "unknown mode %d.\n", speed);
		return;
	}

	if (peer) {
		/* This may be over conservative */
		if (peer->dma_mode) {
			ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
			ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
		}
		ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT);
		ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
	}

	if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
	if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;

	/*
	 *	Now do the setup work
	 */

	/* Configure the address set up timing */
	pci_read_config_byte(pdev, offset + 0x0C, &t);
	t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
	pci_write_config_byte(pdev, offset + 0x0C , t);

	/* Configure the 8bit I/O timing */
	pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
		((clamp_val(at.act8b, 1, 16) - 1) << 4) | (clamp_val(at.rec8b, 1, 16) - 1));

	/* Drive timing */
	pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
		((clamp_val(at.active, 1, 16) - 1) << 4) | (clamp_val(at.recover, 1, 16) - 1));

	switch (clock) {
		case 1:
		t = at.udma ? (0xc0 | (clamp_val(at.udma, 2, 5) - 2)) : 0x03;
		break;

		case 2:
		t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 2, 10)]) : 0x03;
		break;

		case 3:
		t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 10)]) : 0x03;
		break;

		case 4:
		t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 15)]) : 0x03;
		break;

		default:
			return;
	}

	/* UDMA timing */
	if (at.udma)
		pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t);
}

/**
 *	amd_pre_reset		-	perform reset handling
 *	@link: ATA link
 *	@deadline: deadline jiffies for the operation
 *
 *	Reset sequence checking enable bits to see which ports are
 *	active.
 */

static int amd_pre_reset(struct ata_link *link, unsigned long deadline)
{
	static const struct pci_bits amd_enable_bits[] = {
		{ 0x40, 1, 0x02, 0x02 },
		{ 0x40, 1, 0x01, 0x01 }
	};

	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
		return -ENOENT;

	return ata_sff_prereset(link, deadline);
}

static int amd_cable_detect(struct ata_port *ap)
{
	static const u32 bitmask[2] = {0x03, 0x0C};
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 ata66;

	pci_read_config_byte(pdev, 0x42, &ata66);
	if (ata66 & bitmask[ap->port_no])
		return ATA_CBL_PATA80;
	return ATA_CBL_PATA40;
}

/**
 *	amd33_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the AMD registers for PIO mode.
 */

static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
}

static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
}

static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
}

static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
}

/**
 *	amd33_set_dmamode	-	set initial DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the MWDMA/UDMA modes for the AMD and Nvidia
 *	chipset.
 */

static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x40, adev->dma_mode, 1);
}

static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x40, adev->dma_mode, 2);
}

static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x40, adev->dma_mode, 3);
}

static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x40, adev->dma_mode, 4);
}

/* Both host-side and drive-side detection results are worthless on NV
 * PATAs.  Ignore them and just follow what BIOS configured.  Both the
 * current configuration in PCI config reg and ACPI GTM result are
 * cached during driver attach and are consulted to select transfer
 * mode.
 */
static unsigned long nv_mode_filter(struct ata_device *dev,
				    unsigned long xfer_mask)
{
	static const unsigned int udma_mask_map[] =
		{ ATA_UDMA2, ATA_UDMA1, ATA_UDMA0, 0,
		  ATA_UDMA3, ATA_UDMA4, ATA_UDMA5, ATA_UDMA6 };
	struct ata_port *ap = dev->link->ap;
	char acpi_str[32] = "";
	u32 saved_udma, udma;
	const struct ata_acpi_gtm *gtm;
	unsigned long bios_limit = 0, acpi_limit = 0, limit;

	/* find out what BIOS configured */
	udma = saved_udma = (unsigned long)ap->host->private_data;

	if (ap->port_no == 0)
		udma >>= 16;
	if (dev->devno == 0)
		udma >>= 8;

	if ((udma & 0xc0) == 0xc0)
		bios_limit = ata_pack_xfermask(0, 0, udma_mask_map[udma & 0x7]);

	/* consult ACPI GTM too */
	gtm = ata_acpi_init_gtm(ap);
	if (gtm) {
		acpi_limit = ata_acpi_gtm_xfermask(dev, gtm);

		snprintf(acpi_str, sizeof(acpi_str), " (%u:%u:0x%x)",
			 gtm->drive[0].dma, gtm->drive[1].dma, gtm->flags);
	}

	/* be optimistic, EH can take care of things if something goes wrong */
	limit = bios_limit | acpi_limit;

	/* If PIO or DMA isn't configured at all, don't limit.  Let EH
	 * handle it.
	 */
	if (!(limit & ATA_MASK_PIO))
		limit |= ATA_MASK_PIO;
	if (!(limit & (ATA_MASK_MWDMA | ATA_MASK_UDMA)))
		limit |= ATA_MASK_MWDMA | ATA_MASK_UDMA;

	ata_port_printk(ap, KERN_DEBUG, "nv_mode_filter: 0x%lx&0x%lx->0x%lx, "
			"BIOS=0x%lx (0x%x) ACPI=0x%lx%s\n",
			xfer_mask, limit, xfer_mask & limit, bios_limit,
			saved_udma, acpi_limit, acpi_str);

	return xfer_mask & limit;
}

/**
 *	nv_probe_init	-	cable detection
 *	@lin: ATA link
 *
 *	Perform cable detection. The BIOS stores this in PCI config
 *	space for us.
 */

static int nv_pre_reset(struct ata_link *link, unsigned long deadline)
{
	static const struct pci_bits nv_enable_bits[] = {
		{ 0x50, 1, 0x02, 0x02 },
		{ 0x50, 1, 0x01, 0x01 }
	};

	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no]))
		return -ENOENT;

	return ata_sff_prereset(link, deadline);
}

/**
 *	nv100_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the AMD registers for PIO mode.
 */

static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x50, adev->pio_mode, 3);
}

static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x50, adev->pio_mode, 4);
}

/**
 *	nv100_set_dmamode	-	set initial DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the MWDMA/UDMA modes for the AMD and Nvidia
 *	chipset.
 */

static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x50, adev->dma_mode, 3);
}

static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x50, adev->dma_mode, 4);
}

static void nv_host_stop(struct ata_host *host)
{
	u32 udma = (unsigned long)host->private_data;

	/* restore PCI config register 0x60 */
	pci_write_config_dword(to_pci_dev(host->dev), 0x60, udma);
}

static struct scsi_host_template amd_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static const struct ata_port_operations amd_base_port_ops = {
	.inherits	= &ata_bmdma32_port_ops,
	.prereset	= amd_pre_reset,
};

static struct ata_port_operations amd33_port_ops = {
	.inherits	= &amd_base_port_ops,
	.cable_detect	= ata_cable_40wire,
	.set_piomode	= amd33_set_piomode,
	.set_dmamode	= amd33_set_dmamode,
};

static struct ata_port_operations amd66_port_ops = {
	.inherits	= &amd_base_port_ops,
	.cable_detect	= ata_cable_unknown,
	.set_piomode	= amd66_set_piomode,
	.set_dmamode	= amd66_set_dmamode,
};

static struct ata_port_operations amd100_port_ops = {
	.inherits	= &amd_base_port_ops,
	.cable_detect	= ata_cable_unknown,
	.set_piomode	= amd100_set_piomode,
	.set_dmamode	= amd100_set_dmamode,
};

static struct ata_port_operations amd133_port_ops = {
	.inherits	= &amd_base_port_ops,
	.cable_detect	= amd_cable_detect,
	.set_piomode	= amd133_set_piomode,
	.set_dmamode	= amd133_set_dmamode,
};

static const struct ata_port_operations nv_base_port_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.cable_detect	= ata_cable_ignore,
	.mode_filter	= nv_mode_filter,
	.prereset	= nv_pre_reset,
	.host_stop	= nv_host_stop,
};

static struct ata_port_operations nv100_port_ops = {
	.inherits	= &nv_base_port_ops,
	.set_piomode	= nv100_set_piomode,
	.set_dmamode	= nv100_set_dmamode,
};

static struct ata_port_operations nv133_port_ops = {
	.inherits	= &nv_base_port_ops,
	.set_piomode	= nv133_set_piomode,
	.set_dmamode	= nv133_set_dmamode,
};

static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const struct ata_port_info info[10] = {
		{	/* 0: AMD 7401 */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,	/* No SWDMA */
			.udma_mask = 0x07,	/* UDMA 33 */
			.port_ops = &amd33_port_ops
		},
		{	/* 1: Early AMD7409 - no swdma */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA4,	/* UDMA 66 */
			.port_ops = &amd66_port_ops
		},
		{	/* 2: AMD 7409, no swdma errata */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA4,	/* UDMA 66 */
			.port_ops = &amd66_port_ops
		},
		{	/* 3: AMD 7411 */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA5,	/* UDMA 100 */
			.port_ops = &amd100_port_ops
		},
		{	/* 4: AMD 7441 */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA5,	/* UDMA 100 */
			.port_ops = &amd100_port_ops
		},
		{	/* 5: AMD 8111*/
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA6,	/* UDMA 133, no swdma */
			.port_ops = &amd133_port_ops
		},
		{	/* 6: AMD 8111 UDMA 100 (Serenade) */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA5,	/* UDMA 100, no swdma */
			.port_ops = &amd133_port_ops
		},
		{	/* 7: Nvidia Nforce */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA5,	/* UDMA 100 */
			.port_ops = &nv100_port_ops
		},
		{	/* 8: Nvidia Nforce2 and later */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA6,	/* UDMA 133, no swdma */
			.port_ops = &nv133_port_ops
		},
		{	/* 9: AMD CS5536 (Geode companion) */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA5,	/* UDMA 100 */
			.port_ops = &amd100_port_ops
		}
	};
	const struct ata_port_info *ppi[] = { NULL, NULL };
	static int printed_version;
	int type = id->driver_data;
	void *hpriv = NULL;
	u8 fifo;
	int rc;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	pci_read_config_byte(pdev, 0x41, &fifo);

	/* Check for AMD7409 without swdma errata and if found adjust type */
	if (type == 1 && pdev->revision > 0x7)
		type = 2;

	/* Serenade ? */
	if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
			 pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
		type = 6;	/* UDMA 100 only */

	/*
	 * Okay, type is determined now.  Apply type-specific workarounds.
	 */
	ppi[0] = &info[type];

	if (type < 3)
		ata_pci_bmdma_clear_simplex(pdev);

	/* Check for AMD7411 */
	if (type == 3)
		/* FIFO is broken */
		pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
	else
		pci_write_config_byte(pdev, 0x41, fifo | 0xF0);

	/* Cable detection on Nvidia chips doesn't work too well,
	 * cache BIOS programmed UDMA mode.
	 */
	if (type == 7 || type == 8) {
		u32 udma;

		pci_read_config_dword(pdev, 0x60, &udma);
		hpriv = (void *)(unsigned long)udma;
	}

	/* And fire it up */
	return ata_pci_sff_init_one(pdev, ppi, &amd_sht, hpriv);
}

#ifdef CONFIG_PM
static int amd_reinit_one(struct pci_dev *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	int rc;

	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;

	if (pdev->vendor == PCI_VENDOR_ID_AMD) {
		u8 fifo;
		pci_read_config_byte(pdev, 0x41, &fifo);
		if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411)
			/* FIFO is broken */
			pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
		else
			pci_write_config_byte(pdev, 0x41, fifo | 0xF0);
		if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 ||
		    pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
			ata_pci_bmdma_clear_simplex(pdev);
	}

	ata_host_resume(host);
	return 0;
}
#endif

static const struct pci_device_id amd[] = {
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_COBRA_7401),		0 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_VIPER_7409),		1 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_VIPER_7411),		3 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_OPUS_7441),		4 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_8111_IDE),		5 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_IDE),	7 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE),	8 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_CS5536_IDE),		9 },

	{ },
};

static struct pci_driver amd_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= amd,
	.probe 		= amd_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= amd_reinit_one,
#endif
};

static int __init amd_init(void)
{
	return pci_register_driver(&amd_pci_driver);
}

static void __exit amd_exit(void)
{
	pci_unregister_driver(&amd_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for AMD and Nvidia PATA IDE");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, amd);
MODULE_VERSION(DRV_VERSION);

module_init(amd_init);
module_exit(amd_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_amd.c - AMD PATA for new ATA layer
	3	* (C) 2005-2006 Red Hat Inc
669a5db4 JG	4	*
	5	* Based on pata-sil680. Errata information is taken from data sheets
	6	* and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
	7	* claimed by sata-nv.c.
	8	*
	9	* TODO:
	10	* Variable system clock when/if it makes sense
	11	* Power management on ports
	12	*
	13	*
	14	* Documentation publically available.
	15	*/
	16
	17	#include <linux/kernel.h>
	18	#include <linux/module.h>
	19	#include <linux/pci.h>
	20	#include <linux/init.h>
	21	#include <linux/blkdev.h>
	22	#include <linux/delay.h>
	23	#include <scsi/scsi_host.h>
	24	#include <linux/libata.h>
	25
	26	#define DRV_NAME "pata_amd"
871af121	27	#define DRV_VERSION "0.3.11"
669a5db4 JG	28
	29	/**
	30	* timing_setup - shared timing computation and load
	31	* @ap: ATA port being set up
	32	* @adev: drive being configured
	33	* @offset: port offset
	34	* @speed: target speed
	35	* @clock: clock multiplier (number of times 33MHz for this part)
	36	*
	37	* Perform the actual timing set up for Nvidia or AMD PATA devices.
	38	* The actual devices vary so they all call into this helper function
	39	* providing the clock multipler and offset (because AMD and Nvidia put
	40	* the ports at different locations).
	41	*/
	42
	43	static void timing_setup(struct ata_port ap, struct ata_device adev, int offset, int speed, int clock)
	44	{
	45	static const unsigned char amd_cyc2udma[] = {
	46	6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
	47	};
	48
	49	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	50	struct ata_device *peer = ata_dev_pair(adev);
	51	int dn = ap->port_no * 2 + adev->devno;
	52	struct ata_timing at, apeer;
	53	int T, UT;
	54	const int amd_clock = 33333; /* KHz. */
	55	u8 t;
	56
	57	T = 1000000000 / amd_clock;
d9c74fbe HH	58	UT = T;
	59	if (clock >= 2)
	60	UT = T / 2;
669a5db4 JG	61
	62	if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
	63	dev_printk(KERN_ERR, &pdev->dev, "unknown mode %d.\n", speed);
	64	return;
	65	}
	66
	67	if (peer) {
	68	/* This may be over conservative */
	69	if (peer->dma_mode) {
	70	ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
	71	ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
	72	}
	73	ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT);
	74	ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
	75	}
	76
	77	if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
	78	if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;
	79
	80	/*
	81	* Now do the setup work
	82	*/
	83
	84	/* Configure the address set up timing */
	85	pci_read_config_byte(pdev, offset + 0x0C, &t);
07633b5d	86	t = (t & ~(3 << ((3 - dn) << 1))) \| ((clamp_val(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
669a5db4 JG	87	pci_write_config_byte(pdev, offset + 0x0C , t);
	88
	89	/* Configure the 8bit I/O timing */
	90	pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
07633b5d	91	((clamp_val(at.act8b, 1, 16) - 1) << 4) \| (clamp_val(at.rec8b, 1, 16) - 1));
669a5db4 JG	92
	93	/* Drive timing */
	94	pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
07633b5d	95	((clamp_val(at.active, 1, 16) - 1) << 4) \| (clamp_val(at.recover, 1, 16) - 1));
669a5db4 JG	96
	97	switch (clock) {
	98	case 1:
07633b5d	99	t = at.udma ? (0xc0 \| (clamp_val(at.udma, 2, 5) - 2)) : 0x03;
669a5db4 JG	100	break;
	101
	102	case 2:
07633b5d	103	t = at.udma ? (0xc0 \| amd_cyc2udma[clamp_val(at.udma, 2, 10)]) : 0x03;
669a5db4 JG	104	break;
	105
	106	case 3:
07633b5d	107	t = at.udma ? (0xc0 \| amd_cyc2udma[clamp_val(at.udma, 1, 10)]) : 0x03;
669a5db4 JG	108	break;
	109
	110	case 4:
07633b5d	111	t = at.udma ? (0xc0 \| amd_cyc2udma[clamp_val(at.udma, 1, 15)]) : 0x03;
669a5db4 JG	112	break;
	113
	114	default:
	115	return;
	116	}
	117
	118	/* UDMA timing */
943547ab BZ	119	if (at.udma)
943547ab BZ	120	pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t);
669a5db4 JG	121	}
	122
	123	/**
cc0680a5 TH	124	* amd_pre_reset - perform reset handling
cc0680a5 TH	125	* @link: ATA link
d4b2bab4	126	* @deadline: deadline jiffies for the operation
669a5db4	127	*
eb4a2c7f AC	128	* Reset sequence checking enable bits to see which ports are
eb4a2c7f AC	129	* active.
669a5db4 JG	130	*/
669a5db4 JG	131
cc0680a5	132	static int amd_pre_reset(struct ata_link *link, unsigned long deadline)
669a5db4	133	{
669a5db4 JG	134	static const struct pci_bits amd_enable_bits[] = {
	135	{ 0x40, 1, 0x02, 0x02 },
	136	{ 0x40, 1, 0x01, 0x01 }
	137	};
	138
cc0680a5	139	struct ata_port *ap = link->ap;
669a5db4	140	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
85cd7251	141
c961922b AC	142	if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
c961922b AC	143	return -ENOENT;
669a5db4	144
9363c382	145	return ata_sff_prereset(link, deadline);
669a5db4 JG	146	}
669a5db4 JG	147
eb4a2c7f	148	static int amd_cable_detect(struct ata_port *ap)
669a5db4	149	{
eb4a2c7f	150	static const u32 bitmask[2] = {0x03, 0x0C};
669a5db4	151	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
eb4a2c7f	152	u8 ata66;
669a5db4	153
eb4a2c7f AC	154	pci_read_config_byte(pdev, 0x42, &ata66);
	155	if (ata66 & bitmask[ap->port_no])
	156	return ATA_CBL_PATA80;
	157	return ATA_CBL_PATA40;
669a5db4 JG	158	}
	159
	160	/**
	161	* amd33_set_piomode - set initial PIO mode data
	162	* @ap: ATA interface
	163	* @adev: ATA device
	164	*
	165	* Program the AMD registers for PIO mode.
	166	*/
	167
	168	static void amd33_set_piomode(struct ata_port ap, struct ata_device adev)
	169	{
	170	timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
	171	}
	172
	173	static void amd66_set_piomode(struct ata_port ap, struct ata_device adev)
	174	{
	175	timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
	176	}
	177
	178	static void amd100_set_piomode(struct ata_port ap, struct ata_device adev)
	179	{
	180	timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
	181	}
	182
	183	static void amd133_set_piomode(struct ata_port ap, struct ata_device adev)
	184	{
	185	timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
	186	}
	187
	188	/**
	189	* amd33_set_dmamode - set initial DMA mode data
	190	* @ap: ATA interface
	191	* @adev: ATA device
	192	*
	193	* Program the MWDMA/UDMA modes for the AMD and Nvidia
	194	* chipset.
	195	*/
	196
	197	static void amd33_set_dmamode(struct ata_port ap, struct ata_device adev)
	198	{
	199	timing_setup(ap, adev, 0x40, adev->dma_mode, 1);
	200	}
	201
	202	static void amd66_set_dmamode(struct ata_port ap, struct ata_device adev)
	203	{
	204	timing_setup(ap, adev, 0x40, adev->dma_mode, 2);
	205	}
	206
	207	static void amd100_set_dmamode(struct ata_port ap, struct ata_device adev)
	208	{
	209	timing_setup(ap, adev, 0x40, adev->dma_mode, 3);
	210	}
	211
	212	static void amd133_set_dmamode(struct ata_port ap, struct ata_device adev)
	213	{
	214	timing_setup(ap, adev, 0x40, adev->dma_mode, 4);
	215	}
	216
ce54d161 TH	217	/* Both host-side and drive-side detection results are worthless on NV
	218	* PATAs. Ignore them and just follow what BIOS configured. Both the
	219	* current configuration in PCI config reg and ACPI GTM result are
	220	* cached during driver attach and are consulted to select transfer
	221	* mode.
	222	*/
	223	static unsigned long nv_mode_filter(struct ata_device *dev,
	224	unsigned long xfer_mask)
	225	{
	226	static const unsigned int udma_mask_map[] =
	227	{ ATA_UDMA2, ATA_UDMA1, ATA_UDMA0, 0,
	228	ATA_UDMA3, ATA_UDMA4, ATA_UDMA5, ATA_UDMA6 };
	229	struct ata_port *ap = dev->link->ap;
	230	char acpi_str[32] = "";
	231	u32 saved_udma, udma;
	232	const struct ata_acpi_gtm *gtm;
	233	unsigned long bios_limit = 0, acpi_limit = 0, limit;
	234
	235	/* find out what BIOS configured */
	236	udma = saved_udma = (unsigned long)ap->host->private_data;
	237
	238	if (ap->port_no == 0)
	239	udma >>= 16;
	240	if (dev->devno == 0)
	241	udma >>= 8;
	242
	243	if ((udma & 0xc0) == 0xc0)
	244	bios_limit = ata_pack_xfermask(0, 0, udma_mask_map[udma & 0x7]);
	245
	246	/* consult ACPI GTM too */
	247	gtm = ata_acpi_init_gtm(ap);
	248	if (gtm) {
	249	acpi_limit = ata_acpi_gtm_xfermask(dev, gtm);
	250
	251	snprintf(acpi_str, sizeof(acpi_str), " (%u:%u:0x%x)",
	252	gtm->drive[0].dma, gtm->drive[1].dma, gtm->flags);
	253	}
	254
	255	/* be optimistic, EH can take care of things if something goes wrong */
	256	limit = bios_limit \| acpi_limit;
	257
	258	/* If PIO or DMA isn't configured at all, don't limit. Let EH
	259	* handle it.
	260	*/
	261	if (!(limit & ATA_MASK_PIO))
	262	limit \|= ATA_MASK_PIO;
	263	if (!(limit & (ATA_MASK_MWDMA \| ATA_MASK_UDMA)))
	264	limit \|= ATA_MASK_MWDMA \| ATA_MASK_UDMA;
	265
	266	ata_port_printk(ap, KERN_DEBUG, "nv_mode_filter: 0x%lx&0x%lx->0x%lx, "
	267	"BIOS=0x%lx (0x%x) ACPI=0x%lx%s\n",
	268	xfer_mask, limit, xfer_mask & limit, bios_limit,
	269	saved_udma, acpi_limit, acpi_str);
	270
	271	return xfer_mask & limit;
	272	}
669a5db4 JG	273
	274	/**
	275	* nv_probe_init - cable detection
cc0680a5	276	* @lin: ATA link
669a5db4 JG	277	*
	278	* Perform cable detection. The BIOS stores this in PCI config
	279	* space for us.
	280	*/
	281
cc0680a5	282	static int nv_pre_reset(struct ata_link *link, unsigned long deadline)
d4b2bab4	283	{
76ff3c6e AC	284	static const struct pci_bits nv_enable_bits[] = {
	285	{ 0x50, 1, 0x02, 0x02 },
	286	{ 0x50, 1, 0x01, 0x01 }
	287	};
669a5db4	288
cc0680a5	289	struct ata_port *ap = link->ap;
669a5db4	290	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
669a5db4	291
c961922b AC	292	if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no]))
c961922b AC	293	return -ENOENT;
76ff3c6e	294
9363c382	295	return ata_sff_prereset(link, deadline);
669a5db4 JG	296	}
669a5db4 JG	297
669a5db4 JG	298	/**
	299	* nv100_set_piomode - set initial PIO mode data
	300	* @ap: ATA interface
	301	* @adev: ATA device
	302	*
	303	* Program the AMD registers for PIO mode.
	304	*/
	305
	306	static void nv100_set_piomode(struct ata_port ap, struct ata_device adev)
	307	{
	308	timing_setup(ap, adev, 0x50, adev->pio_mode, 3);
	309	}
	310
	311	static void nv133_set_piomode(struct ata_port ap, struct ata_device adev)
	312	{
	313	timing_setup(ap, adev, 0x50, adev->pio_mode, 4);
	314	}
	315
	316	/**
	317	* nv100_set_dmamode - set initial DMA mode data
	318	* @ap: ATA interface
	319	* @adev: ATA device
	320	*
	321	* Program the MWDMA/UDMA modes for the AMD and Nvidia
	322	* chipset.
	323	*/
	324
	325	static void nv100_set_dmamode(struct ata_port ap, struct ata_device adev)
	326	{
	327	timing_setup(ap, adev, 0x50, adev->dma_mode, 3);
	328	}
	329
	330	static void nv133_set_dmamode(struct ata_port ap, struct ata_device adev)
	331	{
	332	timing_setup(ap, adev, 0x50, adev->dma_mode, 4);
	333	}
	334
ce54d161 TH	335	static void nv_host_stop(struct ata_host *host)
	336	{
	337	u32 udma = (unsigned long)host->private_data;
	338
	339	/* restore PCI config register 0x60 */
	340	pci_write_config_dword(to_pci_dev(host->dev), 0x60, udma);
	341	}
	342
669a5db4	343	static struct scsi_host_template amd_sht = {
68d1d07b	344	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	345	};
669a5db4 JG	346
029cfd6b	347	static const struct ata_port_operations amd_base_port_ops = {
871af121	348	.inherits = &ata_bmdma32_port_ops,
887125e3	349	.prereset = amd_pre_reset,
029cfd6b TH	350	};
029cfd6b TH	351
669a5db4	352	static struct ata_port_operations amd33_port_ops = {
029cfd6b TH	353	.inherits = &amd_base_port_ops,
029cfd6b TH	354	.cable_detect = ata_cable_40wire,
669a5db4 JG	355	.set_piomode = amd33_set_piomode,
669a5db4 JG	356	.set_dmamode = amd33_set_dmamode,
669a5db4 JG	357	};
	358
	359	static struct ata_port_operations amd66_port_ops = {
029cfd6b TH	360	.inherits = &amd_base_port_ops,
029cfd6b TH	361	.cable_detect = ata_cable_unknown,
669a5db4 JG	362	.set_piomode = amd66_set_piomode,
669a5db4 JG	363	.set_dmamode = amd66_set_dmamode,
669a5db4 JG	364	};
	365
	366	static struct ata_port_operations amd100_port_ops = {
029cfd6b TH	367	.inherits = &amd_base_port_ops,
029cfd6b TH	368	.cable_detect = ata_cable_unknown,
669a5db4 JG	369	.set_piomode = amd100_set_piomode,
669a5db4 JG	370	.set_dmamode = amd100_set_dmamode,
669a5db4 JG	371	};
	372
	373	static struct ata_port_operations amd133_port_ops = {
029cfd6b TH	374	.inherits = &amd_base_port_ops,
029cfd6b TH	375	.cable_detect = amd_cable_detect,
669a5db4 JG	376	.set_piomode = amd133_set_piomode,
669a5db4 JG	377	.set_dmamode = amd133_set_dmamode,
029cfd6b	378	};
669a5db4	379
029cfd6b TH	380	static const struct ata_port_operations nv_base_port_ops = {
	381	.inherits = &ata_bmdma_port_ops,
	382	.cable_detect = ata_cable_ignore,
	383	.mode_filter = nv_mode_filter,
887125e3	384	.prereset = nv_pre_reset,
029cfd6b	385	.host_stop = nv_host_stop,
669a5db4 JG	386	};
	387
	388	static struct ata_port_operations nv100_port_ops = {
029cfd6b	389	.inherits = &nv_base_port_ops,
669a5db4 JG	390	.set_piomode = nv100_set_piomode,
669a5db4 JG	391	.set_dmamode = nv100_set_dmamode,
669a5db4 JG	392	};
	393
	394	static struct ata_port_operations nv133_port_ops = {
029cfd6b	395	.inherits = &nv_base_port_ops,
669a5db4 JG	396	.set_piomode = nv133_set_piomode,
669a5db4 JG	397	.set_dmamode = nv133_set_dmamode,
669a5db4 JG	398	};
	399
	400	static int amd_init_one(struct pci_dev pdev, const struct pci_device_id id)
	401	{
1626aeb8	402	static const struct ata_port_info info[10] = {
669a5db4	403	{ /* 0: AMD 7401 */
1d2808fd	404	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	405	.pio_mask = 0x1f,
	406	.mwdma_mask = 0x07, /* No SWDMA */
	407	.udma_mask = 0x07, /* UDMA 33 */
	408	.port_ops = &amd33_port_ops
	409	},
	410	{ /* 1: Early AMD7409 - no swdma */
1d2808fd	411	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	412	.pio_mask = 0x1f,
669a5db4 JG	413	.mwdma_mask = 0x07,
bf6263a8	414	.udma_mask = ATA_UDMA4, /* UDMA 66 */
669a5db4 JG	415	.port_ops = &amd66_port_ops
	416	},
	417	{ /* 2: AMD 7409, no swdma errata */
1d2808fd	418	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	419	.pio_mask = 0x1f,
669a5db4 JG	420	.mwdma_mask = 0x07,
bf6263a8	421	.udma_mask = ATA_UDMA4, /* UDMA 66 */
669a5db4 JG	422	.port_ops = &amd66_port_ops
	423	},
	424	{ /* 3: AMD 7411 */
1d2808fd	425	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	426	.pio_mask = 0x1f,
669a5db4 JG	427	.mwdma_mask = 0x07,
bf6263a8	428	.udma_mask = ATA_UDMA5, /* UDMA 100 */
669a5db4 JG	429	.port_ops = &amd100_port_ops
	430	},
	431	{ /* 4: AMD 7441 */
1d2808fd	432	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	433	.pio_mask = 0x1f,
669a5db4 JG	434	.mwdma_mask = 0x07,
bf6263a8	435	.udma_mask = ATA_UDMA5, /* UDMA 100 */
669a5db4 JG	436	.port_ops = &amd100_port_ops
	437	},
	438	{ /* 5: AMD 8111*/
1d2808fd	439	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	440	.pio_mask = 0x1f,
669a5db4 JG	441	.mwdma_mask = 0x07,
bf6263a8	442	.udma_mask = ATA_UDMA6, /* UDMA 133, no swdma */
669a5db4 JG	443	.port_ops = &amd133_port_ops
	444	},
	445	{ /* 6: AMD 8111 UDMA 100 (Serenade) */
1d2808fd	446	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	447	.pio_mask = 0x1f,
669a5db4 JG	448	.mwdma_mask = 0x07,
bf6263a8	449	.udma_mask = ATA_UDMA5, /* UDMA 100, no swdma */
669a5db4 JG	450	.port_ops = &amd133_port_ops
	451	},
	452	{ /* 7: Nvidia Nforce */
1d2808fd	453	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	454	.pio_mask = 0x1f,
669a5db4 JG	455	.mwdma_mask = 0x07,
bf6263a8	456	.udma_mask = ATA_UDMA5, /* UDMA 100 */
669a5db4 JG	457	.port_ops = &nv100_port_ops
	458	},
	459	{ /* 8: Nvidia Nforce2 and later */
1d2808fd	460	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	461	.pio_mask = 0x1f,
669a5db4 JG	462	.mwdma_mask = 0x07,
bf6263a8	463	.udma_mask = ATA_UDMA6, /* UDMA 133, no swdma */
669a5db4 JG	464	.port_ops = &nv133_port_ops
	465	},
	466	{ /* 9: AMD CS5536 (Geode companion) */
1d2808fd	467	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	468	.pio_mask = 0x1f,
669a5db4 JG	469	.mwdma_mask = 0x07,
bf6263a8	470	.udma_mask = ATA_UDMA5, /* UDMA 100 */
669a5db4 JG	471	.port_ops = &amd100_port_ops
	472	}
	473	};
887125e3	474	const struct ata_port_info *ppi[] = { NULL, NULL };
669a5db4 JG	475	static int printed_version;
669a5db4 JG	476	int type = id->driver_data;
887125e3	477	void *hpriv = NULL;
669a5db4	478	u8 fifo;
f08048e9	479	int rc;
669a5db4 JG	480
	481	if (!printed_version++)
	482	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
	483
f08048e9 TH	484	rc = pcim_enable_device(pdev);
	485	if (rc)
	486	return rc;
	487
669a5db4 JG	488	pci_read_config_byte(pdev, 0x41, &fifo);
	489
	490	/* Check for AMD7409 without swdma errata and if found adjust type */
44c10138	491	if (type == 1 && pdev->revision > 0x7)
669a5db4 JG	492	type = 2;
669a5db4 JG	493
ce54d161 TH	494	/* Serenade ? */
	495	if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
	496	pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
	497	type = 6; /* UDMA 100 only */
	498
	499	/*
	500	* Okay, type is determined now. Apply type-specific workarounds.
	501	*/
887125e3	502	ppi[0] = &info[type];
ce54d161 TH	503
ce54d161 TH	504	if (type < 3)
9363c382	505	ata_pci_bmdma_clear_simplex(pdev);
ce54d161	506
669a5db4 JG	507	/* Check for AMD7411 */
	508	if (type == 3)
	509	/* FIFO is broken */
	510	pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
	511	else
	512	pci_write_config_byte(pdev, 0x41, fifo \| 0xF0);
	513
ce54d161 TH	514	/* Cable detection on Nvidia chips doesn't work too well,
	515	* cache BIOS programmed UDMA mode.
	516	*/
	517	if (type == 7 \|\| type == 8) {
	518	u32 udma;
669a5db4	519
ce54d161	520	pci_read_config_dword(pdev, 0x60, &udma);
887125e3	521	hpriv = (void *)(unsigned long)udma;
ce54d161	522	}
669a5db4 JG	523
669a5db4 JG	524	/* And fire it up */
9363c382	525	return ata_pci_sff_init_one(pdev, ppi, &amd_sht, hpriv);
669a5db4 JG	526	}
669a5db4 JG	527
438ac6d5	528	#ifdef CONFIG_PM
c304193a A	529	static int amd_reinit_one(struct pci_dev *pdev)
c304193a A	530	{
f08048e9 TH	531	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	532	int rc;
	533
	534	rc = ata_pci_device_do_resume(pdev);
	535	if (rc)
	536	return rc;
	537
c304193a A	538	if (pdev->vendor == PCI_VENDOR_ID_AMD) {
	539	u8 fifo;
	540	pci_read_config_byte(pdev, 0x41, &fifo);
	541	if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411)
	542	/* FIFO is broken */
	543	pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
	544	else
	545	pci_write_config_byte(pdev, 0x41, fifo \| 0xF0);
	546	if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 \|\|
	547	pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
9363c382	548	ata_pci_bmdma_clear_simplex(pdev);
c304193a	549	}
f08048e9 TH	550
	551	ata_host_resume(host);
	552	return 0;
c304193a	553	}
438ac6d5	554	#endif
c304193a	555
669a5db4	556	static const struct pci_device_id amd[] = {
2d2744fc JG	557	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
	558	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
	559	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 3 },
	560	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 4 },
	561	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 5 },
	562	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 7 },
	563	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 8 },
	564	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 8 },
	565	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 8 },
	566	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 8 },
	567	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 8 },
	568	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 8 },
	569	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 8 },
	570	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 8 },
	571	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 8 },
05e2867a PC	572	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 8 },
05e2867a PC	573	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 8 },
9f789755 PC	574	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 8 },
9f789755 PC	575	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 8 },
2d2744fc JG	576	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 9 },
	577
	578	{ },
669a5db4 JG	579	};
	580
	581	static struct pci_driver amd_pci_driver = {
2d2744fc	582	.name = DRV_NAME,
669a5db4 JG	583	.id_table = amd,
669a5db4 JG	584	.probe = amd_init_one,
c304193a	585	.remove = ata_pci_remove_one,
438ac6d5	586	#ifdef CONFIG_PM
c304193a A	587	.suspend = ata_pci_device_suspend,
c304193a A	588	.resume = amd_reinit_one,
438ac6d5	589	#endif
669a5db4 JG	590	};
	591
	592	static int __init amd_init(void)
	593	{
	594	return pci_register_driver(&amd_pci_driver);
	595	}
	596
	597	static void __exit amd_exit(void)
	598	{
	599	pci_unregister_driver(&amd_pci_driver);
	600	}
	601
669a5db4	602	MODULE_AUTHOR("Alan Cox");
c9544bcb	603	MODULE_DESCRIPTION("low-level driver for AMD and Nvidia PATA IDE");
669a5db4 JG	604	MODULE_LICENSE("GPL");
	605	MODULE_DEVICE_TABLE(pci, amd);
	606	MODULE_VERSION(DRV_VERSION);
	607
	608	module_init(amd_init);
	609	module_exit(amd_exit);