libata-sff: use WARN instead of BUG on illegal host state machine state
[linux-2.6-block.git] / drivers / ata / libata-sff.c
CommitLineData
1fdffbce 1/*
f3a03b09 2 * libata-sff.c - helper library for PCI IDE BMDMA
1fdffbce 3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <tj@kernel.org>
1fdffbce
JG
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2006 Jeff Garzik
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
32 *
33 */
34
1fdffbce 35#include <linux/kernel.h>
5a0e3ad6 36#include <linux/gfp.h>
1fdffbce 37#include <linux/pci.h>
bff7832d 38#include <linux/module.h>
1fdffbce 39#include <linux/libata.h>
624d5c51 40#include <linux/highmem.h>
1fdffbce
JG
41
42#include "libata.h"
43
c429137a
TH
44static struct workqueue_struct *ata_sff_wq;
45
624d5c51
TH
46const struct ata_port_operations ata_sff_port_ops = {
47 .inherits = &ata_base_port_ops,
48
f47451c4 49 .qc_prep = ata_noop_qc_prep,
9363c382 50 .qc_issue = ata_sff_qc_issue,
4c9bf4e7 51 .qc_fill_rtf = ata_sff_qc_fill_rtf,
9363c382
TH
52
53 .freeze = ata_sff_freeze,
54 .thaw = ata_sff_thaw,
0aa1113d 55 .prereset = ata_sff_prereset,
9363c382 56 .softreset = ata_sff_softreset,
57c9efdf 57 .hardreset = sata_sff_hardreset,
203c75b8 58 .postreset = ata_sff_postreset,
9363c382 59 .error_handler = ata_sff_error_handler,
9363c382 60
5682ed33
TH
61 .sff_dev_select = ata_sff_dev_select,
62 .sff_check_status = ata_sff_check_status,
63 .sff_tf_load = ata_sff_tf_load,
64 .sff_tf_read = ata_sff_tf_read,
65 .sff_exec_command = ata_sff_exec_command,
66 .sff_data_xfer = ata_sff_data_xfer,
8244cd05 67 .sff_drain_fifo = ata_sff_drain_fifo,
624d5c51 68
c96f1732 69 .lost_interrupt = ata_sff_lost_interrupt,
624d5c51 70};
0fe40ff8 71EXPORT_SYMBOL_GPL(ata_sff_port_ops);
624d5c51 72
272f7884 73/**
9363c382 74 * ata_sff_check_status - Read device status reg & clear interrupt
272f7884
TH
75 * @ap: port where the device is
76 *
77 * Reads ATA taskfile status register for currently-selected device
78 * and return its value. This also clears pending interrupts
79 * from this device
80 *
81 * LOCKING:
82 * Inherited from caller.
83 */
9363c382 84u8 ata_sff_check_status(struct ata_port *ap)
272f7884
TH
85{
86 return ioread8(ap->ioaddr.status_addr);
87}
0fe40ff8 88EXPORT_SYMBOL_GPL(ata_sff_check_status);
272f7884
TH
89
90/**
9363c382 91 * ata_sff_altstatus - Read device alternate status reg
272f7884
TH
92 * @ap: port where the device is
93 *
94 * Reads ATA taskfile alternate status register for
95 * currently-selected device and return its value.
96 *
97 * Note: may NOT be used as the check_altstatus() entry in
98 * ata_port_operations.
99 *
100 * LOCKING:
101 * Inherited from caller.
102 */
a57c1bad 103static u8 ata_sff_altstatus(struct ata_port *ap)
624d5c51 104{
5682ed33
TH
105 if (ap->ops->sff_check_altstatus)
106 return ap->ops->sff_check_altstatus(ap);
624d5c51
TH
107
108 return ioread8(ap->ioaddr.altstatus_addr);
109}
110
a57c1bad
AC
111/**
112 * ata_sff_irq_status - Check if the device is busy
113 * @ap: port where the device is
114 *
115 * Determine if the port is currently busy. Uses altstatus
116 * if available in order to avoid clearing shared IRQ status
117 * when finding an IRQ source. Non ctl capable devices don't
118 * share interrupt lines fortunately for us.
119 *
120 * LOCKING:
121 * Inherited from caller.
122 */
123static u8 ata_sff_irq_status(struct ata_port *ap)
124{
125 u8 status;
126
127 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
128 status = ata_sff_altstatus(ap);
129 /* Not us: We are busy */
130 if (status & ATA_BUSY)
0fe40ff8 131 return status;
a57c1bad
AC
132 }
133 /* Clear INTRQ latch */
6311c90a 134 status = ap->ops->sff_check_status(ap);
a57c1bad
AC
135 return status;
136}
137
138/**
139 * ata_sff_sync - Flush writes
140 * @ap: Port to wait for.
141 *
142 * CAUTION:
143 * If we have an mmio device with no ctl and no altstatus
144 * method this will fail. No such devices are known to exist.
145 *
146 * LOCKING:
147 * Inherited from caller.
148 */
149
150static void ata_sff_sync(struct ata_port *ap)
151{
152 if (ap->ops->sff_check_altstatus)
153 ap->ops->sff_check_altstatus(ap);
154 else if (ap->ioaddr.altstatus_addr)
155 ioread8(ap->ioaddr.altstatus_addr);
156}
157
158/**
159 * ata_sff_pause - Flush writes and wait 400nS
160 * @ap: Port to pause for.
161 *
162 * CAUTION:
163 * If we have an mmio device with no ctl and no altstatus
164 * method this will fail. No such devices are known to exist.
165 *
166 * LOCKING:
167 * Inherited from caller.
168 */
169
170void ata_sff_pause(struct ata_port *ap)
171{
172 ata_sff_sync(ap);
173 ndelay(400);
174}
0fe40ff8 175EXPORT_SYMBOL_GPL(ata_sff_pause);
a57c1bad
AC
176
177/**
178 * ata_sff_dma_pause - Pause before commencing DMA
179 * @ap: Port to pause for.
180 *
181 * Perform I/O fencing and ensure sufficient cycle delays occur
182 * for the HDMA1:0 transition
183 */
0fe40ff8 184
a57c1bad
AC
185void ata_sff_dma_pause(struct ata_port *ap)
186{
187 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
188 /* An altstatus read will cause the needed delay without
189 messing up the IRQ status */
190 ata_sff_altstatus(ap);
191 return;
192 }
193 /* There are no DMA controllers without ctl. BUG here to ensure
194 we never violate the HDMA1:0 transition timing and risk
195 corruption. */
196 BUG();
197}
0fe40ff8 198EXPORT_SYMBOL_GPL(ata_sff_dma_pause);
a57c1bad 199
624d5c51 200/**
9363c382 201 * ata_sff_busy_sleep - sleep until BSY clears, or timeout
624d5c51 202 * @ap: port containing status register to be polled
341c2c95
TH
203 * @tmout_pat: impatience timeout in msecs
204 * @tmout: overall timeout in msecs
624d5c51
TH
205 *
206 * Sleep until ATA Status register bit BSY clears,
207 * or a timeout occurs.
208 *
209 * LOCKING:
210 * Kernel thread context (may sleep).
211 *
212 * RETURNS:
213 * 0 on success, -errno otherwise.
214 */
9363c382
TH
215int ata_sff_busy_sleep(struct ata_port *ap,
216 unsigned long tmout_pat, unsigned long tmout)
624d5c51
TH
217{
218 unsigned long timer_start, timeout;
219 u8 status;
220
9363c382 221 status = ata_sff_busy_wait(ap, ATA_BUSY, 300);
624d5c51 222 timer_start = jiffies;
341c2c95 223 timeout = ata_deadline(timer_start, tmout_pat);
624d5c51
TH
224 while (status != 0xff && (status & ATA_BUSY) &&
225 time_before(jiffies, timeout)) {
97750ceb 226 ata_msleep(ap, 50);
9363c382 227 status = ata_sff_busy_wait(ap, ATA_BUSY, 3);
624d5c51
TH
228 }
229
230 if (status != 0xff && (status & ATA_BUSY))
a9a79dfe
JP
231 ata_port_warn(ap,
232 "port is slow to respond, please be patient (Status 0x%x)\n",
233 status);
624d5c51 234
341c2c95 235 timeout = ata_deadline(timer_start, tmout);
624d5c51
TH
236 while (status != 0xff && (status & ATA_BUSY) &&
237 time_before(jiffies, timeout)) {
97750ceb 238 ata_msleep(ap, 50);
5682ed33 239 status = ap->ops->sff_check_status(ap);
624d5c51
TH
240 }
241
242 if (status == 0xff)
243 return -ENODEV;
244
245 if (status & ATA_BUSY) {
a9a79dfe
JP
246 ata_port_err(ap,
247 "port failed to respond (%lu secs, Status 0x%x)\n",
248 DIV_ROUND_UP(tmout, 1000), status);
624d5c51
TH
249 return -EBUSY;
250 }
251
252 return 0;
253}
0fe40ff8 254EXPORT_SYMBOL_GPL(ata_sff_busy_sleep);
624d5c51 255
aa2731ad
TH
256static int ata_sff_check_ready(struct ata_link *link)
257{
258 u8 status = link->ap->ops->sff_check_status(link->ap);
259
78ab88f0 260 return ata_check_ready(status);
aa2731ad
TH
261}
262
624d5c51 263/**
9363c382 264 * ata_sff_wait_ready - sleep until BSY clears, or timeout
705e76be 265 * @link: SFF link to wait ready status for
624d5c51
TH
266 * @deadline: deadline jiffies for the operation
267 *
268 * Sleep until ATA Status register bit BSY clears, or timeout
269 * occurs.
270 *
271 * LOCKING:
272 * Kernel thread context (may sleep).
273 *
274 * RETURNS:
275 * 0 on success, -errno otherwise.
276 */
705e76be 277int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline)
624d5c51 278{
aa2731ad 279 return ata_wait_ready(link, deadline, ata_sff_check_ready);
624d5c51 280}
0fe40ff8 281EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
624d5c51 282
41dec29b
SS
283/**
284 * ata_sff_set_devctl - Write device control reg
285 * @ap: port where the device is
286 * @ctl: value to write
287 *
288 * Writes ATA taskfile device control register.
289 *
290 * Note: may NOT be used as the sff_set_devctl() entry in
291 * ata_port_operations.
292 *
293 * LOCKING:
294 * Inherited from caller.
295 */
296static void ata_sff_set_devctl(struct ata_port *ap, u8 ctl)
297{
298 if (ap->ops->sff_set_devctl)
299 ap->ops->sff_set_devctl(ap, ctl);
300 else
301 iowrite8(ctl, ap->ioaddr.ctl_addr);
302}
303
624d5c51 304/**
9363c382 305 * ata_sff_dev_select - Select device 0/1 on ATA bus
624d5c51
TH
306 * @ap: ATA channel to manipulate
307 * @device: ATA device (numbered from zero) to select
308 *
309 * Use the method defined in the ATA specification to
310 * make either device 0, or device 1, active on the
311 * ATA channel. Works with both PIO and MMIO.
312 *
313 * May be used as the dev_select() entry in ata_port_operations.
314 *
315 * LOCKING:
316 * caller.
317 */
9363c382 318void ata_sff_dev_select(struct ata_port *ap, unsigned int device)
624d5c51
TH
319{
320 u8 tmp;
321
322 if (device == 0)
323 tmp = ATA_DEVICE_OBS;
324 else
325 tmp = ATA_DEVICE_OBS | ATA_DEV1;
326
327 iowrite8(tmp, ap->ioaddr.device_addr);
9363c382 328 ata_sff_pause(ap); /* needed; also flushes, for mmio */
624d5c51 329}
0fe40ff8 330EXPORT_SYMBOL_GPL(ata_sff_dev_select);
624d5c51
TH
331
332/**
333 * ata_dev_select - Select device 0/1 on ATA bus
334 * @ap: ATA channel to manipulate
335 * @device: ATA device (numbered from zero) to select
336 * @wait: non-zero to wait for Status register BSY bit to clear
337 * @can_sleep: non-zero if context allows sleeping
338 *
339 * Use the method defined in the ATA specification to
340 * make either device 0, or device 1, active on the
341 * ATA channel.
342 *
9363c382
TH
343 * This is a high-level version of ata_sff_dev_select(), which
344 * additionally provides the services of inserting the proper
345 * pauses and status polling, where needed.
624d5c51
TH
346 *
347 * LOCKING:
348 * caller.
349 */
c7a8209f 350static void ata_dev_select(struct ata_port *ap, unsigned int device,
624d5c51
TH
351 unsigned int wait, unsigned int can_sleep)
352{
353 if (ata_msg_probe(ap))
a9a79dfe
JP
354 ata_port_info(ap, "ata_dev_select: ENTER, device %u, wait %u\n",
355 device, wait);
624d5c51
TH
356
357 if (wait)
358 ata_wait_idle(ap);
359
5682ed33 360 ap->ops->sff_dev_select(ap, device);
624d5c51
TH
361
362 if (wait) {
363 if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
97750ceb 364 ata_msleep(ap, 150);
624d5c51
TH
365 ata_wait_idle(ap);
366 }
367}
368
369/**
9363c382 370 * ata_sff_irq_on - Enable interrupts on a port.
624d5c51
TH
371 * @ap: Port on which interrupts are enabled.
372 *
373 * Enable interrupts on a legacy IDE device using MMIO or PIO,
374 * wait for idle, clear any pending interrupts.
375 *
e42a542b
SS
376 * Note: may NOT be used as the sff_irq_on() entry in
377 * ata_port_operations.
378 *
624d5c51
TH
379 * LOCKING:
380 * Inherited from caller.
381 */
e42a542b 382void ata_sff_irq_on(struct ata_port *ap)
624d5c51
TH
383{
384 struct ata_ioports *ioaddr = &ap->ioaddr;
e42a542b
SS
385
386 if (ap->ops->sff_irq_on) {
387 ap->ops->sff_irq_on(ap);
388 return;
389 }
624d5c51
TH
390
391 ap->ctl &= ~ATA_NIEN;
392 ap->last_ctl = ap->ctl;
393
e42a542b
SS
394 if (ap->ops->sff_set_devctl || ioaddr->ctl_addr)
395 ata_sff_set_devctl(ap, ap->ctl);
396 ata_wait_idle(ap);
624d5c51 397
37f65b8b
TH
398 if (ap->ops->sff_irq_clear)
399 ap->ops->sff_irq_clear(ap);
624d5c51 400}
0fe40ff8 401EXPORT_SYMBOL_GPL(ata_sff_irq_on);
624d5c51 402
624d5c51 403/**
9363c382 404 * ata_sff_tf_load - send taskfile registers to host controller
624d5c51
TH
405 * @ap: Port to which output is sent
406 * @tf: ATA taskfile register set
407 *
408 * Outputs ATA taskfile to standard ATA host controller.
409 *
410 * LOCKING:
411 * Inherited from caller.
412 */
9363c382 413void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
624d5c51
TH
414{
415 struct ata_ioports *ioaddr = &ap->ioaddr;
416 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
417
418 if (tf->ctl != ap->last_ctl) {
419 if (ioaddr->ctl_addr)
420 iowrite8(tf->ctl, ioaddr->ctl_addr);
421 ap->last_ctl = tf->ctl;
40c60230 422 ata_wait_idle(ap);
624d5c51
TH
423 }
424
425 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
efcb3cf7 426 WARN_ON_ONCE(!ioaddr->ctl_addr);
624d5c51
TH
427 iowrite8(tf->hob_feature, ioaddr->feature_addr);
428 iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
429 iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
430 iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
431 iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
432 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
433 tf->hob_feature,
434 tf->hob_nsect,
435 tf->hob_lbal,
436 tf->hob_lbam,
437 tf->hob_lbah);
438 }
439
440 if (is_addr) {
441 iowrite8(tf->feature, ioaddr->feature_addr);
442 iowrite8(tf->nsect, ioaddr->nsect_addr);
443 iowrite8(tf->lbal, ioaddr->lbal_addr);
444 iowrite8(tf->lbam, ioaddr->lbam_addr);
445 iowrite8(tf->lbah, ioaddr->lbah_addr);
446 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
447 tf->feature,
448 tf->nsect,
449 tf->lbal,
450 tf->lbam,
451 tf->lbah);
452 }
453
454 if (tf->flags & ATA_TFLAG_DEVICE) {
455 iowrite8(tf->device, ioaddr->device_addr);
456 VPRINTK("device 0x%X\n", tf->device);
457 }
40c60230
TH
458
459 ata_wait_idle(ap);
624d5c51 460}
0fe40ff8 461EXPORT_SYMBOL_GPL(ata_sff_tf_load);
624d5c51
TH
462
463/**
9363c382 464 * ata_sff_tf_read - input device's ATA taskfile shadow registers
624d5c51
TH
465 * @ap: Port from which input is read
466 * @tf: ATA taskfile register set for storing input
467 *
468 * Reads ATA taskfile registers for currently-selected device
469 * into @tf. Assumes the device has a fully SFF compliant task file
470 * layout and behaviour. If you device does not (eg has a different
471 * status method) then you will need to provide a replacement tf_read
472 *
473 * LOCKING:
474 * Inherited from caller.
475 */
9363c382 476void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
624d5c51
TH
477{
478 struct ata_ioports *ioaddr = &ap->ioaddr;
479
9363c382 480 tf->command = ata_sff_check_status(ap);
624d5c51
TH
481 tf->feature = ioread8(ioaddr->error_addr);
482 tf->nsect = ioread8(ioaddr->nsect_addr);
483 tf->lbal = ioread8(ioaddr->lbal_addr);
484 tf->lbam = ioread8(ioaddr->lbam_addr);
485 tf->lbah = ioread8(ioaddr->lbah_addr);
486 tf->device = ioread8(ioaddr->device_addr);
487
488 if (tf->flags & ATA_TFLAG_LBA48) {
489 if (likely(ioaddr->ctl_addr)) {
490 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
491 tf->hob_feature = ioread8(ioaddr->error_addr);
492 tf->hob_nsect = ioread8(ioaddr->nsect_addr);
493 tf->hob_lbal = ioread8(ioaddr->lbal_addr);
494 tf->hob_lbam = ioread8(ioaddr->lbam_addr);
495 tf->hob_lbah = ioread8(ioaddr->lbah_addr);
496 iowrite8(tf->ctl, ioaddr->ctl_addr);
497 ap->last_ctl = tf->ctl;
498 } else
efcb3cf7 499 WARN_ON_ONCE(1);
624d5c51
TH
500 }
501}
0fe40ff8 502EXPORT_SYMBOL_GPL(ata_sff_tf_read);
624d5c51
TH
503
504/**
9363c382 505 * ata_sff_exec_command - issue ATA command to host controller
624d5c51
TH
506 * @ap: port to which command is being issued
507 * @tf: ATA taskfile register set
508 *
509 * Issues ATA command, with proper synchronization with interrupt
510 * handler / other threads.
511 *
512 * LOCKING:
513 * spin_lock_irqsave(host lock)
514 */
9363c382 515void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
624d5c51
TH
516{
517 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
518
519 iowrite8(tf->command, ap->ioaddr.command_addr);
9363c382 520 ata_sff_pause(ap);
624d5c51 521}
0fe40ff8 522EXPORT_SYMBOL_GPL(ata_sff_exec_command);
624d5c51
TH
523
524/**
525 * ata_tf_to_host - issue ATA taskfile to host controller
526 * @ap: port to which command is being issued
527 * @tf: ATA taskfile register set
528 *
529 * Issues ATA taskfile register set to ATA host controller,
530 * with proper synchronization with interrupt handler and
531 * other threads.
532 *
533 * LOCKING:
534 * spin_lock_irqsave(host lock)
535 */
536static inline void ata_tf_to_host(struct ata_port *ap,
537 const struct ata_taskfile *tf)
538{
5682ed33
TH
539 ap->ops->sff_tf_load(ap, tf);
540 ap->ops->sff_exec_command(ap, tf);
624d5c51
TH
541}
542
543/**
9363c382 544 * ata_sff_data_xfer - Transfer data by PIO
624d5c51
TH
545 * @dev: device to target
546 * @buf: data buffer
547 * @buflen: buffer length
548 * @rw: read/write
549 *
550 * Transfer data from/to the device data register by PIO.
551 *
552 * LOCKING:
553 * Inherited from caller.
554 *
555 * RETURNS:
556 * Bytes consumed.
557 */
9363c382
TH
558unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf,
559 unsigned int buflen, int rw)
624d5c51
TH
560{
561 struct ata_port *ap = dev->link->ap;
562 void __iomem *data_addr = ap->ioaddr.data_addr;
563 unsigned int words = buflen >> 1;
564
565 /* Transfer multiple of 2 bytes */
566 if (rw == READ)
567 ioread16_rep(data_addr, buf, words);
568 else
569 iowrite16_rep(data_addr, buf, words);
570
2102d749 571 /* Transfer trailing byte, if any. */
624d5c51 572 if (unlikely(buflen & 0x01)) {
21dba244 573 unsigned char pad[2] = { };
624d5c51 574
2102d749
SS
575 /* Point buf to the tail of buffer */
576 buf += buflen - 1;
577
578 /*
579 * Use io*16_rep() accessors here as well to avoid pointlessly
972b94ff 580 * swapping bytes to and from on the big endian machines...
2102d749 581 */
624d5c51 582 if (rw == READ) {
2102d749
SS
583 ioread16_rep(data_addr, pad, 1);
584 *buf = pad[0];
624d5c51 585 } else {
2102d749
SS
586 pad[0] = *buf;
587 iowrite16_rep(data_addr, pad, 1);
624d5c51
TH
588 }
589 words++;
590 }
591
592 return words << 1;
593}
0fe40ff8 594EXPORT_SYMBOL_GPL(ata_sff_data_xfer);
624d5c51 595
871af121
AC
596/**
597 * ata_sff_data_xfer32 - Transfer data by PIO
598 * @dev: device to target
599 * @buf: data buffer
600 * @buflen: buffer length
601 * @rw: read/write
602 *
603 * Transfer data from/to the device data register by PIO using 32bit
604 * I/O operations.
605 *
606 * LOCKING:
607 * Inherited from caller.
608 *
609 * RETURNS:
610 * Bytes consumed.
611 */
612
613unsigned int ata_sff_data_xfer32(struct ata_device *dev, unsigned char *buf,
614 unsigned int buflen, int rw)
615{
616 struct ata_port *ap = dev->link->ap;
617 void __iomem *data_addr = ap->ioaddr.data_addr;
618 unsigned int words = buflen >> 2;
619 int slop = buflen & 3;
972b94ff 620
e3cf95dd
AC
621 if (!(ap->pflags & ATA_PFLAG_PIO32))
622 return ata_sff_data_xfer(dev, buf, buflen, rw);
871af121
AC
623
624 /* Transfer multiple of 4 bytes */
625 if (rw == READ)
626 ioread32_rep(data_addr, buf, words);
627 else
628 iowrite32_rep(data_addr, buf, words);
629
d1b3525b 630 /* Transfer trailing bytes, if any */
871af121 631 if (unlikely(slop)) {
21dba244 632 unsigned char pad[4] = { };
d1b3525b
SS
633
634 /* Point buf to the tail of buffer */
635 buf += buflen - slop;
636
637 /*
638 * Use io*_rep() accessors here as well to avoid pointlessly
972b94ff 639 * swapping bytes to and from on the big endian machines...
d1b3525b 640 */
871af121 641 if (rw == READ) {
d1b3525b
SS
642 if (slop < 3)
643 ioread16_rep(data_addr, pad, 1);
644 else
645 ioread32_rep(data_addr, pad, 1);
646 memcpy(buf, pad, slop);
871af121 647 } else {
d1b3525b
SS
648 memcpy(pad, buf, slop);
649 if (slop < 3)
650 iowrite16_rep(data_addr, pad, 1);
651 else
652 iowrite32_rep(data_addr, pad, 1);
871af121 653 }
871af121 654 }
d1b3525b 655 return (buflen + 1) & ~1;
871af121
AC
656}
657EXPORT_SYMBOL_GPL(ata_sff_data_xfer32);
658
624d5c51 659/**
9363c382 660 * ata_sff_data_xfer_noirq - Transfer data by PIO
624d5c51
TH
661 * @dev: device to target
662 * @buf: data buffer
663 * @buflen: buffer length
664 * @rw: read/write
665 *
666 * Transfer data from/to the device data register by PIO. Do the
667 * transfer with interrupts disabled.
668 *
669 * LOCKING:
670 * Inherited from caller.
671 *
672 * RETURNS:
673 * Bytes consumed.
674 */
9363c382
TH
675unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf,
676 unsigned int buflen, int rw)
624d5c51
TH
677{
678 unsigned long flags;
679 unsigned int consumed;
680
681 local_irq_save(flags);
418fae27 682 consumed = ata_sff_data_xfer32(dev, buf, buflen, rw);
624d5c51
TH
683 local_irq_restore(flags);
684
685 return consumed;
686}
0fe40ff8 687EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq);
624d5c51
TH
688
689/**
690 * ata_pio_sector - Transfer a sector of data.
691 * @qc: Command on going
692 *
693 * Transfer qc->sect_size bytes of data from/to the ATA device.
694 *
695 * LOCKING:
696 * Inherited from caller.
697 */
698static void ata_pio_sector(struct ata_queued_cmd *qc)
699{
700 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
701 struct ata_port *ap = qc->ap;
702 struct page *page;
703 unsigned int offset;
704 unsigned char *buf;
705
706 if (qc->curbytes == qc->nbytes - qc->sect_size)
707 ap->hsm_task_state = HSM_ST_LAST;
708
709 page = sg_page(qc->cursg);
710 offset = qc->cursg->offset + qc->cursg_ofs;
711
712 /* get the current page and offset */
713 page = nth_page(page, (offset >> PAGE_SHIFT));
714 offset %= PAGE_SIZE;
715
716 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
717
718 if (PageHighMem(page)) {
719 unsigned long flags;
720
721 /* FIXME: use a bounce buffer */
722 local_irq_save(flags);
496cda8e 723 buf = kmap_atomic(page);
624d5c51
TH
724
725 /* do the actual data transfer */
5682ed33
TH
726 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
727 do_write);
624d5c51 728
496cda8e 729 kunmap_atomic(buf);
624d5c51
TH
730 local_irq_restore(flags);
731 } else {
732 buf = page_address(page);
5682ed33
TH
733 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
734 do_write);
624d5c51
TH
735 }
736
3842e835 737 if (!do_write && !PageSlab(page))
2d68b7fe
CM
738 flush_dcache_page(page);
739
624d5c51
TH
740 qc->curbytes += qc->sect_size;
741 qc->cursg_ofs += qc->sect_size;
742
743 if (qc->cursg_ofs == qc->cursg->length) {
744 qc->cursg = sg_next(qc->cursg);
745 qc->cursg_ofs = 0;
746 }
747}
748
749/**
750 * ata_pio_sectors - Transfer one or many sectors.
751 * @qc: Command on going
752 *
753 * Transfer one or many sectors of data from/to the
754 * ATA device for the DRQ request.
755 *
756 * LOCKING:
757 * Inherited from caller.
758 */
759static void ata_pio_sectors(struct ata_queued_cmd *qc)
760{
761 if (is_multi_taskfile(&qc->tf)) {
762 /* READ/WRITE MULTIPLE */
763 unsigned int nsect;
764
efcb3cf7 765 WARN_ON_ONCE(qc->dev->multi_count == 0);
624d5c51
TH
766
767 nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
768 qc->dev->multi_count);
769 while (nsect--)
770 ata_pio_sector(qc);
771 } else
772 ata_pio_sector(qc);
773
a57c1bad 774 ata_sff_sync(qc->ap); /* flush */
624d5c51
TH
775}
776
777/**
778 * atapi_send_cdb - Write CDB bytes to hardware
779 * @ap: Port to which ATAPI device is attached.
780 * @qc: Taskfile currently active
781 *
782 * When device has indicated its readiness to accept
783 * a CDB, this function is called. Send the CDB.
784 *
785 * LOCKING:
786 * caller.
787 */
788static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
789{
790 /* send SCSI cdb */
791 DPRINTK("send cdb\n");
efcb3cf7 792 WARN_ON_ONCE(qc->dev->cdb_len < 12);
624d5c51 793
5682ed33 794 ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
a57c1bad
AC
795 ata_sff_sync(ap);
796 /* FIXME: If the CDB is for DMA do we need to do the transition delay
797 or is bmdma_start guaranteed to do it ? */
624d5c51
TH
798 switch (qc->tf.protocol) {
799 case ATAPI_PROT_PIO:
800 ap->hsm_task_state = HSM_ST;
801 break;
802 case ATAPI_PROT_NODATA:
803 ap->hsm_task_state = HSM_ST_LAST;
804 break;
9a7780c9 805#ifdef CONFIG_ATA_BMDMA
624d5c51
TH
806 case ATAPI_PROT_DMA:
807 ap->hsm_task_state = HSM_ST_LAST;
808 /* initiate bmdma */
809 ap->ops->bmdma_start(qc);
810 break;
9a7780c9
TH
811#endif /* CONFIG_ATA_BMDMA */
812 default:
813 BUG();
624d5c51
TH
814 }
815}
816
817/**
818 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
819 * @qc: Command on going
820 * @bytes: number of bytes
821 *
822 * Transfer Transfer data from/to the ATAPI device.
823 *
824 * LOCKING:
825 * Inherited from caller.
826 *
827 */
828static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
829{
830 int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
831 struct ata_port *ap = qc->ap;
832 struct ata_device *dev = qc->dev;
833 struct ata_eh_info *ehi = &dev->link->eh_info;
834 struct scatterlist *sg;
835 struct page *page;
836 unsigned char *buf;
837 unsigned int offset, count, consumed;
838
839next_sg:
840 sg = qc->cursg;
841 if (unlikely(!sg)) {
842 ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
843 "buf=%u cur=%u bytes=%u",
844 qc->nbytes, qc->curbytes, bytes);
845 return -1;
846 }
847
848 page = sg_page(sg);
849 offset = sg->offset + qc->cursg_ofs;
850
851 /* get the current page and offset */
852 page = nth_page(page, (offset >> PAGE_SHIFT));
853 offset %= PAGE_SIZE;
854
855 /* don't overrun current sg */
856 count = min(sg->length - qc->cursg_ofs, bytes);
857
858 /* don't cross page boundaries */
859 count = min(count, (unsigned int)PAGE_SIZE - offset);
860
861 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
862
863 if (PageHighMem(page)) {
864 unsigned long flags;
865
866 /* FIXME: use bounce buffer */
867 local_irq_save(flags);
496cda8e 868 buf = kmap_atomic(page);
624d5c51
TH
869
870 /* do the actual data transfer */
0fe40ff8
AC
871 consumed = ap->ops->sff_data_xfer(dev, buf + offset,
872 count, rw);
624d5c51 873
496cda8e 874 kunmap_atomic(buf);
624d5c51
TH
875 local_irq_restore(flags);
876 } else {
877 buf = page_address(page);
0fe40ff8
AC
878 consumed = ap->ops->sff_data_xfer(dev, buf + offset,
879 count, rw);
624d5c51
TH
880 }
881
882 bytes -= min(bytes, consumed);
883 qc->curbytes += count;
884 qc->cursg_ofs += count;
885
886 if (qc->cursg_ofs == sg->length) {
887 qc->cursg = sg_next(qc->cursg);
888 qc->cursg_ofs = 0;
889 }
890
a0f79f7a
CB
891 /*
892 * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed);
893 * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN
894 * check correctly as it doesn't know if it is the last request being
895 * made. Somebody should implement a proper sanity check.
896 */
624d5c51
TH
897 if (bytes)
898 goto next_sg;
899 return 0;
900}
901
902/**
903 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
904 * @qc: Command on going
905 *
906 * Transfer Transfer data from/to the ATAPI device.
907 *
908 * LOCKING:
909 * Inherited from caller.
910 */
911static void atapi_pio_bytes(struct ata_queued_cmd *qc)
912{
913 struct ata_port *ap = qc->ap;
914 struct ata_device *dev = qc->dev;
915 struct ata_eh_info *ehi = &dev->link->eh_info;
916 unsigned int ireason, bc_lo, bc_hi, bytes;
917 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
918
919 /* Abuse qc->result_tf for temp storage of intermediate TF
920 * here to save some kernel stack usage.
921 * For normal completion, qc->result_tf is not relevant. For
922 * error, qc->result_tf is later overwritten by ata_qc_complete().
923 * So, the correctness of qc->result_tf is not affected.
924 */
5682ed33 925 ap->ops->sff_tf_read(ap, &qc->result_tf);
624d5c51
TH
926 ireason = qc->result_tf.nsect;
927 bc_lo = qc->result_tf.lbam;
928 bc_hi = qc->result_tf.lbah;
929 bytes = (bc_hi << 8) | bc_lo;
930
931 /* shall be cleared to zero, indicating xfer of data */
002ae084 932 if (unlikely(ireason & ATAPI_COD))
624d5c51
TH
933 goto atapi_check;
934
935 /* make sure transfer direction matches expected */
002ae084 936 i_write = ((ireason & ATAPI_IO) == 0) ? 1 : 0;
624d5c51
TH
937 if (unlikely(do_write != i_write))
938 goto atapi_check;
939
940 if (unlikely(!bytes))
941 goto atapi_check;
942
943 VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
944
945 if (unlikely(__atapi_pio_bytes(qc, bytes)))
946 goto err_out;
a57c1bad 947 ata_sff_sync(ap); /* flush */
624d5c51
TH
948
949 return;
950
951 atapi_check:
952 ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
953 ireason, bytes);
954 err_out:
955 qc->err_mask |= AC_ERR_HSM;
956 ap->hsm_task_state = HSM_ST_ERR;
957}
958
959/**
960 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
961 * @ap: the target ata_port
962 * @qc: qc on going
963 *
964 * RETURNS:
965 * 1 if ok in workqueue, 0 otherwise.
966 */
0fe40ff8
AC
967static inline int ata_hsm_ok_in_wq(struct ata_port *ap,
968 struct ata_queued_cmd *qc)
624d5c51
TH
969{
970 if (qc->tf.flags & ATA_TFLAG_POLLING)
971 return 1;
972
973 if (ap->hsm_task_state == HSM_ST_FIRST) {
974 if (qc->tf.protocol == ATA_PROT_PIO &&
0fe40ff8 975 (qc->tf.flags & ATA_TFLAG_WRITE))
624d5c51
TH
976 return 1;
977
978 if (ata_is_atapi(qc->tf.protocol) &&
0fe40ff8 979 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
624d5c51
TH
980 return 1;
981 }
982
983 return 0;
984}
985
986/**
987 * ata_hsm_qc_complete - finish a qc running on standard HSM
988 * @qc: Command to complete
989 * @in_wq: 1 if called from workqueue, 0 otherwise
990 *
991 * Finish @qc which is running on standard HSM.
992 *
993 * LOCKING:
994 * If @in_wq is zero, spin_lock_irqsave(host lock).
995 * Otherwise, none on entry and grabs host lock.
996 */
997static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
998{
999 struct ata_port *ap = qc->ap;
1000 unsigned long flags;
1001
1002 if (ap->ops->error_handler) {
1003 if (in_wq) {
1004 spin_lock_irqsave(ap->lock, flags);
1005
1006 /* EH might have kicked in while host lock is
1007 * released.
1008 */
1009 qc = ata_qc_from_tag(ap, qc->tag);
1010 if (qc) {
1011 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
e42a542b 1012 ata_sff_irq_on(ap);
624d5c51
TH
1013 ata_qc_complete(qc);
1014 } else
1015 ata_port_freeze(ap);
1016 }
1017
1018 spin_unlock_irqrestore(ap->lock, flags);
1019 } else {
1020 if (likely(!(qc->err_mask & AC_ERR_HSM)))
1021 ata_qc_complete(qc);
1022 else
1023 ata_port_freeze(ap);
1024 }
1025 } else {
1026 if (in_wq) {
1027 spin_lock_irqsave(ap->lock, flags);
e42a542b 1028 ata_sff_irq_on(ap);
624d5c51
TH
1029 ata_qc_complete(qc);
1030 spin_unlock_irqrestore(ap->lock, flags);
1031 } else
1032 ata_qc_complete(qc);
1033 }
1034}
1035
1036/**
9363c382 1037 * ata_sff_hsm_move - move the HSM to the next state.
624d5c51
TH
1038 * @ap: the target ata_port
1039 * @qc: qc on going
1040 * @status: current device status
1041 * @in_wq: 1 if called from workqueue, 0 otherwise
1042 *
1043 * RETURNS:
1044 * 1 when poll next status needed, 0 otherwise.
1045 */
9363c382
TH
1046int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
1047 u8 status, int in_wq)
624d5c51 1048{
ea3c6450
GG
1049 struct ata_link *link = qc->dev->link;
1050 struct ata_eh_info *ehi = &link->eh_info;
624d5c51
TH
1051 unsigned long flags = 0;
1052 int poll_next;
1053
efcb3cf7 1054 WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
624d5c51 1055
9363c382 1056 /* Make sure ata_sff_qc_issue() does not throw things
624d5c51
TH
1057 * like DMA polling into the workqueue. Notice that
1058 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
1059 */
efcb3cf7 1060 WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc));
624d5c51
TH
1061
1062fsm_start:
1063 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
1064 ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
1065
1066 switch (ap->hsm_task_state) {
1067 case HSM_ST_FIRST:
1068 /* Send first data block or PACKET CDB */
1069
1070 /* If polling, we will stay in the work queue after
1071 * sending the data. Otherwise, interrupt handler
1072 * takes over after sending the data.
1073 */
1074 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
1075
1076 /* check device status */
1077 if (unlikely((status & ATA_DRQ) == 0)) {
1078 /* handle BSY=0, DRQ=0 as error */
1079 if (likely(status & (ATA_ERR | ATA_DF)))
1080 /* device stops HSM for abort/error */
1081 qc->err_mask |= AC_ERR_DEV;
a836d3e8 1082 else {
624d5c51 1083 /* HSM violation. Let EH handle this */
a836d3e8
TH
1084 ata_ehi_push_desc(ehi,
1085 "ST_FIRST: !(DRQ|ERR|DF)");
624d5c51 1086 qc->err_mask |= AC_ERR_HSM;
a836d3e8 1087 }
624d5c51
TH
1088
1089 ap->hsm_task_state = HSM_ST_ERR;
1090 goto fsm_start;
1091 }
1092
1093 /* Device should not ask for data transfer (DRQ=1)
1094 * when it finds something wrong.
1095 * We ignore DRQ here and stop the HSM by
1096 * changing hsm_task_state to HSM_ST_ERR and
1097 * let the EH abort the command or reset the device.
1098 */
1099 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1100 /* Some ATAPI tape drives forget to clear the ERR bit
1101 * when doing the next command (mostly request sense).
1102 * We ignore ERR here to workaround and proceed sending
1103 * the CDB.
1104 */
1105 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
a836d3e8
TH
1106 ata_ehi_push_desc(ehi, "ST_FIRST: "
1107 "DRQ=1 with device error, "
1108 "dev_stat 0x%X", status);
624d5c51
TH
1109 qc->err_mask |= AC_ERR_HSM;
1110 ap->hsm_task_state = HSM_ST_ERR;
1111 goto fsm_start;
1112 }
1113 }
1114
1115 /* Send the CDB (atapi) or the first data block (ata pio out).
1116 * During the state transition, interrupt handler shouldn't
1117 * be invoked before the data transfer is complete and
1118 * hsm_task_state is changed. Hence, the following locking.
1119 */
1120 if (in_wq)
1121 spin_lock_irqsave(ap->lock, flags);
1122
1123 if (qc->tf.protocol == ATA_PROT_PIO) {
1124 /* PIO data out protocol.
1125 * send first data block.
1126 */
1127
1128 /* ata_pio_sectors() might change the state
1129 * to HSM_ST_LAST. so, the state is changed here
1130 * before ata_pio_sectors().
1131 */
1132 ap->hsm_task_state = HSM_ST;
1133 ata_pio_sectors(qc);
1134 } else
1135 /* send CDB */
1136 atapi_send_cdb(ap, qc);
1137
1138 if (in_wq)
1139 spin_unlock_irqrestore(ap->lock, flags);
1140
c429137a 1141 /* if polling, ata_sff_pio_task() handles the rest.
624d5c51
TH
1142 * otherwise, interrupt handler takes over from here.
1143 */
1144 break;
1145
1146 case HSM_ST:
1147 /* complete command or read/write the data register */
1148 if (qc->tf.protocol == ATAPI_PROT_PIO) {
1149 /* ATAPI PIO protocol */
1150 if ((status & ATA_DRQ) == 0) {
1151 /* No more data to transfer or device error.
1152 * Device error will be tagged in HSM_ST_LAST.
1153 */
1154 ap->hsm_task_state = HSM_ST_LAST;
1155 goto fsm_start;
1156 }
1157
1158 /* Device should not ask for data transfer (DRQ=1)
1159 * when it finds something wrong.
1160 * We ignore DRQ here and stop the HSM by
1161 * changing hsm_task_state to HSM_ST_ERR and
1162 * let the EH abort the command or reset the device.
1163 */
1164 if (unlikely(status & (ATA_ERR | ATA_DF))) {
a836d3e8
TH
1165 ata_ehi_push_desc(ehi, "ST-ATAPI: "
1166 "DRQ=1 with device error, "
1167 "dev_stat 0x%X", status);
624d5c51
TH
1168 qc->err_mask |= AC_ERR_HSM;
1169 ap->hsm_task_state = HSM_ST_ERR;
1170 goto fsm_start;
1171 }
1172
1173 atapi_pio_bytes(qc);
1174
1175 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
1176 /* bad ireason reported by device */
1177 goto fsm_start;
1178
1179 } else {
1180 /* ATA PIO protocol */
1181 if (unlikely((status & ATA_DRQ) == 0)) {
1182 /* handle BSY=0, DRQ=0 as error */
6a6b97d3 1183 if (likely(status & (ATA_ERR | ATA_DF))) {
624d5c51
TH
1184 /* device stops HSM for abort/error */
1185 qc->err_mask |= AC_ERR_DEV;
6a6b97d3
TH
1186
1187 /* If diagnostic failed and this is
1188 * IDENTIFY, it's likely a phantom
1189 * device. Mark hint.
1190 */
1191 if (qc->dev->horkage &
1192 ATA_HORKAGE_DIAGNOSTIC)
1193 qc->err_mask |=
1194 AC_ERR_NODEV_HINT;
1195 } else {
624d5c51
TH
1196 /* HSM violation. Let EH handle this.
1197 * Phantom devices also trigger this
1198 * condition. Mark hint.
1199 */
a836d3e8 1200 ata_ehi_push_desc(ehi, "ST-ATA: "
80ee6f54 1201 "DRQ=0 without device error, "
a836d3e8 1202 "dev_stat 0x%X", status);
624d5c51
TH
1203 qc->err_mask |= AC_ERR_HSM |
1204 AC_ERR_NODEV_HINT;
a836d3e8 1205 }
624d5c51
TH
1206
1207 ap->hsm_task_state = HSM_ST_ERR;
1208 goto fsm_start;
1209 }
1210
1211 /* For PIO reads, some devices may ask for
1212 * data transfer (DRQ=1) alone with ERR=1.
1213 * We respect DRQ here and transfer one
1214 * block of junk data before changing the
1215 * hsm_task_state to HSM_ST_ERR.
1216 *
1217 * For PIO writes, ERR=1 DRQ=1 doesn't make
1218 * sense since the data block has been
1219 * transferred to the device.
1220 */
1221 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1222 /* data might be corrputed */
1223 qc->err_mask |= AC_ERR_DEV;
1224
1225 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
1226 ata_pio_sectors(qc);
1227 status = ata_wait_idle(ap);
1228 }
1229
a836d3e8
TH
1230 if (status & (ATA_BUSY | ATA_DRQ)) {
1231 ata_ehi_push_desc(ehi, "ST-ATA: "
1232 "BUSY|DRQ persists on ERR|DF, "
1233 "dev_stat 0x%X", status);
624d5c51 1234 qc->err_mask |= AC_ERR_HSM;
a836d3e8 1235 }
624d5c51 1236
b919930c
TH
1237 /* There are oddball controllers with
1238 * status register stuck at 0x7f and
1239 * lbal/m/h at zero which makes it
1240 * pass all other presence detection
1241 * mechanisms we have. Set NODEV_HINT
1242 * for it. Kernel bz#7241.
1243 */
1244 if (status == 0x7f)
1245 qc->err_mask |= AC_ERR_NODEV_HINT;
1246
624d5c51
TH
1247 /* ata_pio_sectors() might change the
1248 * state to HSM_ST_LAST. so, the state
1249 * is changed after ata_pio_sectors().
1250 */
1251 ap->hsm_task_state = HSM_ST_ERR;
1252 goto fsm_start;
1253 }
1254
1255 ata_pio_sectors(qc);
1256
1257 if (ap->hsm_task_state == HSM_ST_LAST &&
1258 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
1259 /* all data read */
1260 status = ata_wait_idle(ap);
1261 goto fsm_start;
1262 }
1263 }
1264
1265 poll_next = 1;
1266 break;
1267
1268 case HSM_ST_LAST:
1269 if (unlikely(!ata_ok(status))) {
1270 qc->err_mask |= __ac_err_mask(status);
1271 ap->hsm_task_state = HSM_ST_ERR;
1272 goto fsm_start;
1273 }
1274
1275 /* no more data to transfer */
1276 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
1277 ap->print_id, qc->dev->devno, status);
1278
efcb3cf7 1279 WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM));
624d5c51
TH
1280
1281 ap->hsm_task_state = HSM_ST_IDLE;
1282
1283 /* complete taskfile transaction */
1284 ata_hsm_qc_complete(qc, in_wq);
1285
1286 poll_next = 0;
1287 break;
1288
1289 case HSM_ST_ERR:
624d5c51
TH
1290 ap->hsm_task_state = HSM_ST_IDLE;
1291
1292 /* complete taskfile transaction */
1293 ata_hsm_qc_complete(qc, in_wq);
1294
1295 poll_next = 0;
1296 break;
1297 default:
1298 poll_next = 0;
a588afc9
TH
1299 WARN(true, "ata%d: SFF host state machine in invalid state %d",
1300 ap->print_id, ap->hsm_task_state);
624d5c51
TH
1301 }
1302
1303 return poll_next;
1304}
0fe40ff8 1305EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
624d5c51 1306
64b97594
VK
1307void ata_sff_queue_work(struct work_struct *work)
1308{
1309 queue_work(ata_sff_wq, work);
1310}
1311EXPORT_SYMBOL_GPL(ata_sff_queue_work);
1312
1313void ata_sff_queue_delayed_work(struct delayed_work *dwork, unsigned long delay)
1314{
1315 queue_delayed_work(ata_sff_wq, dwork, delay);
1316}
1317EXPORT_SYMBOL_GPL(ata_sff_queue_delayed_work);
1318
ea3c6450 1319void ata_sff_queue_pio_task(struct ata_link *link, unsigned long delay)
c429137a 1320{
ea3c6450
GG
1321 struct ata_port *ap = link->ap;
1322
1323 WARN_ON((ap->sff_pio_task_link != NULL) &&
1324 (ap->sff_pio_task_link != link));
1325 ap->sff_pio_task_link = link;
1326
c429137a 1327 /* may fail if ata_sff_flush_pio_task() in progress */
64b97594 1328 ata_sff_queue_delayed_work(&ap->sff_pio_task, msecs_to_jiffies(delay));
c429137a
TH
1329}
1330EXPORT_SYMBOL_GPL(ata_sff_queue_pio_task);
1331
1332void ata_sff_flush_pio_task(struct ata_port *ap)
1333{
1334 DPRINTK("ENTER\n");
1335
afe2c511 1336 cancel_delayed_work_sync(&ap->sff_pio_task);
ce751452
DJ
1337
1338 /*
1339 * We wanna reset the HSM state to IDLE. If we do so without
1340 * grabbing the port lock, critical sections protected by it which
1341 * expect the HSM state to stay stable may get surprised. For
1342 * example, we may set IDLE in between the time
1343 * __ata_sff_port_intr() checks for HSM_ST_IDLE and before it calls
1344 * ata_sff_hsm_move() causing ata_sff_hsm_move() to BUG().
1345 */
1346 spin_lock_irq(ap->lock);
c429137a 1347 ap->hsm_task_state = HSM_ST_IDLE;
ce751452
DJ
1348 spin_unlock_irq(ap->lock);
1349
d4d8eaff 1350 ap->sff_pio_task_link = NULL;
c429137a
TH
1351
1352 if (ata_msg_ctl(ap))
a9a79dfe 1353 ata_port_dbg(ap, "%s: EXIT\n", __func__);
c429137a
TH
1354}
1355
1356static void ata_sff_pio_task(struct work_struct *work)
624d5c51
TH
1357{
1358 struct ata_port *ap =
c429137a 1359 container_of(work, struct ata_port, sff_pio_task.work);
ea3c6450 1360 struct ata_link *link = ap->sff_pio_task_link;
c429137a 1361 struct ata_queued_cmd *qc;
624d5c51
TH
1362 u8 status;
1363 int poll_next;
1364
4fca377f 1365 BUG_ON(ap->sff_pio_task_link == NULL);
c429137a 1366 /* qc can be NULL if timeout occurred */
ea3c6450
GG
1367 qc = ata_qc_from_tag(ap, link->active_tag);
1368 if (!qc) {
1369 ap->sff_pio_task_link = NULL;
c429137a 1370 return;
ea3c6450 1371 }
c429137a 1372
624d5c51 1373fsm_start:
efcb3cf7 1374 WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE);
624d5c51
TH
1375
1376 /*
1377 * This is purely heuristic. This is a fast path.
1378 * Sometimes when we enter, BSY will be cleared in
1379 * a chk-status or two. If not, the drive is probably seeking
1380 * or something. Snooze for a couple msecs, then
1381 * chk-status again. If still busy, queue delayed work.
1382 */
9363c382 1383 status = ata_sff_busy_wait(ap, ATA_BUSY, 5);
624d5c51 1384 if (status & ATA_BUSY) {
97750ceb 1385 ata_msleep(ap, 2);
9363c382 1386 status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
624d5c51 1387 if (status & ATA_BUSY) {
ea3c6450 1388 ata_sff_queue_pio_task(link, ATA_SHORT_PAUSE);
624d5c51
TH
1389 return;
1390 }
1391 }
1392
ea3c6450
GG
1393 /*
1394 * hsm_move() may trigger another command to be processed.
1395 * clean the link beforehand.
1396 */
1397 ap->sff_pio_task_link = NULL;
624d5c51 1398 /* move the HSM */
9363c382 1399 poll_next = ata_sff_hsm_move(ap, qc, status, 1);
624d5c51
TH
1400
1401 /* another command or interrupt handler
1402 * may be running at this point.
1403 */
1404 if (poll_next)
1405 goto fsm_start;
1406}
1407
1408/**
360ff783 1409 * ata_sff_qc_issue - issue taskfile to a SFF controller
624d5c51
TH
1410 * @qc: command to issue to device
1411 *
360ff783
TH
1412 * This function issues a PIO or NODATA command to a SFF
1413 * controller.
624d5c51
TH
1414 *
1415 * LOCKING:
1416 * spin_lock_irqsave(host lock)
1417 *
1418 * RETURNS:
1419 * Zero on success, AC_ERR_* mask on failure
1420 */
9363c382 1421unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
624d5c51
TH
1422{
1423 struct ata_port *ap = qc->ap;
ea3c6450 1424 struct ata_link *link = qc->dev->link;
624d5c51
TH
1425
1426 /* Use polling pio if the LLD doesn't handle
1427 * interrupt driven pio and atapi CDB interrupt.
1428 */
360ff783
TH
1429 if (ap->flags & ATA_FLAG_PIO_POLLING)
1430 qc->tf.flags |= ATA_TFLAG_POLLING;
624d5c51
TH
1431
1432 /* select the device */
1433 ata_dev_select(ap, qc->dev->devno, 1, 0);
1434
1435 /* start the command */
1436 switch (qc->tf.protocol) {
1437 case ATA_PROT_NODATA:
1438 if (qc->tf.flags & ATA_TFLAG_POLLING)
1439 ata_qc_set_polling(qc);
1440
1441 ata_tf_to_host(ap, &qc->tf);
1442 ap->hsm_task_state = HSM_ST_LAST;
1443
1444 if (qc->tf.flags & ATA_TFLAG_POLLING)
ea3c6450 1445 ata_sff_queue_pio_task(link, 0);
624d5c51
TH
1446
1447 break;
1448
624d5c51
TH
1449 case ATA_PROT_PIO:
1450 if (qc->tf.flags & ATA_TFLAG_POLLING)
1451 ata_qc_set_polling(qc);
1452
1453 ata_tf_to_host(ap, &qc->tf);
1454
1455 if (qc->tf.flags & ATA_TFLAG_WRITE) {
1456 /* PIO data out protocol */
1457 ap->hsm_task_state = HSM_ST_FIRST;
ea3c6450 1458 ata_sff_queue_pio_task(link, 0);
624d5c51 1459
c429137a
TH
1460 /* always send first data block using the
1461 * ata_sff_pio_task() codepath.
624d5c51
TH
1462 */
1463 } else {
1464 /* PIO data in protocol */
1465 ap->hsm_task_state = HSM_ST;
1466
1467 if (qc->tf.flags & ATA_TFLAG_POLLING)
ea3c6450 1468 ata_sff_queue_pio_task(link, 0);
624d5c51 1469
c429137a
TH
1470 /* if polling, ata_sff_pio_task() handles the
1471 * rest. otherwise, interrupt handler takes
1472 * over from here.
624d5c51
TH
1473 */
1474 }
1475
1476 break;
1477
1478 case ATAPI_PROT_PIO:
1479 case ATAPI_PROT_NODATA:
1480 if (qc->tf.flags & ATA_TFLAG_POLLING)
1481 ata_qc_set_polling(qc);
1482
1483 ata_tf_to_host(ap, &qc->tf);
1484
1485 ap->hsm_task_state = HSM_ST_FIRST;
1486
1487 /* send cdb by polling if no cdb interrupt */
1488 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
1489 (qc->tf.flags & ATA_TFLAG_POLLING))
ea3c6450 1490 ata_sff_queue_pio_task(link, 0);
624d5c51
TH
1491 break;
1492
624d5c51 1493 default:
efcb3cf7 1494 WARN_ON_ONCE(1);
624d5c51
TH
1495 return AC_ERR_SYSTEM;
1496 }
1497
1498 return 0;
1499}
0fe40ff8 1500EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
624d5c51 1501
22183bf5
TH
1502/**
1503 * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read
1504 * @qc: qc to fill result TF for
1505 *
1506 * @qc is finished and result TF needs to be filled. Fill it
1507 * using ->sff_tf_read.
1508 *
1509 * LOCKING:
1510 * spin_lock_irqsave(host lock)
1511 *
1512 * RETURNS:
1513 * true indicating that result TF is successfully filled.
1514 */
1515bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
1516{
1517 qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf);
1518 return true;
1519}
0fe40ff8 1520EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
22183bf5 1521
c3b28894 1522static unsigned int ata_sff_idle_irq(struct ata_port *ap)
624d5c51 1523{
c3b28894
TH
1524 ap->stats.idle_irq++;
1525
1526#ifdef ATA_IRQ_TRAP
1527 if ((ap->stats.idle_irq % 1000) == 0) {
1528 ap->ops->sff_check_status(ap);
1529 if (ap->ops->sff_irq_clear)
1530 ap->ops->sff_irq_clear(ap);
a9a79dfe 1531 ata_port_warn(ap, "irq trap\n");
c3b28894
TH
1532 return 1;
1533 }
1534#endif
1535 return 0; /* irq not handled */
1536}
1537
1538static unsigned int __ata_sff_port_intr(struct ata_port *ap,
1539 struct ata_queued_cmd *qc,
1540 bool hsmv_on_idle)
1541{
1542 u8 status;
624d5c51
TH
1543
1544 VPRINTK("ata%u: protocol %d task_state %d\n",
1545 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
1546
1547 /* Check whether we are expecting interrupt in this state */
1548 switch (ap->hsm_task_state) {
1549 case HSM_ST_FIRST:
1550 /* Some pre-ATAPI-4 devices assert INTRQ
1551 * at this state when ready to receive CDB.
1552 */
1553
1554 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1555 * The flag was turned on only for atapi devices. No
1556 * need to check ata_is_atapi(qc->tf.protocol) again.
1557 */
1558 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
c3b28894 1559 return ata_sff_idle_irq(ap);
624d5c51 1560 break;
687a9933 1561 case HSM_ST_IDLE:
c3b28894 1562 return ata_sff_idle_irq(ap);
687a9933
TH
1563 default:
1564 break;
624d5c51
TH
1565 }
1566
a57c1bad
AC
1567 /* check main status, clearing INTRQ if needed */
1568 status = ata_sff_irq_status(ap);
332ac7ff 1569 if (status & ATA_BUSY) {
c3b28894 1570 if (hsmv_on_idle) {
332ac7ff
TH
1571 /* BMDMA engine is already stopped, we're screwed */
1572 qc->err_mask |= AC_ERR_HSM;
1573 ap->hsm_task_state = HSM_ST_ERR;
1574 } else
c3b28894 1575 return ata_sff_idle_irq(ap);
332ac7ff 1576 }
624d5c51 1577
9f2f7210 1578 /* clear irq events */
37f65b8b
TH
1579 if (ap->ops->sff_irq_clear)
1580 ap->ops->sff_irq_clear(ap);
624d5c51 1581
9363c382 1582 ata_sff_hsm_move(ap, qc, status, 0);
624d5c51 1583
624d5c51 1584 return 1; /* irq handled */
624d5c51
TH
1585}
1586
1587/**
c3b28894
TH
1588 * ata_sff_port_intr - Handle SFF port interrupt
1589 * @ap: Port on which interrupt arrived (possibly...)
1590 * @qc: Taskfile currently active in engine
624d5c51 1591 *
c3b28894 1592 * Handle port interrupt for given queued command.
624d5c51
TH
1593 *
1594 * LOCKING:
c3b28894 1595 * spin_lock_irqsave(host lock)
624d5c51
TH
1596 *
1597 * RETURNS:
c3b28894 1598 * One if interrupt was handled, zero if not (shared irq).
624d5c51 1599 */
c3b28894
TH
1600unsigned int ata_sff_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
1601{
1602 return __ata_sff_port_intr(ap, qc, false);
1603}
1604EXPORT_SYMBOL_GPL(ata_sff_port_intr);
1605
1606static inline irqreturn_t __ata_sff_interrupt(int irq, void *dev_instance,
1607 unsigned int (*port_intr)(struct ata_port *, struct ata_queued_cmd *))
624d5c51
TH
1608{
1609 struct ata_host *host = dev_instance;
332ac7ff 1610 bool retried = false;
624d5c51 1611 unsigned int i;
332ac7ff 1612 unsigned int handled, idle, polling;
624d5c51
TH
1613 unsigned long flags;
1614
1615 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1616 spin_lock_irqsave(&host->lock, flags);
1617
332ac7ff
TH
1618retry:
1619 handled = idle = polling = 0;
624d5c51 1620 for (i = 0; i < host->n_ports; i++) {
d88ec2e5
TH
1621 struct ata_port *ap = host->ports[i];
1622 struct ata_queued_cmd *qc;
624d5c51 1623
d88ec2e5 1624 qc = ata_qc_from_tag(ap, ap->link.active_tag);
27943620
TH
1625 if (qc) {
1626 if (!(qc->tf.flags & ATA_TFLAG_POLLING))
c3b28894 1627 handled |= port_intr(ap, qc);
27943620
TH
1628 else
1629 polling |= 1 << i;
332ac7ff
TH
1630 } else
1631 idle |= 1 << i;
27943620
TH
1632 }
1633
1634 /*
1635 * If no port was expecting IRQ but the controller is actually
1636 * asserting IRQ line, nobody cared will ensue. Check IRQ
1637 * pending status if available and clear spurious IRQ.
1638 */
332ac7ff
TH
1639 if (!handled && !retried) {
1640 bool retry = false;
1641
27943620
TH
1642 for (i = 0; i < host->n_ports; i++) {
1643 struct ata_port *ap = host->ports[i];
1644
1645 if (polling & (1 << i))
1646 continue;
1647
1648 if (!ap->ops->sff_irq_check ||
1649 !ap->ops->sff_irq_check(ap))
1650 continue;
1651
332ac7ff
TH
1652 if (idle & (1 << i)) {
1653 ap->ops->sff_check_status(ap);
37f65b8b
TH
1654 if (ap->ops->sff_irq_clear)
1655 ap->ops->sff_irq_clear(ap);
332ac7ff
TH
1656 } else {
1657 /* clear INTRQ and check if BUSY cleared */
1658 if (!(ap->ops->sff_check_status(ap) & ATA_BUSY))
1659 retry |= true;
1660 /*
1661 * With command in flight, we can't do
1662 * sff_irq_clear() w/o racing with completion.
1663 */
1664 }
1665 }
1666
1667 if (retry) {
1668 retried = true;
1669 goto retry;
27943620 1670 }
624d5c51
TH
1671 }
1672
1673 spin_unlock_irqrestore(&host->lock, flags);
1674
1675 return IRQ_RETVAL(handled);
1676}
c3b28894
TH
1677
1678/**
1679 * ata_sff_interrupt - Default SFF ATA host interrupt handler
1680 * @irq: irq line (unused)
1681 * @dev_instance: pointer to our ata_host information structure
1682 *
1683 * Default interrupt handler for PCI IDE devices. Calls
1684 * ata_sff_port_intr() for each port that is not disabled.
1685 *
1686 * LOCKING:
1687 * Obtains host lock during operation.
1688 *
1689 * RETURNS:
1690 * IRQ_NONE or IRQ_HANDLED.
1691 */
1692irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
1693{
1694 return __ata_sff_interrupt(irq, dev_instance, ata_sff_port_intr);
1695}
0fe40ff8 1696EXPORT_SYMBOL_GPL(ata_sff_interrupt);
624d5c51 1697
c96f1732
AC
1698/**
1699 * ata_sff_lost_interrupt - Check for an apparent lost interrupt
1700 * @ap: port that appears to have timed out
1701 *
1702 * Called from the libata error handlers when the core code suspects
1703 * an interrupt has been lost. If it has complete anything we can and
1704 * then return. Interface must support altstatus for this faster
1705 * recovery to occur.
1706 *
1707 * Locking:
1708 * Caller holds host lock
1709 */
1710
1711void ata_sff_lost_interrupt(struct ata_port *ap)
1712{
1713 u8 status;
1714 struct ata_queued_cmd *qc;
1715
1716 /* Only one outstanding command per SFF channel */
1717 qc = ata_qc_from_tag(ap, ap->link.active_tag);
3e4ec344
TH
1718 /* We cannot lose an interrupt on a non-existent or polled command */
1719 if (!qc || qc->tf.flags & ATA_TFLAG_POLLING)
c96f1732
AC
1720 return;
1721 /* See if the controller thinks it is still busy - if so the command
1722 isn't a lost IRQ but is still in progress */
1723 status = ata_sff_altstatus(ap);
1724 if (status & ATA_BUSY)
1725 return;
1726
1727 /* There was a command running, we are no longer busy and we have
1728 no interrupt. */
a9a79dfe 1729 ata_port_warn(ap, "lost interrupt (Status 0x%x)\n",
c96f1732
AC
1730 status);
1731 /* Run the host interrupt logic as if the interrupt had not been
1732 lost */
c3b28894 1733 ata_sff_port_intr(ap, qc);
c96f1732
AC
1734}
1735EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt);
1736
624d5c51 1737/**
9363c382 1738 * ata_sff_freeze - Freeze SFF controller port
624d5c51
TH
1739 * @ap: port to freeze
1740 *
9f2f7210 1741 * Freeze SFF controller port.
624d5c51
TH
1742 *
1743 * LOCKING:
1744 * Inherited from caller.
1745 */
9363c382 1746void ata_sff_freeze(struct ata_port *ap)
624d5c51 1747{
624d5c51
TH
1748 ap->ctl |= ATA_NIEN;
1749 ap->last_ctl = ap->ctl;
1750
41dec29b
SS
1751 if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr)
1752 ata_sff_set_devctl(ap, ap->ctl);
624d5c51
TH
1753
1754 /* Under certain circumstances, some controllers raise IRQ on
1755 * ATA_NIEN manipulation. Also, many controllers fail to mask
1756 * previously pending IRQ on ATA_NIEN assertion. Clear it.
1757 */
5682ed33 1758 ap->ops->sff_check_status(ap);
624d5c51 1759
37f65b8b
TH
1760 if (ap->ops->sff_irq_clear)
1761 ap->ops->sff_irq_clear(ap);
624d5c51 1762}
0fe40ff8 1763EXPORT_SYMBOL_GPL(ata_sff_freeze);
624d5c51
TH
1764
1765/**
9363c382 1766 * ata_sff_thaw - Thaw SFF controller port
624d5c51
TH
1767 * @ap: port to thaw
1768 *
9363c382 1769 * Thaw SFF controller port.
624d5c51
TH
1770 *
1771 * LOCKING:
1772 * Inherited from caller.
1773 */
9363c382 1774void ata_sff_thaw(struct ata_port *ap)
272f7884 1775{
624d5c51 1776 /* clear & re-enable interrupts */
5682ed33 1777 ap->ops->sff_check_status(ap);
37f65b8b
TH
1778 if (ap->ops->sff_irq_clear)
1779 ap->ops->sff_irq_clear(ap);
e42a542b 1780 ata_sff_irq_on(ap);
272f7884 1781}
0fe40ff8 1782EXPORT_SYMBOL_GPL(ata_sff_thaw);
272f7884 1783
0aa1113d
TH
1784/**
1785 * ata_sff_prereset - prepare SFF link for reset
1786 * @link: SFF link to be reset
1787 * @deadline: deadline jiffies for the operation
1788 *
1789 * SFF link @link is about to be reset. Initialize it. It first
1790 * calls ata_std_prereset() and wait for !BSY if the port is
1791 * being softreset.
1792 *
1793 * LOCKING:
1794 * Kernel thread context (may sleep)
1795 *
1796 * RETURNS:
1797 * 0 on success, -errno otherwise.
1798 */
1799int ata_sff_prereset(struct ata_link *link, unsigned long deadline)
1800{
0aa1113d
TH
1801 struct ata_eh_context *ehc = &link->eh_context;
1802 int rc;
1803
1804 rc = ata_std_prereset(link, deadline);
1805 if (rc)
1806 return rc;
1807
1808 /* if we're about to do hardreset, nothing more to do */
1809 if (ehc->i.action & ATA_EH_HARDRESET)
1810 return 0;
1811
1812 /* wait for !BSY if we don't know that no device is attached */
1813 if (!ata_link_offline(link)) {
705e76be 1814 rc = ata_sff_wait_ready(link, deadline);
0aa1113d 1815 if (rc && rc != -ENODEV) {
a9a79dfe
JP
1816 ata_link_warn(link,
1817 "device not ready (errno=%d), forcing hardreset\n",
1818 rc);
0aa1113d
TH
1819 ehc->i.action |= ATA_EH_HARDRESET;
1820 }
1821 }
1822
1823 return 0;
1824}
0fe40ff8 1825EXPORT_SYMBOL_GPL(ata_sff_prereset);
0aa1113d 1826
90088bb4 1827/**
624d5c51
TH
1828 * ata_devchk - PATA device presence detection
1829 * @ap: ATA channel to examine
1830 * @device: Device to examine (starting at zero)
90088bb4 1831 *
624d5c51
TH
1832 * This technique was originally described in
1833 * Hale Landis's ATADRVR (www.ata-atapi.com), and
1834 * later found its way into the ATA/ATAPI spec.
1835 *
1836 * Write a pattern to the ATA shadow registers,
1837 * and if a device is present, it will respond by
1838 * correctly storing and echoing back the
1839 * ATA shadow register contents.
90088bb4
TH
1840 *
1841 * LOCKING:
624d5c51 1842 * caller.
90088bb4 1843 */
624d5c51 1844static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
90088bb4
TH
1845{
1846 struct ata_ioports *ioaddr = &ap->ioaddr;
624d5c51 1847 u8 nsect, lbal;
90088bb4 1848
5682ed33 1849 ap->ops->sff_dev_select(ap, device);
90088bb4 1850
624d5c51
TH
1851 iowrite8(0x55, ioaddr->nsect_addr);
1852 iowrite8(0xaa, ioaddr->lbal_addr);
90088bb4 1853
624d5c51
TH
1854 iowrite8(0xaa, ioaddr->nsect_addr);
1855 iowrite8(0x55, ioaddr->lbal_addr);
90088bb4 1856
624d5c51
TH
1857 iowrite8(0x55, ioaddr->nsect_addr);
1858 iowrite8(0xaa, ioaddr->lbal_addr);
1859
1860 nsect = ioread8(ioaddr->nsect_addr);
1861 lbal = ioread8(ioaddr->lbal_addr);
1862
1863 if ((nsect == 0x55) && (lbal == 0xaa))
1864 return 1; /* we found a device */
1865
1866 return 0; /* nothing found */
90088bb4
TH
1867}
1868
272f7884 1869/**
9363c382 1870 * ata_sff_dev_classify - Parse returned ATA device signature
624d5c51
TH
1871 * @dev: ATA device to classify (starting at zero)
1872 * @present: device seems present
1873 * @r_err: Value of error register on completion
272f7884 1874 *
624d5c51
TH
1875 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
1876 * an ATA/ATAPI-defined set of values is placed in the ATA
1877 * shadow registers, indicating the results of device detection
1878 * and diagnostics.
272f7884 1879 *
624d5c51
TH
1880 * Select the ATA device, and read the values from the ATA shadow
1881 * registers. Then parse according to the Error register value,
1882 * and the spec-defined values examined by ata_dev_classify().
272f7884
TH
1883 *
1884 * LOCKING:
624d5c51
TH
1885 * caller.
1886 *
1887 * RETURNS:
1888 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
272f7884 1889 */
9363c382 1890unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
624d5c51 1891 u8 *r_err)
272f7884 1892{
624d5c51
TH
1893 struct ata_port *ap = dev->link->ap;
1894 struct ata_taskfile tf;
1895 unsigned int class;
1896 u8 err;
1897
5682ed33 1898 ap->ops->sff_dev_select(ap, dev->devno);
624d5c51
TH
1899
1900 memset(&tf, 0, sizeof(tf));
1901
5682ed33 1902 ap->ops->sff_tf_read(ap, &tf);
624d5c51
TH
1903 err = tf.feature;
1904 if (r_err)
1905 *r_err = err;
1906
1907 /* see if device passed diags: continue and warn later */
1908 if (err == 0)
1909 /* diagnostic fail : do nothing _YET_ */
1910 dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
1911 else if (err == 1)
1912 /* do nothing */ ;
1913 else if ((dev->devno == 0) && (err == 0x81))
1914 /* do nothing */ ;
1915 else
1916 return ATA_DEV_NONE;
272f7884 1917
624d5c51
TH
1918 /* determine if device is ATA or ATAPI */
1919 class = ata_dev_classify(&tf);
272f7884 1920
624d5c51
TH
1921 if (class == ATA_DEV_UNKNOWN) {
1922 /* If the device failed diagnostic, it's likely to
1923 * have reported incorrect device signature too.
1924 * Assume ATA device if the device seems present but
1925 * device signature is invalid with diagnostic
1926 * failure.
1927 */
1928 if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
1929 class = ATA_DEV_ATA;
1930 else
1931 class = ATA_DEV_NONE;
5682ed33
TH
1932 } else if ((class == ATA_DEV_ATA) &&
1933 (ap->ops->sff_check_status(ap) == 0))
624d5c51
TH
1934 class = ATA_DEV_NONE;
1935
1936 return class;
272f7884 1937}
0fe40ff8 1938EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
272f7884 1939
705e76be
TH
1940/**
1941 * ata_sff_wait_after_reset - wait for devices to become ready after reset
1942 * @link: SFF link which is just reset
1943 * @devmask: mask of present devices
1944 * @deadline: deadline jiffies for the operation
1945 *
1946 * Wait devices attached to SFF @link to become ready after
1947 * reset. It contains preceding 150ms wait to avoid accessing TF
1948 * status register too early.
1949 *
1950 * LOCKING:
1951 * Kernel thread context (may sleep).
1952 *
1953 * RETURNS:
1954 * 0 on success, -ENODEV if some or all of devices in @devmask
1955 * don't seem to exist. -errno on other errors.
1956 */
1957int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
1958 unsigned long deadline)
1fdffbce 1959{
705e76be 1960 struct ata_port *ap = link->ap;
1fdffbce 1961 struct ata_ioports *ioaddr = &ap->ioaddr;
624d5c51
TH
1962 unsigned int dev0 = devmask & (1 << 0);
1963 unsigned int dev1 = devmask & (1 << 1);
1964 int rc, ret = 0;
1fdffbce 1965
97750ceb 1966 ata_msleep(ap, ATA_WAIT_AFTER_RESET);
705e76be
TH
1967
1968 /* always check readiness of the master device */
1969 rc = ata_sff_wait_ready(link, deadline);
1970 /* -ENODEV means the odd clown forgot the D7 pulldown resistor
1971 * and TF status is 0xff, bail out on it too.
624d5c51 1972 */
705e76be
TH
1973 if (rc)
1974 return rc;
1fdffbce 1975
624d5c51
TH
1976 /* if device 1 was found in ata_devchk, wait for register
1977 * access briefly, then wait for BSY to clear.
1978 */
1979 if (dev1) {
1980 int i;
1fdffbce 1981
5682ed33 1982 ap->ops->sff_dev_select(ap, 1);
1fdffbce 1983
624d5c51
TH
1984 /* Wait for register access. Some ATAPI devices fail
1985 * to set nsect/lbal after reset, so don't waste too
1986 * much time on it. We're gonna wait for !BSY anyway.
1987 */
1988 for (i = 0; i < 2; i++) {
1989 u8 nsect, lbal;
1990
1991 nsect = ioread8(ioaddr->nsect_addr);
1992 lbal = ioread8(ioaddr->lbal_addr);
1993 if ((nsect == 1) && (lbal == 1))
1994 break;
97750ceb 1995 ata_msleep(ap, 50); /* give drive a breather */
624d5c51
TH
1996 }
1997
705e76be 1998 rc = ata_sff_wait_ready(link, deadline);
624d5c51
TH
1999 if (rc) {
2000 if (rc != -ENODEV)
2001 return rc;
2002 ret = rc;
2003 }
1fdffbce
JG
2004 }
2005
624d5c51 2006 /* is all this really necessary? */
5682ed33 2007 ap->ops->sff_dev_select(ap, 0);
624d5c51 2008 if (dev1)
5682ed33 2009 ap->ops->sff_dev_select(ap, 1);
624d5c51 2010 if (dev0)
5682ed33 2011 ap->ops->sff_dev_select(ap, 0);
624d5c51
TH
2012
2013 return ret;
1fdffbce 2014}
0fe40ff8 2015EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset);
1fdffbce 2016
624d5c51
TH
2017static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
2018 unsigned long deadline)
2cc432ee 2019{
624d5c51 2020 struct ata_ioports *ioaddr = &ap->ioaddr;
2cc432ee 2021
624d5c51
TH
2022 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
2023
6d8ca28f
OZ
2024 if (ap->ioaddr.ctl_addr) {
2025 /* software reset. causes dev0 to be selected */
2026 iowrite8(ap->ctl, ioaddr->ctl_addr);
2027 udelay(20); /* FIXME: flush */
2028 iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
2029 udelay(20); /* FIXME: flush */
2030 iowrite8(ap->ctl, ioaddr->ctl_addr);
2031 ap->last_ctl = ap->ctl;
2032 }
624d5c51 2033
705e76be
TH
2034 /* wait the port to become ready */
2035 return ata_sff_wait_after_reset(&ap->link, devmask, deadline);
2cc432ee
JG
2036}
2037
6d97dbd7 2038/**
9363c382 2039 * ata_sff_softreset - reset host port via ATA SRST
624d5c51
TH
2040 * @link: ATA link to reset
2041 * @classes: resulting classes of attached devices
2042 * @deadline: deadline jiffies for the operation
6d97dbd7 2043 *
624d5c51 2044 * Reset host port using ATA SRST.
6d97dbd7
TH
2045 *
2046 * LOCKING:
624d5c51
TH
2047 * Kernel thread context (may sleep)
2048 *
2049 * RETURNS:
2050 * 0 on success, -errno otherwise.
6d97dbd7 2051 */
9363c382 2052int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
624d5c51 2053 unsigned long deadline)
6d97dbd7 2054{
624d5c51
TH
2055 struct ata_port *ap = link->ap;
2056 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2057 unsigned int devmask = 0;
2058 int rc;
2059 u8 err;
6d97dbd7 2060
624d5c51 2061 DPRINTK("ENTER\n");
6d97dbd7 2062
624d5c51
TH
2063 /* determine if device 0/1 are present */
2064 if (ata_devchk(ap, 0))
2065 devmask |= (1 << 0);
2066 if (slave_possible && ata_devchk(ap, 1))
2067 devmask |= (1 << 1);
2068
2069 /* select device 0 again */
5682ed33 2070 ap->ops->sff_dev_select(ap, 0);
624d5c51
TH
2071
2072 /* issue bus reset */
2073 DPRINTK("about to softreset, devmask=%x\n", devmask);
2074 rc = ata_bus_softreset(ap, devmask, deadline);
2075 /* if link is occupied, -ENODEV too is an error */
2076 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
a9a79dfe 2077 ata_link_err(link, "SRST failed (errno=%d)\n", rc);
624d5c51
TH
2078 return rc;
2079 }
0f0a3ad3 2080
624d5c51 2081 /* determine by signature whether we have ATA or ATAPI devices */
9363c382 2082 classes[0] = ata_sff_dev_classify(&link->device[0],
624d5c51
TH
2083 devmask & (1 << 0), &err);
2084 if (slave_possible && err != 0x81)
9363c382 2085 classes[1] = ata_sff_dev_classify(&link->device[1],
624d5c51
TH
2086 devmask & (1 << 1), &err);
2087
624d5c51
TH
2088 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
2089 return 0;
6d97dbd7 2090}
0fe40ff8 2091EXPORT_SYMBOL_GPL(ata_sff_softreset);
6d97dbd7
TH
2092
2093/**
9363c382 2094 * sata_sff_hardreset - reset host port via SATA phy reset
624d5c51
TH
2095 * @link: link to reset
2096 * @class: resulting class of attached device
2097 * @deadline: deadline jiffies for the operation
6d97dbd7 2098 *
624d5c51
TH
2099 * SATA phy-reset host port using DET bits of SControl register,
2100 * wait for !BSY and classify the attached device.
6d97dbd7
TH
2101 *
2102 * LOCKING:
624d5c51
TH
2103 * Kernel thread context (may sleep)
2104 *
2105 * RETURNS:
2106 * 0 on success, -errno otherwise.
6d97dbd7 2107 */
9363c382 2108int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
624d5c51 2109 unsigned long deadline)
6d97dbd7 2110{
9dadd45b
TH
2111 struct ata_eh_context *ehc = &link->eh_context;
2112 const unsigned long *timing = sata_ehc_deb_timing(ehc);
2113 bool online;
624d5c51
TH
2114 int rc;
2115
9dadd45b
TH
2116 rc = sata_link_hardreset(link, timing, deadline, &online,
2117 ata_sff_check_ready);
9dadd45b
TH
2118 if (online)
2119 *class = ata_sff_dev_classify(link->device, 1, NULL);
624d5c51
TH
2120
2121 DPRINTK("EXIT, class=%u\n", *class);
9dadd45b 2122 return rc;
6d97dbd7 2123}
0fe40ff8 2124EXPORT_SYMBOL_GPL(sata_sff_hardreset);
6d97dbd7 2125
203c75b8
TH
2126/**
2127 * ata_sff_postreset - SFF postreset callback
2128 * @link: the target SFF ata_link
2129 * @classes: classes of attached devices
2130 *
2131 * This function is invoked after a successful reset. It first
2132 * calls ata_std_postreset() and performs SFF specific postreset
2133 * processing.
2134 *
2135 * LOCKING:
2136 * Kernel thread context (may sleep)
2137 */
2138void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
2139{
2140 struct ata_port *ap = link->ap;
2141
2142 ata_std_postreset(link, classes);
2143
2144 /* is double-select really necessary? */
2145 if (classes[0] != ATA_DEV_NONE)
2146 ap->ops->sff_dev_select(ap, 1);
2147 if (classes[1] != ATA_DEV_NONE)
2148 ap->ops->sff_dev_select(ap, 0);
2149
2150 /* bail out if no device is present */
2151 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2152 DPRINTK("EXIT, no device\n");
2153 return;
2154 }
2155
2156 /* set up device control */
41dec29b
SS
2157 if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) {
2158 ata_sff_set_devctl(ap, ap->ctl);
e3e4385f
SM
2159 ap->last_ctl = ap->ctl;
2160 }
203c75b8 2161}
0fe40ff8 2162EXPORT_SYMBOL_GPL(ata_sff_postreset);
203c75b8 2163
3d47aa8e
AC
2164/**
2165 * ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers
2166 * @qc: command
2167 *
2168 * Drain the FIFO and device of any stuck data following a command
3ad2f3fb 2169 * failing to complete. In some cases this is necessary before a
3d47aa8e
AC
2170 * reset will recover the device.
2171 *
2172 */
2173
2174void ata_sff_drain_fifo(struct ata_queued_cmd *qc)
2175{
2176 int count;
2177 struct ata_port *ap;
2178
2179 /* We only need to flush incoming data when a command was running */
2180 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
2181 return;
2182
2183 ap = qc->ap;
2184 /* Drain up to 64K of data before we give up this recovery method */
2185 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ)
9a8fd68b 2186 && count < 65536; count += 2)
3d47aa8e
AC
2187 ioread16(ap->ioaddr.data_addr);
2188
2189 /* Can become DEBUG later */
2190 if (count)
a9a79dfe 2191 ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
3d47aa8e
AC
2192
2193}
2194EXPORT_SYMBOL_GPL(ata_sff_drain_fifo);
2195
6d97dbd7 2196/**
fe06e5f9 2197 * ata_sff_error_handler - Stock error handler for SFF controller
6d97dbd7 2198 * @ap: port to handle error for
6d97dbd7 2199 *
9363c382 2200 * Stock error handler for SFF controller. It can handle both
6d97dbd7
TH
2201 * PATA and SATA controllers. Many controllers should be able to
2202 * use this EH as-is or with some added handling before and
2203 * after.
2204 *
6d97dbd7
TH
2205 * LOCKING:
2206 * Kernel thread context (may sleep)
2207 */
9363c382 2208void ata_sff_error_handler(struct ata_port *ap)
6d97dbd7 2209{
a1efdaba
TH
2210 ata_reset_fn_t softreset = ap->ops->softreset;
2211 ata_reset_fn_t hardreset = ap->ops->hardreset;
6d97dbd7
TH
2212 struct ata_queued_cmd *qc;
2213 unsigned long flags;
6d97dbd7 2214
9af5c9c9 2215 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
6d97dbd7
TH
2216 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2217 qc = NULL;
2218
ba6a1308 2219 spin_lock_irqsave(ap->lock, flags);
6d97dbd7 2220
fe06e5f9
TH
2221 /*
2222 * We *MUST* do FIFO draining before we issue a reset as
2223 * several devices helpfully clear their internal state and
2224 * will lock solid if we touch the data port post reset. Pass
2225 * qc in case anyone wants to do different PIO/DMA recovery or
2226 * has per command fixups
3d47aa8e 2227 */
8244cd05
TH
2228 if (ap->ops->sff_drain_fifo)
2229 ap->ops->sff_drain_fifo(qc);
6d97dbd7 2230
ba6a1308 2231 spin_unlock_irqrestore(ap->lock, flags);
6d97dbd7 2232
fe06e5f9
TH
2233 /* ignore built-in hardresets if SCR access is not available */
2234 if ((hardreset == sata_std_hardreset ||
2235 hardreset == sata_sff_hardreset) && !sata_scr_valid(&ap->link))
a1efdaba 2236 hardreset = NULL;
6d97dbd7 2237
a1efdaba
TH
2238 ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
2239 ap->ops->postreset);
6d97dbd7 2240}
0fe40ff8 2241EXPORT_SYMBOL_GPL(ata_sff_error_handler);
6d97dbd7 2242
624d5c51 2243/**
9363c382 2244 * ata_sff_std_ports - initialize ioaddr with standard port offsets.
624d5c51
TH
2245 * @ioaddr: IO address structure to be initialized
2246 *
2247 * Utility function which initializes data_addr, error_addr,
2248 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
2249 * device_addr, status_addr, and command_addr to standard offsets
2250 * relative to cmd_addr.
2251 *
2252 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
2253 */
9363c382 2254void ata_sff_std_ports(struct ata_ioports *ioaddr)
624d5c51
TH
2255{
2256 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
2257 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
2258 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
2259 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
2260 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
2261 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
2262 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
2263 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
2264 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
2265 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
2266}
0fe40ff8 2267EXPORT_SYMBOL_GPL(ata_sff_std_ports);
624d5c51 2268
1fdffbce 2269#ifdef CONFIG_PCI
4112e16a 2270
272f7884
TH
2271static int ata_resources_present(struct pci_dev *pdev, int port)
2272{
2273 int i;
2274
2275 /* Check the PCI resources for this channel are enabled */
2276 port = port * 2;
0fe40ff8 2277 for (i = 0; i < 2; i++) {
272f7884
TH
2278 if (pci_resource_start(pdev, port + i) == 0 ||
2279 pci_resource_len(pdev, port + i) == 0)
2280 return 0;
2281 }
2282 return 1;
2283}
2284
d491b27b 2285/**
9363c382 2286 * ata_pci_sff_init_host - acquire native PCI ATA resources and init host
d491b27b 2287 * @host: target ATA host
d491b27b 2288 *
1626aeb8
TH
2289 * Acquire native PCI ATA resources for @host and initialize the
2290 * first two ports of @host accordingly. Ports marked dummy are
2291 * skipped and allocation failure makes the port dummy.
d491b27b 2292 *
d583bc18
TH
2293 * Note that native PCI resources are valid even for legacy hosts
2294 * as we fix up pdev resources array early in boot, so this
2295 * function can be used for both native and legacy SFF hosts.
2296 *
d491b27b
TH
2297 * LOCKING:
2298 * Inherited from calling layer (may sleep).
2299 *
2300 * RETURNS:
1626aeb8
TH
2301 * 0 if at least one port is initialized, -ENODEV if no port is
2302 * available.
d491b27b 2303 */
9363c382 2304int ata_pci_sff_init_host(struct ata_host *host)
d491b27b
TH
2305{
2306 struct device *gdev = host->dev;
2307 struct pci_dev *pdev = to_pci_dev(gdev);
1626aeb8 2308 unsigned int mask = 0;
d491b27b
TH
2309 int i, rc;
2310
d491b27b
TH
2311 /* request, iomap BARs and init port addresses accordingly */
2312 for (i = 0; i < 2; i++) {
2313 struct ata_port *ap = host->ports[i];
2314 int base = i * 2;
2315 void __iomem * const *iomap;
2316
1626aeb8
TH
2317 if (ata_port_is_dummy(ap))
2318 continue;
2319
2320 /* Discard disabled ports. Some controllers show
2321 * their unused channels this way. Disabled ports are
2322 * made dummy.
2323 */
2324 if (!ata_resources_present(pdev, i)) {
2325 ap->ops = &ata_dummy_port_ops;
d491b27b 2326 continue;
1626aeb8 2327 }
d491b27b 2328
35a10a80
TH
2329 rc = pcim_iomap_regions(pdev, 0x3 << base,
2330 dev_driver_string(gdev));
d491b27b 2331 if (rc) {
a44fec1f
JP
2332 dev_warn(gdev,
2333 "failed to request/iomap BARs for port %d (errno=%d)\n",
2334 i, rc);
d491b27b
TH
2335 if (rc == -EBUSY)
2336 pcim_pin_device(pdev);
1626aeb8
TH
2337 ap->ops = &ata_dummy_port_ops;
2338 continue;
d491b27b
TH
2339 }
2340 host->iomap = iomap = pcim_iomap_table(pdev);
2341
2342 ap->ioaddr.cmd_addr = iomap[base];
2343 ap->ioaddr.altstatus_addr =
2344 ap->ioaddr.ctl_addr = (void __iomem *)
2345 ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
9363c382 2346 ata_sff_std_ports(&ap->ioaddr);
1626aeb8 2347
cbcdd875
TH
2348 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
2349 (unsigned long long)pci_resource_start(pdev, base),
2350 (unsigned long long)pci_resource_start(pdev, base + 1));
2351
1626aeb8
TH
2352 mask |= 1 << i;
2353 }
2354
2355 if (!mask) {
a44fec1f 2356 dev_err(gdev, "no available native port\n");
1626aeb8 2357 return -ENODEV;
d491b27b
TH
2358 }
2359
2360 return 0;
2361}
0fe40ff8 2362EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
d491b27b 2363
21b0ad4f 2364/**
1c5afdf7 2365 * ata_pci_sff_prepare_host - helper to prepare PCI PIO-only SFF ATA host
21b0ad4f 2366 * @pdev: target PCI device
1626aeb8 2367 * @ppi: array of port_info, must be enough for two ports
21b0ad4f
TH
2368 * @r_host: out argument for the initialized ATA host
2369 *
1c5afdf7
TH
2370 * Helper to allocate PIO-only SFF ATA host for @pdev, acquire
2371 * all PCI resources and initialize it accordingly in one go.
21b0ad4f
TH
2372 *
2373 * LOCKING:
2374 * Inherited from calling layer (may sleep).
2375 *
2376 * RETURNS:
2377 * 0 on success, -errno otherwise.
2378 */
9363c382 2379int ata_pci_sff_prepare_host(struct pci_dev *pdev,
0fe40ff8 2380 const struct ata_port_info * const *ppi,
d583bc18 2381 struct ata_host **r_host)
21b0ad4f
TH
2382{
2383 struct ata_host *host;
21b0ad4f
TH
2384 int rc;
2385
2386 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
2387 return -ENOMEM;
2388
2389 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
2390 if (!host) {
a44fec1f 2391 dev_err(&pdev->dev, "failed to allocate ATA host\n");
21b0ad4f
TH
2392 rc = -ENOMEM;
2393 goto err_out;
2394 }
2395
9363c382 2396 rc = ata_pci_sff_init_host(host);
21b0ad4f
TH
2397 if (rc)
2398 goto err_out;
2399
21b0ad4f
TH
2400 devres_remove_group(&pdev->dev, NULL);
2401 *r_host = host;
2402 return 0;
2403
0fe40ff8 2404err_out:
21b0ad4f
TH
2405 devres_release_group(&pdev->dev, NULL);
2406 return rc;
2407}
0fe40ff8 2408EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
21b0ad4f 2409
4e6b79fa 2410/**
9363c382 2411 * ata_pci_sff_activate_host - start SFF host, request IRQ and register it
4e6b79fa
TH
2412 * @host: target SFF ATA host
2413 * @irq_handler: irq_handler used when requesting IRQ(s)
2414 * @sht: scsi_host_template to use when registering the host
2415 *
2416 * This is the counterpart of ata_host_activate() for SFF ATA
2417 * hosts. This separate helper is necessary because SFF hosts
2418 * use two separate interrupts in legacy mode.
2419 *
2420 * LOCKING:
2421 * Inherited from calling layer (may sleep).
2422 *
2423 * RETURNS:
2424 * 0 on success, -errno otherwise.
2425 */
9363c382 2426int ata_pci_sff_activate_host(struct ata_host *host,
4e6b79fa
TH
2427 irq_handler_t irq_handler,
2428 struct scsi_host_template *sht)
2429{
2430 struct device *dev = host->dev;
2431 struct pci_dev *pdev = to_pci_dev(dev);
2432 const char *drv_name = dev_driver_string(host->dev);
2433 int legacy_mode = 0, rc;
2434
2435 rc = ata_host_start(host);
2436 if (rc)
2437 return rc;
2438
2439 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
2440 u8 tmp8, mask;
2441
2442 /* TODO: What if one channel is in native mode ... */
2443 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
2444 mask = (1 << 2) | (1 << 0);
2445 if ((tmp8 & mask) != mask)
2446 legacy_mode = 1;
4e6b79fa
TH
2447 }
2448
2449 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2450 return -ENOMEM;
2451
2452 if (!legacy_mode && pdev->irq) {
af649a1b
JB
2453 int i;
2454
4e6b79fa
TH
2455 rc = devm_request_irq(dev, pdev->irq, irq_handler,
2456 IRQF_SHARED, drv_name, host);
2457 if (rc)
2458 goto out;
2459
af649a1b
JB
2460 for (i = 0; i < 2; i++) {
2461 if (ata_port_is_dummy(host->ports[i]))
2462 continue;
2463 ata_port_desc(host->ports[i], "irq %d", pdev->irq);
2464 }
4e6b79fa
TH
2465 } else if (legacy_mode) {
2466 if (!ata_port_is_dummy(host->ports[0])) {
2467 rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
2468 irq_handler, IRQF_SHARED,
2469 drv_name, host);
2470 if (rc)
2471 goto out;
2472
2473 ata_port_desc(host->ports[0], "irq %d",
2474 ATA_PRIMARY_IRQ(pdev));
2475 }
2476
2477 if (!ata_port_is_dummy(host->ports[1])) {
2478 rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
2479 irq_handler, IRQF_SHARED,
2480 drv_name, host);
2481 if (rc)
2482 goto out;
2483
2484 ata_port_desc(host->ports[1], "irq %d",
2485 ATA_SECONDARY_IRQ(pdev));
2486 }
2487 }
2488
2489 rc = ata_host_register(host, sht);
0fe40ff8 2490out:
4e6b79fa
TH
2491 if (rc == 0)
2492 devres_remove_group(dev, NULL);
2493 else
2494 devres_release_group(dev, NULL);
2495
2496 return rc;
2497}
0fe40ff8 2498EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
4e6b79fa 2499
1c5afdf7
TH
2500static const struct ata_port_info *ata_sff_find_valid_pi(
2501 const struct ata_port_info * const *ppi)
2502{
2503 int i;
2504
2505 /* look up the first valid port_info */
2506 for (i = 0; i < 2 && ppi[i]; i++)
2507 if (ppi[i]->port_ops != &ata_dummy_port_ops)
2508 return ppi[i];
2509
2510 return NULL;
2511}
2512
c2036033
BZ
2513static int ata_pci_init_one(struct pci_dev *pdev,
2514 const struct ata_port_info * const *ppi,
2515 struct scsi_host_template *sht, void *host_priv,
2516 int hflags, bool bmdma)
1fdffbce 2517{
f0d36efd 2518 struct device *dev = &pdev->dev;
1c5afdf7 2519 const struct ata_port_info *pi;
0f834de3 2520 struct ata_host *host = NULL;
1c5afdf7 2521 int rc;
1fdffbce
JG
2522
2523 DPRINTK("ENTER\n");
2524
1c5afdf7 2525 pi = ata_sff_find_valid_pi(ppi);
1626aeb8 2526 if (!pi) {
a44fec1f 2527 dev_err(&pdev->dev, "no valid port_info specified\n");
1626aeb8
TH
2528 return -EINVAL;
2529 }
c791c306 2530
1626aeb8
TH
2531 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2532 return -ENOMEM;
1fdffbce 2533
f0d36efd 2534 rc = pcim_enable_device(pdev);
1fdffbce 2535 if (rc)
4e6b79fa 2536 goto out;
1fdffbce 2537
aab94404 2538#ifdef CONFIG_ATA_BMDMA
c2036033
BZ
2539 if (bmdma)
2540 /* prepare and activate BMDMA host */
2541 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
2542 else
aab94404 2543#endif
c2036033
BZ
2544 /* prepare and activate SFF host */
2545 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
d583bc18 2546 if (rc)
4e6b79fa 2547 goto out;
887125e3 2548 host->private_data = host_priv;
c2036033 2549 host->flags |= hflags;
d491b27b 2550
aab94404 2551#ifdef CONFIG_ATA_BMDMA
c2036033
BZ
2552 if (bmdma) {
2553 pci_set_master(pdev);
2554 rc = ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
2555 } else
aab94404 2556#endif
c2036033 2557 rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
0fe40ff8 2558out:
4e6b79fa
TH
2559 if (rc == 0)
2560 devres_remove_group(&pdev->dev, NULL);
2561 else
2562 devres_release_group(&pdev->dev, NULL);
d491b27b 2563
1fdffbce
JG
2564 return rc;
2565}
c2036033
BZ
2566
2567/**
2568 * ata_pci_sff_init_one - Initialize/register PIO-only PCI IDE controller
2569 * @pdev: Controller to be initialized
2570 * @ppi: array of port_info, must be enough for two ports
2571 * @sht: scsi_host_template to use when registering the host
2572 * @host_priv: host private_data
2573 * @hflag: host flags
2574 *
2575 * This is a helper function which can be called from a driver's
2576 * xxx_init_one() probe function if the hardware uses traditional
2577 * IDE taskfile registers and is PIO only.
2578 *
2579 * ASSUMPTION:
2580 * Nobody makes a single channel controller that appears solely as
2581 * the secondary legacy port on PCI.
2582 *
2583 * LOCKING:
2584 * Inherited from PCI layer (may sleep).
2585 *
2586 * RETURNS:
2587 * Zero on success, negative on errno-based value on error.
2588 */
2589int ata_pci_sff_init_one(struct pci_dev *pdev,
2590 const struct ata_port_info * const *ppi,
2591 struct scsi_host_template *sht, void *host_priv, int hflag)
2592{
2593 return ata_pci_init_one(pdev, ppi, sht, host_priv, hflag, 0);
2594}
0fe40ff8 2595EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
1fdffbce
JG
2596
2597#endif /* CONFIG_PCI */
9f2f7210 2598
9a7780c9
TH
2599/*
2600 * BMDMA support
2601 */
2602
2603#ifdef CONFIG_ATA_BMDMA
2604
9f2f7210
TH
2605const struct ata_port_operations ata_bmdma_port_ops = {
2606 .inherits = &ata_sff_port_ops,
2607
fe06e5f9
TH
2608 .error_handler = ata_bmdma_error_handler,
2609 .post_internal_cmd = ata_bmdma_post_internal_cmd,
2610
f47451c4 2611 .qc_prep = ata_bmdma_qc_prep,
360ff783 2612 .qc_issue = ata_bmdma_qc_issue,
f47451c4 2613
37f65b8b 2614 .sff_irq_clear = ata_bmdma_irq_clear,
9f2f7210
TH
2615 .bmdma_setup = ata_bmdma_setup,
2616 .bmdma_start = ata_bmdma_start,
2617 .bmdma_stop = ata_bmdma_stop,
2618 .bmdma_status = ata_bmdma_status,
c7087652
TH
2619
2620 .port_start = ata_bmdma_port_start,
9f2f7210
TH
2621};
2622EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
2623
2624const struct ata_port_operations ata_bmdma32_port_ops = {
2625 .inherits = &ata_bmdma_port_ops,
2626
2627 .sff_data_xfer = ata_sff_data_xfer32,
c7087652 2628 .port_start = ata_bmdma_port_start32,
9f2f7210
TH
2629};
2630EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops);
2631
f47451c4
TH
2632/**
2633 * ata_bmdma_fill_sg - Fill PCI IDE PRD table
2634 * @qc: Metadata associated with taskfile to be transferred
2635 *
2636 * Fill PCI IDE PRD (scatter-gather) table with segments
2637 * associated with the current disk command.
2638 *
2639 * LOCKING:
2640 * spin_lock_irqsave(host lock)
2641 *
2642 */
2643static void ata_bmdma_fill_sg(struct ata_queued_cmd *qc)
2644{
2645 struct ata_port *ap = qc->ap;
f60d7011 2646 struct ata_bmdma_prd *prd = ap->bmdma_prd;
f47451c4
TH
2647 struct scatterlist *sg;
2648 unsigned int si, pi;
2649
2650 pi = 0;
2651 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2652 u32 addr, offset;
2653 u32 sg_len, len;
2654
2655 /* determine if physical DMA addr spans 64K boundary.
2656 * Note h/w doesn't support 64-bit, so we unconditionally
2657 * truncate dma_addr_t to u32.
2658 */
2659 addr = (u32) sg_dma_address(sg);
2660 sg_len = sg_dma_len(sg);
2661
2662 while (sg_len) {
2663 offset = addr & 0xffff;
2664 len = sg_len;
2665 if ((offset + sg_len) > 0x10000)
2666 len = 0x10000 - offset;
2667
f60d7011
TH
2668 prd[pi].addr = cpu_to_le32(addr);
2669 prd[pi].flags_len = cpu_to_le32(len & 0xffff);
f47451c4
TH
2670 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
2671
2672 pi++;
2673 sg_len -= len;
2674 addr += len;
2675 }
2676 }
2677
f60d7011 2678 prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
f47451c4
TH
2679}
2680
2681/**
2682 * ata_bmdma_fill_sg_dumb - Fill PCI IDE PRD table
2683 * @qc: Metadata associated with taskfile to be transferred
2684 *
2685 * Fill PCI IDE PRD (scatter-gather) table with segments
2686 * associated with the current disk command. Perform the fill
2687 * so that we avoid writing any length 64K records for
2688 * controllers that don't follow the spec.
2689 *
2690 * LOCKING:
2691 * spin_lock_irqsave(host lock)
2692 *
2693 */
2694static void ata_bmdma_fill_sg_dumb(struct ata_queued_cmd *qc)
2695{
2696 struct ata_port *ap = qc->ap;
f60d7011 2697 struct ata_bmdma_prd *prd = ap->bmdma_prd;
f47451c4
TH
2698 struct scatterlist *sg;
2699 unsigned int si, pi;
2700
2701 pi = 0;
2702 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2703 u32 addr, offset;
2704 u32 sg_len, len, blen;
2705
2706 /* determine if physical DMA addr spans 64K boundary.
2707 * Note h/w doesn't support 64-bit, so we unconditionally
2708 * truncate dma_addr_t to u32.
2709 */
2710 addr = (u32) sg_dma_address(sg);
2711 sg_len = sg_dma_len(sg);
2712
2713 while (sg_len) {
2714 offset = addr & 0xffff;
2715 len = sg_len;
2716 if ((offset + sg_len) > 0x10000)
2717 len = 0x10000 - offset;
2718
2719 blen = len & 0xffff;
f60d7011 2720 prd[pi].addr = cpu_to_le32(addr);
f47451c4
TH
2721 if (blen == 0) {
2722 /* Some PATA chipsets like the CS5530 can't
2723 cope with 0x0000 meaning 64K as the spec
2724 says */
f60d7011 2725 prd[pi].flags_len = cpu_to_le32(0x8000);
f47451c4 2726 blen = 0x8000;
f60d7011 2727 prd[++pi].addr = cpu_to_le32(addr + 0x8000);
f47451c4 2728 }
f60d7011 2729 prd[pi].flags_len = cpu_to_le32(blen);
f47451c4
TH
2730 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
2731
2732 pi++;
2733 sg_len -= len;
2734 addr += len;
2735 }
2736 }
2737
f60d7011 2738 prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
f47451c4
TH
2739}
2740
2741/**
2742 * ata_bmdma_qc_prep - Prepare taskfile for submission
2743 * @qc: Metadata associated with taskfile to be prepared
2744 *
2745 * Prepare ATA taskfile for submission.
2746 *
2747 * LOCKING:
2748 * spin_lock_irqsave(host lock)
2749 */
2750void ata_bmdma_qc_prep(struct ata_queued_cmd *qc)
2751{
2752 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2753 return;
2754
2755 ata_bmdma_fill_sg(qc);
2756}
2757EXPORT_SYMBOL_GPL(ata_bmdma_qc_prep);
2758
2759/**
2760 * ata_bmdma_dumb_qc_prep - Prepare taskfile for submission
2761 * @qc: Metadata associated with taskfile to be prepared
2762 *
2763 * Prepare ATA taskfile for submission.
2764 *
2765 * LOCKING:
2766 * spin_lock_irqsave(host lock)
2767 */
2768void ata_bmdma_dumb_qc_prep(struct ata_queued_cmd *qc)
2769{
2770 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2771 return;
2772
2773 ata_bmdma_fill_sg_dumb(qc);
2774}
2775EXPORT_SYMBOL_GPL(ata_bmdma_dumb_qc_prep);
2776
360ff783
TH
2777/**
2778 * ata_bmdma_qc_issue - issue taskfile to a BMDMA controller
2779 * @qc: command to issue to device
2780 *
2781 * This function issues a PIO, NODATA or DMA command to a
2782 * SFF/BMDMA controller. PIO and NODATA are handled by
2783 * ata_sff_qc_issue().
2784 *
2785 * LOCKING:
2786 * spin_lock_irqsave(host lock)
2787 *
2788 * RETURNS:
2789 * Zero on success, AC_ERR_* mask on failure
2790 */
2791unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd *qc)
2792{
2793 struct ata_port *ap = qc->ap;
ea3c6450 2794 struct ata_link *link = qc->dev->link;
360ff783 2795
360ff783
TH
2796 /* defer PIO handling to sff_qc_issue */
2797 if (!ata_is_dma(qc->tf.protocol))
2798 return ata_sff_qc_issue(qc);
2799
2800 /* select the device */
2801 ata_dev_select(ap, qc->dev->devno, 1, 0);
2802
2803 /* start the command */
2804 switch (qc->tf.protocol) {
2805 case ATA_PROT_DMA:
2806 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
2807
2808 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2809 ap->ops->bmdma_setup(qc); /* set up bmdma */
2810 ap->ops->bmdma_start(qc); /* initiate bmdma */
2811 ap->hsm_task_state = HSM_ST_LAST;
2812 break;
2813
2814 case ATAPI_PROT_DMA:
2815 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
2816
2817 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2818 ap->ops->bmdma_setup(qc); /* set up bmdma */
2819 ap->hsm_task_state = HSM_ST_FIRST;
2820
2821 /* send cdb by polling if no cdb interrupt */
2822 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
ea3c6450 2823 ata_sff_queue_pio_task(link, 0);
360ff783
TH
2824 break;
2825
2826 default:
2827 WARN_ON(1);
2828 return AC_ERR_SYSTEM;
2829 }
2830
2831 return 0;
2832}
2833EXPORT_SYMBOL_GPL(ata_bmdma_qc_issue);
2834
c3b28894
TH
2835/**
2836 * ata_bmdma_port_intr - Handle BMDMA port interrupt
2837 * @ap: Port on which interrupt arrived (possibly...)
2838 * @qc: Taskfile currently active in engine
2839 *
2840 * Handle port interrupt for given queued command.
2841 *
2842 * LOCKING:
2843 * spin_lock_irqsave(host lock)
2844 *
2845 * RETURNS:
2846 * One if interrupt was handled, zero if not (shared irq).
2847 */
2848unsigned int ata_bmdma_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
2849{
2850 struct ata_eh_info *ehi = &ap->link.eh_info;
2851 u8 host_stat = 0;
2852 bool bmdma_stopped = false;
2853 unsigned int handled;
2854
2855 if (ap->hsm_task_state == HSM_ST_LAST && ata_is_dma(qc->tf.protocol)) {
2856 /* check status of DMA engine */
2857 host_stat = ap->ops->bmdma_status(ap);
2858 VPRINTK("ata%u: host_stat 0x%X\n", ap->print_id, host_stat);
2859
2860 /* if it's not our irq... */
2861 if (!(host_stat & ATA_DMA_INTR))
2862 return ata_sff_idle_irq(ap);
2863
2864 /* before we do anything else, clear DMA-Start bit */
2865 ap->ops->bmdma_stop(qc);
2866 bmdma_stopped = true;
2867
2868 if (unlikely(host_stat & ATA_DMA_ERR)) {
25985edc 2869 /* error when transferring data to/from memory */
c3b28894
TH
2870 qc->err_mask |= AC_ERR_HOST_BUS;
2871 ap->hsm_task_state = HSM_ST_ERR;
2872 }
2873 }
2874
2875 handled = __ata_sff_port_intr(ap, qc, bmdma_stopped);
2876
2877 if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
2878 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
2879
2880 return handled;
2881}
2882EXPORT_SYMBOL_GPL(ata_bmdma_port_intr);
2883
2884/**
2885 * ata_bmdma_interrupt - Default BMDMA ATA host interrupt handler
2886 * @irq: irq line (unused)
2887 * @dev_instance: pointer to our ata_host information structure
2888 *
2889 * Default interrupt handler for PCI IDE devices. Calls
2890 * ata_bmdma_port_intr() for each port that is not disabled.
2891 *
2892 * LOCKING:
2893 * Obtains host lock during operation.
2894 *
2895 * RETURNS:
2896 * IRQ_NONE or IRQ_HANDLED.
2897 */
2898irqreturn_t ata_bmdma_interrupt(int irq, void *dev_instance)
2899{
2900 return __ata_sff_interrupt(irq, dev_instance, ata_bmdma_port_intr);
2901}
2902EXPORT_SYMBOL_GPL(ata_bmdma_interrupt);
2903
fe06e5f9
TH
2904/**
2905 * ata_bmdma_error_handler - Stock error handler for BMDMA controller
2906 * @ap: port to handle error for
2907 *
2908 * Stock error handler for BMDMA controller. It can handle both
2909 * PATA and SATA controllers. Most BMDMA controllers should be
2910 * able to use this EH as-is or with some added handling before
2911 * and after.
2912 *
2913 * LOCKING:
2914 * Kernel thread context (may sleep)
2915 */
2916void ata_bmdma_error_handler(struct ata_port *ap)
2917{
2918 struct ata_queued_cmd *qc;
2919 unsigned long flags;
2920 bool thaw = false;
2921
2922 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2923 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2924 qc = NULL;
2925
2926 /* reset PIO HSM and stop DMA engine */
2927 spin_lock_irqsave(ap->lock, flags);
2928
2929 if (qc && ata_is_dma(qc->tf.protocol)) {
2930 u8 host_stat;
2931
2932 host_stat = ap->ops->bmdma_status(ap);
2933
2934 /* BMDMA controllers indicate host bus error by
2935 * setting DMA_ERR bit and timing out. As it wasn't
2936 * really a timeout event, adjust error mask and
2937 * cancel frozen state.
2938 */
2939 if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
2940 qc->err_mask = AC_ERR_HOST_BUS;
2941 thaw = true;
2942 }
2943
2944 ap->ops->bmdma_stop(qc);
2945
2946 /* if we're gonna thaw, make sure IRQ is clear */
2947 if (thaw) {
2948 ap->ops->sff_check_status(ap);
37f65b8b
TH
2949 if (ap->ops->sff_irq_clear)
2950 ap->ops->sff_irq_clear(ap);
fe06e5f9
TH
2951 }
2952 }
2953
2954 spin_unlock_irqrestore(ap->lock, flags);
2955
2956 if (thaw)
2957 ata_eh_thaw_port(ap);
2958
2959 ata_sff_error_handler(ap);
2960}
2961EXPORT_SYMBOL_GPL(ata_bmdma_error_handler);
2962
2963/**
2964 * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for BMDMA
2965 * @qc: internal command to clean up
2966 *
2967 * LOCKING:
2968 * Kernel thread context (may sleep)
2969 */
2970void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc)
2971{
2972 struct ata_port *ap = qc->ap;
2973 unsigned long flags;
2974
2975 if (ata_is_dma(qc->tf.protocol)) {
2976 spin_lock_irqsave(ap->lock, flags);
2977 ap->ops->bmdma_stop(qc);
2978 spin_unlock_irqrestore(ap->lock, flags);
2979 }
2980}
2981EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd);
2982
37f65b8b
TH
2983/**
2984 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
2985 * @ap: Port associated with this ATA transaction.
2986 *
2987 * Clear interrupt and error flags in DMA status register.
2988 *
2989 * May be used as the irq_clear() entry in ata_port_operations.
2990 *
2991 * LOCKING:
2992 * spin_lock_irqsave(host lock)
2993 */
2994void ata_bmdma_irq_clear(struct ata_port *ap)
2995{
2996 void __iomem *mmio = ap->ioaddr.bmdma_addr;
2997
2998 if (!mmio)
2999 return;
3000
3001 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
3002}
3003EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
3004
9f2f7210
TH
3005/**
3006 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
3007 * @qc: Info associated with this ATA transaction.
3008 *
3009 * LOCKING:
3010 * spin_lock_irqsave(host lock)
3011 */
3012void ata_bmdma_setup(struct ata_queued_cmd *qc)
3013{
3014 struct ata_port *ap = qc->ap;
3015 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
3016 u8 dmactl;
3017
3018 /* load PRD table addr. */
3019 mb(); /* make sure PRD table writes are visible to controller */
f60d7011 3020 iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
9f2f7210
TH
3021
3022 /* specify data direction, triple-check start bit is clear */
3023 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3024 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
3025 if (!rw)
3026 dmactl |= ATA_DMA_WR;
3027 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3028
3029 /* issue r/w command */
3030 ap->ops->sff_exec_command(ap, &qc->tf);
3031}
3032EXPORT_SYMBOL_GPL(ata_bmdma_setup);
3033
3034/**
3035 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
3036 * @qc: Info associated with this ATA transaction.
3037 *
3038 * LOCKING:
3039 * spin_lock_irqsave(host lock)
3040 */
3041void ata_bmdma_start(struct ata_queued_cmd *qc)
3042{
3043 struct ata_port *ap = qc->ap;
3044 u8 dmactl;
3045
3046 /* start host DMA transaction */
3047 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3048 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3049
3050 /* Strictly, one may wish to issue an ioread8() here, to
3051 * flush the mmio write. However, control also passes
3052 * to the hardware at this point, and it will interrupt
3053 * us when we are to resume control. So, in effect,
3054 * we don't care when the mmio write flushes.
3055 * Further, a read of the DMA status register _immediately_
3056 * following the write may not be what certain flaky hardware
3057 * is expected, so I think it is best to not add a readb()
3058 * without first all the MMIO ATA cards/mobos.
3059 * Or maybe I'm just being paranoid.
3060 *
3061 * FIXME: The posting of this write means I/O starts are
25985edc 3062 * unnecessarily delayed for MMIO
9f2f7210
TH
3063 */
3064}
3065EXPORT_SYMBOL_GPL(ata_bmdma_start);
3066
3067/**
3068 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
3069 * @qc: Command we are ending DMA for
3070 *
3071 * Clears the ATA_DMA_START flag in the dma control register
3072 *
3073 * May be used as the bmdma_stop() entry in ata_port_operations.
3074 *
3075 * LOCKING:
3076 * spin_lock_irqsave(host lock)
3077 */
3078void ata_bmdma_stop(struct ata_queued_cmd *qc)
3079{
3080 struct ata_port *ap = qc->ap;
3081 void __iomem *mmio = ap->ioaddr.bmdma_addr;
3082
3083 /* clear start/stop bit */
3084 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
3085 mmio + ATA_DMA_CMD);
3086
3087 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
3088 ata_sff_dma_pause(ap);
3089}
3090EXPORT_SYMBOL_GPL(ata_bmdma_stop);
3091
3092/**
3093 * ata_bmdma_status - Read PCI IDE BMDMA status
3094 * @ap: Port associated with this ATA transaction.
3095 *
3096 * Read and return BMDMA status register.
3097 *
3098 * May be used as the bmdma_status() entry in ata_port_operations.
3099 *
3100 * LOCKING:
3101 * spin_lock_irqsave(host lock)
3102 */
3103u8 ata_bmdma_status(struct ata_port *ap)
3104{
3105 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
3106}
3107EXPORT_SYMBOL_GPL(ata_bmdma_status);
3108
c7087652
TH
3109
3110/**
3111 * ata_bmdma_port_start - Set port up for bmdma.
3112 * @ap: Port to initialize
3113 *
3114 * Called just after data structures for each port are
3115 * initialized. Allocates space for PRD table.
3116 *
3117 * May be used as the port_start() entry in ata_port_operations.
3118 *
3119 * LOCKING:
3120 * Inherited from caller.
3121 */
3122int ata_bmdma_port_start(struct ata_port *ap)
3123{
3124 if (ap->mwdma_mask || ap->udma_mask) {
f60d7011
TH
3125 ap->bmdma_prd =
3126 dmam_alloc_coherent(ap->host->dev, ATA_PRD_TBL_SZ,
3127 &ap->bmdma_prd_dma, GFP_KERNEL);
3128 if (!ap->bmdma_prd)
c7087652
TH
3129 return -ENOMEM;
3130 }
3131
3132 return 0;
3133}
3134EXPORT_SYMBOL_GPL(ata_bmdma_port_start);
3135
3136/**
3137 * ata_bmdma_port_start32 - Set port up for dma.
3138 * @ap: Port to initialize
3139 *
3140 * Called just after data structures for each port are
3141 * initialized. Enables 32bit PIO and allocates space for PRD
3142 * table.
3143 *
3144 * May be used as the port_start() entry in ata_port_operations for
3145 * devices that are capable of 32bit PIO.
3146 *
3147 * LOCKING:
3148 * Inherited from caller.
3149 */
3150int ata_bmdma_port_start32(struct ata_port *ap)
3151{
3152 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
3153 return ata_bmdma_port_start(ap);
3154}
3155EXPORT_SYMBOL_GPL(ata_bmdma_port_start32);
3156
9f2f7210
TH
3157#ifdef CONFIG_PCI
3158
3159/**
3160 * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex
3161 * @pdev: PCI device
3162 *
3163 * Some PCI ATA devices report simplex mode but in fact can be told to
3164 * enter non simplex mode. This implements the necessary logic to
3165 * perform the task on such devices. Calling it on other devices will
3166 * have -undefined- behaviour.
3167 */
3168int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
3169{
3170 unsigned long bmdma = pci_resource_start(pdev, 4);
3171 u8 simplex;
3172
3173 if (bmdma == 0)
3174 return -ENOENT;
3175
3176 simplex = inb(bmdma + 0x02);
3177 outb(simplex & 0x60, bmdma + 0x02);
3178 simplex = inb(bmdma + 0x02);
3179 if (simplex & 0x80)
3180 return -EOPNOTSUPP;
3181 return 0;
3182}
3183EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
3184
c7087652
TH
3185static void ata_bmdma_nodma(struct ata_host *host, const char *reason)
3186{
3187 int i;
3188
a44fec1f 3189 dev_err(host->dev, "BMDMA: %s, falling back to PIO\n", reason);
c7087652
TH
3190
3191 for (i = 0; i < 2; i++) {
3192 host->ports[i]->mwdma_mask = 0;
3193 host->ports[i]->udma_mask = 0;
3194 }
3195}
3196
9f2f7210
TH
3197/**
3198 * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
3199 * @host: target ATA host
3200 *
3201 * Acquire PCI BMDMA resources and initialize @host accordingly.
3202 *
3203 * LOCKING:
3204 * Inherited from calling layer (may sleep).
9f2f7210 3205 */
c7087652 3206void ata_pci_bmdma_init(struct ata_host *host)
9f2f7210
TH
3207{
3208 struct device *gdev = host->dev;
3209 struct pci_dev *pdev = to_pci_dev(gdev);
3210 int i, rc;
3211
3212 /* No BAR4 allocation: No DMA */
c7087652
TH
3213 if (pci_resource_start(pdev, 4) == 0) {
3214 ata_bmdma_nodma(host, "BAR4 is zero");
3215 return;
3216 }
9f2f7210 3217
c7087652
TH
3218 /*
3219 * Some controllers require BMDMA region to be initialized
3220 * even if DMA is not in use to clear IRQ status via
3221 * ->sff_irq_clear method. Try to initialize bmdma_addr
3222 * regardless of dma masks.
3223 */
c54c719b 3224 rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK);
9f2f7210 3225 if (rc)
c7087652
TH
3226 ata_bmdma_nodma(host, "failed to set dma mask");
3227 if (!rc) {
c54c719b 3228 rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK);
c7087652
TH
3229 if (rc)
3230 ata_bmdma_nodma(host,
3231 "failed to set consistent dma mask");
3232 }
9f2f7210
TH
3233
3234 /* request and iomap DMA region */
3235 rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
3236 if (rc) {
c7087652
TH
3237 ata_bmdma_nodma(host, "failed to request/iomap BAR4");
3238 return;
9f2f7210
TH
3239 }
3240 host->iomap = pcim_iomap_table(pdev);
3241
3242 for (i = 0; i < 2; i++) {
3243 struct ata_port *ap = host->ports[i];
3244 void __iomem *bmdma = host->iomap[4] + 8 * i;
3245
3246 if (ata_port_is_dummy(ap))
3247 continue;
3248
3249 ap->ioaddr.bmdma_addr = bmdma;
3250 if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
3251 (ioread8(bmdma + 2) & 0x80))
3252 host->flags |= ATA_HOST_SIMPLEX;
3253
3254 ata_port_desc(ap, "bmdma 0x%llx",
3255 (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
3256 }
9f2f7210
TH
3257}
3258EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
3259
1c5afdf7
TH
3260/**
3261 * ata_pci_bmdma_prepare_host - helper to prepare PCI BMDMA ATA host
3262 * @pdev: target PCI device
3263 * @ppi: array of port_info, must be enough for two ports
3264 * @r_host: out argument for the initialized ATA host
3265 *
3266 * Helper to allocate BMDMA ATA host for @pdev, acquire all PCI
3267 * resources and initialize it accordingly in one go.
3268 *
3269 * LOCKING:
3270 * Inherited from calling layer (may sleep).
3271 *
3272 * RETURNS:
3273 * 0 on success, -errno otherwise.
3274 */
3275int ata_pci_bmdma_prepare_host(struct pci_dev *pdev,
3276 const struct ata_port_info * const * ppi,
3277 struct ata_host **r_host)
3278{
3279 int rc;
3280
3281 rc = ata_pci_sff_prepare_host(pdev, ppi, r_host);
3282 if (rc)
3283 return rc;
3284
3285 ata_pci_bmdma_init(*r_host);
3286 return 0;
3287}
3288EXPORT_SYMBOL_GPL(ata_pci_bmdma_prepare_host);
3289
3290/**
3291 * ata_pci_bmdma_init_one - Initialize/register BMDMA PCI IDE controller
3292 * @pdev: Controller to be initialized
3293 * @ppi: array of port_info, must be enough for two ports
3294 * @sht: scsi_host_template to use when registering the host
3295 * @host_priv: host private_data
3296 * @hflags: host flags
3297 *
3298 * This function is similar to ata_pci_sff_init_one() but also
3299 * takes care of BMDMA initialization.
3300 *
3301 * LOCKING:
3302 * Inherited from PCI layer (may sleep).
3303 *
3304 * RETURNS:
3305 * Zero on success, negative on errno-based value on error.
3306 */
3307int ata_pci_bmdma_init_one(struct pci_dev *pdev,
3308 const struct ata_port_info * const * ppi,
3309 struct scsi_host_template *sht, void *host_priv,
3310 int hflags)
3311{
c2036033 3312 return ata_pci_init_one(pdev, ppi, sht, host_priv, hflags, 1);
1c5afdf7
TH
3313}
3314EXPORT_SYMBOL_GPL(ata_pci_bmdma_init_one);
3315
9f2f7210 3316#endif /* CONFIG_PCI */
9a7780c9 3317#endif /* CONFIG_ATA_BMDMA */
270390e1
TH
3318
3319/**
3320 * ata_sff_port_init - Initialize SFF/BMDMA ATA port
3321 * @ap: Port to initialize
3322 *
3323 * Called on port allocation to initialize SFF/BMDMA specific
3324 * fields.
3325 *
3326 * LOCKING:
3327 * None.
3328 */
3329void ata_sff_port_init(struct ata_port *ap)
3330{
c429137a 3331 INIT_DELAYED_WORK(&ap->sff_pio_task, ata_sff_pio_task);
5fe7454a
TH
3332 ap->ctl = ATA_DEVCTL_OBS;
3333 ap->last_ctl = 0xFF;
270390e1
TH
3334}
3335
3336int __init ata_sff_init(void)
3337{
6370a6ad 3338 ata_sff_wq = alloc_workqueue("ata_sff", WQ_MEM_RECLAIM, WQ_MAX_ACTIVE);
c429137a
TH
3339 if (!ata_sff_wq)
3340 return -ENOMEM;
3341
270390e1
TH
3342 return 0;
3343}
3344
c43d559f 3345void ata_sff_exit(void)
270390e1 3346{
c429137a 3347 destroy_workqueue(ata_sff_wq);
270390e1 3348}