Commit | Line | Data |
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1fdffbce | 1 | /* |
f3a03b09 | 2 | * libata-sff.c - helper library for PCI IDE BMDMA |
1fdffbce JG |
3 | * |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2006 Red Hat, Inc. All rights reserved. | |
9 | * Copyright 2003-2006 Jeff Garzik | |
10 | * | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
28 | * as Documentation/DocBook/libata.* | |
29 | * | |
30 | * Hardware documentation available from http://www.t13.org/ and | |
31 | * http://www.sata-io.org/ | |
32 | * | |
33 | */ | |
34 | ||
1fdffbce | 35 | #include <linux/kernel.h> |
5a0e3ad6 | 36 | #include <linux/gfp.h> |
1fdffbce JG |
37 | #include <linux/pci.h> |
38 | #include <linux/libata.h> | |
624d5c51 | 39 | #include <linux/highmem.h> |
1fdffbce JG |
40 | |
41 | #include "libata.h" | |
42 | ||
624d5c51 TH |
43 | const struct ata_port_operations ata_sff_port_ops = { |
44 | .inherits = &ata_base_port_ops, | |
45 | ||
9363c382 TH |
46 | .qc_prep = ata_sff_qc_prep, |
47 | .qc_issue = ata_sff_qc_issue, | |
4c9bf4e7 | 48 | .qc_fill_rtf = ata_sff_qc_fill_rtf, |
9363c382 TH |
49 | |
50 | .freeze = ata_sff_freeze, | |
51 | .thaw = ata_sff_thaw, | |
0aa1113d | 52 | .prereset = ata_sff_prereset, |
9363c382 | 53 | .softreset = ata_sff_softreset, |
57c9efdf | 54 | .hardreset = sata_sff_hardreset, |
203c75b8 | 55 | .postreset = ata_sff_postreset, |
3d47aa8e | 56 | .drain_fifo = ata_sff_drain_fifo, |
9363c382 TH |
57 | .error_handler = ata_sff_error_handler, |
58 | .post_internal_cmd = ata_sff_post_internal_cmd, | |
59 | ||
5682ed33 TH |
60 | .sff_dev_select = ata_sff_dev_select, |
61 | .sff_check_status = ata_sff_check_status, | |
62 | .sff_tf_load = ata_sff_tf_load, | |
63 | .sff_tf_read = ata_sff_tf_read, | |
64 | .sff_exec_command = ata_sff_exec_command, | |
65 | .sff_data_xfer = ata_sff_data_xfer, | |
66 | .sff_irq_on = ata_sff_irq_on, | |
288623a0 | 67 | .sff_irq_clear = ata_sff_irq_clear, |
624d5c51 | 68 | |
c96f1732 AC |
69 | .lost_interrupt = ata_sff_lost_interrupt, |
70 | ||
624d5c51 TH |
71 | .port_start = ata_sff_port_start, |
72 | }; | |
0fe40ff8 | 73 | EXPORT_SYMBOL_GPL(ata_sff_port_ops); |
624d5c51 TH |
74 | |
75 | const struct ata_port_operations ata_bmdma_port_ops = { | |
76 | .inherits = &ata_sff_port_ops, | |
77 | ||
9363c382 | 78 | .mode_filter = ata_bmdma_mode_filter, |
624d5c51 TH |
79 | |
80 | .bmdma_setup = ata_bmdma_setup, | |
81 | .bmdma_start = ata_bmdma_start, | |
82 | .bmdma_stop = ata_bmdma_stop, | |
83 | .bmdma_status = ata_bmdma_status, | |
624d5c51 | 84 | }; |
0fe40ff8 | 85 | EXPORT_SYMBOL_GPL(ata_bmdma_port_ops); |
624d5c51 | 86 | |
871af121 AC |
87 | const struct ata_port_operations ata_bmdma32_port_ops = { |
88 | .inherits = &ata_bmdma_port_ops, | |
89 | ||
90 | .sff_data_xfer = ata_sff_data_xfer32, | |
e3cf95dd | 91 | .port_start = ata_sff_port_start32, |
871af121 AC |
92 | }; |
93 | EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops); | |
94 | ||
624d5c51 TH |
95 | /** |
96 | * ata_fill_sg - Fill PCI IDE PRD table | |
97 | * @qc: Metadata associated with taskfile to be transferred | |
98 | * | |
99 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
100 | * associated with the current disk command. | |
101 | * | |
102 | * LOCKING: | |
103 | * spin_lock_irqsave(host lock) | |
104 | * | |
105 | */ | |
106 | static void ata_fill_sg(struct ata_queued_cmd *qc) | |
107 | { | |
108 | struct ata_port *ap = qc->ap; | |
109 | struct scatterlist *sg; | |
110 | unsigned int si, pi; | |
111 | ||
112 | pi = 0; | |
113 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
114 | u32 addr, offset; | |
115 | u32 sg_len, len; | |
116 | ||
117 | /* determine if physical DMA addr spans 64K boundary. | |
118 | * Note h/w doesn't support 64-bit, so we unconditionally | |
119 | * truncate dma_addr_t to u32. | |
120 | */ | |
121 | addr = (u32) sg_dma_address(sg); | |
122 | sg_len = sg_dma_len(sg); | |
123 | ||
124 | while (sg_len) { | |
125 | offset = addr & 0xffff; | |
126 | len = sg_len; | |
127 | if ((offset + sg_len) > 0x10000) | |
128 | len = 0x10000 - offset; | |
129 | ||
130 | ap->prd[pi].addr = cpu_to_le32(addr); | |
131 | ap->prd[pi].flags_len = cpu_to_le32(len & 0xffff); | |
132 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); | |
133 | ||
134 | pi++; | |
135 | sg_len -= len; | |
136 | addr += len; | |
137 | } | |
138 | } | |
139 | ||
140 | ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); | |
141 | } | |
142 | ||
143 | /** | |
144 | * ata_fill_sg_dumb - Fill PCI IDE PRD table | |
145 | * @qc: Metadata associated with taskfile to be transferred | |
146 | * | |
147 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
148 | * associated with the current disk command. Perform the fill | |
149 | * so that we avoid writing any length 64K records for | |
150 | * controllers that don't follow the spec. | |
151 | * | |
152 | * LOCKING: | |
153 | * spin_lock_irqsave(host lock) | |
154 | * | |
155 | */ | |
156 | static void ata_fill_sg_dumb(struct ata_queued_cmd *qc) | |
157 | { | |
158 | struct ata_port *ap = qc->ap; | |
159 | struct scatterlist *sg; | |
160 | unsigned int si, pi; | |
161 | ||
162 | pi = 0; | |
163 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
164 | u32 addr, offset; | |
165 | u32 sg_len, len, blen; | |
166 | ||
167 | /* determine if physical DMA addr spans 64K boundary. | |
168 | * Note h/w doesn't support 64-bit, so we unconditionally | |
169 | * truncate dma_addr_t to u32. | |
170 | */ | |
171 | addr = (u32) sg_dma_address(sg); | |
172 | sg_len = sg_dma_len(sg); | |
173 | ||
174 | while (sg_len) { | |
175 | offset = addr & 0xffff; | |
176 | len = sg_len; | |
177 | if ((offset + sg_len) > 0x10000) | |
178 | len = 0x10000 - offset; | |
179 | ||
180 | blen = len & 0xffff; | |
181 | ap->prd[pi].addr = cpu_to_le32(addr); | |
182 | if (blen == 0) { | |
0fe40ff8 AC |
183 | /* Some PATA chipsets like the CS5530 can't |
184 | cope with 0x0000 meaning 64K as the spec | |
185 | says */ | |
624d5c51 TH |
186 | ap->prd[pi].flags_len = cpu_to_le32(0x8000); |
187 | blen = 0x8000; | |
188 | ap->prd[++pi].addr = cpu_to_le32(addr + 0x8000); | |
189 | } | |
190 | ap->prd[pi].flags_len = cpu_to_le32(blen); | |
191 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); | |
192 | ||
193 | pi++; | |
194 | sg_len -= len; | |
195 | addr += len; | |
196 | } | |
197 | } | |
198 | ||
199 | ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); | |
200 | } | |
201 | ||
202 | /** | |
9363c382 | 203 | * ata_sff_qc_prep - Prepare taskfile for submission |
624d5c51 TH |
204 | * @qc: Metadata associated with taskfile to be prepared |
205 | * | |
206 | * Prepare ATA taskfile for submission. | |
207 | * | |
208 | * LOCKING: | |
209 | * spin_lock_irqsave(host lock) | |
210 | */ | |
9363c382 | 211 | void ata_sff_qc_prep(struct ata_queued_cmd *qc) |
624d5c51 TH |
212 | { |
213 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
214 | return; | |
215 | ||
216 | ata_fill_sg(qc); | |
217 | } | |
0fe40ff8 | 218 | EXPORT_SYMBOL_GPL(ata_sff_qc_prep); |
624d5c51 TH |
219 | |
220 | /** | |
9363c382 | 221 | * ata_sff_dumb_qc_prep - Prepare taskfile for submission |
624d5c51 TH |
222 | * @qc: Metadata associated with taskfile to be prepared |
223 | * | |
224 | * Prepare ATA taskfile for submission. | |
225 | * | |
226 | * LOCKING: | |
227 | * spin_lock_irqsave(host lock) | |
228 | */ | |
9363c382 | 229 | void ata_sff_dumb_qc_prep(struct ata_queued_cmd *qc) |
624d5c51 TH |
230 | { |
231 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
232 | return; | |
233 | ||
234 | ata_fill_sg_dumb(qc); | |
235 | } | |
0fe40ff8 | 236 | EXPORT_SYMBOL_GPL(ata_sff_dumb_qc_prep); |
624d5c51 | 237 | |
272f7884 | 238 | /** |
9363c382 | 239 | * ata_sff_check_status - Read device status reg & clear interrupt |
272f7884 TH |
240 | * @ap: port where the device is |
241 | * | |
242 | * Reads ATA taskfile status register for currently-selected device | |
243 | * and return its value. This also clears pending interrupts | |
244 | * from this device | |
245 | * | |
246 | * LOCKING: | |
247 | * Inherited from caller. | |
248 | */ | |
9363c382 | 249 | u8 ata_sff_check_status(struct ata_port *ap) |
272f7884 TH |
250 | { |
251 | return ioread8(ap->ioaddr.status_addr); | |
252 | } | |
0fe40ff8 | 253 | EXPORT_SYMBOL_GPL(ata_sff_check_status); |
272f7884 TH |
254 | |
255 | /** | |
9363c382 | 256 | * ata_sff_altstatus - Read device alternate status reg |
272f7884 TH |
257 | * @ap: port where the device is |
258 | * | |
259 | * Reads ATA taskfile alternate status register for | |
260 | * currently-selected device and return its value. | |
261 | * | |
262 | * Note: may NOT be used as the check_altstatus() entry in | |
263 | * ata_port_operations. | |
264 | * | |
265 | * LOCKING: | |
266 | * Inherited from caller. | |
267 | */ | |
a57c1bad | 268 | static u8 ata_sff_altstatus(struct ata_port *ap) |
624d5c51 | 269 | { |
5682ed33 TH |
270 | if (ap->ops->sff_check_altstatus) |
271 | return ap->ops->sff_check_altstatus(ap); | |
624d5c51 TH |
272 | |
273 | return ioread8(ap->ioaddr.altstatus_addr); | |
274 | } | |
275 | ||
a57c1bad AC |
276 | /** |
277 | * ata_sff_irq_status - Check if the device is busy | |
278 | * @ap: port where the device is | |
279 | * | |
280 | * Determine if the port is currently busy. Uses altstatus | |
281 | * if available in order to avoid clearing shared IRQ status | |
282 | * when finding an IRQ source. Non ctl capable devices don't | |
283 | * share interrupt lines fortunately for us. | |
284 | * | |
285 | * LOCKING: | |
286 | * Inherited from caller. | |
287 | */ | |
288 | static u8 ata_sff_irq_status(struct ata_port *ap) | |
289 | { | |
290 | u8 status; | |
291 | ||
292 | if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) { | |
293 | status = ata_sff_altstatus(ap); | |
294 | /* Not us: We are busy */ | |
295 | if (status & ATA_BUSY) | |
0fe40ff8 | 296 | return status; |
a57c1bad AC |
297 | } |
298 | /* Clear INTRQ latch */ | |
6311c90a | 299 | status = ap->ops->sff_check_status(ap); |
a57c1bad AC |
300 | return status; |
301 | } | |
302 | ||
303 | /** | |
304 | * ata_sff_sync - Flush writes | |
305 | * @ap: Port to wait for. | |
306 | * | |
307 | * CAUTION: | |
308 | * If we have an mmio device with no ctl and no altstatus | |
309 | * method this will fail. No such devices are known to exist. | |
310 | * | |
311 | * LOCKING: | |
312 | * Inherited from caller. | |
313 | */ | |
314 | ||
315 | static void ata_sff_sync(struct ata_port *ap) | |
316 | { | |
317 | if (ap->ops->sff_check_altstatus) | |
318 | ap->ops->sff_check_altstatus(ap); | |
319 | else if (ap->ioaddr.altstatus_addr) | |
320 | ioread8(ap->ioaddr.altstatus_addr); | |
321 | } | |
322 | ||
323 | /** | |
324 | * ata_sff_pause - Flush writes and wait 400nS | |
325 | * @ap: Port to pause for. | |
326 | * | |
327 | * CAUTION: | |
328 | * If we have an mmio device with no ctl and no altstatus | |
329 | * method this will fail. No such devices are known to exist. | |
330 | * | |
331 | * LOCKING: | |
332 | * Inherited from caller. | |
333 | */ | |
334 | ||
335 | void ata_sff_pause(struct ata_port *ap) | |
336 | { | |
337 | ata_sff_sync(ap); | |
338 | ndelay(400); | |
339 | } | |
0fe40ff8 | 340 | EXPORT_SYMBOL_GPL(ata_sff_pause); |
a57c1bad AC |
341 | |
342 | /** | |
343 | * ata_sff_dma_pause - Pause before commencing DMA | |
344 | * @ap: Port to pause for. | |
345 | * | |
346 | * Perform I/O fencing and ensure sufficient cycle delays occur | |
347 | * for the HDMA1:0 transition | |
348 | */ | |
0fe40ff8 | 349 | |
a57c1bad AC |
350 | void ata_sff_dma_pause(struct ata_port *ap) |
351 | { | |
352 | if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) { | |
353 | /* An altstatus read will cause the needed delay without | |
354 | messing up the IRQ status */ | |
355 | ata_sff_altstatus(ap); | |
356 | return; | |
357 | } | |
358 | /* There are no DMA controllers without ctl. BUG here to ensure | |
359 | we never violate the HDMA1:0 transition timing and risk | |
360 | corruption. */ | |
361 | BUG(); | |
362 | } | |
0fe40ff8 | 363 | EXPORT_SYMBOL_GPL(ata_sff_dma_pause); |
a57c1bad | 364 | |
624d5c51 | 365 | /** |
9363c382 | 366 | * ata_sff_busy_sleep - sleep until BSY clears, or timeout |
624d5c51 | 367 | * @ap: port containing status register to be polled |
341c2c95 TH |
368 | * @tmout_pat: impatience timeout in msecs |
369 | * @tmout: overall timeout in msecs | |
624d5c51 TH |
370 | * |
371 | * Sleep until ATA Status register bit BSY clears, | |
372 | * or a timeout occurs. | |
373 | * | |
374 | * LOCKING: | |
375 | * Kernel thread context (may sleep). | |
376 | * | |
377 | * RETURNS: | |
378 | * 0 on success, -errno otherwise. | |
379 | */ | |
9363c382 TH |
380 | int ata_sff_busy_sleep(struct ata_port *ap, |
381 | unsigned long tmout_pat, unsigned long tmout) | |
624d5c51 TH |
382 | { |
383 | unsigned long timer_start, timeout; | |
384 | u8 status; | |
385 | ||
9363c382 | 386 | status = ata_sff_busy_wait(ap, ATA_BUSY, 300); |
624d5c51 | 387 | timer_start = jiffies; |
341c2c95 | 388 | timeout = ata_deadline(timer_start, tmout_pat); |
624d5c51 TH |
389 | while (status != 0xff && (status & ATA_BUSY) && |
390 | time_before(jiffies, timeout)) { | |
391 | msleep(50); | |
9363c382 | 392 | status = ata_sff_busy_wait(ap, ATA_BUSY, 3); |
624d5c51 TH |
393 | } |
394 | ||
395 | if (status != 0xff && (status & ATA_BUSY)) | |
396 | ata_port_printk(ap, KERN_WARNING, | |
397 | "port is slow to respond, please be patient " | |
398 | "(Status 0x%x)\n", status); | |
399 | ||
341c2c95 | 400 | timeout = ata_deadline(timer_start, tmout); |
624d5c51 TH |
401 | while (status != 0xff && (status & ATA_BUSY) && |
402 | time_before(jiffies, timeout)) { | |
403 | msleep(50); | |
5682ed33 | 404 | status = ap->ops->sff_check_status(ap); |
624d5c51 TH |
405 | } |
406 | ||
407 | if (status == 0xff) | |
408 | return -ENODEV; | |
409 | ||
410 | if (status & ATA_BUSY) { | |
411 | ata_port_printk(ap, KERN_ERR, "port failed to respond " | |
412 | "(%lu secs, Status 0x%x)\n", | |
341c2c95 | 413 | DIV_ROUND_UP(tmout, 1000), status); |
624d5c51 TH |
414 | return -EBUSY; |
415 | } | |
416 | ||
417 | return 0; | |
418 | } | |
0fe40ff8 | 419 | EXPORT_SYMBOL_GPL(ata_sff_busy_sleep); |
624d5c51 | 420 | |
aa2731ad TH |
421 | static int ata_sff_check_ready(struct ata_link *link) |
422 | { | |
423 | u8 status = link->ap->ops->sff_check_status(link->ap); | |
424 | ||
78ab88f0 | 425 | return ata_check_ready(status); |
aa2731ad TH |
426 | } |
427 | ||
624d5c51 | 428 | /** |
9363c382 | 429 | * ata_sff_wait_ready - sleep until BSY clears, or timeout |
705e76be | 430 | * @link: SFF link to wait ready status for |
624d5c51 TH |
431 | * @deadline: deadline jiffies for the operation |
432 | * | |
433 | * Sleep until ATA Status register bit BSY clears, or timeout | |
434 | * occurs. | |
435 | * | |
436 | * LOCKING: | |
437 | * Kernel thread context (may sleep). | |
438 | * | |
439 | * RETURNS: | |
440 | * 0 on success, -errno otherwise. | |
441 | */ | |
705e76be | 442 | int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline) |
624d5c51 | 443 | { |
aa2731ad | 444 | return ata_wait_ready(link, deadline, ata_sff_check_ready); |
624d5c51 | 445 | } |
0fe40ff8 | 446 | EXPORT_SYMBOL_GPL(ata_sff_wait_ready); |
624d5c51 | 447 | |
41dec29b SS |
448 | /** |
449 | * ata_sff_set_devctl - Write device control reg | |
450 | * @ap: port where the device is | |
451 | * @ctl: value to write | |
452 | * | |
453 | * Writes ATA taskfile device control register. | |
454 | * | |
455 | * Note: may NOT be used as the sff_set_devctl() entry in | |
456 | * ata_port_operations. | |
457 | * | |
458 | * LOCKING: | |
459 | * Inherited from caller. | |
460 | */ | |
461 | static void ata_sff_set_devctl(struct ata_port *ap, u8 ctl) | |
462 | { | |
463 | if (ap->ops->sff_set_devctl) | |
464 | ap->ops->sff_set_devctl(ap, ctl); | |
465 | else | |
466 | iowrite8(ctl, ap->ioaddr.ctl_addr); | |
467 | } | |
468 | ||
624d5c51 | 469 | /** |
9363c382 | 470 | * ata_sff_dev_select - Select device 0/1 on ATA bus |
624d5c51 TH |
471 | * @ap: ATA channel to manipulate |
472 | * @device: ATA device (numbered from zero) to select | |
473 | * | |
474 | * Use the method defined in the ATA specification to | |
475 | * make either device 0, or device 1, active on the | |
476 | * ATA channel. Works with both PIO and MMIO. | |
477 | * | |
478 | * May be used as the dev_select() entry in ata_port_operations. | |
479 | * | |
480 | * LOCKING: | |
481 | * caller. | |
482 | */ | |
9363c382 | 483 | void ata_sff_dev_select(struct ata_port *ap, unsigned int device) |
624d5c51 TH |
484 | { |
485 | u8 tmp; | |
486 | ||
487 | if (device == 0) | |
488 | tmp = ATA_DEVICE_OBS; | |
489 | else | |
490 | tmp = ATA_DEVICE_OBS | ATA_DEV1; | |
491 | ||
492 | iowrite8(tmp, ap->ioaddr.device_addr); | |
9363c382 | 493 | ata_sff_pause(ap); /* needed; also flushes, for mmio */ |
624d5c51 | 494 | } |
0fe40ff8 | 495 | EXPORT_SYMBOL_GPL(ata_sff_dev_select); |
624d5c51 TH |
496 | |
497 | /** | |
498 | * ata_dev_select - Select device 0/1 on ATA bus | |
499 | * @ap: ATA channel to manipulate | |
500 | * @device: ATA device (numbered from zero) to select | |
501 | * @wait: non-zero to wait for Status register BSY bit to clear | |
502 | * @can_sleep: non-zero if context allows sleeping | |
503 | * | |
504 | * Use the method defined in the ATA specification to | |
505 | * make either device 0, or device 1, active on the | |
506 | * ATA channel. | |
507 | * | |
9363c382 TH |
508 | * This is a high-level version of ata_sff_dev_select(), which |
509 | * additionally provides the services of inserting the proper | |
510 | * pauses and status polling, where needed. | |
624d5c51 TH |
511 | * |
512 | * LOCKING: | |
513 | * caller. | |
514 | */ | |
515 | void ata_dev_select(struct ata_port *ap, unsigned int device, | |
516 | unsigned int wait, unsigned int can_sleep) | |
517 | { | |
518 | if (ata_msg_probe(ap)) | |
519 | ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, " | |
520 | "device %u, wait %u\n", device, wait); | |
521 | ||
522 | if (wait) | |
523 | ata_wait_idle(ap); | |
524 | ||
5682ed33 | 525 | ap->ops->sff_dev_select(ap, device); |
624d5c51 TH |
526 | |
527 | if (wait) { | |
528 | if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI) | |
529 | msleep(150); | |
530 | ata_wait_idle(ap); | |
531 | } | |
532 | } | |
533 | ||
534 | /** | |
9363c382 | 535 | * ata_sff_irq_on - Enable interrupts on a port. |
624d5c51 TH |
536 | * @ap: Port on which interrupts are enabled. |
537 | * | |
538 | * Enable interrupts on a legacy IDE device using MMIO or PIO, | |
539 | * wait for idle, clear any pending interrupts. | |
540 | * | |
541 | * LOCKING: | |
542 | * Inherited from caller. | |
543 | */ | |
9363c382 | 544 | u8 ata_sff_irq_on(struct ata_port *ap) |
624d5c51 TH |
545 | { |
546 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
547 | u8 tmp; | |
548 | ||
549 | ap->ctl &= ~ATA_NIEN; | |
550 | ap->last_ctl = ap->ctl; | |
551 | ||
552 | if (ioaddr->ctl_addr) | |
553 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
554 | tmp = ata_wait_idle(ap); | |
555 | ||
5682ed33 | 556 | ap->ops->sff_irq_clear(ap); |
624d5c51 TH |
557 | |
558 | return tmp; | |
559 | } | |
0fe40ff8 | 560 | EXPORT_SYMBOL_GPL(ata_sff_irq_on); |
624d5c51 TH |
561 | |
562 | /** | |
9363c382 | 563 | * ata_sff_irq_clear - Clear PCI IDE BMDMA interrupt. |
624d5c51 TH |
564 | * @ap: Port associated with this ATA transaction. |
565 | * | |
566 | * Clear interrupt and error flags in DMA status register. | |
567 | * | |
568 | * May be used as the irq_clear() entry in ata_port_operations. | |
569 | * | |
570 | * LOCKING: | |
571 | * spin_lock_irqsave(host lock) | |
572 | */ | |
9363c382 | 573 | void ata_sff_irq_clear(struct ata_port *ap) |
624d5c51 TH |
574 | { |
575 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
576 | ||
577 | if (!mmio) | |
578 | return; | |
579 | ||
580 | iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS); | |
581 | } | |
0fe40ff8 | 582 | EXPORT_SYMBOL_GPL(ata_sff_irq_clear); |
624d5c51 TH |
583 | |
584 | /** | |
9363c382 | 585 | * ata_sff_tf_load - send taskfile registers to host controller |
624d5c51 TH |
586 | * @ap: Port to which output is sent |
587 | * @tf: ATA taskfile register set | |
588 | * | |
589 | * Outputs ATA taskfile to standard ATA host controller. | |
590 | * | |
591 | * LOCKING: | |
592 | * Inherited from caller. | |
593 | */ | |
9363c382 | 594 | void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
624d5c51 TH |
595 | { |
596 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
597 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
598 | ||
599 | if (tf->ctl != ap->last_ctl) { | |
600 | if (ioaddr->ctl_addr) | |
601 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
602 | ap->last_ctl = tf->ctl; | |
603 | ata_wait_idle(ap); | |
604 | } | |
605 | ||
606 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
efcb3cf7 | 607 | WARN_ON_ONCE(!ioaddr->ctl_addr); |
624d5c51 TH |
608 | iowrite8(tf->hob_feature, ioaddr->feature_addr); |
609 | iowrite8(tf->hob_nsect, ioaddr->nsect_addr); | |
610 | iowrite8(tf->hob_lbal, ioaddr->lbal_addr); | |
611 | iowrite8(tf->hob_lbam, ioaddr->lbam_addr); | |
612 | iowrite8(tf->hob_lbah, ioaddr->lbah_addr); | |
613 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", | |
614 | tf->hob_feature, | |
615 | tf->hob_nsect, | |
616 | tf->hob_lbal, | |
617 | tf->hob_lbam, | |
618 | tf->hob_lbah); | |
619 | } | |
620 | ||
621 | if (is_addr) { | |
622 | iowrite8(tf->feature, ioaddr->feature_addr); | |
623 | iowrite8(tf->nsect, ioaddr->nsect_addr); | |
624 | iowrite8(tf->lbal, ioaddr->lbal_addr); | |
625 | iowrite8(tf->lbam, ioaddr->lbam_addr); | |
626 | iowrite8(tf->lbah, ioaddr->lbah_addr); | |
627 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", | |
628 | tf->feature, | |
629 | tf->nsect, | |
630 | tf->lbal, | |
631 | tf->lbam, | |
632 | tf->lbah); | |
633 | } | |
634 | ||
635 | if (tf->flags & ATA_TFLAG_DEVICE) { | |
636 | iowrite8(tf->device, ioaddr->device_addr); | |
637 | VPRINTK("device 0x%X\n", tf->device); | |
638 | } | |
639 | ||
640 | ata_wait_idle(ap); | |
641 | } | |
0fe40ff8 | 642 | EXPORT_SYMBOL_GPL(ata_sff_tf_load); |
624d5c51 TH |
643 | |
644 | /** | |
9363c382 | 645 | * ata_sff_tf_read - input device's ATA taskfile shadow registers |
624d5c51 TH |
646 | * @ap: Port from which input is read |
647 | * @tf: ATA taskfile register set for storing input | |
648 | * | |
649 | * Reads ATA taskfile registers for currently-selected device | |
650 | * into @tf. Assumes the device has a fully SFF compliant task file | |
651 | * layout and behaviour. If you device does not (eg has a different | |
652 | * status method) then you will need to provide a replacement tf_read | |
653 | * | |
654 | * LOCKING: | |
655 | * Inherited from caller. | |
656 | */ | |
9363c382 | 657 | void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
624d5c51 TH |
658 | { |
659 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
660 | ||
9363c382 | 661 | tf->command = ata_sff_check_status(ap); |
624d5c51 TH |
662 | tf->feature = ioread8(ioaddr->error_addr); |
663 | tf->nsect = ioread8(ioaddr->nsect_addr); | |
664 | tf->lbal = ioread8(ioaddr->lbal_addr); | |
665 | tf->lbam = ioread8(ioaddr->lbam_addr); | |
666 | tf->lbah = ioread8(ioaddr->lbah_addr); | |
667 | tf->device = ioread8(ioaddr->device_addr); | |
668 | ||
669 | if (tf->flags & ATA_TFLAG_LBA48) { | |
670 | if (likely(ioaddr->ctl_addr)) { | |
671 | iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); | |
672 | tf->hob_feature = ioread8(ioaddr->error_addr); | |
673 | tf->hob_nsect = ioread8(ioaddr->nsect_addr); | |
674 | tf->hob_lbal = ioread8(ioaddr->lbal_addr); | |
675 | tf->hob_lbam = ioread8(ioaddr->lbam_addr); | |
676 | tf->hob_lbah = ioread8(ioaddr->lbah_addr); | |
677 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
678 | ap->last_ctl = tf->ctl; | |
679 | } else | |
efcb3cf7 | 680 | WARN_ON_ONCE(1); |
624d5c51 TH |
681 | } |
682 | } | |
0fe40ff8 | 683 | EXPORT_SYMBOL_GPL(ata_sff_tf_read); |
624d5c51 TH |
684 | |
685 | /** | |
9363c382 | 686 | * ata_sff_exec_command - issue ATA command to host controller |
624d5c51 TH |
687 | * @ap: port to which command is being issued |
688 | * @tf: ATA taskfile register set | |
689 | * | |
690 | * Issues ATA command, with proper synchronization with interrupt | |
691 | * handler / other threads. | |
692 | * | |
693 | * LOCKING: | |
694 | * spin_lock_irqsave(host lock) | |
695 | */ | |
9363c382 | 696 | void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) |
624d5c51 TH |
697 | { |
698 | DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); | |
699 | ||
700 | iowrite8(tf->command, ap->ioaddr.command_addr); | |
9363c382 | 701 | ata_sff_pause(ap); |
624d5c51 | 702 | } |
0fe40ff8 | 703 | EXPORT_SYMBOL_GPL(ata_sff_exec_command); |
624d5c51 TH |
704 | |
705 | /** | |
706 | * ata_tf_to_host - issue ATA taskfile to host controller | |
707 | * @ap: port to which command is being issued | |
708 | * @tf: ATA taskfile register set | |
709 | * | |
710 | * Issues ATA taskfile register set to ATA host controller, | |
711 | * with proper synchronization with interrupt handler and | |
712 | * other threads. | |
713 | * | |
714 | * LOCKING: | |
715 | * spin_lock_irqsave(host lock) | |
716 | */ | |
717 | static inline void ata_tf_to_host(struct ata_port *ap, | |
718 | const struct ata_taskfile *tf) | |
719 | { | |
5682ed33 TH |
720 | ap->ops->sff_tf_load(ap, tf); |
721 | ap->ops->sff_exec_command(ap, tf); | |
624d5c51 TH |
722 | } |
723 | ||
724 | /** | |
9363c382 | 725 | * ata_sff_data_xfer - Transfer data by PIO |
624d5c51 TH |
726 | * @dev: device to target |
727 | * @buf: data buffer | |
728 | * @buflen: buffer length | |
729 | * @rw: read/write | |
730 | * | |
731 | * Transfer data from/to the device data register by PIO. | |
732 | * | |
733 | * LOCKING: | |
734 | * Inherited from caller. | |
735 | * | |
736 | * RETURNS: | |
737 | * Bytes consumed. | |
738 | */ | |
9363c382 TH |
739 | unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf, |
740 | unsigned int buflen, int rw) | |
624d5c51 TH |
741 | { |
742 | struct ata_port *ap = dev->link->ap; | |
743 | void __iomem *data_addr = ap->ioaddr.data_addr; | |
744 | unsigned int words = buflen >> 1; | |
745 | ||
746 | /* Transfer multiple of 2 bytes */ | |
747 | if (rw == READ) | |
748 | ioread16_rep(data_addr, buf, words); | |
749 | else | |
750 | iowrite16_rep(data_addr, buf, words); | |
751 | ||
2102d749 | 752 | /* Transfer trailing byte, if any. */ |
624d5c51 | 753 | if (unlikely(buflen & 0x01)) { |
2102d749 | 754 | unsigned char pad[2]; |
624d5c51 | 755 | |
2102d749 SS |
756 | /* Point buf to the tail of buffer */ |
757 | buf += buflen - 1; | |
758 | ||
759 | /* | |
760 | * Use io*16_rep() accessors here as well to avoid pointlessly | |
972b94ff | 761 | * swapping bytes to and from on the big endian machines... |
2102d749 | 762 | */ |
624d5c51 | 763 | if (rw == READ) { |
2102d749 SS |
764 | ioread16_rep(data_addr, pad, 1); |
765 | *buf = pad[0]; | |
624d5c51 | 766 | } else { |
2102d749 SS |
767 | pad[0] = *buf; |
768 | iowrite16_rep(data_addr, pad, 1); | |
624d5c51 TH |
769 | } |
770 | words++; | |
771 | } | |
772 | ||
773 | return words << 1; | |
774 | } | |
0fe40ff8 | 775 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer); |
624d5c51 | 776 | |
871af121 AC |
777 | /** |
778 | * ata_sff_data_xfer32 - Transfer data by PIO | |
779 | * @dev: device to target | |
780 | * @buf: data buffer | |
781 | * @buflen: buffer length | |
782 | * @rw: read/write | |
783 | * | |
784 | * Transfer data from/to the device data register by PIO using 32bit | |
785 | * I/O operations. | |
786 | * | |
787 | * LOCKING: | |
788 | * Inherited from caller. | |
789 | * | |
790 | * RETURNS: | |
791 | * Bytes consumed. | |
792 | */ | |
793 | ||
794 | unsigned int ata_sff_data_xfer32(struct ata_device *dev, unsigned char *buf, | |
795 | unsigned int buflen, int rw) | |
796 | { | |
797 | struct ata_port *ap = dev->link->ap; | |
798 | void __iomem *data_addr = ap->ioaddr.data_addr; | |
799 | unsigned int words = buflen >> 2; | |
800 | int slop = buflen & 3; | |
972b94ff | 801 | |
e3cf95dd AC |
802 | if (!(ap->pflags & ATA_PFLAG_PIO32)) |
803 | return ata_sff_data_xfer(dev, buf, buflen, rw); | |
871af121 AC |
804 | |
805 | /* Transfer multiple of 4 bytes */ | |
806 | if (rw == READ) | |
807 | ioread32_rep(data_addr, buf, words); | |
808 | else | |
809 | iowrite32_rep(data_addr, buf, words); | |
810 | ||
d1b3525b | 811 | /* Transfer trailing bytes, if any */ |
871af121 | 812 | if (unlikely(slop)) { |
d1b3525b SS |
813 | unsigned char pad[4]; |
814 | ||
815 | /* Point buf to the tail of buffer */ | |
816 | buf += buflen - slop; | |
817 | ||
818 | /* | |
819 | * Use io*_rep() accessors here as well to avoid pointlessly | |
972b94ff | 820 | * swapping bytes to and from on the big endian machines... |
d1b3525b | 821 | */ |
871af121 | 822 | if (rw == READ) { |
d1b3525b SS |
823 | if (slop < 3) |
824 | ioread16_rep(data_addr, pad, 1); | |
825 | else | |
826 | ioread32_rep(data_addr, pad, 1); | |
827 | memcpy(buf, pad, slop); | |
871af121 | 828 | } else { |
d1b3525b SS |
829 | memcpy(pad, buf, slop); |
830 | if (slop < 3) | |
831 | iowrite16_rep(data_addr, pad, 1); | |
832 | else | |
833 | iowrite32_rep(data_addr, pad, 1); | |
871af121 | 834 | } |
871af121 | 835 | } |
d1b3525b | 836 | return (buflen + 1) & ~1; |
871af121 AC |
837 | } |
838 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer32); | |
839 | ||
624d5c51 | 840 | /** |
9363c382 | 841 | * ata_sff_data_xfer_noirq - Transfer data by PIO |
624d5c51 TH |
842 | * @dev: device to target |
843 | * @buf: data buffer | |
844 | * @buflen: buffer length | |
845 | * @rw: read/write | |
846 | * | |
847 | * Transfer data from/to the device data register by PIO. Do the | |
848 | * transfer with interrupts disabled. | |
849 | * | |
850 | * LOCKING: | |
851 | * Inherited from caller. | |
852 | * | |
853 | * RETURNS: | |
854 | * Bytes consumed. | |
855 | */ | |
9363c382 TH |
856 | unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf, |
857 | unsigned int buflen, int rw) | |
624d5c51 TH |
858 | { |
859 | unsigned long flags; | |
860 | unsigned int consumed; | |
861 | ||
862 | local_irq_save(flags); | |
9363c382 | 863 | consumed = ata_sff_data_xfer(dev, buf, buflen, rw); |
624d5c51 TH |
864 | local_irq_restore(flags); |
865 | ||
866 | return consumed; | |
867 | } | |
0fe40ff8 | 868 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq); |
624d5c51 TH |
869 | |
870 | /** | |
871 | * ata_pio_sector - Transfer a sector of data. | |
872 | * @qc: Command on going | |
873 | * | |
874 | * Transfer qc->sect_size bytes of data from/to the ATA device. | |
875 | * | |
876 | * LOCKING: | |
877 | * Inherited from caller. | |
878 | */ | |
879 | static void ata_pio_sector(struct ata_queued_cmd *qc) | |
880 | { | |
881 | int do_write = (qc->tf.flags & ATA_TFLAG_WRITE); | |
882 | struct ata_port *ap = qc->ap; | |
883 | struct page *page; | |
884 | unsigned int offset; | |
885 | unsigned char *buf; | |
886 | ||
887 | if (qc->curbytes == qc->nbytes - qc->sect_size) | |
888 | ap->hsm_task_state = HSM_ST_LAST; | |
889 | ||
890 | page = sg_page(qc->cursg); | |
891 | offset = qc->cursg->offset + qc->cursg_ofs; | |
892 | ||
893 | /* get the current page and offset */ | |
894 | page = nth_page(page, (offset >> PAGE_SHIFT)); | |
895 | offset %= PAGE_SIZE; | |
896 | ||
897 | DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); | |
898 | ||
899 | if (PageHighMem(page)) { | |
900 | unsigned long flags; | |
901 | ||
902 | /* FIXME: use a bounce buffer */ | |
903 | local_irq_save(flags); | |
904 | buf = kmap_atomic(page, KM_IRQ0); | |
905 | ||
906 | /* do the actual data transfer */ | |
5682ed33 TH |
907 | ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, |
908 | do_write); | |
624d5c51 TH |
909 | |
910 | kunmap_atomic(buf, KM_IRQ0); | |
911 | local_irq_restore(flags); | |
912 | } else { | |
913 | buf = page_address(page); | |
5682ed33 TH |
914 | ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, |
915 | do_write); | |
624d5c51 TH |
916 | } |
917 | ||
2d68b7fe CM |
918 | if (!do_write) |
919 | flush_dcache_page(page); | |
920 | ||
624d5c51 TH |
921 | qc->curbytes += qc->sect_size; |
922 | qc->cursg_ofs += qc->sect_size; | |
923 | ||
924 | if (qc->cursg_ofs == qc->cursg->length) { | |
925 | qc->cursg = sg_next(qc->cursg); | |
926 | qc->cursg_ofs = 0; | |
927 | } | |
928 | } | |
929 | ||
930 | /** | |
931 | * ata_pio_sectors - Transfer one or many sectors. | |
932 | * @qc: Command on going | |
933 | * | |
934 | * Transfer one or many sectors of data from/to the | |
935 | * ATA device for the DRQ request. | |
936 | * | |
937 | * LOCKING: | |
938 | * Inherited from caller. | |
939 | */ | |
940 | static void ata_pio_sectors(struct ata_queued_cmd *qc) | |
941 | { | |
942 | if (is_multi_taskfile(&qc->tf)) { | |
943 | /* READ/WRITE MULTIPLE */ | |
944 | unsigned int nsect; | |
945 | ||
efcb3cf7 | 946 | WARN_ON_ONCE(qc->dev->multi_count == 0); |
624d5c51 TH |
947 | |
948 | nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size, | |
949 | qc->dev->multi_count); | |
950 | while (nsect--) | |
951 | ata_pio_sector(qc); | |
952 | } else | |
953 | ata_pio_sector(qc); | |
954 | ||
a57c1bad | 955 | ata_sff_sync(qc->ap); /* flush */ |
624d5c51 TH |
956 | } |
957 | ||
958 | /** | |
959 | * atapi_send_cdb - Write CDB bytes to hardware | |
960 | * @ap: Port to which ATAPI device is attached. | |
961 | * @qc: Taskfile currently active | |
962 | * | |
963 | * When device has indicated its readiness to accept | |
964 | * a CDB, this function is called. Send the CDB. | |
965 | * | |
966 | * LOCKING: | |
967 | * caller. | |
968 | */ | |
969 | static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc) | |
970 | { | |
971 | /* send SCSI cdb */ | |
972 | DPRINTK("send cdb\n"); | |
efcb3cf7 | 973 | WARN_ON_ONCE(qc->dev->cdb_len < 12); |
624d5c51 | 974 | |
5682ed33 | 975 | ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1); |
a57c1bad AC |
976 | ata_sff_sync(ap); |
977 | /* FIXME: If the CDB is for DMA do we need to do the transition delay | |
978 | or is bmdma_start guaranteed to do it ? */ | |
624d5c51 TH |
979 | switch (qc->tf.protocol) { |
980 | case ATAPI_PROT_PIO: | |
981 | ap->hsm_task_state = HSM_ST; | |
982 | break; | |
983 | case ATAPI_PROT_NODATA: | |
984 | ap->hsm_task_state = HSM_ST_LAST; | |
985 | break; | |
986 | case ATAPI_PROT_DMA: | |
987 | ap->hsm_task_state = HSM_ST_LAST; | |
988 | /* initiate bmdma */ | |
989 | ap->ops->bmdma_start(qc); | |
990 | break; | |
991 | } | |
992 | } | |
993 | ||
994 | /** | |
995 | * __atapi_pio_bytes - Transfer data from/to the ATAPI device. | |
996 | * @qc: Command on going | |
997 | * @bytes: number of bytes | |
998 | * | |
999 | * Transfer Transfer data from/to the ATAPI device. | |
1000 | * | |
1001 | * LOCKING: | |
1002 | * Inherited from caller. | |
1003 | * | |
1004 | */ | |
1005 | static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes) | |
1006 | { | |
1007 | int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ; | |
1008 | struct ata_port *ap = qc->ap; | |
1009 | struct ata_device *dev = qc->dev; | |
1010 | struct ata_eh_info *ehi = &dev->link->eh_info; | |
1011 | struct scatterlist *sg; | |
1012 | struct page *page; | |
1013 | unsigned char *buf; | |
1014 | unsigned int offset, count, consumed; | |
1015 | ||
1016 | next_sg: | |
1017 | sg = qc->cursg; | |
1018 | if (unlikely(!sg)) { | |
1019 | ata_ehi_push_desc(ehi, "unexpected or too much trailing data " | |
1020 | "buf=%u cur=%u bytes=%u", | |
1021 | qc->nbytes, qc->curbytes, bytes); | |
1022 | return -1; | |
1023 | } | |
1024 | ||
1025 | page = sg_page(sg); | |
1026 | offset = sg->offset + qc->cursg_ofs; | |
1027 | ||
1028 | /* get the current page and offset */ | |
1029 | page = nth_page(page, (offset >> PAGE_SHIFT)); | |
1030 | offset %= PAGE_SIZE; | |
1031 | ||
1032 | /* don't overrun current sg */ | |
1033 | count = min(sg->length - qc->cursg_ofs, bytes); | |
1034 | ||
1035 | /* don't cross page boundaries */ | |
1036 | count = min(count, (unsigned int)PAGE_SIZE - offset); | |
1037 | ||
1038 | DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); | |
1039 | ||
1040 | if (PageHighMem(page)) { | |
1041 | unsigned long flags; | |
1042 | ||
1043 | /* FIXME: use bounce buffer */ | |
1044 | local_irq_save(flags); | |
1045 | buf = kmap_atomic(page, KM_IRQ0); | |
1046 | ||
1047 | /* do the actual data transfer */ | |
0fe40ff8 AC |
1048 | consumed = ap->ops->sff_data_xfer(dev, buf + offset, |
1049 | count, rw); | |
624d5c51 TH |
1050 | |
1051 | kunmap_atomic(buf, KM_IRQ0); | |
1052 | local_irq_restore(flags); | |
1053 | } else { | |
1054 | buf = page_address(page); | |
0fe40ff8 AC |
1055 | consumed = ap->ops->sff_data_xfer(dev, buf + offset, |
1056 | count, rw); | |
624d5c51 TH |
1057 | } |
1058 | ||
1059 | bytes -= min(bytes, consumed); | |
1060 | qc->curbytes += count; | |
1061 | qc->cursg_ofs += count; | |
1062 | ||
1063 | if (qc->cursg_ofs == sg->length) { | |
1064 | qc->cursg = sg_next(qc->cursg); | |
1065 | qc->cursg_ofs = 0; | |
1066 | } | |
1067 | ||
a0f79f7a CB |
1068 | /* |
1069 | * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed); | |
1070 | * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN | |
1071 | * check correctly as it doesn't know if it is the last request being | |
1072 | * made. Somebody should implement a proper sanity check. | |
1073 | */ | |
624d5c51 TH |
1074 | if (bytes) |
1075 | goto next_sg; | |
1076 | return 0; | |
1077 | } | |
1078 | ||
1079 | /** | |
1080 | * atapi_pio_bytes - Transfer data from/to the ATAPI device. | |
1081 | * @qc: Command on going | |
1082 | * | |
1083 | * Transfer Transfer data from/to the ATAPI device. | |
1084 | * | |
1085 | * LOCKING: | |
1086 | * Inherited from caller. | |
1087 | */ | |
1088 | static void atapi_pio_bytes(struct ata_queued_cmd *qc) | |
1089 | { | |
1090 | struct ata_port *ap = qc->ap; | |
1091 | struct ata_device *dev = qc->dev; | |
1092 | struct ata_eh_info *ehi = &dev->link->eh_info; | |
1093 | unsigned int ireason, bc_lo, bc_hi, bytes; | |
1094 | int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0; | |
1095 | ||
1096 | /* Abuse qc->result_tf for temp storage of intermediate TF | |
1097 | * here to save some kernel stack usage. | |
1098 | * For normal completion, qc->result_tf is not relevant. For | |
1099 | * error, qc->result_tf is later overwritten by ata_qc_complete(). | |
1100 | * So, the correctness of qc->result_tf is not affected. | |
1101 | */ | |
5682ed33 | 1102 | ap->ops->sff_tf_read(ap, &qc->result_tf); |
624d5c51 TH |
1103 | ireason = qc->result_tf.nsect; |
1104 | bc_lo = qc->result_tf.lbam; | |
1105 | bc_hi = qc->result_tf.lbah; | |
1106 | bytes = (bc_hi << 8) | bc_lo; | |
1107 | ||
1108 | /* shall be cleared to zero, indicating xfer of data */ | |
1109 | if (unlikely(ireason & (1 << 0))) | |
1110 | goto atapi_check; | |
1111 | ||
1112 | /* make sure transfer direction matches expected */ | |
1113 | i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0; | |
1114 | if (unlikely(do_write != i_write)) | |
1115 | goto atapi_check; | |
1116 | ||
1117 | if (unlikely(!bytes)) | |
1118 | goto atapi_check; | |
1119 | ||
1120 | VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes); | |
1121 | ||
1122 | if (unlikely(__atapi_pio_bytes(qc, bytes))) | |
1123 | goto err_out; | |
a57c1bad | 1124 | ata_sff_sync(ap); /* flush */ |
624d5c51 TH |
1125 | |
1126 | return; | |
1127 | ||
1128 | atapi_check: | |
1129 | ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)", | |
1130 | ireason, bytes); | |
1131 | err_out: | |
1132 | qc->err_mask |= AC_ERR_HSM; | |
1133 | ap->hsm_task_state = HSM_ST_ERR; | |
1134 | } | |
1135 | ||
1136 | /** | |
1137 | * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue. | |
1138 | * @ap: the target ata_port | |
1139 | * @qc: qc on going | |
1140 | * | |
1141 | * RETURNS: | |
1142 | * 1 if ok in workqueue, 0 otherwise. | |
1143 | */ | |
0fe40ff8 AC |
1144 | static inline int ata_hsm_ok_in_wq(struct ata_port *ap, |
1145 | struct ata_queued_cmd *qc) | |
624d5c51 TH |
1146 | { |
1147 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1148 | return 1; | |
1149 | ||
1150 | if (ap->hsm_task_state == HSM_ST_FIRST) { | |
1151 | if (qc->tf.protocol == ATA_PROT_PIO && | |
0fe40ff8 | 1152 | (qc->tf.flags & ATA_TFLAG_WRITE)) |
624d5c51 TH |
1153 | return 1; |
1154 | ||
1155 | if (ata_is_atapi(qc->tf.protocol) && | |
0fe40ff8 | 1156 | !(qc->dev->flags & ATA_DFLAG_CDB_INTR)) |
624d5c51 TH |
1157 | return 1; |
1158 | } | |
1159 | ||
1160 | return 0; | |
1161 | } | |
1162 | ||
1163 | /** | |
1164 | * ata_hsm_qc_complete - finish a qc running on standard HSM | |
1165 | * @qc: Command to complete | |
1166 | * @in_wq: 1 if called from workqueue, 0 otherwise | |
1167 | * | |
1168 | * Finish @qc which is running on standard HSM. | |
1169 | * | |
1170 | * LOCKING: | |
1171 | * If @in_wq is zero, spin_lock_irqsave(host lock). | |
1172 | * Otherwise, none on entry and grabs host lock. | |
1173 | */ | |
1174 | static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq) | |
1175 | { | |
1176 | struct ata_port *ap = qc->ap; | |
1177 | unsigned long flags; | |
1178 | ||
1179 | if (ap->ops->error_handler) { | |
1180 | if (in_wq) { | |
1181 | spin_lock_irqsave(ap->lock, flags); | |
1182 | ||
1183 | /* EH might have kicked in while host lock is | |
1184 | * released. | |
1185 | */ | |
1186 | qc = ata_qc_from_tag(ap, qc->tag); | |
1187 | if (qc) { | |
1188 | if (likely(!(qc->err_mask & AC_ERR_HSM))) { | |
5682ed33 | 1189 | ap->ops->sff_irq_on(ap); |
624d5c51 TH |
1190 | ata_qc_complete(qc); |
1191 | } else | |
1192 | ata_port_freeze(ap); | |
1193 | } | |
1194 | ||
1195 | spin_unlock_irqrestore(ap->lock, flags); | |
1196 | } else { | |
1197 | if (likely(!(qc->err_mask & AC_ERR_HSM))) | |
1198 | ata_qc_complete(qc); | |
1199 | else | |
1200 | ata_port_freeze(ap); | |
1201 | } | |
1202 | } else { | |
1203 | if (in_wq) { | |
1204 | spin_lock_irqsave(ap->lock, flags); | |
5682ed33 | 1205 | ap->ops->sff_irq_on(ap); |
624d5c51 TH |
1206 | ata_qc_complete(qc); |
1207 | spin_unlock_irqrestore(ap->lock, flags); | |
1208 | } else | |
1209 | ata_qc_complete(qc); | |
1210 | } | |
1211 | } | |
1212 | ||
1213 | /** | |
9363c382 | 1214 | * ata_sff_hsm_move - move the HSM to the next state. |
624d5c51 TH |
1215 | * @ap: the target ata_port |
1216 | * @qc: qc on going | |
1217 | * @status: current device status | |
1218 | * @in_wq: 1 if called from workqueue, 0 otherwise | |
1219 | * | |
1220 | * RETURNS: | |
1221 | * 1 when poll next status needed, 0 otherwise. | |
1222 | */ | |
9363c382 TH |
1223 | int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc, |
1224 | u8 status, int in_wq) | |
624d5c51 | 1225 | { |
a836d3e8 | 1226 | struct ata_eh_info *ehi = &ap->link.eh_info; |
624d5c51 TH |
1227 | unsigned long flags = 0; |
1228 | int poll_next; | |
1229 | ||
efcb3cf7 | 1230 | WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0); |
624d5c51 | 1231 | |
9363c382 | 1232 | /* Make sure ata_sff_qc_issue() does not throw things |
624d5c51 TH |
1233 | * like DMA polling into the workqueue. Notice that |
1234 | * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING). | |
1235 | */ | |
efcb3cf7 | 1236 | WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc)); |
624d5c51 TH |
1237 | |
1238 | fsm_start: | |
1239 | DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n", | |
1240 | ap->print_id, qc->tf.protocol, ap->hsm_task_state, status); | |
1241 | ||
1242 | switch (ap->hsm_task_state) { | |
1243 | case HSM_ST_FIRST: | |
1244 | /* Send first data block or PACKET CDB */ | |
1245 | ||
1246 | /* If polling, we will stay in the work queue after | |
1247 | * sending the data. Otherwise, interrupt handler | |
1248 | * takes over after sending the data. | |
1249 | */ | |
1250 | poll_next = (qc->tf.flags & ATA_TFLAG_POLLING); | |
1251 | ||
1252 | /* check device status */ | |
1253 | if (unlikely((status & ATA_DRQ) == 0)) { | |
1254 | /* handle BSY=0, DRQ=0 as error */ | |
1255 | if (likely(status & (ATA_ERR | ATA_DF))) | |
1256 | /* device stops HSM for abort/error */ | |
1257 | qc->err_mask |= AC_ERR_DEV; | |
a836d3e8 | 1258 | else { |
624d5c51 | 1259 | /* HSM violation. Let EH handle this */ |
a836d3e8 TH |
1260 | ata_ehi_push_desc(ehi, |
1261 | "ST_FIRST: !(DRQ|ERR|DF)"); | |
624d5c51 | 1262 | qc->err_mask |= AC_ERR_HSM; |
a836d3e8 | 1263 | } |
624d5c51 TH |
1264 | |
1265 | ap->hsm_task_state = HSM_ST_ERR; | |
1266 | goto fsm_start; | |
1267 | } | |
1268 | ||
1269 | /* Device should not ask for data transfer (DRQ=1) | |
1270 | * when it finds something wrong. | |
1271 | * We ignore DRQ here and stop the HSM by | |
1272 | * changing hsm_task_state to HSM_ST_ERR and | |
1273 | * let the EH abort the command or reset the device. | |
1274 | */ | |
1275 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
1276 | /* Some ATAPI tape drives forget to clear the ERR bit | |
1277 | * when doing the next command (mostly request sense). | |
1278 | * We ignore ERR here to workaround and proceed sending | |
1279 | * the CDB. | |
1280 | */ | |
1281 | if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) { | |
a836d3e8 TH |
1282 | ata_ehi_push_desc(ehi, "ST_FIRST: " |
1283 | "DRQ=1 with device error, " | |
1284 | "dev_stat 0x%X", status); | |
624d5c51 TH |
1285 | qc->err_mask |= AC_ERR_HSM; |
1286 | ap->hsm_task_state = HSM_ST_ERR; | |
1287 | goto fsm_start; | |
1288 | } | |
1289 | } | |
1290 | ||
1291 | /* Send the CDB (atapi) or the first data block (ata pio out). | |
1292 | * During the state transition, interrupt handler shouldn't | |
1293 | * be invoked before the data transfer is complete and | |
1294 | * hsm_task_state is changed. Hence, the following locking. | |
1295 | */ | |
1296 | if (in_wq) | |
1297 | spin_lock_irqsave(ap->lock, flags); | |
1298 | ||
1299 | if (qc->tf.protocol == ATA_PROT_PIO) { | |
1300 | /* PIO data out protocol. | |
1301 | * send first data block. | |
1302 | */ | |
1303 | ||
1304 | /* ata_pio_sectors() might change the state | |
1305 | * to HSM_ST_LAST. so, the state is changed here | |
1306 | * before ata_pio_sectors(). | |
1307 | */ | |
1308 | ap->hsm_task_state = HSM_ST; | |
1309 | ata_pio_sectors(qc); | |
1310 | } else | |
1311 | /* send CDB */ | |
1312 | atapi_send_cdb(ap, qc); | |
1313 | ||
1314 | if (in_wq) | |
1315 | spin_unlock_irqrestore(ap->lock, flags); | |
1316 | ||
1317 | /* if polling, ata_pio_task() handles the rest. | |
1318 | * otherwise, interrupt handler takes over from here. | |
1319 | */ | |
1320 | break; | |
1321 | ||
1322 | case HSM_ST: | |
1323 | /* complete command or read/write the data register */ | |
1324 | if (qc->tf.protocol == ATAPI_PROT_PIO) { | |
1325 | /* ATAPI PIO protocol */ | |
1326 | if ((status & ATA_DRQ) == 0) { | |
1327 | /* No more data to transfer or device error. | |
1328 | * Device error will be tagged in HSM_ST_LAST. | |
1329 | */ | |
1330 | ap->hsm_task_state = HSM_ST_LAST; | |
1331 | goto fsm_start; | |
1332 | } | |
1333 | ||
1334 | /* Device should not ask for data transfer (DRQ=1) | |
1335 | * when it finds something wrong. | |
1336 | * We ignore DRQ here and stop the HSM by | |
1337 | * changing hsm_task_state to HSM_ST_ERR and | |
1338 | * let the EH abort the command or reset the device. | |
1339 | */ | |
1340 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
a836d3e8 TH |
1341 | ata_ehi_push_desc(ehi, "ST-ATAPI: " |
1342 | "DRQ=1 with device error, " | |
1343 | "dev_stat 0x%X", status); | |
624d5c51 TH |
1344 | qc->err_mask |= AC_ERR_HSM; |
1345 | ap->hsm_task_state = HSM_ST_ERR; | |
1346 | goto fsm_start; | |
1347 | } | |
1348 | ||
1349 | atapi_pio_bytes(qc); | |
1350 | ||
1351 | if (unlikely(ap->hsm_task_state == HSM_ST_ERR)) | |
1352 | /* bad ireason reported by device */ | |
1353 | goto fsm_start; | |
1354 | ||
1355 | } else { | |
1356 | /* ATA PIO protocol */ | |
1357 | if (unlikely((status & ATA_DRQ) == 0)) { | |
1358 | /* handle BSY=0, DRQ=0 as error */ | |
6a6b97d3 | 1359 | if (likely(status & (ATA_ERR | ATA_DF))) { |
624d5c51 TH |
1360 | /* device stops HSM for abort/error */ |
1361 | qc->err_mask |= AC_ERR_DEV; | |
6a6b97d3 TH |
1362 | |
1363 | /* If diagnostic failed and this is | |
1364 | * IDENTIFY, it's likely a phantom | |
1365 | * device. Mark hint. | |
1366 | */ | |
1367 | if (qc->dev->horkage & | |
1368 | ATA_HORKAGE_DIAGNOSTIC) | |
1369 | qc->err_mask |= | |
1370 | AC_ERR_NODEV_HINT; | |
1371 | } else { | |
624d5c51 TH |
1372 | /* HSM violation. Let EH handle this. |
1373 | * Phantom devices also trigger this | |
1374 | * condition. Mark hint. | |
1375 | */ | |
a836d3e8 | 1376 | ata_ehi_push_desc(ehi, "ST-ATA: " |
80ee6f54 | 1377 | "DRQ=0 without device error, " |
a836d3e8 | 1378 | "dev_stat 0x%X", status); |
624d5c51 TH |
1379 | qc->err_mask |= AC_ERR_HSM | |
1380 | AC_ERR_NODEV_HINT; | |
a836d3e8 | 1381 | } |
624d5c51 TH |
1382 | |
1383 | ap->hsm_task_state = HSM_ST_ERR; | |
1384 | goto fsm_start; | |
1385 | } | |
1386 | ||
1387 | /* For PIO reads, some devices may ask for | |
1388 | * data transfer (DRQ=1) alone with ERR=1. | |
1389 | * We respect DRQ here and transfer one | |
1390 | * block of junk data before changing the | |
1391 | * hsm_task_state to HSM_ST_ERR. | |
1392 | * | |
1393 | * For PIO writes, ERR=1 DRQ=1 doesn't make | |
1394 | * sense since the data block has been | |
1395 | * transferred to the device. | |
1396 | */ | |
1397 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
1398 | /* data might be corrputed */ | |
1399 | qc->err_mask |= AC_ERR_DEV; | |
1400 | ||
1401 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) { | |
1402 | ata_pio_sectors(qc); | |
1403 | status = ata_wait_idle(ap); | |
1404 | } | |
1405 | ||
a836d3e8 TH |
1406 | if (status & (ATA_BUSY | ATA_DRQ)) { |
1407 | ata_ehi_push_desc(ehi, "ST-ATA: " | |
1408 | "BUSY|DRQ persists on ERR|DF, " | |
1409 | "dev_stat 0x%X", status); | |
624d5c51 | 1410 | qc->err_mask |= AC_ERR_HSM; |
a836d3e8 | 1411 | } |
624d5c51 | 1412 | |
b919930c TH |
1413 | /* There are oddball controllers with |
1414 | * status register stuck at 0x7f and | |
1415 | * lbal/m/h at zero which makes it | |
1416 | * pass all other presence detection | |
1417 | * mechanisms we have. Set NODEV_HINT | |
1418 | * for it. Kernel bz#7241. | |
1419 | */ | |
1420 | if (status == 0x7f) | |
1421 | qc->err_mask |= AC_ERR_NODEV_HINT; | |
1422 | ||
624d5c51 TH |
1423 | /* ata_pio_sectors() might change the |
1424 | * state to HSM_ST_LAST. so, the state | |
1425 | * is changed after ata_pio_sectors(). | |
1426 | */ | |
1427 | ap->hsm_task_state = HSM_ST_ERR; | |
1428 | goto fsm_start; | |
1429 | } | |
1430 | ||
1431 | ata_pio_sectors(qc); | |
1432 | ||
1433 | if (ap->hsm_task_state == HSM_ST_LAST && | |
1434 | (!(qc->tf.flags & ATA_TFLAG_WRITE))) { | |
1435 | /* all data read */ | |
1436 | status = ata_wait_idle(ap); | |
1437 | goto fsm_start; | |
1438 | } | |
1439 | } | |
1440 | ||
1441 | poll_next = 1; | |
1442 | break; | |
1443 | ||
1444 | case HSM_ST_LAST: | |
1445 | if (unlikely(!ata_ok(status))) { | |
1446 | qc->err_mask |= __ac_err_mask(status); | |
1447 | ap->hsm_task_state = HSM_ST_ERR; | |
1448 | goto fsm_start; | |
1449 | } | |
1450 | ||
1451 | /* no more data to transfer */ | |
1452 | DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n", | |
1453 | ap->print_id, qc->dev->devno, status); | |
1454 | ||
efcb3cf7 | 1455 | WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM)); |
624d5c51 TH |
1456 | |
1457 | ap->hsm_task_state = HSM_ST_IDLE; | |
1458 | ||
1459 | /* complete taskfile transaction */ | |
1460 | ata_hsm_qc_complete(qc, in_wq); | |
1461 | ||
1462 | poll_next = 0; | |
1463 | break; | |
1464 | ||
1465 | case HSM_ST_ERR: | |
624d5c51 TH |
1466 | ap->hsm_task_state = HSM_ST_IDLE; |
1467 | ||
1468 | /* complete taskfile transaction */ | |
1469 | ata_hsm_qc_complete(qc, in_wq); | |
1470 | ||
1471 | poll_next = 0; | |
1472 | break; | |
1473 | default: | |
1474 | poll_next = 0; | |
1475 | BUG(); | |
1476 | } | |
1477 | ||
1478 | return poll_next; | |
1479 | } | |
0fe40ff8 | 1480 | EXPORT_SYMBOL_GPL(ata_sff_hsm_move); |
624d5c51 TH |
1481 | |
1482 | void ata_pio_task(struct work_struct *work) | |
1483 | { | |
1484 | struct ata_port *ap = | |
1485 | container_of(work, struct ata_port, port_task.work); | |
1486 | struct ata_queued_cmd *qc = ap->port_task_data; | |
1487 | u8 status; | |
1488 | int poll_next; | |
1489 | ||
1490 | fsm_start: | |
efcb3cf7 | 1491 | WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE); |
624d5c51 TH |
1492 | |
1493 | /* | |
1494 | * This is purely heuristic. This is a fast path. | |
1495 | * Sometimes when we enter, BSY will be cleared in | |
1496 | * a chk-status or two. If not, the drive is probably seeking | |
1497 | * or something. Snooze for a couple msecs, then | |
1498 | * chk-status again. If still busy, queue delayed work. | |
1499 | */ | |
9363c382 | 1500 | status = ata_sff_busy_wait(ap, ATA_BUSY, 5); |
624d5c51 TH |
1501 | if (status & ATA_BUSY) { |
1502 | msleep(2); | |
9363c382 | 1503 | status = ata_sff_busy_wait(ap, ATA_BUSY, 10); |
624d5c51 TH |
1504 | if (status & ATA_BUSY) { |
1505 | ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE); | |
1506 | return; | |
1507 | } | |
1508 | } | |
1509 | ||
1510 | /* move the HSM */ | |
9363c382 | 1511 | poll_next = ata_sff_hsm_move(ap, qc, status, 1); |
624d5c51 TH |
1512 | |
1513 | /* another command or interrupt handler | |
1514 | * may be running at this point. | |
1515 | */ | |
1516 | if (poll_next) | |
1517 | goto fsm_start; | |
1518 | } | |
1519 | ||
1520 | /** | |
9363c382 | 1521 | * ata_sff_qc_issue - issue taskfile to device in proto-dependent manner |
624d5c51 TH |
1522 | * @qc: command to issue to device |
1523 | * | |
1524 | * Using various libata functions and hooks, this function | |
1525 | * starts an ATA command. ATA commands are grouped into | |
1526 | * classes called "protocols", and issuing each type of protocol | |
1527 | * is slightly different. | |
1528 | * | |
1529 | * May be used as the qc_issue() entry in ata_port_operations. | |
1530 | * | |
1531 | * LOCKING: | |
1532 | * spin_lock_irqsave(host lock) | |
1533 | * | |
1534 | * RETURNS: | |
1535 | * Zero on success, AC_ERR_* mask on failure | |
1536 | */ | |
9363c382 | 1537 | unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc) |
624d5c51 TH |
1538 | { |
1539 | struct ata_port *ap = qc->ap; | |
1540 | ||
1541 | /* Use polling pio if the LLD doesn't handle | |
1542 | * interrupt driven pio and atapi CDB interrupt. | |
1543 | */ | |
1544 | if (ap->flags & ATA_FLAG_PIO_POLLING) { | |
1545 | switch (qc->tf.protocol) { | |
1546 | case ATA_PROT_PIO: | |
1547 | case ATA_PROT_NODATA: | |
1548 | case ATAPI_PROT_PIO: | |
1549 | case ATAPI_PROT_NODATA: | |
1550 | qc->tf.flags |= ATA_TFLAG_POLLING; | |
1551 | break; | |
1552 | case ATAPI_PROT_DMA: | |
1553 | if (qc->dev->flags & ATA_DFLAG_CDB_INTR) | |
1554 | /* see ata_dma_blacklisted() */ | |
1555 | BUG(); | |
1556 | break; | |
1557 | default: | |
1558 | break; | |
1559 | } | |
1560 | } | |
1561 | ||
1562 | /* select the device */ | |
1563 | ata_dev_select(ap, qc->dev->devno, 1, 0); | |
1564 | ||
1565 | /* start the command */ | |
1566 | switch (qc->tf.protocol) { | |
1567 | case ATA_PROT_NODATA: | |
1568 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1569 | ata_qc_set_polling(qc); | |
1570 | ||
1571 | ata_tf_to_host(ap, &qc->tf); | |
1572 | ap->hsm_task_state = HSM_ST_LAST; | |
1573 | ||
1574 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1575 | ata_pio_queue_task(ap, qc, 0); | |
1576 | ||
1577 | break; | |
1578 | ||
1579 | case ATA_PROT_DMA: | |
efcb3cf7 | 1580 | WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING); |
624d5c51 | 1581 | |
5682ed33 | 1582 | ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ |
624d5c51 TH |
1583 | ap->ops->bmdma_setup(qc); /* set up bmdma */ |
1584 | ap->ops->bmdma_start(qc); /* initiate bmdma */ | |
1585 | ap->hsm_task_state = HSM_ST_LAST; | |
1586 | break; | |
1587 | ||
1588 | case ATA_PROT_PIO: | |
1589 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1590 | ata_qc_set_polling(qc); | |
1591 | ||
1592 | ata_tf_to_host(ap, &qc->tf); | |
1593 | ||
1594 | if (qc->tf.flags & ATA_TFLAG_WRITE) { | |
1595 | /* PIO data out protocol */ | |
1596 | ap->hsm_task_state = HSM_ST_FIRST; | |
1597 | ata_pio_queue_task(ap, qc, 0); | |
1598 | ||
1599 | /* always send first data block using | |
1600 | * the ata_pio_task() codepath. | |
1601 | */ | |
1602 | } else { | |
1603 | /* PIO data in protocol */ | |
1604 | ap->hsm_task_state = HSM_ST; | |
1605 | ||
1606 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1607 | ata_pio_queue_task(ap, qc, 0); | |
1608 | ||
1609 | /* if polling, ata_pio_task() handles the rest. | |
1610 | * otherwise, interrupt handler takes over from here. | |
1611 | */ | |
1612 | } | |
1613 | ||
1614 | break; | |
1615 | ||
1616 | case ATAPI_PROT_PIO: | |
1617 | case ATAPI_PROT_NODATA: | |
1618 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1619 | ata_qc_set_polling(qc); | |
1620 | ||
1621 | ata_tf_to_host(ap, &qc->tf); | |
1622 | ||
1623 | ap->hsm_task_state = HSM_ST_FIRST; | |
1624 | ||
1625 | /* send cdb by polling if no cdb interrupt */ | |
1626 | if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) || | |
1627 | (qc->tf.flags & ATA_TFLAG_POLLING)) | |
1628 | ata_pio_queue_task(ap, qc, 0); | |
1629 | break; | |
1630 | ||
1631 | case ATAPI_PROT_DMA: | |
efcb3cf7 | 1632 | WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING); |
624d5c51 | 1633 | |
5682ed33 | 1634 | ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ |
624d5c51 TH |
1635 | ap->ops->bmdma_setup(qc); /* set up bmdma */ |
1636 | ap->hsm_task_state = HSM_ST_FIRST; | |
1637 | ||
1638 | /* send cdb by polling if no cdb interrupt */ | |
1639 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
1640 | ata_pio_queue_task(ap, qc, 0); | |
1641 | break; | |
1642 | ||
1643 | default: | |
efcb3cf7 | 1644 | WARN_ON_ONCE(1); |
624d5c51 TH |
1645 | return AC_ERR_SYSTEM; |
1646 | } | |
1647 | ||
1648 | return 0; | |
1649 | } | |
0fe40ff8 | 1650 | EXPORT_SYMBOL_GPL(ata_sff_qc_issue); |
624d5c51 | 1651 | |
22183bf5 TH |
1652 | /** |
1653 | * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read | |
1654 | * @qc: qc to fill result TF for | |
1655 | * | |
1656 | * @qc is finished and result TF needs to be filled. Fill it | |
1657 | * using ->sff_tf_read. | |
1658 | * | |
1659 | * LOCKING: | |
1660 | * spin_lock_irqsave(host lock) | |
1661 | * | |
1662 | * RETURNS: | |
1663 | * true indicating that result TF is successfully filled. | |
1664 | */ | |
1665 | bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc) | |
1666 | { | |
1667 | qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf); | |
1668 | return true; | |
1669 | } | |
0fe40ff8 | 1670 | EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf); |
22183bf5 | 1671 | |
624d5c51 | 1672 | /** |
9363c382 | 1673 | * ata_sff_host_intr - Handle host interrupt for given (port, task) |
624d5c51 TH |
1674 | * @ap: Port on which interrupt arrived (possibly...) |
1675 | * @qc: Taskfile currently active in engine | |
1676 | * | |
1677 | * Handle host interrupt for given queued command. Currently, | |
1678 | * only DMA interrupts are handled. All other commands are | |
1679 | * handled via polling with interrupts disabled (nIEN bit). | |
1680 | * | |
1681 | * LOCKING: | |
1682 | * spin_lock_irqsave(host lock) | |
1683 | * | |
1684 | * RETURNS: | |
1685 | * One if interrupt was handled, zero if not (shared irq). | |
1686 | */ | |
c96f1732 | 1687 | unsigned int ata_sff_host_intr(struct ata_port *ap, |
9363c382 | 1688 | struct ata_queued_cmd *qc) |
624d5c51 TH |
1689 | { |
1690 | struct ata_eh_info *ehi = &ap->link.eh_info; | |
1691 | u8 status, host_stat = 0; | |
332ac7ff | 1692 | bool bmdma_stopped = false; |
624d5c51 TH |
1693 | |
1694 | VPRINTK("ata%u: protocol %d task_state %d\n", | |
1695 | ap->print_id, qc->tf.protocol, ap->hsm_task_state); | |
1696 | ||
1697 | /* Check whether we are expecting interrupt in this state */ | |
1698 | switch (ap->hsm_task_state) { | |
1699 | case HSM_ST_FIRST: | |
1700 | /* Some pre-ATAPI-4 devices assert INTRQ | |
1701 | * at this state when ready to receive CDB. | |
1702 | */ | |
1703 | ||
1704 | /* Check the ATA_DFLAG_CDB_INTR flag is enough here. | |
1705 | * The flag was turned on only for atapi devices. No | |
1706 | * need to check ata_is_atapi(qc->tf.protocol) again. | |
1707 | */ | |
1708 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
1709 | goto idle_irq; | |
1710 | break; | |
1711 | case HSM_ST_LAST: | |
1712 | if (qc->tf.protocol == ATA_PROT_DMA || | |
1713 | qc->tf.protocol == ATAPI_PROT_DMA) { | |
1714 | /* check status of DMA engine */ | |
1715 | host_stat = ap->ops->bmdma_status(ap); | |
1716 | VPRINTK("ata%u: host_stat 0x%X\n", | |
1717 | ap->print_id, host_stat); | |
1718 | ||
1719 | /* if it's not our irq... */ | |
1720 | if (!(host_stat & ATA_DMA_INTR)) | |
1721 | goto idle_irq; | |
1722 | ||
1723 | /* before we do anything else, clear DMA-Start bit */ | |
1724 | ap->ops->bmdma_stop(qc); | |
332ac7ff | 1725 | bmdma_stopped = true; |
624d5c51 TH |
1726 | |
1727 | if (unlikely(host_stat & ATA_DMA_ERR)) { | |
1728 | /* error when transfering data to/from memory */ | |
1729 | qc->err_mask |= AC_ERR_HOST_BUS; | |
1730 | ap->hsm_task_state = HSM_ST_ERR; | |
1731 | } | |
1732 | } | |
1733 | break; | |
1734 | case HSM_ST: | |
1735 | break; | |
1736 | default: | |
1737 | goto idle_irq; | |
1738 | } | |
1739 | ||
624d5c51 | 1740 | |
a57c1bad AC |
1741 | /* check main status, clearing INTRQ if needed */ |
1742 | status = ata_sff_irq_status(ap); | |
332ac7ff TH |
1743 | if (status & ATA_BUSY) { |
1744 | if (bmdma_stopped) { | |
1745 | /* BMDMA engine is already stopped, we're screwed */ | |
1746 | qc->err_mask |= AC_ERR_HSM; | |
1747 | ap->hsm_task_state = HSM_ST_ERR; | |
1748 | } else | |
1749 | goto idle_irq; | |
1750 | } | |
624d5c51 TH |
1751 | |
1752 | /* ack bmdma irq events */ | |
5682ed33 | 1753 | ap->ops->sff_irq_clear(ap); |
624d5c51 | 1754 | |
9363c382 | 1755 | ata_sff_hsm_move(ap, qc, status, 0); |
624d5c51 TH |
1756 | |
1757 | if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA || | |
1758 | qc->tf.protocol == ATAPI_PROT_DMA)) | |
1759 | ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat); | |
1760 | ||
1761 | return 1; /* irq handled */ | |
1762 | ||
1763 | idle_irq: | |
1764 | ap->stats.idle_irq++; | |
1765 | ||
1766 | #ifdef ATA_IRQ_TRAP | |
1767 | if ((ap->stats.idle_irq % 1000) == 0) { | |
5682ed33 TH |
1768 | ap->ops->sff_check_status(ap); |
1769 | ap->ops->sff_irq_clear(ap); | |
624d5c51 TH |
1770 | ata_port_printk(ap, KERN_WARNING, "irq trap\n"); |
1771 | return 1; | |
1772 | } | |
1773 | #endif | |
1774 | return 0; /* irq not handled */ | |
1775 | } | |
0fe40ff8 | 1776 | EXPORT_SYMBOL_GPL(ata_sff_host_intr); |
624d5c51 TH |
1777 | |
1778 | /** | |
9363c382 | 1779 | * ata_sff_interrupt - Default ATA host interrupt handler |
624d5c51 TH |
1780 | * @irq: irq line (unused) |
1781 | * @dev_instance: pointer to our ata_host information structure | |
1782 | * | |
1783 | * Default interrupt handler for PCI IDE devices. Calls | |
9363c382 | 1784 | * ata_sff_host_intr() for each port that is not disabled. |
624d5c51 TH |
1785 | * |
1786 | * LOCKING: | |
1787 | * Obtains host lock during operation. | |
1788 | * | |
1789 | * RETURNS: | |
1790 | * IRQ_NONE or IRQ_HANDLED. | |
1791 | */ | |
9363c382 | 1792 | irqreturn_t ata_sff_interrupt(int irq, void *dev_instance) |
624d5c51 TH |
1793 | { |
1794 | struct ata_host *host = dev_instance; | |
332ac7ff | 1795 | bool retried = false; |
624d5c51 | 1796 | unsigned int i; |
332ac7ff | 1797 | unsigned int handled, idle, polling; |
624d5c51 TH |
1798 | unsigned long flags; |
1799 | ||
1800 | /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */ | |
1801 | spin_lock_irqsave(&host->lock, flags); | |
1802 | ||
332ac7ff TH |
1803 | retry: |
1804 | handled = idle = polling = 0; | |
624d5c51 | 1805 | for (i = 0; i < host->n_ports; i++) { |
d88ec2e5 TH |
1806 | struct ata_port *ap = host->ports[i]; |
1807 | struct ata_queued_cmd *qc; | |
624d5c51 | 1808 | |
d88ec2e5 TH |
1809 | if (unlikely(ap->flags & ATA_FLAG_DISABLED)) |
1810 | continue; | |
624d5c51 | 1811 | |
d88ec2e5 | 1812 | qc = ata_qc_from_tag(ap, ap->link.active_tag); |
27943620 TH |
1813 | if (qc) { |
1814 | if (!(qc->tf.flags & ATA_TFLAG_POLLING)) | |
1815 | handled |= ata_sff_host_intr(ap, qc); | |
1816 | else | |
1817 | polling |= 1 << i; | |
332ac7ff TH |
1818 | } else |
1819 | idle |= 1 << i; | |
27943620 TH |
1820 | } |
1821 | ||
1822 | /* | |
1823 | * If no port was expecting IRQ but the controller is actually | |
1824 | * asserting IRQ line, nobody cared will ensue. Check IRQ | |
1825 | * pending status if available and clear spurious IRQ. | |
1826 | */ | |
332ac7ff TH |
1827 | if (!handled && !retried) { |
1828 | bool retry = false; | |
1829 | ||
27943620 TH |
1830 | for (i = 0; i < host->n_ports; i++) { |
1831 | struct ata_port *ap = host->ports[i]; | |
1832 | ||
1833 | if (polling & (1 << i)) | |
1834 | continue; | |
1835 | ||
1836 | if (!ap->ops->sff_irq_check || | |
1837 | !ap->ops->sff_irq_check(ap)) | |
1838 | continue; | |
1839 | ||
332ac7ff TH |
1840 | if (idle & (1 << i)) { |
1841 | ap->ops->sff_check_status(ap); | |
1842 | ap->ops->sff_irq_clear(ap); | |
1843 | } else { | |
1844 | /* clear INTRQ and check if BUSY cleared */ | |
1845 | if (!(ap->ops->sff_check_status(ap) & ATA_BUSY)) | |
1846 | retry |= true; | |
1847 | /* | |
1848 | * With command in flight, we can't do | |
1849 | * sff_irq_clear() w/o racing with completion. | |
1850 | */ | |
1851 | } | |
1852 | } | |
1853 | ||
1854 | if (retry) { | |
1855 | retried = true; | |
1856 | goto retry; | |
27943620 | 1857 | } |
624d5c51 TH |
1858 | } |
1859 | ||
1860 | spin_unlock_irqrestore(&host->lock, flags); | |
1861 | ||
1862 | return IRQ_RETVAL(handled); | |
1863 | } | |
0fe40ff8 | 1864 | EXPORT_SYMBOL_GPL(ata_sff_interrupt); |
624d5c51 | 1865 | |
c96f1732 AC |
1866 | /** |
1867 | * ata_sff_lost_interrupt - Check for an apparent lost interrupt | |
1868 | * @ap: port that appears to have timed out | |
1869 | * | |
1870 | * Called from the libata error handlers when the core code suspects | |
1871 | * an interrupt has been lost. If it has complete anything we can and | |
1872 | * then return. Interface must support altstatus for this faster | |
1873 | * recovery to occur. | |
1874 | * | |
1875 | * Locking: | |
1876 | * Caller holds host lock | |
1877 | */ | |
1878 | ||
1879 | void ata_sff_lost_interrupt(struct ata_port *ap) | |
1880 | { | |
1881 | u8 status; | |
1882 | struct ata_queued_cmd *qc; | |
1883 | ||
1884 | /* Only one outstanding command per SFF channel */ | |
1885 | qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
1886 | /* Check we have a live one.. */ | |
1887 | if (qc == NULL || !(qc->flags & ATA_QCFLAG_ACTIVE)) | |
1888 | return; | |
1889 | /* We cannot lose an interrupt on a polled command */ | |
1890 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1891 | return; | |
1892 | /* See if the controller thinks it is still busy - if so the command | |
1893 | isn't a lost IRQ but is still in progress */ | |
1894 | status = ata_sff_altstatus(ap); | |
1895 | if (status & ATA_BUSY) | |
1896 | return; | |
1897 | ||
1898 | /* There was a command running, we are no longer busy and we have | |
1899 | no interrupt. */ | |
1900 | ata_port_printk(ap, KERN_WARNING, "lost interrupt (Status 0x%x)\n", | |
1901 | status); | |
1902 | /* Run the host interrupt logic as if the interrupt had not been | |
1903 | lost */ | |
1904 | ata_sff_host_intr(ap, qc); | |
1905 | } | |
1906 | EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt); | |
1907 | ||
624d5c51 | 1908 | /** |
9363c382 | 1909 | * ata_sff_freeze - Freeze SFF controller port |
624d5c51 TH |
1910 | * @ap: port to freeze |
1911 | * | |
1912 | * Freeze BMDMA controller port. | |
1913 | * | |
1914 | * LOCKING: | |
1915 | * Inherited from caller. | |
1916 | */ | |
9363c382 | 1917 | void ata_sff_freeze(struct ata_port *ap) |
624d5c51 | 1918 | { |
624d5c51 TH |
1919 | ap->ctl |= ATA_NIEN; |
1920 | ap->last_ctl = ap->ctl; | |
1921 | ||
41dec29b SS |
1922 | if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) |
1923 | ata_sff_set_devctl(ap, ap->ctl); | |
624d5c51 TH |
1924 | |
1925 | /* Under certain circumstances, some controllers raise IRQ on | |
1926 | * ATA_NIEN manipulation. Also, many controllers fail to mask | |
1927 | * previously pending IRQ on ATA_NIEN assertion. Clear it. | |
1928 | */ | |
5682ed33 | 1929 | ap->ops->sff_check_status(ap); |
624d5c51 | 1930 | |
5682ed33 | 1931 | ap->ops->sff_irq_clear(ap); |
624d5c51 | 1932 | } |
0fe40ff8 | 1933 | EXPORT_SYMBOL_GPL(ata_sff_freeze); |
624d5c51 TH |
1934 | |
1935 | /** | |
9363c382 | 1936 | * ata_sff_thaw - Thaw SFF controller port |
624d5c51 TH |
1937 | * @ap: port to thaw |
1938 | * | |
9363c382 | 1939 | * Thaw SFF controller port. |
624d5c51 TH |
1940 | * |
1941 | * LOCKING: | |
1942 | * Inherited from caller. | |
1943 | */ | |
9363c382 | 1944 | void ata_sff_thaw(struct ata_port *ap) |
272f7884 | 1945 | { |
624d5c51 | 1946 | /* clear & re-enable interrupts */ |
5682ed33 TH |
1947 | ap->ops->sff_check_status(ap); |
1948 | ap->ops->sff_irq_clear(ap); | |
1949 | ap->ops->sff_irq_on(ap); | |
272f7884 | 1950 | } |
0fe40ff8 | 1951 | EXPORT_SYMBOL_GPL(ata_sff_thaw); |
272f7884 | 1952 | |
0aa1113d TH |
1953 | /** |
1954 | * ata_sff_prereset - prepare SFF link for reset | |
1955 | * @link: SFF link to be reset | |
1956 | * @deadline: deadline jiffies for the operation | |
1957 | * | |
1958 | * SFF link @link is about to be reset. Initialize it. It first | |
1959 | * calls ata_std_prereset() and wait for !BSY if the port is | |
1960 | * being softreset. | |
1961 | * | |
1962 | * LOCKING: | |
1963 | * Kernel thread context (may sleep) | |
1964 | * | |
1965 | * RETURNS: | |
1966 | * 0 on success, -errno otherwise. | |
1967 | */ | |
1968 | int ata_sff_prereset(struct ata_link *link, unsigned long deadline) | |
1969 | { | |
0aa1113d TH |
1970 | struct ata_eh_context *ehc = &link->eh_context; |
1971 | int rc; | |
1972 | ||
1973 | rc = ata_std_prereset(link, deadline); | |
1974 | if (rc) | |
1975 | return rc; | |
1976 | ||
1977 | /* if we're about to do hardreset, nothing more to do */ | |
1978 | if (ehc->i.action & ATA_EH_HARDRESET) | |
1979 | return 0; | |
1980 | ||
1981 | /* wait for !BSY if we don't know that no device is attached */ | |
1982 | if (!ata_link_offline(link)) { | |
705e76be | 1983 | rc = ata_sff_wait_ready(link, deadline); |
0aa1113d TH |
1984 | if (rc && rc != -ENODEV) { |
1985 | ata_link_printk(link, KERN_WARNING, "device not ready " | |
1986 | "(errno=%d), forcing hardreset\n", rc); | |
1987 | ehc->i.action |= ATA_EH_HARDRESET; | |
1988 | } | |
1989 | } | |
1990 | ||
1991 | return 0; | |
1992 | } | |
0fe40ff8 | 1993 | EXPORT_SYMBOL_GPL(ata_sff_prereset); |
0aa1113d | 1994 | |
90088bb4 | 1995 | /** |
624d5c51 TH |
1996 | * ata_devchk - PATA device presence detection |
1997 | * @ap: ATA channel to examine | |
1998 | * @device: Device to examine (starting at zero) | |
90088bb4 | 1999 | * |
624d5c51 TH |
2000 | * This technique was originally described in |
2001 | * Hale Landis's ATADRVR (www.ata-atapi.com), and | |
2002 | * later found its way into the ATA/ATAPI spec. | |
2003 | * | |
2004 | * Write a pattern to the ATA shadow registers, | |
2005 | * and if a device is present, it will respond by | |
2006 | * correctly storing and echoing back the | |
2007 | * ATA shadow register contents. | |
90088bb4 TH |
2008 | * |
2009 | * LOCKING: | |
624d5c51 | 2010 | * caller. |
90088bb4 | 2011 | */ |
624d5c51 | 2012 | static unsigned int ata_devchk(struct ata_port *ap, unsigned int device) |
90088bb4 TH |
2013 | { |
2014 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
624d5c51 | 2015 | u8 nsect, lbal; |
90088bb4 | 2016 | |
5682ed33 | 2017 | ap->ops->sff_dev_select(ap, device); |
90088bb4 | 2018 | |
624d5c51 TH |
2019 | iowrite8(0x55, ioaddr->nsect_addr); |
2020 | iowrite8(0xaa, ioaddr->lbal_addr); | |
90088bb4 | 2021 | |
624d5c51 TH |
2022 | iowrite8(0xaa, ioaddr->nsect_addr); |
2023 | iowrite8(0x55, ioaddr->lbal_addr); | |
90088bb4 | 2024 | |
624d5c51 TH |
2025 | iowrite8(0x55, ioaddr->nsect_addr); |
2026 | iowrite8(0xaa, ioaddr->lbal_addr); | |
2027 | ||
2028 | nsect = ioread8(ioaddr->nsect_addr); | |
2029 | lbal = ioread8(ioaddr->lbal_addr); | |
2030 | ||
2031 | if ((nsect == 0x55) && (lbal == 0xaa)) | |
2032 | return 1; /* we found a device */ | |
2033 | ||
2034 | return 0; /* nothing found */ | |
90088bb4 TH |
2035 | } |
2036 | ||
272f7884 | 2037 | /** |
9363c382 | 2038 | * ata_sff_dev_classify - Parse returned ATA device signature |
624d5c51 TH |
2039 | * @dev: ATA device to classify (starting at zero) |
2040 | * @present: device seems present | |
2041 | * @r_err: Value of error register on completion | |
272f7884 | 2042 | * |
624d5c51 TH |
2043 | * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs, |
2044 | * an ATA/ATAPI-defined set of values is placed in the ATA | |
2045 | * shadow registers, indicating the results of device detection | |
2046 | * and diagnostics. | |
272f7884 | 2047 | * |
624d5c51 TH |
2048 | * Select the ATA device, and read the values from the ATA shadow |
2049 | * registers. Then parse according to the Error register value, | |
2050 | * and the spec-defined values examined by ata_dev_classify(). | |
272f7884 TH |
2051 | * |
2052 | * LOCKING: | |
624d5c51 TH |
2053 | * caller. |
2054 | * | |
2055 | * RETURNS: | |
2056 | * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE. | |
272f7884 | 2057 | */ |
9363c382 | 2058 | unsigned int ata_sff_dev_classify(struct ata_device *dev, int present, |
624d5c51 | 2059 | u8 *r_err) |
272f7884 | 2060 | { |
624d5c51 TH |
2061 | struct ata_port *ap = dev->link->ap; |
2062 | struct ata_taskfile tf; | |
2063 | unsigned int class; | |
2064 | u8 err; | |
2065 | ||
5682ed33 | 2066 | ap->ops->sff_dev_select(ap, dev->devno); |
624d5c51 TH |
2067 | |
2068 | memset(&tf, 0, sizeof(tf)); | |
2069 | ||
5682ed33 | 2070 | ap->ops->sff_tf_read(ap, &tf); |
624d5c51 TH |
2071 | err = tf.feature; |
2072 | if (r_err) | |
2073 | *r_err = err; | |
2074 | ||
2075 | /* see if device passed diags: continue and warn later */ | |
2076 | if (err == 0) | |
2077 | /* diagnostic fail : do nothing _YET_ */ | |
2078 | dev->horkage |= ATA_HORKAGE_DIAGNOSTIC; | |
2079 | else if (err == 1) | |
2080 | /* do nothing */ ; | |
2081 | else if ((dev->devno == 0) && (err == 0x81)) | |
2082 | /* do nothing */ ; | |
2083 | else | |
2084 | return ATA_DEV_NONE; | |
272f7884 | 2085 | |
624d5c51 TH |
2086 | /* determine if device is ATA or ATAPI */ |
2087 | class = ata_dev_classify(&tf); | |
272f7884 | 2088 | |
624d5c51 TH |
2089 | if (class == ATA_DEV_UNKNOWN) { |
2090 | /* If the device failed diagnostic, it's likely to | |
2091 | * have reported incorrect device signature too. | |
2092 | * Assume ATA device if the device seems present but | |
2093 | * device signature is invalid with diagnostic | |
2094 | * failure. | |
2095 | */ | |
2096 | if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC)) | |
2097 | class = ATA_DEV_ATA; | |
2098 | else | |
2099 | class = ATA_DEV_NONE; | |
5682ed33 TH |
2100 | } else if ((class == ATA_DEV_ATA) && |
2101 | (ap->ops->sff_check_status(ap) == 0)) | |
624d5c51 TH |
2102 | class = ATA_DEV_NONE; |
2103 | ||
2104 | return class; | |
272f7884 | 2105 | } |
0fe40ff8 | 2106 | EXPORT_SYMBOL_GPL(ata_sff_dev_classify); |
272f7884 | 2107 | |
705e76be TH |
2108 | /** |
2109 | * ata_sff_wait_after_reset - wait for devices to become ready after reset | |
2110 | * @link: SFF link which is just reset | |
2111 | * @devmask: mask of present devices | |
2112 | * @deadline: deadline jiffies for the operation | |
2113 | * | |
2114 | * Wait devices attached to SFF @link to become ready after | |
2115 | * reset. It contains preceding 150ms wait to avoid accessing TF | |
2116 | * status register too early. | |
2117 | * | |
2118 | * LOCKING: | |
2119 | * Kernel thread context (may sleep). | |
2120 | * | |
2121 | * RETURNS: | |
2122 | * 0 on success, -ENODEV if some or all of devices in @devmask | |
2123 | * don't seem to exist. -errno on other errors. | |
2124 | */ | |
2125 | int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask, | |
2126 | unsigned long deadline) | |
1fdffbce | 2127 | { |
705e76be | 2128 | struct ata_port *ap = link->ap; |
1fdffbce | 2129 | struct ata_ioports *ioaddr = &ap->ioaddr; |
624d5c51 TH |
2130 | unsigned int dev0 = devmask & (1 << 0); |
2131 | unsigned int dev1 = devmask & (1 << 1); | |
2132 | int rc, ret = 0; | |
1fdffbce | 2133 | |
341c2c95 | 2134 | msleep(ATA_WAIT_AFTER_RESET); |
705e76be TH |
2135 | |
2136 | /* always check readiness of the master device */ | |
2137 | rc = ata_sff_wait_ready(link, deadline); | |
2138 | /* -ENODEV means the odd clown forgot the D7 pulldown resistor | |
2139 | * and TF status is 0xff, bail out on it too. | |
624d5c51 | 2140 | */ |
705e76be TH |
2141 | if (rc) |
2142 | return rc; | |
1fdffbce | 2143 | |
624d5c51 TH |
2144 | /* if device 1 was found in ata_devchk, wait for register |
2145 | * access briefly, then wait for BSY to clear. | |
2146 | */ | |
2147 | if (dev1) { | |
2148 | int i; | |
1fdffbce | 2149 | |
5682ed33 | 2150 | ap->ops->sff_dev_select(ap, 1); |
1fdffbce | 2151 | |
624d5c51 TH |
2152 | /* Wait for register access. Some ATAPI devices fail |
2153 | * to set nsect/lbal after reset, so don't waste too | |
2154 | * much time on it. We're gonna wait for !BSY anyway. | |
2155 | */ | |
2156 | for (i = 0; i < 2; i++) { | |
2157 | u8 nsect, lbal; | |
2158 | ||
2159 | nsect = ioread8(ioaddr->nsect_addr); | |
2160 | lbal = ioread8(ioaddr->lbal_addr); | |
2161 | if ((nsect == 1) && (lbal == 1)) | |
2162 | break; | |
2163 | msleep(50); /* give drive a breather */ | |
2164 | } | |
2165 | ||
705e76be | 2166 | rc = ata_sff_wait_ready(link, deadline); |
624d5c51 TH |
2167 | if (rc) { |
2168 | if (rc != -ENODEV) | |
2169 | return rc; | |
2170 | ret = rc; | |
2171 | } | |
1fdffbce JG |
2172 | } |
2173 | ||
624d5c51 | 2174 | /* is all this really necessary? */ |
5682ed33 | 2175 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 | 2176 | if (dev1) |
5682ed33 | 2177 | ap->ops->sff_dev_select(ap, 1); |
624d5c51 | 2178 | if (dev0) |
5682ed33 | 2179 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
2180 | |
2181 | return ret; | |
1fdffbce | 2182 | } |
0fe40ff8 | 2183 | EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset); |
1fdffbce | 2184 | |
624d5c51 TH |
2185 | static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask, |
2186 | unsigned long deadline) | |
2cc432ee | 2187 | { |
624d5c51 | 2188 | struct ata_ioports *ioaddr = &ap->ioaddr; |
2cc432ee | 2189 | |
624d5c51 TH |
2190 | DPRINTK("ata%u: bus reset via SRST\n", ap->print_id); |
2191 | ||
2192 | /* software reset. causes dev0 to be selected */ | |
2193 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
2194 | udelay(20); /* FIXME: flush */ | |
2195 | iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr); | |
2196 | udelay(20); /* FIXME: flush */ | |
2197 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
e3e4385f | 2198 | ap->last_ctl = ap->ctl; |
624d5c51 | 2199 | |
705e76be TH |
2200 | /* wait the port to become ready */ |
2201 | return ata_sff_wait_after_reset(&ap->link, devmask, deadline); | |
2cc432ee JG |
2202 | } |
2203 | ||
6d97dbd7 | 2204 | /** |
9363c382 | 2205 | * ata_sff_softreset - reset host port via ATA SRST |
624d5c51 TH |
2206 | * @link: ATA link to reset |
2207 | * @classes: resulting classes of attached devices | |
2208 | * @deadline: deadline jiffies for the operation | |
6d97dbd7 | 2209 | * |
624d5c51 | 2210 | * Reset host port using ATA SRST. |
6d97dbd7 TH |
2211 | * |
2212 | * LOCKING: | |
624d5c51 TH |
2213 | * Kernel thread context (may sleep) |
2214 | * | |
2215 | * RETURNS: | |
2216 | * 0 on success, -errno otherwise. | |
6d97dbd7 | 2217 | */ |
9363c382 | 2218 | int ata_sff_softreset(struct ata_link *link, unsigned int *classes, |
624d5c51 | 2219 | unsigned long deadline) |
6d97dbd7 | 2220 | { |
624d5c51 TH |
2221 | struct ata_port *ap = link->ap; |
2222 | unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; | |
2223 | unsigned int devmask = 0; | |
2224 | int rc; | |
2225 | u8 err; | |
6d97dbd7 | 2226 | |
624d5c51 | 2227 | DPRINTK("ENTER\n"); |
6d97dbd7 | 2228 | |
624d5c51 TH |
2229 | /* determine if device 0/1 are present */ |
2230 | if (ata_devchk(ap, 0)) | |
2231 | devmask |= (1 << 0); | |
2232 | if (slave_possible && ata_devchk(ap, 1)) | |
2233 | devmask |= (1 << 1); | |
2234 | ||
2235 | /* select device 0 again */ | |
5682ed33 | 2236 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
2237 | |
2238 | /* issue bus reset */ | |
2239 | DPRINTK("about to softreset, devmask=%x\n", devmask); | |
2240 | rc = ata_bus_softreset(ap, devmask, deadline); | |
2241 | /* if link is occupied, -ENODEV too is an error */ | |
2242 | if (rc && (rc != -ENODEV || sata_scr_valid(link))) { | |
2243 | ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc); | |
2244 | return rc; | |
2245 | } | |
0f0a3ad3 | 2246 | |
624d5c51 | 2247 | /* determine by signature whether we have ATA or ATAPI devices */ |
9363c382 | 2248 | classes[0] = ata_sff_dev_classify(&link->device[0], |
624d5c51 TH |
2249 | devmask & (1 << 0), &err); |
2250 | if (slave_possible && err != 0x81) | |
9363c382 | 2251 | classes[1] = ata_sff_dev_classify(&link->device[1], |
624d5c51 TH |
2252 | devmask & (1 << 1), &err); |
2253 | ||
624d5c51 TH |
2254 | DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]); |
2255 | return 0; | |
6d97dbd7 | 2256 | } |
0fe40ff8 | 2257 | EXPORT_SYMBOL_GPL(ata_sff_softreset); |
6d97dbd7 TH |
2258 | |
2259 | /** | |
9363c382 | 2260 | * sata_sff_hardreset - reset host port via SATA phy reset |
624d5c51 TH |
2261 | * @link: link to reset |
2262 | * @class: resulting class of attached device | |
2263 | * @deadline: deadline jiffies for the operation | |
6d97dbd7 | 2264 | * |
624d5c51 TH |
2265 | * SATA phy-reset host port using DET bits of SControl register, |
2266 | * wait for !BSY and classify the attached device. | |
6d97dbd7 TH |
2267 | * |
2268 | * LOCKING: | |
624d5c51 TH |
2269 | * Kernel thread context (may sleep) |
2270 | * | |
2271 | * RETURNS: | |
2272 | * 0 on success, -errno otherwise. | |
6d97dbd7 | 2273 | */ |
9363c382 | 2274 | int sata_sff_hardreset(struct ata_link *link, unsigned int *class, |
624d5c51 | 2275 | unsigned long deadline) |
6d97dbd7 | 2276 | { |
9dadd45b TH |
2277 | struct ata_eh_context *ehc = &link->eh_context; |
2278 | const unsigned long *timing = sata_ehc_deb_timing(ehc); | |
2279 | bool online; | |
624d5c51 TH |
2280 | int rc; |
2281 | ||
9dadd45b TH |
2282 | rc = sata_link_hardreset(link, timing, deadline, &online, |
2283 | ata_sff_check_ready); | |
9dadd45b TH |
2284 | if (online) |
2285 | *class = ata_sff_dev_classify(link->device, 1, NULL); | |
624d5c51 TH |
2286 | |
2287 | DPRINTK("EXIT, class=%u\n", *class); | |
9dadd45b | 2288 | return rc; |
6d97dbd7 | 2289 | } |
0fe40ff8 | 2290 | EXPORT_SYMBOL_GPL(sata_sff_hardreset); |
6d97dbd7 | 2291 | |
203c75b8 TH |
2292 | /** |
2293 | * ata_sff_postreset - SFF postreset callback | |
2294 | * @link: the target SFF ata_link | |
2295 | * @classes: classes of attached devices | |
2296 | * | |
2297 | * This function is invoked after a successful reset. It first | |
2298 | * calls ata_std_postreset() and performs SFF specific postreset | |
2299 | * processing. | |
2300 | * | |
2301 | * LOCKING: | |
2302 | * Kernel thread context (may sleep) | |
2303 | */ | |
2304 | void ata_sff_postreset(struct ata_link *link, unsigned int *classes) | |
2305 | { | |
2306 | struct ata_port *ap = link->ap; | |
2307 | ||
2308 | ata_std_postreset(link, classes); | |
2309 | ||
2310 | /* is double-select really necessary? */ | |
2311 | if (classes[0] != ATA_DEV_NONE) | |
2312 | ap->ops->sff_dev_select(ap, 1); | |
2313 | if (classes[1] != ATA_DEV_NONE) | |
2314 | ap->ops->sff_dev_select(ap, 0); | |
2315 | ||
2316 | /* bail out if no device is present */ | |
2317 | if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) { | |
2318 | DPRINTK("EXIT, no device\n"); | |
2319 | return; | |
2320 | } | |
2321 | ||
2322 | /* set up device control */ | |
41dec29b SS |
2323 | if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) { |
2324 | ata_sff_set_devctl(ap, ap->ctl); | |
e3e4385f SM |
2325 | ap->last_ctl = ap->ctl; |
2326 | } | |
203c75b8 | 2327 | } |
0fe40ff8 | 2328 | EXPORT_SYMBOL_GPL(ata_sff_postreset); |
203c75b8 | 2329 | |
3d47aa8e AC |
2330 | /** |
2331 | * ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers | |
2332 | * @qc: command | |
2333 | * | |
2334 | * Drain the FIFO and device of any stuck data following a command | |
3ad2f3fb | 2335 | * failing to complete. In some cases this is necessary before a |
3d47aa8e AC |
2336 | * reset will recover the device. |
2337 | * | |
2338 | */ | |
2339 | ||
2340 | void ata_sff_drain_fifo(struct ata_queued_cmd *qc) | |
2341 | { | |
2342 | int count; | |
2343 | struct ata_port *ap; | |
2344 | ||
2345 | /* We only need to flush incoming data when a command was running */ | |
2346 | if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE) | |
2347 | return; | |
2348 | ||
2349 | ap = qc->ap; | |
2350 | /* Drain up to 64K of data before we give up this recovery method */ | |
2351 | for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) | |
9a8fd68b | 2352 | && count < 65536; count += 2) |
3d47aa8e AC |
2353 | ioread16(ap->ioaddr.data_addr); |
2354 | ||
2355 | /* Can become DEBUG later */ | |
2356 | if (count) | |
2357 | ata_port_printk(ap, KERN_DEBUG, | |
2358 | "drained %d bytes to clear DRQ.\n", count); | |
2359 | ||
2360 | } | |
2361 | EXPORT_SYMBOL_GPL(ata_sff_drain_fifo); | |
2362 | ||
6d97dbd7 | 2363 | /** |
9363c382 | 2364 | * ata_sff_error_handler - Stock error handler for BMDMA controller |
6d97dbd7 | 2365 | * @ap: port to handle error for |
6d97dbd7 | 2366 | * |
9363c382 | 2367 | * Stock error handler for SFF controller. It can handle both |
6d97dbd7 TH |
2368 | * PATA and SATA controllers. Many controllers should be able to |
2369 | * use this EH as-is or with some added handling before and | |
2370 | * after. | |
2371 | * | |
6d97dbd7 TH |
2372 | * LOCKING: |
2373 | * Kernel thread context (may sleep) | |
2374 | */ | |
9363c382 | 2375 | void ata_sff_error_handler(struct ata_port *ap) |
6d97dbd7 | 2376 | { |
a1efdaba TH |
2377 | ata_reset_fn_t softreset = ap->ops->softreset; |
2378 | ata_reset_fn_t hardreset = ap->ops->hardreset; | |
6d97dbd7 TH |
2379 | struct ata_queued_cmd *qc; |
2380 | unsigned long flags; | |
2381 | int thaw = 0; | |
2382 | ||
9af5c9c9 | 2383 | qc = __ata_qc_from_tag(ap, ap->link.active_tag); |
6d97dbd7 TH |
2384 | if (qc && !(qc->flags & ATA_QCFLAG_FAILED)) |
2385 | qc = NULL; | |
2386 | ||
2387 | /* reset PIO HSM and stop DMA engine */ | |
ba6a1308 | 2388 | spin_lock_irqsave(ap->lock, flags); |
6d97dbd7 | 2389 | |
6d97dbd7 TH |
2390 | ap->hsm_task_state = HSM_ST_IDLE; |
2391 | ||
ed82f964 TH |
2392 | if (ap->ioaddr.bmdma_addr && |
2393 | qc && (qc->tf.protocol == ATA_PROT_DMA || | |
0dc36888 | 2394 | qc->tf.protocol == ATAPI_PROT_DMA)) { |
6d97dbd7 TH |
2395 | u8 host_stat; |
2396 | ||
fbbb262d | 2397 | host_stat = ap->ops->bmdma_status(ap); |
6d97dbd7 | 2398 | |
6d97dbd7 TH |
2399 | /* BMDMA controllers indicate host bus error by |
2400 | * setting DMA_ERR bit and timing out. As it wasn't | |
2401 | * really a timeout event, adjust error mask and | |
2402 | * cancel frozen state. | |
2403 | */ | |
3d47aa8e AC |
2404 | if (qc->err_mask == AC_ERR_TIMEOUT |
2405 | && (host_stat & ATA_DMA_ERR)) { | |
6d97dbd7 TH |
2406 | qc->err_mask = AC_ERR_HOST_BUS; |
2407 | thaw = 1; | |
2408 | } | |
2409 | ||
2410 | ap->ops->bmdma_stop(qc); | |
2411 | } | |
2412 | ||
a57c1bad | 2413 | ata_sff_sync(ap); /* FIXME: We don't need this */ |
5682ed33 TH |
2414 | ap->ops->sff_check_status(ap); |
2415 | ap->ops->sff_irq_clear(ap); | |
3d47aa8e AC |
2416 | /* We *MUST* do FIFO draining before we issue a reset as several |
2417 | * devices helpfully clear their internal state and will lock solid | |
2418 | * if we touch the data port post reset. Pass qc in case anyone wants | |
2419 | * to do different PIO/DMA recovery or has per command fixups | |
2420 | */ | |
2421 | if (ap->ops->drain_fifo) | |
2422 | ap->ops->drain_fifo(qc); | |
6d97dbd7 | 2423 | |
ba6a1308 | 2424 | spin_unlock_irqrestore(ap->lock, flags); |
6d97dbd7 TH |
2425 | |
2426 | if (thaw) | |
2427 | ata_eh_thaw_port(ap); | |
2428 | ||
2429 | /* PIO and DMA engines have been stopped, perform recovery */ | |
6d97dbd7 | 2430 | |
57c9efdf TH |
2431 | /* Ignore ata_sff_softreset if ctl isn't accessible and |
2432 | * built-in hardresets if SCR access isn't available. | |
a1efdaba | 2433 | */ |
9363c382 | 2434 | if (softreset == ata_sff_softreset && !ap->ioaddr.ctl_addr) |
a1efdaba | 2435 | softreset = NULL; |
57c9efdf | 2436 | if (ata_is_builtin_hardreset(hardreset) && !sata_scr_valid(&ap->link)) |
a1efdaba | 2437 | hardreset = NULL; |
6d97dbd7 | 2438 | |
a1efdaba TH |
2439 | ata_do_eh(ap, ap->ops->prereset, softreset, hardreset, |
2440 | ap->ops->postreset); | |
6d97dbd7 | 2441 | } |
0fe40ff8 | 2442 | EXPORT_SYMBOL_GPL(ata_sff_error_handler); |
6d97dbd7 TH |
2443 | |
2444 | /** | |
9363c382 | 2445 | * ata_sff_post_internal_cmd - Stock post_internal_cmd for SFF controller |
6d97dbd7 TH |
2446 | * @qc: internal command to clean up |
2447 | * | |
2448 | * LOCKING: | |
2449 | * Kernel thread context (may sleep) | |
2450 | */ | |
9363c382 | 2451 | void ata_sff_post_internal_cmd(struct ata_queued_cmd *qc) |
6d97dbd7 | 2452 | { |
570106df TH |
2453 | struct ata_port *ap = qc->ap; |
2454 | unsigned long flags; | |
2455 | ||
2456 | spin_lock_irqsave(ap->lock, flags); | |
2457 | ||
2458 | ap->hsm_task_state = HSM_ST_IDLE; | |
2459 | ||
2460 | if (ap->ioaddr.bmdma_addr) | |
294264a9 | 2461 | ap->ops->bmdma_stop(qc); |
570106df TH |
2462 | |
2463 | spin_unlock_irqrestore(ap->lock, flags); | |
6d97dbd7 | 2464 | } |
0fe40ff8 | 2465 | EXPORT_SYMBOL_GPL(ata_sff_post_internal_cmd); |
6d97dbd7 | 2466 | |
d92e74d3 AC |
2467 | /** |
2468 | * ata_sff_port_start - Set port up for dma. | |
2469 | * @ap: Port to initialize | |
2470 | * | |
2471 | * Called just after data structures for each port are | |
2472 | * initialized. Allocates space for PRD table if the device | |
2473 | * is DMA capable SFF. | |
2474 | * | |
2475 | * May be used as the port_start() entry in ata_port_operations. | |
2476 | * | |
2477 | * LOCKING: | |
2478 | * Inherited from caller. | |
2479 | */ | |
d92e74d3 AC |
2480 | int ata_sff_port_start(struct ata_port *ap) |
2481 | { | |
2482 | if (ap->ioaddr.bmdma_addr) | |
2483 | return ata_port_start(ap); | |
2484 | return 0; | |
2485 | } | |
0fe40ff8 | 2486 | EXPORT_SYMBOL_GPL(ata_sff_port_start); |
d92e74d3 | 2487 | |
e3cf95dd AC |
2488 | /** |
2489 | * ata_sff_port_start32 - Set port up for dma. | |
2490 | * @ap: Port to initialize | |
2491 | * | |
2492 | * Called just after data structures for each port are | |
2493 | * initialized. Allocates space for PRD table if the device | |
2494 | * is DMA capable SFF. | |
2495 | * | |
2496 | * May be used as the port_start() entry in ata_port_operations for | |
2497 | * devices that are capable of 32bit PIO. | |
2498 | * | |
2499 | * LOCKING: | |
2500 | * Inherited from caller. | |
2501 | */ | |
2502 | int ata_sff_port_start32(struct ata_port *ap) | |
2503 | { | |
2504 | ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE; | |
2505 | if (ap->ioaddr.bmdma_addr) | |
2506 | return ata_port_start(ap); | |
2507 | return 0; | |
2508 | } | |
2509 | EXPORT_SYMBOL_GPL(ata_sff_port_start32); | |
2510 | ||
624d5c51 | 2511 | /** |
9363c382 | 2512 | * ata_sff_std_ports - initialize ioaddr with standard port offsets. |
624d5c51 TH |
2513 | * @ioaddr: IO address structure to be initialized |
2514 | * | |
2515 | * Utility function which initializes data_addr, error_addr, | |
2516 | * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr, | |
2517 | * device_addr, status_addr, and command_addr to standard offsets | |
2518 | * relative to cmd_addr. | |
2519 | * | |
2520 | * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr. | |
2521 | */ | |
9363c382 | 2522 | void ata_sff_std_ports(struct ata_ioports *ioaddr) |
624d5c51 TH |
2523 | { |
2524 | ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA; | |
2525 | ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR; | |
2526 | ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE; | |
2527 | ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT; | |
2528 | ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL; | |
2529 | ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM; | |
2530 | ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH; | |
2531 | ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE; | |
2532 | ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS; | |
2533 | ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD; | |
2534 | } | |
0fe40ff8 | 2535 | EXPORT_SYMBOL_GPL(ata_sff_std_ports); |
624d5c51 | 2536 | |
9363c382 TH |
2537 | unsigned long ata_bmdma_mode_filter(struct ata_device *adev, |
2538 | unsigned long xfer_mask) | |
071ce34d TH |
2539 | { |
2540 | /* Filter out DMA modes if the device has been configured by | |
2541 | the BIOS as PIO only */ | |
2542 | ||
2543 | if (adev->link->ap->ioaddr.bmdma_addr == NULL) | |
2544 | xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA); | |
2545 | return xfer_mask; | |
2546 | } | |
0fe40ff8 | 2547 | EXPORT_SYMBOL_GPL(ata_bmdma_mode_filter); |
071ce34d | 2548 | |
272f7884 TH |
2549 | /** |
2550 | * ata_bmdma_setup - Set up PCI IDE BMDMA transaction | |
2551 | * @qc: Info associated with this ATA transaction. | |
2552 | * | |
2553 | * LOCKING: | |
2554 | * spin_lock_irqsave(host lock) | |
2555 | */ | |
2556 | void ata_bmdma_setup(struct ata_queued_cmd *qc) | |
2557 | { | |
2558 | struct ata_port *ap = qc->ap; | |
2559 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
2560 | u8 dmactl; | |
2561 | ||
2562 | /* load PRD table addr. */ | |
2563 | mb(); /* make sure PRD table writes are visible to controller */ | |
2564 | iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); | |
2565 | ||
2566 | /* specify data direction, triple-check start bit is clear */ | |
2567 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2568 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | |
2569 | if (!rw) | |
2570 | dmactl |= ATA_DMA_WR; | |
2571 | iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2572 | ||
2573 | /* issue r/w command */ | |
5682ed33 | 2574 | ap->ops->sff_exec_command(ap, &qc->tf); |
272f7884 | 2575 | } |
0fe40ff8 | 2576 | EXPORT_SYMBOL_GPL(ata_bmdma_setup); |
272f7884 TH |
2577 | |
2578 | /** | |
2579 | * ata_bmdma_start - Start a PCI IDE BMDMA transaction | |
2580 | * @qc: Info associated with this ATA transaction. | |
2581 | * | |
2582 | * LOCKING: | |
2583 | * spin_lock_irqsave(host lock) | |
2584 | */ | |
2585 | void ata_bmdma_start(struct ata_queued_cmd *qc) | |
2586 | { | |
2587 | struct ata_port *ap = qc->ap; | |
2588 | u8 dmactl; | |
2589 | ||
2590 | /* start host DMA transaction */ | |
2591 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2592 | iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2593 | ||
2594 | /* Strictly, one may wish to issue an ioread8() here, to | |
2595 | * flush the mmio write. However, control also passes | |
2596 | * to the hardware at this point, and it will interrupt | |
2597 | * us when we are to resume control. So, in effect, | |
2598 | * we don't care when the mmio write flushes. | |
2599 | * Further, a read of the DMA status register _immediately_ | |
2600 | * following the write may not be what certain flaky hardware | |
2601 | * is expected, so I think it is best to not add a readb() | |
2602 | * without first all the MMIO ATA cards/mobos. | |
2603 | * Or maybe I'm just being paranoid. | |
2604 | * | |
2605 | * FIXME: The posting of this write means I/O starts are | |
2606 | * unneccessarily delayed for MMIO | |
2607 | */ | |
2608 | } | |
0fe40ff8 | 2609 | EXPORT_SYMBOL_GPL(ata_bmdma_start); |
272f7884 TH |
2610 | |
2611 | /** | |
2612 | * ata_bmdma_stop - Stop PCI IDE BMDMA transfer | |
2613 | * @qc: Command we are ending DMA for | |
2614 | * | |
2615 | * Clears the ATA_DMA_START flag in the dma control register | |
2616 | * | |
2617 | * May be used as the bmdma_stop() entry in ata_port_operations. | |
2618 | * | |
2619 | * LOCKING: | |
2620 | * spin_lock_irqsave(host lock) | |
2621 | */ | |
2622 | void ata_bmdma_stop(struct ata_queued_cmd *qc) | |
2623 | { | |
2624 | struct ata_port *ap = qc->ap; | |
2625 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
2626 | ||
2627 | /* clear start/stop bit */ | |
2628 | iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, | |
2629 | mmio + ATA_DMA_CMD); | |
2630 | ||
2631 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | |
a57c1bad | 2632 | ata_sff_dma_pause(ap); |
272f7884 | 2633 | } |
0fe40ff8 | 2634 | EXPORT_SYMBOL_GPL(ata_bmdma_stop); |
272f7884 TH |
2635 | |
2636 | /** | |
2637 | * ata_bmdma_status - Read PCI IDE BMDMA status | |
2638 | * @ap: Port associated with this ATA transaction. | |
2639 | * | |
2640 | * Read and return BMDMA status register. | |
2641 | * | |
2642 | * May be used as the bmdma_status() entry in ata_port_operations. | |
2643 | * | |
2644 | * LOCKING: | |
2645 | * spin_lock_irqsave(host lock) | |
2646 | */ | |
2647 | u8 ata_bmdma_status(struct ata_port *ap) | |
2648 | { | |
2649 | return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); | |
2650 | } | |
0fe40ff8 | 2651 | EXPORT_SYMBOL_GPL(ata_bmdma_status); |
272f7884 | 2652 | |
1fdffbce | 2653 | #ifdef CONFIG_PCI |
4112e16a | 2654 | |
272f7884 | 2655 | /** |
9363c382 | 2656 | * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex |
272f7884 TH |
2657 | * @pdev: PCI device |
2658 | * | |
2659 | * Some PCI ATA devices report simplex mode but in fact can be told to | |
2660 | * enter non simplex mode. This implements the necessary logic to | |
2661 | * perform the task on such devices. Calling it on other devices will | |
2662 | * have -undefined- behaviour. | |
2663 | */ | |
9363c382 | 2664 | int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev) |
4112e16a | 2665 | { |
272f7884 TH |
2666 | unsigned long bmdma = pci_resource_start(pdev, 4); |
2667 | u8 simplex; | |
a84471fe | 2668 | |
272f7884 TH |
2669 | if (bmdma == 0) |
2670 | return -ENOENT; | |
2671 | ||
2672 | simplex = inb(bmdma + 0x02); | |
2673 | outb(simplex & 0x60, bmdma + 0x02); | |
2674 | simplex = inb(bmdma + 0x02); | |
2675 | if (simplex & 0x80) | |
2676 | return -EOPNOTSUPP; | |
2677 | return 0; | |
2678 | } | |
0fe40ff8 | 2679 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex); |
272f7884 | 2680 | |
0f834de3 | 2681 | /** |
9363c382 | 2682 | * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host |
0f834de3 TH |
2683 | * @host: target ATA host |
2684 | * | |
2685 | * Acquire PCI BMDMA resources and initialize @host accordingly. | |
2686 | * | |
2687 | * LOCKING: | |
2688 | * Inherited from calling layer (may sleep). | |
2689 | * | |
2690 | * RETURNS: | |
2691 | * 0 on success, -errno otherwise. | |
2692 | */ | |
9363c382 | 2693 | int ata_pci_bmdma_init(struct ata_host *host) |
1fdffbce | 2694 | { |
0f834de3 TH |
2695 | struct device *gdev = host->dev; |
2696 | struct pci_dev *pdev = to_pci_dev(gdev); | |
2697 | int i, rc; | |
0d5ff566 | 2698 | |
6fdc99a2 AC |
2699 | /* No BAR4 allocation: No DMA */ |
2700 | if (pci_resource_start(pdev, 4) == 0) | |
2701 | return 0; | |
2702 | ||
0f834de3 TH |
2703 | /* TODO: If we get no DMA mask we should fall back to PIO */ |
2704 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
2705 | if (rc) | |
2706 | return rc; | |
2707 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
2708 | if (rc) | |
2709 | return rc; | |
2710 | ||
2711 | /* request and iomap DMA region */ | |
35a10a80 | 2712 | rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev)); |
0f834de3 TH |
2713 | if (rc) { |
2714 | dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n"); | |
2715 | return -ENOMEM; | |
0d5ff566 | 2716 | } |
0f834de3 | 2717 | host->iomap = pcim_iomap_table(pdev); |
0d5ff566 | 2718 | |
1626aeb8 | 2719 | for (i = 0; i < 2; i++) { |
0f834de3 | 2720 | struct ata_port *ap = host->ports[i]; |
0f834de3 TH |
2721 | void __iomem *bmdma = host->iomap[4] + 8 * i; |
2722 | ||
2723 | if (ata_port_is_dummy(ap)) | |
2724 | continue; | |
2725 | ||
21b0ad4f | 2726 | ap->ioaddr.bmdma_addr = bmdma; |
0f834de3 TH |
2727 | if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) && |
2728 | (ioread8(bmdma + 2) & 0x80)) | |
2729 | host->flags |= ATA_HOST_SIMPLEX; | |
cbcdd875 TH |
2730 | |
2731 | ata_port_desc(ap, "bmdma 0x%llx", | |
0fe40ff8 | 2732 | (unsigned long long)pci_resource_start(pdev, 4) + 8 * i); |
0d5ff566 TH |
2733 | } |
2734 | ||
0f834de3 TH |
2735 | return 0; |
2736 | } | |
0fe40ff8 | 2737 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_init); |
2ec7df04 | 2738 | |
272f7884 TH |
2739 | static int ata_resources_present(struct pci_dev *pdev, int port) |
2740 | { | |
2741 | int i; | |
2742 | ||
2743 | /* Check the PCI resources for this channel are enabled */ | |
2744 | port = port * 2; | |
0fe40ff8 | 2745 | for (i = 0; i < 2; i++) { |
272f7884 TH |
2746 | if (pci_resource_start(pdev, port + i) == 0 || |
2747 | pci_resource_len(pdev, port + i) == 0) | |
2748 | return 0; | |
2749 | } | |
2750 | return 1; | |
2751 | } | |
2752 | ||
d491b27b | 2753 | /** |
9363c382 | 2754 | * ata_pci_sff_init_host - acquire native PCI ATA resources and init host |
d491b27b | 2755 | * @host: target ATA host |
d491b27b | 2756 | * |
1626aeb8 TH |
2757 | * Acquire native PCI ATA resources for @host and initialize the |
2758 | * first two ports of @host accordingly. Ports marked dummy are | |
2759 | * skipped and allocation failure makes the port dummy. | |
d491b27b | 2760 | * |
d583bc18 TH |
2761 | * Note that native PCI resources are valid even for legacy hosts |
2762 | * as we fix up pdev resources array early in boot, so this | |
2763 | * function can be used for both native and legacy SFF hosts. | |
2764 | * | |
d491b27b TH |
2765 | * LOCKING: |
2766 | * Inherited from calling layer (may sleep). | |
2767 | * | |
2768 | * RETURNS: | |
1626aeb8 TH |
2769 | * 0 if at least one port is initialized, -ENODEV if no port is |
2770 | * available. | |
d491b27b | 2771 | */ |
9363c382 | 2772 | int ata_pci_sff_init_host(struct ata_host *host) |
d491b27b TH |
2773 | { |
2774 | struct device *gdev = host->dev; | |
2775 | struct pci_dev *pdev = to_pci_dev(gdev); | |
1626aeb8 | 2776 | unsigned int mask = 0; |
d491b27b TH |
2777 | int i, rc; |
2778 | ||
d491b27b TH |
2779 | /* request, iomap BARs and init port addresses accordingly */ |
2780 | for (i = 0; i < 2; i++) { | |
2781 | struct ata_port *ap = host->ports[i]; | |
2782 | int base = i * 2; | |
2783 | void __iomem * const *iomap; | |
2784 | ||
1626aeb8 TH |
2785 | if (ata_port_is_dummy(ap)) |
2786 | continue; | |
2787 | ||
2788 | /* Discard disabled ports. Some controllers show | |
2789 | * their unused channels this way. Disabled ports are | |
2790 | * made dummy. | |
2791 | */ | |
2792 | if (!ata_resources_present(pdev, i)) { | |
2793 | ap->ops = &ata_dummy_port_ops; | |
d491b27b | 2794 | continue; |
1626aeb8 | 2795 | } |
d491b27b | 2796 | |
35a10a80 TH |
2797 | rc = pcim_iomap_regions(pdev, 0x3 << base, |
2798 | dev_driver_string(gdev)); | |
d491b27b | 2799 | if (rc) { |
1626aeb8 TH |
2800 | dev_printk(KERN_WARNING, gdev, |
2801 | "failed to request/iomap BARs for port %d " | |
2802 | "(errno=%d)\n", i, rc); | |
d491b27b TH |
2803 | if (rc == -EBUSY) |
2804 | pcim_pin_device(pdev); | |
1626aeb8 TH |
2805 | ap->ops = &ata_dummy_port_ops; |
2806 | continue; | |
d491b27b TH |
2807 | } |
2808 | host->iomap = iomap = pcim_iomap_table(pdev); | |
2809 | ||
2810 | ap->ioaddr.cmd_addr = iomap[base]; | |
2811 | ap->ioaddr.altstatus_addr = | |
2812 | ap->ioaddr.ctl_addr = (void __iomem *) | |
2813 | ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS); | |
9363c382 | 2814 | ata_sff_std_ports(&ap->ioaddr); |
1626aeb8 | 2815 | |
cbcdd875 TH |
2816 | ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx", |
2817 | (unsigned long long)pci_resource_start(pdev, base), | |
2818 | (unsigned long long)pci_resource_start(pdev, base + 1)); | |
2819 | ||
1626aeb8 TH |
2820 | mask |= 1 << i; |
2821 | } | |
2822 | ||
2823 | if (!mask) { | |
2824 | dev_printk(KERN_ERR, gdev, "no available native port\n"); | |
2825 | return -ENODEV; | |
d491b27b TH |
2826 | } |
2827 | ||
2828 | return 0; | |
2829 | } | |
0fe40ff8 | 2830 | EXPORT_SYMBOL_GPL(ata_pci_sff_init_host); |
d491b27b | 2831 | |
21b0ad4f | 2832 | /** |
9363c382 | 2833 | * ata_pci_sff_prepare_host - helper to prepare native PCI ATA host |
21b0ad4f | 2834 | * @pdev: target PCI device |
1626aeb8 | 2835 | * @ppi: array of port_info, must be enough for two ports |
21b0ad4f TH |
2836 | * @r_host: out argument for the initialized ATA host |
2837 | * | |
2838 | * Helper to allocate ATA host for @pdev, acquire all native PCI | |
2839 | * resources and initialize it accordingly in one go. | |
2840 | * | |
2841 | * LOCKING: | |
2842 | * Inherited from calling layer (may sleep). | |
2843 | * | |
2844 | * RETURNS: | |
2845 | * 0 on success, -errno otherwise. | |
2846 | */ | |
9363c382 | 2847 | int ata_pci_sff_prepare_host(struct pci_dev *pdev, |
0fe40ff8 | 2848 | const struct ata_port_info * const *ppi, |
d583bc18 | 2849 | struct ata_host **r_host) |
21b0ad4f TH |
2850 | { |
2851 | struct ata_host *host; | |
21b0ad4f TH |
2852 | int rc; |
2853 | ||
2854 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) | |
2855 | return -ENOMEM; | |
2856 | ||
2857 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); | |
2858 | if (!host) { | |
2859 | dev_printk(KERN_ERR, &pdev->dev, | |
2860 | "failed to allocate ATA host\n"); | |
2861 | rc = -ENOMEM; | |
2862 | goto err_out; | |
2863 | } | |
2864 | ||
9363c382 | 2865 | rc = ata_pci_sff_init_host(host); |
21b0ad4f TH |
2866 | if (rc) |
2867 | goto err_out; | |
2868 | ||
2869 | /* init DMA related stuff */ | |
9363c382 | 2870 | rc = ata_pci_bmdma_init(host); |
21b0ad4f TH |
2871 | if (rc) |
2872 | goto err_bmdma; | |
2873 | ||
2874 | devres_remove_group(&pdev->dev, NULL); | |
2875 | *r_host = host; | |
2876 | return 0; | |
2877 | ||
0fe40ff8 | 2878 | err_bmdma: |
21b0ad4f TH |
2879 | /* This is necessary because PCI and iomap resources are |
2880 | * merged and releasing the top group won't release the | |
2881 | * acquired resources if some of those have been acquired | |
2882 | * before entering this function. | |
2883 | */ | |
2884 | pcim_iounmap_regions(pdev, 0xf); | |
0fe40ff8 | 2885 | err_out: |
21b0ad4f TH |
2886 | devres_release_group(&pdev->dev, NULL); |
2887 | return rc; | |
2888 | } | |
0fe40ff8 | 2889 | EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host); |
21b0ad4f | 2890 | |
4e6b79fa | 2891 | /** |
9363c382 | 2892 | * ata_pci_sff_activate_host - start SFF host, request IRQ and register it |
4e6b79fa TH |
2893 | * @host: target SFF ATA host |
2894 | * @irq_handler: irq_handler used when requesting IRQ(s) | |
2895 | * @sht: scsi_host_template to use when registering the host | |
2896 | * | |
2897 | * This is the counterpart of ata_host_activate() for SFF ATA | |
2898 | * hosts. This separate helper is necessary because SFF hosts | |
2899 | * use two separate interrupts in legacy mode. | |
2900 | * | |
2901 | * LOCKING: | |
2902 | * Inherited from calling layer (may sleep). | |
2903 | * | |
2904 | * RETURNS: | |
2905 | * 0 on success, -errno otherwise. | |
2906 | */ | |
9363c382 | 2907 | int ata_pci_sff_activate_host(struct ata_host *host, |
4e6b79fa TH |
2908 | irq_handler_t irq_handler, |
2909 | struct scsi_host_template *sht) | |
2910 | { | |
2911 | struct device *dev = host->dev; | |
2912 | struct pci_dev *pdev = to_pci_dev(dev); | |
2913 | const char *drv_name = dev_driver_string(host->dev); | |
2914 | int legacy_mode = 0, rc; | |
2915 | ||
2916 | rc = ata_host_start(host); | |
2917 | if (rc) | |
2918 | return rc; | |
2919 | ||
2920 | if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) { | |
2921 | u8 tmp8, mask; | |
2922 | ||
2923 | /* TODO: What if one channel is in native mode ... */ | |
2924 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8); | |
2925 | mask = (1 << 2) | (1 << 0); | |
2926 | if ((tmp8 & mask) != mask) | |
2927 | legacy_mode = 1; | |
2928 | #if defined(CONFIG_NO_ATA_LEGACY) | |
2929 | /* Some platforms with PCI limits cannot address compat | |
2930 | port space. In that case we punt if their firmware has | |
2931 | left a device in compatibility mode */ | |
2932 | if (legacy_mode) { | |
2933 | printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n"); | |
2934 | return -EOPNOTSUPP; | |
2935 | } | |
2936 | #endif | |
2937 | } | |
2938 | ||
2939 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) | |
2940 | return -ENOMEM; | |
2941 | ||
2942 | if (!legacy_mode && pdev->irq) { | |
2943 | rc = devm_request_irq(dev, pdev->irq, irq_handler, | |
2944 | IRQF_SHARED, drv_name, host); | |
2945 | if (rc) | |
2946 | goto out; | |
2947 | ||
2948 | ata_port_desc(host->ports[0], "irq %d", pdev->irq); | |
2949 | ata_port_desc(host->ports[1], "irq %d", pdev->irq); | |
2950 | } else if (legacy_mode) { | |
2951 | if (!ata_port_is_dummy(host->ports[0])) { | |
2952 | rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev), | |
2953 | irq_handler, IRQF_SHARED, | |
2954 | drv_name, host); | |
2955 | if (rc) | |
2956 | goto out; | |
2957 | ||
2958 | ata_port_desc(host->ports[0], "irq %d", | |
2959 | ATA_PRIMARY_IRQ(pdev)); | |
2960 | } | |
2961 | ||
2962 | if (!ata_port_is_dummy(host->ports[1])) { | |
2963 | rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev), | |
2964 | irq_handler, IRQF_SHARED, | |
2965 | drv_name, host); | |
2966 | if (rc) | |
2967 | goto out; | |
2968 | ||
2969 | ata_port_desc(host->ports[1], "irq %d", | |
2970 | ATA_SECONDARY_IRQ(pdev)); | |
2971 | } | |
2972 | } | |
2973 | ||
2974 | rc = ata_host_register(host, sht); | |
0fe40ff8 | 2975 | out: |
4e6b79fa TH |
2976 | if (rc == 0) |
2977 | devres_remove_group(dev, NULL); | |
2978 | else | |
2979 | devres_release_group(dev, NULL); | |
2980 | ||
2981 | return rc; | |
2982 | } | |
0fe40ff8 | 2983 | EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host); |
4e6b79fa | 2984 | |
1fdffbce | 2985 | /** |
9363c382 | 2986 | * ata_pci_sff_init_one - Initialize/register PCI IDE host controller |
1fdffbce | 2987 | * @pdev: Controller to be initialized |
1626aeb8 | 2988 | * @ppi: array of port_info, must be enough for two ports |
1bd5b715 | 2989 | * @sht: scsi_host_template to use when registering the host |
887125e3 | 2990 | * @host_priv: host private_data |
16ea0fc9 | 2991 | * @hflag: host flags |
1fdffbce JG |
2992 | * |
2993 | * This is a helper function which can be called from a driver's | |
2994 | * xxx_init_one() probe function if the hardware uses traditional | |
2995 | * IDE taskfile registers. | |
2996 | * | |
2997 | * This function calls pci_enable_device(), reserves its register | |
2998 | * regions, sets the dma mask, enables bus master mode, and calls | |
2999 | * ata_device_add() | |
3000 | * | |
2ec7df04 AC |
3001 | * ASSUMPTION: |
3002 | * Nobody makes a single channel controller that appears solely as | |
3003 | * the secondary legacy port on PCI. | |
3004 | * | |
1fdffbce JG |
3005 | * LOCKING: |
3006 | * Inherited from PCI layer (may sleep). | |
3007 | * | |
3008 | * RETURNS: | |
3009 | * Zero on success, negative on errno-based value on error. | |
3010 | */ | |
9363c382 | 3011 | int ata_pci_sff_init_one(struct pci_dev *pdev, |
16ea0fc9 AC |
3012 | const struct ata_port_info * const *ppi, |
3013 | struct scsi_host_template *sht, void *host_priv, int hflag) | |
1fdffbce | 3014 | { |
f0d36efd | 3015 | struct device *dev = &pdev->dev; |
1626aeb8 | 3016 | const struct ata_port_info *pi = NULL; |
0f834de3 | 3017 | struct ata_host *host = NULL; |
1626aeb8 | 3018 | int i, rc; |
1fdffbce JG |
3019 | |
3020 | DPRINTK("ENTER\n"); | |
3021 | ||
1626aeb8 TH |
3022 | /* look up the first valid port_info */ |
3023 | for (i = 0; i < 2 && ppi[i]; i++) { | |
3024 | if (ppi[i]->port_ops != &ata_dummy_port_ops) { | |
3025 | pi = ppi[i]; | |
3026 | break; | |
3027 | } | |
3028 | } | |
f0d36efd | 3029 | |
1626aeb8 TH |
3030 | if (!pi) { |
3031 | dev_printk(KERN_ERR, &pdev->dev, | |
3032 | "no valid port_info specified\n"); | |
3033 | return -EINVAL; | |
3034 | } | |
c791c306 | 3035 | |
1626aeb8 TH |
3036 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) |
3037 | return -ENOMEM; | |
1fdffbce | 3038 | |
f0d36efd | 3039 | rc = pcim_enable_device(pdev); |
1fdffbce | 3040 | if (rc) |
4e6b79fa | 3041 | goto out; |
1fdffbce | 3042 | |
4e6b79fa | 3043 | /* prepare and activate SFF host */ |
9363c382 | 3044 | rc = ata_pci_sff_prepare_host(pdev, ppi, &host); |
d583bc18 | 3045 | if (rc) |
4e6b79fa | 3046 | goto out; |
887125e3 | 3047 | host->private_data = host_priv; |
16ea0fc9 | 3048 | host->flags |= hflag; |
d491b27b | 3049 | |
d491b27b | 3050 | pci_set_master(pdev); |
9363c382 | 3051 | rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht); |
0fe40ff8 | 3052 | out: |
4e6b79fa TH |
3053 | if (rc == 0) |
3054 | devres_remove_group(&pdev->dev, NULL); | |
3055 | else | |
3056 | devres_release_group(&pdev->dev, NULL); | |
d491b27b | 3057 | |
1fdffbce JG |
3058 | return rc; |
3059 | } | |
0fe40ff8 | 3060 | EXPORT_SYMBOL_GPL(ata_pci_sff_init_one); |
1fdffbce JG |
3061 | |
3062 | #endif /* CONFIG_PCI */ |