Commit | Line | Data |
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1fdffbce | 1 | /* |
f3a03b09 | 2 | * libata-sff.c - helper library for PCI IDE BMDMA |
1fdffbce | 3 | * |
8c3d3d4b | 4 | * Maintained by: Tejun Heo <tj@kernel.org> |
1fdffbce JG |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2006 Red Hat, Inc. All rights reserved. | |
9 | * Copyright 2003-2006 Jeff Garzik | |
10 | * | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
9bb9a39c | 28 | * as Documentation/driver-api/libata.rst |
1fdffbce JG |
29 | * |
30 | * Hardware documentation available from http://www.t13.org/ and | |
31 | * http://www.sata-io.org/ | |
32 | * | |
33 | */ | |
34 | ||
1fdffbce | 35 | #include <linux/kernel.h> |
5a0e3ad6 | 36 | #include <linux/gfp.h> |
1fdffbce | 37 | #include <linux/pci.h> |
bff7832d | 38 | #include <linux/module.h> |
1fdffbce | 39 | #include <linux/libata.h> |
624d5c51 | 40 | #include <linux/highmem.h> |
1fdffbce JG |
41 | |
42 | #include "libata.h" | |
43 | ||
c429137a TH |
44 | static struct workqueue_struct *ata_sff_wq; |
45 | ||
624d5c51 TH |
46 | const struct ata_port_operations ata_sff_port_ops = { |
47 | .inherits = &ata_base_port_ops, | |
48 | ||
f47451c4 | 49 | .qc_prep = ata_noop_qc_prep, |
9363c382 | 50 | .qc_issue = ata_sff_qc_issue, |
4c9bf4e7 | 51 | .qc_fill_rtf = ata_sff_qc_fill_rtf, |
9363c382 TH |
52 | |
53 | .freeze = ata_sff_freeze, | |
54 | .thaw = ata_sff_thaw, | |
0aa1113d | 55 | .prereset = ata_sff_prereset, |
9363c382 | 56 | .softreset = ata_sff_softreset, |
57c9efdf | 57 | .hardreset = sata_sff_hardreset, |
203c75b8 | 58 | .postreset = ata_sff_postreset, |
9363c382 | 59 | .error_handler = ata_sff_error_handler, |
9363c382 | 60 | |
5682ed33 TH |
61 | .sff_dev_select = ata_sff_dev_select, |
62 | .sff_check_status = ata_sff_check_status, | |
63 | .sff_tf_load = ata_sff_tf_load, | |
64 | .sff_tf_read = ata_sff_tf_read, | |
65 | .sff_exec_command = ata_sff_exec_command, | |
66 | .sff_data_xfer = ata_sff_data_xfer, | |
8244cd05 | 67 | .sff_drain_fifo = ata_sff_drain_fifo, |
624d5c51 | 68 | |
c96f1732 | 69 | .lost_interrupt = ata_sff_lost_interrupt, |
624d5c51 | 70 | }; |
0fe40ff8 | 71 | EXPORT_SYMBOL_GPL(ata_sff_port_ops); |
624d5c51 | 72 | |
272f7884 | 73 | /** |
9363c382 | 74 | * ata_sff_check_status - Read device status reg & clear interrupt |
272f7884 TH |
75 | * @ap: port where the device is |
76 | * | |
77 | * Reads ATA taskfile status register for currently-selected device | |
78 | * and return its value. This also clears pending interrupts | |
79 | * from this device | |
80 | * | |
81 | * LOCKING: | |
82 | * Inherited from caller. | |
83 | */ | |
9363c382 | 84 | u8 ata_sff_check_status(struct ata_port *ap) |
272f7884 TH |
85 | { |
86 | return ioread8(ap->ioaddr.status_addr); | |
87 | } | |
0fe40ff8 | 88 | EXPORT_SYMBOL_GPL(ata_sff_check_status); |
272f7884 TH |
89 | |
90 | /** | |
9363c382 | 91 | * ata_sff_altstatus - Read device alternate status reg |
272f7884 TH |
92 | * @ap: port where the device is |
93 | * | |
94 | * Reads ATA taskfile alternate status register for | |
95 | * currently-selected device and return its value. | |
96 | * | |
97 | * Note: may NOT be used as the check_altstatus() entry in | |
98 | * ata_port_operations. | |
99 | * | |
100 | * LOCKING: | |
101 | * Inherited from caller. | |
102 | */ | |
a57c1bad | 103 | static u8 ata_sff_altstatus(struct ata_port *ap) |
624d5c51 | 104 | { |
5682ed33 TH |
105 | if (ap->ops->sff_check_altstatus) |
106 | return ap->ops->sff_check_altstatus(ap); | |
624d5c51 TH |
107 | |
108 | return ioread8(ap->ioaddr.altstatus_addr); | |
109 | } | |
110 | ||
a57c1bad AC |
111 | /** |
112 | * ata_sff_irq_status - Check if the device is busy | |
113 | * @ap: port where the device is | |
114 | * | |
115 | * Determine if the port is currently busy. Uses altstatus | |
116 | * if available in order to avoid clearing shared IRQ status | |
117 | * when finding an IRQ source. Non ctl capable devices don't | |
118 | * share interrupt lines fortunately for us. | |
119 | * | |
120 | * LOCKING: | |
121 | * Inherited from caller. | |
122 | */ | |
123 | static u8 ata_sff_irq_status(struct ata_port *ap) | |
124 | { | |
125 | u8 status; | |
126 | ||
127 | if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) { | |
128 | status = ata_sff_altstatus(ap); | |
129 | /* Not us: We are busy */ | |
130 | if (status & ATA_BUSY) | |
0fe40ff8 | 131 | return status; |
a57c1bad AC |
132 | } |
133 | /* Clear INTRQ latch */ | |
6311c90a | 134 | status = ap->ops->sff_check_status(ap); |
a57c1bad AC |
135 | return status; |
136 | } | |
137 | ||
138 | /** | |
139 | * ata_sff_sync - Flush writes | |
140 | * @ap: Port to wait for. | |
141 | * | |
142 | * CAUTION: | |
143 | * If we have an mmio device with no ctl and no altstatus | |
144 | * method this will fail. No such devices are known to exist. | |
145 | * | |
146 | * LOCKING: | |
147 | * Inherited from caller. | |
148 | */ | |
149 | ||
150 | static void ata_sff_sync(struct ata_port *ap) | |
151 | { | |
152 | if (ap->ops->sff_check_altstatus) | |
153 | ap->ops->sff_check_altstatus(ap); | |
154 | else if (ap->ioaddr.altstatus_addr) | |
155 | ioread8(ap->ioaddr.altstatus_addr); | |
156 | } | |
157 | ||
158 | /** | |
159 | * ata_sff_pause - Flush writes and wait 400nS | |
160 | * @ap: Port to pause for. | |
161 | * | |
162 | * CAUTION: | |
163 | * If we have an mmio device with no ctl and no altstatus | |
164 | * method this will fail. No such devices are known to exist. | |
165 | * | |
166 | * LOCKING: | |
167 | * Inherited from caller. | |
168 | */ | |
169 | ||
170 | void ata_sff_pause(struct ata_port *ap) | |
171 | { | |
172 | ata_sff_sync(ap); | |
173 | ndelay(400); | |
174 | } | |
0fe40ff8 | 175 | EXPORT_SYMBOL_GPL(ata_sff_pause); |
a57c1bad AC |
176 | |
177 | /** | |
178 | * ata_sff_dma_pause - Pause before commencing DMA | |
179 | * @ap: Port to pause for. | |
180 | * | |
181 | * Perform I/O fencing and ensure sufficient cycle delays occur | |
182 | * for the HDMA1:0 transition | |
183 | */ | |
0fe40ff8 | 184 | |
a57c1bad AC |
185 | void ata_sff_dma_pause(struct ata_port *ap) |
186 | { | |
187 | if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) { | |
188 | /* An altstatus read will cause the needed delay without | |
189 | messing up the IRQ status */ | |
190 | ata_sff_altstatus(ap); | |
191 | return; | |
192 | } | |
193 | /* There are no DMA controllers without ctl. BUG here to ensure | |
194 | we never violate the HDMA1:0 transition timing and risk | |
195 | corruption. */ | |
196 | BUG(); | |
197 | } | |
0fe40ff8 | 198 | EXPORT_SYMBOL_GPL(ata_sff_dma_pause); |
a57c1bad | 199 | |
624d5c51 | 200 | /** |
9363c382 | 201 | * ata_sff_busy_sleep - sleep until BSY clears, or timeout |
624d5c51 | 202 | * @ap: port containing status register to be polled |
341c2c95 TH |
203 | * @tmout_pat: impatience timeout in msecs |
204 | * @tmout: overall timeout in msecs | |
624d5c51 TH |
205 | * |
206 | * Sleep until ATA Status register bit BSY clears, | |
207 | * or a timeout occurs. | |
208 | * | |
209 | * LOCKING: | |
210 | * Kernel thread context (may sleep). | |
211 | * | |
212 | * RETURNS: | |
213 | * 0 on success, -errno otherwise. | |
214 | */ | |
9363c382 TH |
215 | int ata_sff_busy_sleep(struct ata_port *ap, |
216 | unsigned long tmout_pat, unsigned long tmout) | |
624d5c51 TH |
217 | { |
218 | unsigned long timer_start, timeout; | |
219 | u8 status; | |
220 | ||
9363c382 | 221 | status = ata_sff_busy_wait(ap, ATA_BUSY, 300); |
624d5c51 | 222 | timer_start = jiffies; |
341c2c95 | 223 | timeout = ata_deadline(timer_start, tmout_pat); |
624d5c51 TH |
224 | while (status != 0xff && (status & ATA_BUSY) && |
225 | time_before(jiffies, timeout)) { | |
97750ceb | 226 | ata_msleep(ap, 50); |
9363c382 | 227 | status = ata_sff_busy_wait(ap, ATA_BUSY, 3); |
624d5c51 TH |
228 | } |
229 | ||
230 | if (status != 0xff && (status & ATA_BUSY)) | |
a9a79dfe JP |
231 | ata_port_warn(ap, |
232 | "port is slow to respond, please be patient (Status 0x%x)\n", | |
233 | status); | |
624d5c51 | 234 | |
341c2c95 | 235 | timeout = ata_deadline(timer_start, tmout); |
624d5c51 TH |
236 | while (status != 0xff && (status & ATA_BUSY) && |
237 | time_before(jiffies, timeout)) { | |
97750ceb | 238 | ata_msleep(ap, 50); |
5682ed33 | 239 | status = ap->ops->sff_check_status(ap); |
624d5c51 TH |
240 | } |
241 | ||
242 | if (status == 0xff) | |
243 | return -ENODEV; | |
244 | ||
245 | if (status & ATA_BUSY) { | |
a9a79dfe JP |
246 | ata_port_err(ap, |
247 | "port failed to respond (%lu secs, Status 0x%x)\n", | |
248 | DIV_ROUND_UP(tmout, 1000), status); | |
624d5c51 TH |
249 | return -EBUSY; |
250 | } | |
251 | ||
252 | return 0; | |
253 | } | |
0fe40ff8 | 254 | EXPORT_SYMBOL_GPL(ata_sff_busy_sleep); |
624d5c51 | 255 | |
aa2731ad TH |
256 | static int ata_sff_check_ready(struct ata_link *link) |
257 | { | |
258 | u8 status = link->ap->ops->sff_check_status(link->ap); | |
259 | ||
78ab88f0 | 260 | return ata_check_ready(status); |
aa2731ad TH |
261 | } |
262 | ||
624d5c51 | 263 | /** |
9363c382 | 264 | * ata_sff_wait_ready - sleep until BSY clears, or timeout |
705e76be | 265 | * @link: SFF link to wait ready status for |
624d5c51 TH |
266 | * @deadline: deadline jiffies for the operation |
267 | * | |
268 | * Sleep until ATA Status register bit BSY clears, or timeout | |
269 | * occurs. | |
270 | * | |
271 | * LOCKING: | |
272 | * Kernel thread context (may sleep). | |
273 | * | |
274 | * RETURNS: | |
275 | * 0 on success, -errno otherwise. | |
276 | */ | |
705e76be | 277 | int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline) |
624d5c51 | 278 | { |
aa2731ad | 279 | return ata_wait_ready(link, deadline, ata_sff_check_ready); |
624d5c51 | 280 | } |
0fe40ff8 | 281 | EXPORT_SYMBOL_GPL(ata_sff_wait_ready); |
624d5c51 | 282 | |
41dec29b SS |
283 | /** |
284 | * ata_sff_set_devctl - Write device control reg | |
285 | * @ap: port where the device is | |
286 | * @ctl: value to write | |
287 | * | |
288 | * Writes ATA taskfile device control register. | |
289 | * | |
290 | * Note: may NOT be used as the sff_set_devctl() entry in | |
291 | * ata_port_operations. | |
292 | * | |
293 | * LOCKING: | |
294 | * Inherited from caller. | |
295 | */ | |
296 | static void ata_sff_set_devctl(struct ata_port *ap, u8 ctl) | |
297 | { | |
298 | if (ap->ops->sff_set_devctl) | |
299 | ap->ops->sff_set_devctl(ap, ctl); | |
300 | else | |
301 | iowrite8(ctl, ap->ioaddr.ctl_addr); | |
302 | } | |
303 | ||
624d5c51 | 304 | /** |
9363c382 | 305 | * ata_sff_dev_select - Select device 0/1 on ATA bus |
624d5c51 TH |
306 | * @ap: ATA channel to manipulate |
307 | * @device: ATA device (numbered from zero) to select | |
308 | * | |
309 | * Use the method defined in the ATA specification to | |
310 | * make either device 0, or device 1, active on the | |
311 | * ATA channel. Works with both PIO and MMIO. | |
312 | * | |
313 | * May be used as the dev_select() entry in ata_port_operations. | |
314 | * | |
315 | * LOCKING: | |
316 | * caller. | |
317 | */ | |
9363c382 | 318 | void ata_sff_dev_select(struct ata_port *ap, unsigned int device) |
624d5c51 TH |
319 | { |
320 | u8 tmp; | |
321 | ||
322 | if (device == 0) | |
323 | tmp = ATA_DEVICE_OBS; | |
324 | else | |
325 | tmp = ATA_DEVICE_OBS | ATA_DEV1; | |
326 | ||
327 | iowrite8(tmp, ap->ioaddr.device_addr); | |
9363c382 | 328 | ata_sff_pause(ap); /* needed; also flushes, for mmio */ |
624d5c51 | 329 | } |
0fe40ff8 | 330 | EXPORT_SYMBOL_GPL(ata_sff_dev_select); |
624d5c51 TH |
331 | |
332 | /** | |
333 | * ata_dev_select - Select device 0/1 on ATA bus | |
334 | * @ap: ATA channel to manipulate | |
335 | * @device: ATA device (numbered from zero) to select | |
336 | * @wait: non-zero to wait for Status register BSY bit to clear | |
337 | * @can_sleep: non-zero if context allows sleeping | |
338 | * | |
339 | * Use the method defined in the ATA specification to | |
340 | * make either device 0, or device 1, active on the | |
341 | * ATA channel. | |
342 | * | |
9363c382 TH |
343 | * This is a high-level version of ata_sff_dev_select(), which |
344 | * additionally provides the services of inserting the proper | |
345 | * pauses and status polling, where needed. | |
624d5c51 TH |
346 | * |
347 | * LOCKING: | |
348 | * caller. | |
349 | */ | |
c7a8209f | 350 | static void ata_dev_select(struct ata_port *ap, unsigned int device, |
624d5c51 TH |
351 | unsigned int wait, unsigned int can_sleep) |
352 | { | |
353 | if (ata_msg_probe(ap)) | |
a9a79dfe JP |
354 | ata_port_info(ap, "ata_dev_select: ENTER, device %u, wait %u\n", |
355 | device, wait); | |
624d5c51 TH |
356 | |
357 | if (wait) | |
358 | ata_wait_idle(ap); | |
359 | ||
5682ed33 | 360 | ap->ops->sff_dev_select(ap, device); |
624d5c51 TH |
361 | |
362 | if (wait) { | |
363 | if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI) | |
97750ceb | 364 | ata_msleep(ap, 150); |
624d5c51 TH |
365 | ata_wait_idle(ap); |
366 | } | |
367 | } | |
368 | ||
369 | /** | |
9363c382 | 370 | * ata_sff_irq_on - Enable interrupts on a port. |
624d5c51 TH |
371 | * @ap: Port on which interrupts are enabled. |
372 | * | |
373 | * Enable interrupts on a legacy IDE device using MMIO or PIO, | |
374 | * wait for idle, clear any pending interrupts. | |
375 | * | |
e42a542b SS |
376 | * Note: may NOT be used as the sff_irq_on() entry in |
377 | * ata_port_operations. | |
378 | * | |
624d5c51 TH |
379 | * LOCKING: |
380 | * Inherited from caller. | |
381 | */ | |
e42a542b | 382 | void ata_sff_irq_on(struct ata_port *ap) |
624d5c51 TH |
383 | { |
384 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
e42a542b SS |
385 | |
386 | if (ap->ops->sff_irq_on) { | |
387 | ap->ops->sff_irq_on(ap); | |
388 | return; | |
389 | } | |
624d5c51 TH |
390 | |
391 | ap->ctl &= ~ATA_NIEN; | |
392 | ap->last_ctl = ap->ctl; | |
393 | ||
e42a542b SS |
394 | if (ap->ops->sff_set_devctl || ioaddr->ctl_addr) |
395 | ata_sff_set_devctl(ap, ap->ctl); | |
396 | ata_wait_idle(ap); | |
624d5c51 | 397 | |
37f65b8b TH |
398 | if (ap->ops->sff_irq_clear) |
399 | ap->ops->sff_irq_clear(ap); | |
624d5c51 | 400 | } |
0fe40ff8 | 401 | EXPORT_SYMBOL_GPL(ata_sff_irq_on); |
624d5c51 | 402 | |
624d5c51 | 403 | /** |
9363c382 | 404 | * ata_sff_tf_load - send taskfile registers to host controller |
624d5c51 TH |
405 | * @ap: Port to which output is sent |
406 | * @tf: ATA taskfile register set | |
407 | * | |
408 | * Outputs ATA taskfile to standard ATA host controller. | |
409 | * | |
410 | * LOCKING: | |
411 | * Inherited from caller. | |
412 | */ | |
9363c382 | 413 | void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
624d5c51 TH |
414 | { |
415 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
416 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
417 | ||
418 | if (tf->ctl != ap->last_ctl) { | |
419 | if (ioaddr->ctl_addr) | |
420 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
421 | ap->last_ctl = tf->ctl; | |
40c60230 | 422 | ata_wait_idle(ap); |
624d5c51 TH |
423 | } |
424 | ||
425 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
efcb3cf7 | 426 | WARN_ON_ONCE(!ioaddr->ctl_addr); |
624d5c51 TH |
427 | iowrite8(tf->hob_feature, ioaddr->feature_addr); |
428 | iowrite8(tf->hob_nsect, ioaddr->nsect_addr); | |
429 | iowrite8(tf->hob_lbal, ioaddr->lbal_addr); | |
430 | iowrite8(tf->hob_lbam, ioaddr->lbam_addr); | |
431 | iowrite8(tf->hob_lbah, ioaddr->lbah_addr); | |
432 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", | |
433 | tf->hob_feature, | |
434 | tf->hob_nsect, | |
435 | tf->hob_lbal, | |
436 | tf->hob_lbam, | |
437 | tf->hob_lbah); | |
438 | } | |
439 | ||
440 | if (is_addr) { | |
441 | iowrite8(tf->feature, ioaddr->feature_addr); | |
442 | iowrite8(tf->nsect, ioaddr->nsect_addr); | |
443 | iowrite8(tf->lbal, ioaddr->lbal_addr); | |
444 | iowrite8(tf->lbam, ioaddr->lbam_addr); | |
445 | iowrite8(tf->lbah, ioaddr->lbah_addr); | |
446 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", | |
447 | tf->feature, | |
448 | tf->nsect, | |
449 | tf->lbal, | |
450 | tf->lbam, | |
451 | tf->lbah); | |
452 | } | |
453 | ||
454 | if (tf->flags & ATA_TFLAG_DEVICE) { | |
455 | iowrite8(tf->device, ioaddr->device_addr); | |
456 | VPRINTK("device 0x%X\n", tf->device); | |
457 | } | |
40c60230 TH |
458 | |
459 | ata_wait_idle(ap); | |
624d5c51 | 460 | } |
0fe40ff8 | 461 | EXPORT_SYMBOL_GPL(ata_sff_tf_load); |
624d5c51 TH |
462 | |
463 | /** | |
9363c382 | 464 | * ata_sff_tf_read - input device's ATA taskfile shadow registers |
624d5c51 TH |
465 | * @ap: Port from which input is read |
466 | * @tf: ATA taskfile register set for storing input | |
467 | * | |
468 | * Reads ATA taskfile registers for currently-selected device | |
469 | * into @tf. Assumes the device has a fully SFF compliant task file | |
470 | * layout and behaviour. If you device does not (eg has a different | |
471 | * status method) then you will need to provide a replacement tf_read | |
472 | * | |
473 | * LOCKING: | |
474 | * Inherited from caller. | |
475 | */ | |
9363c382 | 476 | void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
624d5c51 TH |
477 | { |
478 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
479 | ||
9363c382 | 480 | tf->command = ata_sff_check_status(ap); |
624d5c51 TH |
481 | tf->feature = ioread8(ioaddr->error_addr); |
482 | tf->nsect = ioread8(ioaddr->nsect_addr); | |
483 | tf->lbal = ioread8(ioaddr->lbal_addr); | |
484 | tf->lbam = ioread8(ioaddr->lbam_addr); | |
485 | tf->lbah = ioread8(ioaddr->lbah_addr); | |
486 | tf->device = ioread8(ioaddr->device_addr); | |
487 | ||
488 | if (tf->flags & ATA_TFLAG_LBA48) { | |
489 | if (likely(ioaddr->ctl_addr)) { | |
490 | iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); | |
491 | tf->hob_feature = ioread8(ioaddr->error_addr); | |
492 | tf->hob_nsect = ioread8(ioaddr->nsect_addr); | |
493 | tf->hob_lbal = ioread8(ioaddr->lbal_addr); | |
494 | tf->hob_lbam = ioread8(ioaddr->lbam_addr); | |
495 | tf->hob_lbah = ioread8(ioaddr->lbah_addr); | |
496 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
497 | ap->last_ctl = tf->ctl; | |
498 | } else | |
efcb3cf7 | 499 | WARN_ON_ONCE(1); |
624d5c51 TH |
500 | } |
501 | } | |
0fe40ff8 | 502 | EXPORT_SYMBOL_GPL(ata_sff_tf_read); |
624d5c51 TH |
503 | |
504 | /** | |
9363c382 | 505 | * ata_sff_exec_command - issue ATA command to host controller |
624d5c51 TH |
506 | * @ap: port to which command is being issued |
507 | * @tf: ATA taskfile register set | |
508 | * | |
509 | * Issues ATA command, with proper synchronization with interrupt | |
510 | * handler / other threads. | |
511 | * | |
512 | * LOCKING: | |
513 | * spin_lock_irqsave(host lock) | |
514 | */ | |
9363c382 | 515 | void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) |
624d5c51 TH |
516 | { |
517 | DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); | |
518 | ||
519 | iowrite8(tf->command, ap->ioaddr.command_addr); | |
9363c382 | 520 | ata_sff_pause(ap); |
624d5c51 | 521 | } |
0fe40ff8 | 522 | EXPORT_SYMBOL_GPL(ata_sff_exec_command); |
624d5c51 TH |
523 | |
524 | /** | |
525 | * ata_tf_to_host - issue ATA taskfile to host controller | |
526 | * @ap: port to which command is being issued | |
527 | * @tf: ATA taskfile register set | |
528 | * | |
529 | * Issues ATA taskfile register set to ATA host controller, | |
530 | * with proper synchronization with interrupt handler and | |
531 | * other threads. | |
532 | * | |
533 | * LOCKING: | |
534 | * spin_lock_irqsave(host lock) | |
535 | */ | |
536 | static inline void ata_tf_to_host(struct ata_port *ap, | |
537 | const struct ata_taskfile *tf) | |
538 | { | |
5682ed33 TH |
539 | ap->ops->sff_tf_load(ap, tf); |
540 | ap->ops->sff_exec_command(ap, tf); | |
624d5c51 TH |
541 | } |
542 | ||
543 | /** | |
9363c382 | 544 | * ata_sff_data_xfer - Transfer data by PIO |
989e0aac | 545 | * @qc: queued command |
624d5c51 TH |
546 | * @buf: data buffer |
547 | * @buflen: buffer length | |
548 | * @rw: read/write | |
549 | * | |
550 | * Transfer data from/to the device data register by PIO. | |
551 | * | |
552 | * LOCKING: | |
553 | * Inherited from caller. | |
554 | * | |
555 | * RETURNS: | |
556 | * Bytes consumed. | |
557 | */ | |
989e0aac | 558 | unsigned int ata_sff_data_xfer(struct ata_queued_cmd *qc, unsigned char *buf, |
9363c382 | 559 | unsigned int buflen, int rw) |
624d5c51 | 560 | { |
989e0aac | 561 | struct ata_port *ap = qc->dev->link->ap; |
624d5c51 TH |
562 | void __iomem *data_addr = ap->ioaddr.data_addr; |
563 | unsigned int words = buflen >> 1; | |
564 | ||
565 | /* Transfer multiple of 2 bytes */ | |
566 | if (rw == READ) | |
567 | ioread16_rep(data_addr, buf, words); | |
568 | else | |
569 | iowrite16_rep(data_addr, buf, words); | |
570 | ||
2102d749 | 571 | /* Transfer trailing byte, if any. */ |
624d5c51 | 572 | if (unlikely(buflen & 0x01)) { |
21dba244 | 573 | unsigned char pad[2] = { }; |
624d5c51 | 574 | |
2102d749 SS |
575 | /* Point buf to the tail of buffer */ |
576 | buf += buflen - 1; | |
577 | ||
578 | /* | |
579 | * Use io*16_rep() accessors here as well to avoid pointlessly | |
972b94ff | 580 | * swapping bytes to and from on the big endian machines... |
2102d749 | 581 | */ |
624d5c51 | 582 | if (rw == READ) { |
2102d749 SS |
583 | ioread16_rep(data_addr, pad, 1); |
584 | *buf = pad[0]; | |
624d5c51 | 585 | } else { |
2102d749 SS |
586 | pad[0] = *buf; |
587 | iowrite16_rep(data_addr, pad, 1); | |
624d5c51 TH |
588 | } |
589 | words++; | |
590 | } | |
591 | ||
592 | return words << 1; | |
593 | } | |
0fe40ff8 | 594 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer); |
624d5c51 | 595 | |
871af121 AC |
596 | /** |
597 | * ata_sff_data_xfer32 - Transfer data by PIO | |
989e0aac | 598 | * @qc: queued command |
871af121 AC |
599 | * @buf: data buffer |
600 | * @buflen: buffer length | |
601 | * @rw: read/write | |
602 | * | |
603 | * Transfer data from/to the device data register by PIO using 32bit | |
604 | * I/O operations. | |
605 | * | |
606 | * LOCKING: | |
607 | * Inherited from caller. | |
608 | * | |
609 | * RETURNS: | |
610 | * Bytes consumed. | |
611 | */ | |
612 | ||
989e0aac | 613 | unsigned int ata_sff_data_xfer32(struct ata_queued_cmd *qc, unsigned char *buf, |
871af121 AC |
614 | unsigned int buflen, int rw) |
615 | { | |
989e0aac | 616 | struct ata_device *dev = qc->dev; |
871af121 AC |
617 | struct ata_port *ap = dev->link->ap; |
618 | void __iomem *data_addr = ap->ioaddr.data_addr; | |
619 | unsigned int words = buflen >> 2; | |
620 | int slop = buflen & 3; | |
972b94ff | 621 | |
e3cf95dd | 622 | if (!(ap->pflags & ATA_PFLAG_PIO32)) |
989e0aac | 623 | return ata_sff_data_xfer(qc, buf, buflen, rw); |
871af121 AC |
624 | |
625 | /* Transfer multiple of 4 bytes */ | |
626 | if (rw == READ) | |
627 | ioread32_rep(data_addr, buf, words); | |
628 | else | |
629 | iowrite32_rep(data_addr, buf, words); | |
630 | ||
d1b3525b | 631 | /* Transfer trailing bytes, if any */ |
871af121 | 632 | if (unlikely(slop)) { |
21dba244 | 633 | unsigned char pad[4] = { }; |
d1b3525b SS |
634 | |
635 | /* Point buf to the tail of buffer */ | |
636 | buf += buflen - slop; | |
637 | ||
638 | /* | |
639 | * Use io*_rep() accessors here as well to avoid pointlessly | |
972b94ff | 640 | * swapping bytes to and from on the big endian machines... |
d1b3525b | 641 | */ |
871af121 | 642 | if (rw == READ) { |
d1b3525b SS |
643 | if (slop < 3) |
644 | ioread16_rep(data_addr, pad, 1); | |
645 | else | |
646 | ioread32_rep(data_addr, pad, 1); | |
647 | memcpy(buf, pad, slop); | |
871af121 | 648 | } else { |
d1b3525b SS |
649 | memcpy(pad, buf, slop); |
650 | if (slop < 3) | |
651 | iowrite16_rep(data_addr, pad, 1); | |
652 | else | |
653 | iowrite32_rep(data_addr, pad, 1); | |
871af121 | 654 | } |
871af121 | 655 | } |
d1b3525b | 656 | return (buflen + 1) & ~1; |
871af121 AC |
657 | } |
658 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer32); | |
659 | ||
624d5c51 TH |
660 | /** |
661 | * ata_pio_sector - Transfer a sector of data. | |
662 | * @qc: Command on going | |
663 | * | |
664 | * Transfer qc->sect_size bytes of data from/to the ATA device. | |
665 | * | |
666 | * LOCKING: | |
667 | * Inherited from caller. | |
668 | */ | |
669 | static void ata_pio_sector(struct ata_queued_cmd *qc) | |
670 | { | |
671 | int do_write = (qc->tf.flags & ATA_TFLAG_WRITE); | |
672 | struct ata_port *ap = qc->ap; | |
673 | struct page *page; | |
674 | unsigned int offset; | |
675 | unsigned char *buf; | |
676 | ||
677 | if (qc->curbytes == qc->nbytes - qc->sect_size) | |
678 | ap->hsm_task_state = HSM_ST_LAST; | |
679 | ||
680 | page = sg_page(qc->cursg); | |
681 | offset = qc->cursg->offset + qc->cursg_ofs; | |
682 | ||
683 | /* get the current page and offset */ | |
684 | page = nth_page(page, (offset >> PAGE_SHIFT)); | |
685 | offset %= PAGE_SIZE; | |
686 | ||
687 | DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); | |
688 | ||
5d7a288c TA |
689 | /* do the actual data transfer */ |
690 | buf = kmap_atomic(page); | |
691 | ap->ops->sff_data_xfer(qc, buf + offset, qc->sect_size, do_write); | |
692 | kunmap_atomic(buf); | |
624d5c51 | 693 | |
3842e835 | 694 | if (!do_write && !PageSlab(page)) |
2d68b7fe CM |
695 | flush_dcache_page(page); |
696 | ||
624d5c51 TH |
697 | qc->curbytes += qc->sect_size; |
698 | qc->cursg_ofs += qc->sect_size; | |
699 | ||
700 | if (qc->cursg_ofs == qc->cursg->length) { | |
701 | qc->cursg = sg_next(qc->cursg); | |
702 | qc->cursg_ofs = 0; | |
703 | } | |
704 | } | |
705 | ||
706 | /** | |
707 | * ata_pio_sectors - Transfer one or many sectors. | |
708 | * @qc: Command on going | |
709 | * | |
710 | * Transfer one or many sectors of data from/to the | |
711 | * ATA device for the DRQ request. | |
712 | * | |
713 | * LOCKING: | |
714 | * Inherited from caller. | |
715 | */ | |
716 | static void ata_pio_sectors(struct ata_queued_cmd *qc) | |
717 | { | |
718 | if (is_multi_taskfile(&qc->tf)) { | |
719 | /* READ/WRITE MULTIPLE */ | |
720 | unsigned int nsect; | |
721 | ||
efcb3cf7 | 722 | WARN_ON_ONCE(qc->dev->multi_count == 0); |
624d5c51 TH |
723 | |
724 | nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size, | |
725 | qc->dev->multi_count); | |
726 | while (nsect--) | |
727 | ata_pio_sector(qc); | |
728 | } else | |
729 | ata_pio_sector(qc); | |
730 | ||
a57c1bad | 731 | ata_sff_sync(qc->ap); /* flush */ |
624d5c51 TH |
732 | } |
733 | ||
734 | /** | |
735 | * atapi_send_cdb - Write CDB bytes to hardware | |
736 | * @ap: Port to which ATAPI device is attached. | |
737 | * @qc: Taskfile currently active | |
738 | * | |
739 | * When device has indicated its readiness to accept | |
740 | * a CDB, this function is called. Send the CDB. | |
741 | * | |
742 | * LOCKING: | |
743 | * caller. | |
744 | */ | |
745 | static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc) | |
746 | { | |
747 | /* send SCSI cdb */ | |
748 | DPRINTK("send cdb\n"); | |
efcb3cf7 | 749 | WARN_ON_ONCE(qc->dev->cdb_len < 12); |
624d5c51 | 750 | |
989e0aac | 751 | ap->ops->sff_data_xfer(qc, qc->cdb, qc->dev->cdb_len, 1); |
a57c1bad AC |
752 | ata_sff_sync(ap); |
753 | /* FIXME: If the CDB is for DMA do we need to do the transition delay | |
754 | or is bmdma_start guaranteed to do it ? */ | |
624d5c51 TH |
755 | switch (qc->tf.protocol) { |
756 | case ATAPI_PROT_PIO: | |
757 | ap->hsm_task_state = HSM_ST; | |
758 | break; | |
759 | case ATAPI_PROT_NODATA: | |
760 | ap->hsm_task_state = HSM_ST_LAST; | |
761 | break; | |
9a7780c9 | 762 | #ifdef CONFIG_ATA_BMDMA |
624d5c51 TH |
763 | case ATAPI_PROT_DMA: |
764 | ap->hsm_task_state = HSM_ST_LAST; | |
765 | /* initiate bmdma */ | |
766 | ap->ops->bmdma_start(qc); | |
767 | break; | |
9a7780c9 TH |
768 | #endif /* CONFIG_ATA_BMDMA */ |
769 | default: | |
770 | BUG(); | |
624d5c51 TH |
771 | } |
772 | } | |
773 | ||
774 | /** | |
775 | * __atapi_pio_bytes - Transfer data from/to the ATAPI device. | |
776 | * @qc: Command on going | |
777 | * @bytes: number of bytes | |
778 | * | |
779 | * Transfer Transfer data from/to the ATAPI device. | |
780 | * | |
781 | * LOCKING: | |
782 | * Inherited from caller. | |
783 | * | |
784 | */ | |
785 | static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes) | |
786 | { | |
787 | int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ; | |
788 | struct ata_port *ap = qc->ap; | |
789 | struct ata_device *dev = qc->dev; | |
790 | struct ata_eh_info *ehi = &dev->link->eh_info; | |
791 | struct scatterlist *sg; | |
792 | struct page *page; | |
793 | unsigned char *buf; | |
794 | unsigned int offset, count, consumed; | |
795 | ||
796 | next_sg: | |
797 | sg = qc->cursg; | |
798 | if (unlikely(!sg)) { | |
799 | ata_ehi_push_desc(ehi, "unexpected or too much trailing data " | |
800 | "buf=%u cur=%u bytes=%u", | |
801 | qc->nbytes, qc->curbytes, bytes); | |
802 | return -1; | |
803 | } | |
804 | ||
805 | page = sg_page(sg); | |
806 | offset = sg->offset + qc->cursg_ofs; | |
807 | ||
808 | /* get the current page and offset */ | |
809 | page = nth_page(page, (offset >> PAGE_SHIFT)); | |
810 | offset %= PAGE_SIZE; | |
811 | ||
812 | /* don't overrun current sg */ | |
813 | count = min(sg->length - qc->cursg_ofs, bytes); | |
814 | ||
815 | /* don't cross page boundaries */ | |
816 | count = min(count, (unsigned int)PAGE_SIZE - offset); | |
817 | ||
818 | DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); | |
819 | ||
5d7a288c TA |
820 | /* do the actual data transfer */ |
821 | buf = kmap_atomic(page); | |
822 | consumed = ap->ops->sff_data_xfer(qc, buf + offset, count, rw); | |
823 | kunmap_atomic(buf); | |
624d5c51 TH |
824 | |
825 | bytes -= min(bytes, consumed); | |
826 | qc->curbytes += count; | |
827 | qc->cursg_ofs += count; | |
828 | ||
829 | if (qc->cursg_ofs == sg->length) { | |
830 | qc->cursg = sg_next(qc->cursg); | |
831 | qc->cursg_ofs = 0; | |
832 | } | |
833 | ||
a0f79f7a CB |
834 | /* |
835 | * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed); | |
836 | * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN | |
837 | * check correctly as it doesn't know if it is the last request being | |
838 | * made. Somebody should implement a proper sanity check. | |
839 | */ | |
624d5c51 TH |
840 | if (bytes) |
841 | goto next_sg; | |
842 | return 0; | |
843 | } | |
844 | ||
845 | /** | |
846 | * atapi_pio_bytes - Transfer data from/to the ATAPI device. | |
847 | * @qc: Command on going | |
848 | * | |
849 | * Transfer Transfer data from/to the ATAPI device. | |
850 | * | |
851 | * LOCKING: | |
852 | * Inherited from caller. | |
853 | */ | |
854 | static void atapi_pio_bytes(struct ata_queued_cmd *qc) | |
855 | { | |
856 | struct ata_port *ap = qc->ap; | |
857 | struct ata_device *dev = qc->dev; | |
858 | struct ata_eh_info *ehi = &dev->link->eh_info; | |
859 | unsigned int ireason, bc_lo, bc_hi, bytes; | |
860 | int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0; | |
861 | ||
862 | /* Abuse qc->result_tf for temp storage of intermediate TF | |
863 | * here to save some kernel stack usage. | |
864 | * For normal completion, qc->result_tf is not relevant. For | |
865 | * error, qc->result_tf is later overwritten by ata_qc_complete(). | |
866 | * So, the correctness of qc->result_tf is not affected. | |
867 | */ | |
5682ed33 | 868 | ap->ops->sff_tf_read(ap, &qc->result_tf); |
624d5c51 TH |
869 | ireason = qc->result_tf.nsect; |
870 | bc_lo = qc->result_tf.lbam; | |
871 | bc_hi = qc->result_tf.lbah; | |
872 | bytes = (bc_hi << 8) | bc_lo; | |
873 | ||
874 | /* shall be cleared to zero, indicating xfer of data */ | |
002ae084 | 875 | if (unlikely(ireason & ATAPI_COD)) |
624d5c51 TH |
876 | goto atapi_check; |
877 | ||
878 | /* make sure transfer direction matches expected */ | |
002ae084 | 879 | i_write = ((ireason & ATAPI_IO) == 0) ? 1 : 0; |
624d5c51 TH |
880 | if (unlikely(do_write != i_write)) |
881 | goto atapi_check; | |
882 | ||
883 | if (unlikely(!bytes)) | |
884 | goto atapi_check; | |
885 | ||
886 | VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes); | |
887 | ||
888 | if (unlikely(__atapi_pio_bytes(qc, bytes))) | |
889 | goto err_out; | |
a57c1bad | 890 | ata_sff_sync(ap); /* flush */ |
624d5c51 TH |
891 | |
892 | return; | |
893 | ||
894 | atapi_check: | |
895 | ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)", | |
896 | ireason, bytes); | |
897 | err_out: | |
898 | qc->err_mask |= AC_ERR_HSM; | |
899 | ap->hsm_task_state = HSM_ST_ERR; | |
900 | } | |
901 | ||
902 | /** | |
903 | * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue. | |
904 | * @ap: the target ata_port | |
905 | * @qc: qc on going | |
906 | * | |
907 | * RETURNS: | |
908 | * 1 if ok in workqueue, 0 otherwise. | |
909 | */ | |
0fe40ff8 AC |
910 | static inline int ata_hsm_ok_in_wq(struct ata_port *ap, |
911 | struct ata_queued_cmd *qc) | |
624d5c51 TH |
912 | { |
913 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
914 | return 1; | |
915 | ||
916 | if (ap->hsm_task_state == HSM_ST_FIRST) { | |
917 | if (qc->tf.protocol == ATA_PROT_PIO && | |
0fe40ff8 | 918 | (qc->tf.flags & ATA_TFLAG_WRITE)) |
624d5c51 TH |
919 | return 1; |
920 | ||
921 | if (ata_is_atapi(qc->tf.protocol) && | |
0fe40ff8 | 922 | !(qc->dev->flags & ATA_DFLAG_CDB_INTR)) |
624d5c51 TH |
923 | return 1; |
924 | } | |
925 | ||
926 | return 0; | |
927 | } | |
928 | ||
929 | /** | |
930 | * ata_hsm_qc_complete - finish a qc running on standard HSM | |
931 | * @qc: Command to complete | |
932 | * @in_wq: 1 if called from workqueue, 0 otherwise | |
933 | * | |
934 | * Finish @qc which is running on standard HSM. | |
935 | * | |
936 | * LOCKING: | |
937 | * If @in_wq is zero, spin_lock_irqsave(host lock). | |
938 | * Otherwise, none on entry and grabs host lock. | |
939 | */ | |
940 | static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq) | |
941 | { | |
942 | struct ata_port *ap = qc->ap; | |
624d5c51 TH |
943 | |
944 | if (ap->ops->error_handler) { | |
945 | if (in_wq) { | |
624d5c51 TH |
946 | /* EH might have kicked in while host lock is |
947 | * released. | |
948 | */ | |
949 | qc = ata_qc_from_tag(ap, qc->tag); | |
950 | if (qc) { | |
951 | if (likely(!(qc->err_mask & AC_ERR_HSM))) { | |
e42a542b | 952 | ata_sff_irq_on(ap); |
624d5c51 TH |
953 | ata_qc_complete(qc); |
954 | } else | |
955 | ata_port_freeze(ap); | |
956 | } | |
624d5c51 TH |
957 | } else { |
958 | if (likely(!(qc->err_mask & AC_ERR_HSM))) | |
959 | ata_qc_complete(qc); | |
960 | else | |
961 | ata_port_freeze(ap); | |
962 | } | |
963 | } else { | |
964 | if (in_wq) { | |
e42a542b | 965 | ata_sff_irq_on(ap); |
624d5c51 | 966 | ata_qc_complete(qc); |
624d5c51 TH |
967 | } else |
968 | ata_qc_complete(qc); | |
969 | } | |
970 | } | |
971 | ||
972 | /** | |
9363c382 | 973 | * ata_sff_hsm_move - move the HSM to the next state. |
624d5c51 TH |
974 | * @ap: the target ata_port |
975 | * @qc: qc on going | |
976 | * @status: current device status | |
977 | * @in_wq: 1 if called from workqueue, 0 otherwise | |
978 | * | |
979 | * RETURNS: | |
980 | * 1 when poll next status needed, 0 otherwise. | |
981 | */ | |
9363c382 TH |
982 | int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc, |
983 | u8 status, int in_wq) | |
624d5c51 | 984 | { |
ea3c6450 GG |
985 | struct ata_link *link = qc->dev->link; |
986 | struct ata_eh_info *ehi = &link->eh_info; | |
624d5c51 TH |
987 | int poll_next; |
988 | ||
8eee1d3e TH |
989 | lockdep_assert_held(ap->lock); |
990 | ||
efcb3cf7 | 991 | WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0); |
624d5c51 | 992 | |
9363c382 | 993 | /* Make sure ata_sff_qc_issue() does not throw things |
624d5c51 TH |
994 | * like DMA polling into the workqueue. Notice that |
995 | * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING). | |
996 | */ | |
efcb3cf7 | 997 | WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc)); |
624d5c51 TH |
998 | |
999 | fsm_start: | |
1000 | DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n", | |
1001 | ap->print_id, qc->tf.protocol, ap->hsm_task_state, status); | |
1002 | ||
1003 | switch (ap->hsm_task_state) { | |
1004 | case HSM_ST_FIRST: | |
1005 | /* Send first data block or PACKET CDB */ | |
1006 | ||
1007 | /* If polling, we will stay in the work queue after | |
1008 | * sending the data. Otherwise, interrupt handler | |
1009 | * takes over after sending the data. | |
1010 | */ | |
1011 | poll_next = (qc->tf.flags & ATA_TFLAG_POLLING); | |
1012 | ||
1013 | /* check device status */ | |
1014 | if (unlikely((status & ATA_DRQ) == 0)) { | |
1015 | /* handle BSY=0, DRQ=0 as error */ | |
1016 | if (likely(status & (ATA_ERR | ATA_DF))) | |
1017 | /* device stops HSM for abort/error */ | |
1018 | qc->err_mask |= AC_ERR_DEV; | |
a836d3e8 | 1019 | else { |
624d5c51 | 1020 | /* HSM violation. Let EH handle this */ |
a836d3e8 TH |
1021 | ata_ehi_push_desc(ehi, |
1022 | "ST_FIRST: !(DRQ|ERR|DF)"); | |
624d5c51 | 1023 | qc->err_mask |= AC_ERR_HSM; |
a836d3e8 | 1024 | } |
624d5c51 TH |
1025 | |
1026 | ap->hsm_task_state = HSM_ST_ERR; | |
1027 | goto fsm_start; | |
1028 | } | |
1029 | ||
1030 | /* Device should not ask for data transfer (DRQ=1) | |
1031 | * when it finds something wrong. | |
1032 | * We ignore DRQ here and stop the HSM by | |
1033 | * changing hsm_task_state to HSM_ST_ERR and | |
1034 | * let the EH abort the command or reset the device. | |
1035 | */ | |
1036 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
1037 | /* Some ATAPI tape drives forget to clear the ERR bit | |
1038 | * when doing the next command (mostly request sense). | |
1039 | * We ignore ERR here to workaround and proceed sending | |
1040 | * the CDB. | |
1041 | */ | |
1042 | if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) { | |
a836d3e8 TH |
1043 | ata_ehi_push_desc(ehi, "ST_FIRST: " |
1044 | "DRQ=1 with device error, " | |
1045 | "dev_stat 0x%X", status); | |
624d5c51 TH |
1046 | qc->err_mask |= AC_ERR_HSM; |
1047 | ap->hsm_task_state = HSM_ST_ERR; | |
1048 | goto fsm_start; | |
1049 | } | |
1050 | } | |
1051 | ||
624d5c51 TH |
1052 | if (qc->tf.protocol == ATA_PROT_PIO) { |
1053 | /* PIO data out protocol. | |
1054 | * send first data block. | |
1055 | */ | |
1056 | ||
1057 | /* ata_pio_sectors() might change the state | |
1058 | * to HSM_ST_LAST. so, the state is changed here | |
1059 | * before ata_pio_sectors(). | |
1060 | */ | |
1061 | ap->hsm_task_state = HSM_ST; | |
1062 | ata_pio_sectors(qc); | |
1063 | } else | |
1064 | /* send CDB */ | |
1065 | atapi_send_cdb(ap, qc); | |
1066 | ||
c429137a | 1067 | /* if polling, ata_sff_pio_task() handles the rest. |
624d5c51 TH |
1068 | * otherwise, interrupt handler takes over from here. |
1069 | */ | |
1070 | break; | |
1071 | ||
1072 | case HSM_ST: | |
1073 | /* complete command or read/write the data register */ | |
1074 | if (qc->tf.protocol == ATAPI_PROT_PIO) { | |
1075 | /* ATAPI PIO protocol */ | |
1076 | if ((status & ATA_DRQ) == 0) { | |
1077 | /* No more data to transfer or device error. | |
1078 | * Device error will be tagged in HSM_ST_LAST. | |
1079 | */ | |
1080 | ap->hsm_task_state = HSM_ST_LAST; | |
1081 | goto fsm_start; | |
1082 | } | |
1083 | ||
1084 | /* Device should not ask for data transfer (DRQ=1) | |
1085 | * when it finds something wrong. | |
1086 | * We ignore DRQ here and stop the HSM by | |
1087 | * changing hsm_task_state to HSM_ST_ERR and | |
1088 | * let the EH abort the command or reset the device. | |
1089 | */ | |
1090 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
a836d3e8 TH |
1091 | ata_ehi_push_desc(ehi, "ST-ATAPI: " |
1092 | "DRQ=1 with device error, " | |
1093 | "dev_stat 0x%X", status); | |
624d5c51 TH |
1094 | qc->err_mask |= AC_ERR_HSM; |
1095 | ap->hsm_task_state = HSM_ST_ERR; | |
1096 | goto fsm_start; | |
1097 | } | |
1098 | ||
1099 | atapi_pio_bytes(qc); | |
1100 | ||
1101 | if (unlikely(ap->hsm_task_state == HSM_ST_ERR)) | |
1102 | /* bad ireason reported by device */ | |
1103 | goto fsm_start; | |
1104 | ||
1105 | } else { | |
1106 | /* ATA PIO protocol */ | |
1107 | if (unlikely((status & ATA_DRQ) == 0)) { | |
1108 | /* handle BSY=0, DRQ=0 as error */ | |
6a6b97d3 | 1109 | if (likely(status & (ATA_ERR | ATA_DF))) { |
624d5c51 TH |
1110 | /* device stops HSM for abort/error */ |
1111 | qc->err_mask |= AC_ERR_DEV; | |
6a6b97d3 TH |
1112 | |
1113 | /* If diagnostic failed and this is | |
1114 | * IDENTIFY, it's likely a phantom | |
1115 | * device. Mark hint. | |
1116 | */ | |
1117 | if (qc->dev->horkage & | |
1118 | ATA_HORKAGE_DIAGNOSTIC) | |
1119 | qc->err_mask |= | |
1120 | AC_ERR_NODEV_HINT; | |
1121 | } else { | |
624d5c51 TH |
1122 | /* HSM violation. Let EH handle this. |
1123 | * Phantom devices also trigger this | |
1124 | * condition. Mark hint. | |
1125 | */ | |
a836d3e8 | 1126 | ata_ehi_push_desc(ehi, "ST-ATA: " |
80ee6f54 | 1127 | "DRQ=0 without device error, " |
a836d3e8 | 1128 | "dev_stat 0x%X", status); |
624d5c51 TH |
1129 | qc->err_mask |= AC_ERR_HSM | |
1130 | AC_ERR_NODEV_HINT; | |
a836d3e8 | 1131 | } |
624d5c51 TH |
1132 | |
1133 | ap->hsm_task_state = HSM_ST_ERR; | |
1134 | goto fsm_start; | |
1135 | } | |
1136 | ||
1137 | /* For PIO reads, some devices may ask for | |
1138 | * data transfer (DRQ=1) alone with ERR=1. | |
1139 | * We respect DRQ here and transfer one | |
1140 | * block of junk data before changing the | |
1141 | * hsm_task_state to HSM_ST_ERR. | |
1142 | * | |
1143 | * For PIO writes, ERR=1 DRQ=1 doesn't make | |
1144 | * sense since the data block has been | |
1145 | * transferred to the device. | |
1146 | */ | |
1147 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
1148 | /* data might be corrputed */ | |
1149 | qc->err_mask |= AC_ERR_DEV; | |
1150 | ||
1151 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) { | |
1152 | ata_pio_sectors(qc); | |
1153 | status = ata_wait_idle(ap); | |
1154 | } | |
1155 | ||
a836d3e8 TH |
1156 | if (status & (ATA_BUSY | ATA_DRQ)) { |
1157 | ata_ehi_push_desc(ehi, "ST-ATA: " | |
1158 | "BUSY|DRQ persists on ERR|DF, " | |
1159 | "dev_stat 0x%X", status); | |
624d5c51 | 1160 | qc->err_mask |= AC_ERR_HSM; |
a836d3e8 | 1161 | } |
624d5c51 | 1162 | |
b919930c TH |
1163 | /* There are oddball controllers with |
1164 | * status register stuck at 0x7f and | |
1165 | * lbal/m/h at zero which makes it | |
1166 | * pass all other presence detection | |
1167 | * mechanisms we have. Set NODEV_HINT | |
1168 | * for it. Kernel bz#7241. | |
1169 | */ | |
1170 | if (status == 0x7f) | |
1171 | qc->err_mask |= AC_ERR_NODEV_HINT; | |
1172 | ||
624d5c51 TH |
1173 | /* ata_pio_sectors() might change the |
1174 | * state to HSM_ST_LAST. so, the state | |
1175 | * is changed after ata_pio_sectors(). | |
1176 | */ | |
1177 | ap->hsm_task_state = HSM_ST_ERR; | |
1178 | goto fsm_start; | |
1179 | } | |
1180 | ||
1181 | ata_pio_sectors(qc); | |
1182 | ||
1183 | if (ap->hsm_task_state == HSM_ST_LAST && | |
1184 | (!(qc->tf.flags & ATA_TFLAG_WRITE))) { | |
1185 | /* all data read */ | |
1186 | status = ata_wait_idle(ap); | |
1187 | goto fsm_start; | |
1188 | } | |
1189 | } | |
1190 | ||
1191 | poll_next = 1; | |
1192 | break; | |
1193 | ||
1194 | case HSM_ST_LAST: | |
1195 | if (unlikely(!ata_ok(status))) { | |
1196 | qc->err_mask |= __ac_err_mask(status); | |
1197 | ap->hsm_task_state = HSM_ST_ERR; | |
1198 | goto fsm_start; | |
1199 | } | |
1200 | ||
1201 | /* no more data to transfer */ | |
1202 | DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n", | |
1203 | ap->print_id, qc->dev->devno, status); | |
1204 | ||
efcb3cf7 | 1205 | WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM)); |
624d5c51 TH |
1206 | |
1207 | ap->hsm_task_state = HSM_ST_IDLE; | |
1208 | ||
1209 | /* complete taskfile transaction */ | |
1210 | ata_hsm_qc_complete(qc, in_wq); | |
1211 | ||
1212 | poll_next = 0; | |
1213 | break; | |
1214 | ||
1215 | case HSM_ST_ERR: | |
624d5c51 TH |
1216 | ap->hsm_task_state = HSM_ST_IDLE; |
1217 | ||
1218 | /* complete taskfile transaction */ | |
1219 | ata_hsm_qc_complete(qc, in_wq); | |
1220 | ||
1221 | poll_next = 0; | |
1222 | break; | |
1223 | default: | |
1224 | poll_next = 0; | |
a588afc9 TH |
1225 | WARN(true, "ata%d: SFF host state machine in invalid state %d", |
1226 | ap->print_id, ap->hsm_task_state); | |
624d5c51 TH |
1227 | } |
1228 | ||
1229 | return poll_next; | |
1230 | } | |
0fe40ff8 | 1231 | EXPORT_SYMBOL_GPL(ata_sff_hsm_move); |
624d5c51 | 1232 | |
64b97594 VK |
1233 | void ata_sff_queue_work(struct work_struct *work) |
1234 | { | |
1235 | queue_work(ata_sff_wq, work); | |
1236 | } | |
1237 | EXPORT_SYMBOL_GPL(ata_sff_queue_work); | |
1238 | ||
1239 | void ata_sff_queue_delayed_work(struct delayed_work *dwork, unsigned long delay) | |
1240 | { | |
1241 | queue_delayed_work(ata_sff_wq, dwork, delay); | |
1242 | } | |
1243 | EXPORT_SYMBOL_GPL(ata_sff_queue_delayed_work); | |
1244 | ||
ea3c6450 | 1245 | void ata_sff_queue_pio_task(struct ata_link *link, unsigned long delay) |
c429137a | 1246 | { |
ea3c6450 GG |
1247 | struct ata_port *ap = link->ap; |
1248 | ||
1249 | WARN_ON((ap->sff_pio_task_link != NULL) && | |
1250 | (ap->sff_pio_task_link != link)); | |
1251 | ap->sff_pio_task_link = link; | |
1252 | ||
c429137a | 1253 | /* may fail if ata_sff_flush_pio_task() in progress */ |
64b97594 | 1254 | ata_sff_queue_delayed_work(&ap->sff_pio_task, msecs_to_jiffies(delay)); |
c429137a TH |
1255 | } |
1256 | EXPORT_SYMBOL_GPL(ata_sff_queue_pio_task); | |
1257 | ||
1258 | void ata_sff_flush_pio_task(struct ata_port *ap) | |
1259 | { | |
1260 | DPRINTK("ENTER\n"); | |
1261 | ||
afe2c511 | 1262 | cancel_delayed_work_sync(&ap->sff_pio_task); |
ce751452 DJ |
1263 | |
1264 | /* | |
1265 | * We wanna reset the HSM state to IDLE. If we do so without | |
1266 | * grabbing the port lock, critical sections protected by it which | |
1267 | * expect the HSM state to stay stable may get surprised. For | |
1268 | * example, we may set IDLE in between the time | |
1269 | * __ata_sff_port_intr() checks for HSM_ST_IDLE and before it calls | |
1270 | * ata_sff_hsm_move() causing ata_sff_hsm_move() to BUG(). | |
1271 | */ | |
1272 | spin_lock_irq(ap->lock); | |
c429137a | 1273 | ap->hsm_task_state = HSM_ST_IDLE; |
ce751452 DJ |
1274 | spin_unlock_irq(ap->lock); |
1275 | ||
d4d8eaff | 1276 | ap->sff_pio_task_link = NULL; |
c429137a TH |
1277 | |
1278 | if (ata_msg_ctl(ap)) | |
a9a79dfe | 1279 | ata_port_dbg(ap, "%s: EXIT\n", __func__); |
c429137a TH |
1280 | } |
1281 | ||
1282 | static void ata_sff_pio_task(struct work_struct *work) | |
624d5c51 TH |
1283 | { |
1284 | struct ata_port *ap = | |
c429137a | 1285 | container_of(work, struct ata_port, sff_pio_task.work); |
ea3c6450 | 1286 | struct ata_link *link = ap->sff_pio_task_link; |
c429137a | 1287 | struct ata_queued_cmd *qc; |
624d5c51 TH |
1288 | u8 status; |
1289 | int poll_next; | |
1290 | ||
8eee1d3e TH |
1291 | spin_lock_irq(ap->lock); |
1292 | ||
4fca377f | 1293 | BUG_ON(ap->sff_pio_task_link == NULL); |
c429137a | 1294 | /* qc can be NULL if timeout occurred */ |
ea3c6450 GG |
1295 | qc = ata_qc_from_tag(ap, link->active_tag); |
1296 | if (!qc) { | |
1297 | ap->sff_pio_task_link = NULL; | |
8eee1d3e | 1298 | goto out_unlock; |
ea3c6450 | 1299 | } |
c429137a | 1300 | |
624d5c51 | 1301 | fsm_start: |
efcb3cf7 | 1302 | WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE); |
624d5c51 TH |
1303 | |
1304 | /* | |
1305 | * This is purely heuristic. This is a fast path. | |
1306 | * Sometimes when we enter, BSY will be cleared in | |
1307 | * a chk-status or two. If not, the drive is probably seeking | |
1308 | * or something. Snooze for a couple msecs, then | |
1309 | * chk-status again. If still busy, queue delayed work. | |
1310 | */ | |
9363c382 | 1311 | status = ata_sff_busy_wait(ap, ATA_BUSY, 5); |
624d5c51 | 1312 | if (status & ATA_BUSY) { |
8eee1d3e | 1313 | spin_unlock_irq(ap->lock); |
97750ceb | 1314 | ata_msleep(ap, 2); |
8eee1d3e TH |
1315 | spin_lock_irq(ap->lock); |
1316 | ||
9363c382 | 1317 | status = ata_sff_busy_wait(ap, ATA_BUSY, 10); |
624d5c51 | 1318 | if (status & ATA_BUSY) { |
ea3c6450 | 1319 | ata_sff_queue_pio_task(link, ATA_SHORT_PAUSE); |
8eee1d3e | 1320 | goto out_unlock; |
624d5c51 TH |
1321 | } |
1322 | } | |
1323 | ||
ea3c6450 GG |
1324 | /* |
1325 | * hsm_move() may trigger another command to be processed. | |
1326 | * clean the link beforehand. | |
1327 | */ | |
1328 | ap->sff_pio_task_link = NULL; | |
624d5c51 | 1329 | /* move the HSM */ |
9363c382 | 1330 | poll_next = ata_sff_hsm_move(ap, qc, status, 1); |
624d5c51 TH |
1331 | |
1332 | /* another command or interrupt handler | |
1333 | * may be running at this point. | |
1334 | */ | |
1335 | if (poll_next) | |
1336 | goto fsm_start; | |
8eee1d3e TH |
1337 | out_unlock: |
1338 | spin_unlock_irq(ap->lock); | |
624d5c51 TH |
1339 | } |
1340 | ||
1341 | /** | |
360ff783 | 1342 | * ata_sff_qc_issue - issue taskfile to a SFF controller |
624d5c51 TH |
1343 | * @qc: command to issue to device |
1344 | * | |
360ff783 TH |
1345 | * This function issues a PIO or NODATA command to a SFF |
1346 | * controller. | |
624d5c51 TH |
1347 | * |
1348 | * LOCKING: | |
1349 | * spin_lock_irqsave(host lock) | |
1350 | * | |
1351 | * RETURNS: | |
1352 | * Zero on success, AC_ERR_* mask on failure | |
1353 | */ | |
9363c382 | 1354 | unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc) |
624d5c51 TH |
1355 | { |
1356 | struct ata_port *ap = qc->ap; | |
ea3c6450 | 1357 | struct ata_link *link = qc->dev->link; |
624d5c51 TH |
1358 | |
1359 | /* Use polling pio if the LLD doesn't handle | |
1360 | * interrupt driven pio and atapi CDB interrupt. | |
1361 | */ | |
360ff783 TH |
1362 | if (ap->flags & ATA_FLAG_PIO_POLLING) |
1363 | qc->tf.flags |= ATA_TFLAG_POLLING; | |
624d5c51 TH |
1364 | |
1365 | /* select the device */ | |
1366 | ata_dev_select(ap, qc->dev->devno, 1, 0); | |
1367 | ||
1368 | /* start the command */ | |
1369 | switch (qc->tf.protocol) { | |
1370 | case ATA_PROT_NODATA: | |
1371 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1372 | ata_qc_set_polling(qc); | |
1373 | ||
1374 | ata_tf_to_host(ap, &qc->tf); | |
1375 | ap->hsm_task_state = HSM_ST_LAST; | |
1376 | ||
1377 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
ea3c6450 | 1378 | ata_sff_queue_pio_task(link, 0); |
624d5c51 TH |
1379 | |
1380 | break; | |
1381 | ||
624d5c51 TH |
1382 | case ATA_PROT_PIO: |
1383 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1384 | ata_qc_set_polling(qc); | |
1385 | ||
1386 | ata_tf_to_host(ap, &qc->tf); | |
1387 | ||
1388 | if (qc->tf.flags & ATA_TFLAG_WRITE) { | |
1389 | /* PIO data out protocol */ | |
1390 | ap->hsm_task_state = HSM_ST_FIRST; | |
ea3c6450 | 1391 | ata_sff_queue_pio_task(link, 0); |
624d5c51 | 1392 | |
c429137a TH |
1393 | /* always send first data block using the |
1394 | * ata_sff_pio_task() codepath. | |
624d5c51 TH |
1395 | */ |
1396 | } else { | |
1397 | /* PIO data in protocol */ | |
1398 | ap->hsm_task_state = HSM_ST; | |
1399 | ||
1400 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
ea3c6450 | 1401 | ata_sff_queue_pio_task(link, 0); |
624d5c51 | 1402 | |
c429137a TH |
1403 | /* if polling, ata_sff_pio_task() handles the |
1404 | * rest. otherwise, interrupt handler takes | |
1405 | * over from here. | |
624d5c51 TH |
1406 | */ |
1407 | } | |
1408 | ||
1409 | break; | |
1410 | ||
1411 | case ATAPI_PROT_PIO: | |
1412 | case ATAPI_PROT_NODATA: | |
1413 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1414 | ata_qc_set_polling(qc); | |
1415 | ||
1416 | ata_tf_to_host(ap, &qc->tf); | |
1417 | ||
1418 | ap->hsm_task_state = HSM_ST_FIRST; | |
1419 | ||
1420 | /* send cdb by polling if no cdb interrupt */ | |
1421 | if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) || | |
1422 | (qc->tf.flags & ATA_TFLAG_POLLING)) | |
ea3c6450 | 1423 | ata_sff_queue_pio_task(link, 0); |
624d5c51 TH |
1424 | break; |
1425 | ||
624d5c51 | 1426 | default: |
624d5c51 TH |
1427 | return AC_ERR_SYSTEM; |
1428 | } | |
1429 | ||
1430 | return 0; | |
1431 | } | |
0fe40ff8 | 1432 | EXPORT_SYMBOL_GPL(ata_sff_qc_issue); |
624d5c51 | 1433 | |
22183bf5 TH |
1434 | /** |
1435 | * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read | |
1436 | * @qc: qc to fill result TF for | |
1437 | * | |
1438 | * @qc is finished and result TF needs to be filled. Fill it | |
1439 | * using ->sff_tf_read. | |
1440 | * | |
1441 | * LOCKING: | |
1442 | * spin_lock_irqsave(host lock) | |
1443 | * | |
1444 | * RETURNS: | |
1445 | * true indicating that result TF is successfully filled. | |
1446 | */ | |
1447 | bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc) | |
1448 | { | |
1449 | qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf); | |
1450 | return true; | |
1451 | } | |
0fe40ff8 | 1452 | EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf); |
22183bf5 | 1453 | |
c3b28894 | 1454 | static unsigned int ata_sff_idle_irq(struct ata_port *ap) |
624d5c51 | 1455 | { |
c3b28894 TH |
1456 | ap->stats.idle_irq++; |
1457 | ||
1458 | #ifdef ATA_IRQ_TRAP | |
1459 | if ((ap->stats.idle_irq % 1000) == 0) { | |
1460 | ap->ops->sff_check_status(ap); | |
1461 | if (ap->ops->sff_irq_clear) | |
1462 | ap->ops->sff_irq_clear(ap); | |
a9a79dfe | 1463 | ata_port_warn(ap, "irq trap\n"); |
c3b28894 TH |
1464 | return 1; |
1465 | } | |
1466 | #endif | |
1467 | return 0; /* irq not handled */ | |
1468 | } | |
1469 | ||
1470 | static unsigned int __ata_sff_port_intr(struct ata_port *ap, | |
1471 | struct ata_queued_cmd *qc, | |
1472 | bool hsmv_on_idle) | |
1473 | { | |
1474 | u8 status; | |
624d5c51 TH |
1475 | |
1476 | VPRINTK("ata%u: protocol %d task_state %d\n", | |
1477 | ap->print_id, qc->tf.protocol, ap->hsm_task_state); | |
1478 | ||
1479 | /* Check whether we are expecting interrupt in this state */ | |
1480 | switch (ap->hsm_task_state) { | |
1481 | case HSM_ST_FIRST: | |
1482 | /* Some pre-ATAPI-4 devices assert INTRQ | |
1483 | * at this state when ready to receive CDB. | |
1484 | */ | |
1485 | ||
1486 | /* Check the ATA_DFLAG_CDB_INTR flag is enough here. | |
1487 | * The flag was turned on only for atapi devices. No | |
1488 | * need to check ata_is_atapi(qc->tf.protocol) again. | |
1489 | */ | |
1490 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
c3b28894 | 1491 | return ata_sff_idle_irq(ap); |
624d5c51 | 1492 | break; |
687a9933 | 1493 | case HSM_ST_IDLE: |
c3b28894 | 1494 | return ata_sff_idle_irq(ap); |
687a9933 TH |
1495 | default: |
1496 | break; | |
624d5c51 TH |
1497 | } |
1498 | ||
a57c1bad AC |
1499 | /* check main status, clearing INTRQ if needed */ |
1500 | status = ata_sff_irq_status(ap); | |
332ac7ff | 1501 | if (status & ATA_BUSY) { |
c3b28894 | 1502 | if (hsmv_on_idle) { |
332ac7ff TH |
1503 | /* BMDMA engine is already stopped, we're screwed */ |
1504 | qc->err_mask |= AC_ERR_HSM; | |
1505 | ap->hsm_task_state = HSM_ST_ERR; | |
1506 | } else | |
c3b28894 | 1507 | return ata_sff_idle_irq(ap); |
332ac7ff | 1508 | } |
624d5c51 | 1509 | |
9f2f7210 | 1510 | /* clear irq events */ |
37f65b8b TH |
1511 | if (ap->ops->sff_irq_clear) |
1512 | ap->ops->sff_irq_clear(ap); | |
624d5c51 | 1513 | |
9363c382 | 1514 | ata_sff_hsm_move(ap, qc, status, 0); |
624d5c51 | 1515 | |
624d5c51 | 1516 | return 1; /* irq handled */ |
624d5c51 TH |
1517 | } |
1518 | ||
1519 | /** | |
c3b28894 TH |
1520 | * ata_sff_port_intr - Handle SFF port interrupt |
1521 | * @ap: Port on which interrupt arrived (possibly...) | |
1522 | * @qc: Taskfile currently active in engine | |
624d5c51 | 1523 | * |
c3b28894 | 1524 | * Handle port interrupt for given queued command. |
624d5c51 TH |
1525 | * |
1526 | * LOCKING: | |
c3b28894 | 1527 | * spin_lock_irqsave(host lock) |
624d5c51 TH |
1528 | * |
1529 | * RETURNS: | |
c3b28894 | 1530 | * One if interrupt was handled, zero if not (shared irq). |
624d5c51 | 1531 | */ |
c3b28894 TH |
1532 | unsigned int ata_sff_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc) |
1533 | { | |
1534 | return __ata_sff_port_intr(ap, qc, false); | |
1535 | } | |
1536 | EXPORT_SYMBOL_GPL(ata_sff_port_intr); | |
1537 | ||
1538 | static inline irqreturn_t __ata_sff_interrupt(int irq, void *dev_instance, | |
1539 | unsigned int (*port_intr)(struct ata_port *, struct ata_queued_cmd *)) | |
624d5c51 TH |
1540 | { |
1541 | struct ata_host *host = dev_instance; | |
332ac7ff | 1542 | bool retried = false; |
624d5c51 | 1543 | unsigned int i; |
332ac7ff | 1544 | unsigned int handled, idle, polling; |
624d5c51 TH |
1545 | unsigned long flags; |
1546 | ||
1547 | /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */ | |
1548 | spin_lock_irqsave(&host->lock, flags); | |
1549 | ||
332ac7ff TH |
1550 | retry: |
1551 | handled = idle = polling = 0; | |
624d5c51 | 1552 | for (i = 0; i < host->n_ports; i++) { |
d88ec2e5 TH |
1553 | struct ata_port *ap = host->ports[i]; |
1554 | struct ata_queued_cmd *qc; | |
624d5c51 | 1555 | |
d88ec2e5 | 1556 | qc = ata_qc_from_tag(ap, ap->link.active_tag); |
27943620 TH |
1557 | if (qc) { |
1558 | if (!(qc->tf.flags & ATA_TFLAG_POLLING)) | |
c3b28894 | 1559 | handled |= port_intr(ap, qc); |
27943620 TH |
1560 | else |
1561 | polling |= 1 << i; | |
332ac7ff TH |
1562 | } else |
1563 | idle |= 1 << i; | |
27943620 TH |
1564 | } |
1565 | ||
1566 | /* | |
1567 | * If no port was expecting IRQ but the controller is actually | |
1568 | * asserting IRQ line, nobody cared will ensue. Check IRQ | |
1569 | * pending status if available and clear spurious IRQ. | |
1570 | */ | |
332ac7ff TH |
1571 | if (!handled && !retried) { |
1572 | bool retry = false; | |
1573 | ||
27943620 TH |
1574 | for (i = 0; i < host->n_ports; i++) { |
1575 | struct ata_port *ap = host->ports[i]; | |
1576 | ||
1577 | if (polling & (1 << i)) | |
1578 | continue; | |
1579 | ||
1580 | if (!ap->ops->sff_irq_check || | |
1581 | !ap->ops->sff_irq_check(ap)) | |
1582 | continue; | |
1583 | ||
332ac7ff TH |
1584 | if (idle & (1 << i)) { |
1585 | ap->ops->sff_check_status(ap); | |
37f65b8b TH |
1586 | if (ap->ops->sff_irq_clear) |
1587 | ap->ops->sff_irq_clear(ap); | |
332ac7ff TH |
1588 | } else { |
1589 | /* clear INTRQ and check if BUSY cleared */ | |
1590 | if (!(ap->ops->sff_check_status(ap) & ATA_BUSY)) | |
1591 | retry |= true; | |
1592 | /* | |
1593 | * With command in flight, we can't do | |
1594 | * sff_irq_clear() w/o racing with completion. | |
1595 | */ | |
1596 | } | |
1597 | } | |
1598 | ||
1599 | if (retry) { | |
1600 | retried = true; | |
1601 | goto retry; | |
27943620 | 1602 | } |
624d5c51 TH |
1603 | } |
1604 | ||
1605 | spin_unlock_irqrestore(&host->lock, flags); | |
1606 | ||
1607 | return IRQ_RETVAL(handled); | |
1608 | } | |
c3b28894 TH |
1609 | |
1610 | /** | |
1611 | * ata_sff_interrupt - Default SFF ATA host interrupt handler | |
1612 | * @irq: irq line (unused) | |
1613 | * @dev_instance: pointer to our ata_host information structure | |
1614 | * | |
1615 | * Default interrupt handler for PCI IDE devices. Calls | |
1616 | * ata_sff_port_intr() for each port that is not disabled. | |
1617 | * | |
1618 | * LOCKING: | |
1619 | * Obtains host lock during operation. | |
1620 | * | |
1621 | * RETURNS: | |
1622 | * IRQ_NONE or IRQ_HANDLED. | |
1623 | */ | |
1624 | irqreturn_t ata_sff_interrupt(int irq, void *dev_instance) | |
1625 | { | |
1626 | return __ata_sff_interrupt(irq, dev_instance, ata_sff_port_intr); | |
1627 | } | |
0fe40ff8 | 1628 | EXPORT_SYMBOL_GPL(ata_sff_interrupt); |
624d5c51 | 1629 | |
c96f1732 AC |
1630 | /** |
1631 | * ata_sff_lost_interrupt - Check for an apparent lost interrupt | |
1632 | * @ap: port that appears to have timed out | |
1633 | * | |
1634 | * Called from the libata error handlers when the core code suspects | |
1635 | * an interrupt has been lost. If it has complete anything we can and | |
1636 | * then return. Interface must support altstatus for this faster | |
1637 | * recovery to occur. | |
1638 | * | |
1639 | * Locking: | |
1640 | * Caller holds host lock | |
1641 | */ | |
1642 | ||
1643 | void ata_sff_lost_interrupt(struct ata_port *ap) | |
1644 | { | |
1645 | u8 status; | |
1646 | struct ata_queued_cmd *qc; | |
1647 | ||
1648 | /* Only one outstanding command per SFF channel */ | |
1649 | qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
3e4ec344 TH |
1650 | /* We cannot lose an interrupt on a non-existent or polled command */ |
1651 | if (!qc || qc->tf.flags & ATA_TFLAG_POLLING) | |
c96f1732 AC |
1652 | return; |
1653 | /* See if the controller thinks it is still busy - if so the command | |
1654 | isn't a lost IRQ but is still in progress */ | |
1655 | status = ata_sff_altstatus(ap); | |
1656 | if (status & ATA_BUSY) | |
1657 | return; | |
1658 | ||
1659 | /* There was a command running, we are no longer busy and we have | |
1660 | no interrupt. */ | |
a9a79dfe | 1661 | ata_port_warn(ap, "lost interrupt (Status 0x%x)\n", |
c96f1732 AC |
1662 | status); |
1663 | /* Run the host interrupt logic as if the interrupt had not been | |
1664 | lost */ | |
c3b28894 | 1665 | ata_sff_port_intr(ap, qc); |
c96f1732 AC |
1666 | } |
1667 | EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt); | |
1668 | ||
624d5c51 | 1669 | /** |
9363c382 | 1670 | * ata_sff_freeze - Freeze SFF controller port |
624d5c51 TH |
1671 | * @ap: port to freeze |
1672 | * | |
9f2f7210 | 1673 | * Freeze SFF controller port. |
624d5c51 TH |
1674 | * |
1675 | * LOCKING: | |
1676 | * Inherited from caller. | |
1677 | */ | |
9363c382 | 1678 | void ata_sff_freeze(struct ata_port *ap) |
624d5c51 | 1679 | { |
624d5c51 TH |
1680 | ap->ctl |= ATA_NIEN; |
1681 | ap->last_ctl = ap->ctl; | |
1682 | ||
41dec29b SS |
1683 | if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) |
1684 | ata_sff_set_devctl(ap, ap->ctl); | |
624d5c51 TH |
1685 | |
1686 | /* Under certain circumstances, some controllers raise IRQ on | |
1687 | * ATA_NIEN manipulation. Also, many controllers fail to mask | |
1688 | * previously pending IRQ on ATA_NIEN assertion. Clear it. | |
1689 | */ | |
5682ed33 | 1690 | ap->ops->sff_check_status(ap); |
624d5c51 | 1691 | |
37f65b8b TH |
1692 | if (ap->ops->sff_irq_clear) |
1693 | ap->ops->sff_irq_clear(ap); | |
624d5c51 | 1694 | } |
0fe40ff8 | 1695 | EXPORT_SYMBOL_GPL(ata_sff_freeze); |
624d5c51 TH |
1696 | |
1697 | /** | |
9363c382 | 1698 | * ata_sff_thaw - Thaw SFF controller port |
624d5c51 TH |
1699 | * @ap: port to thaw |
1700 | * | |
9363c382 | 1701 | * Thaw SFF controller port. |
624d5c51 TH |
1702 | * |
1703 | * LOCKING: | |
1704 | * Inherited from caller. | |
1705 | */ | |
9363c382 | 1706 | void ata_sff_thaw(struct ata_port *ap) |
272f7884 | 1707 | { |
624d5c51 | 1708 | /* clear & re-enable interrupts */ |
5682ed33 | 1709 | ap->ops->sff_check_status(ap); |
37f65b8b TH |
1710 | if (ap->ops->sff_irq_clear) |
1711 | ap->ops->sff_irq_clear(ap); | |
e42a542b | 1712 | ata_sff_irq_on(ap); |
272f7884 | 1713 | } |
0fe40ff8 | 1714 | EXPORT_SYMBOL_GPL(ata_sff_thaw); |
272f7884 | 1715 | |
0aa1113d TH |
1716 | /** |
1717 | * ata_sff_prereset - prepare SFF link for reset | |
1718 | * @link: SFF link to be reset | |
1719 | * @deadline: deadline jiffies for the operation | |
1720 | * | |
1721 | * SFF link @link is about to be reset. Initialize it. It first | |
1722 | * calls ata_std_prereset() and wait for !BSY if the port is | |
1723 | * being softreset. | |
1724 | * | |
1725 | * LOCKING: | |
1726 | * Kernel thread context (may sleep) | |
1727 | * | |
1728 | * RETURNS: | |
1729 | * 0 on success, -errno otherwise. | |
1730 | */ | |
1731 | int ata_sff_prereset(struct ata_link *link, unsigned long deadline) | |
1732 | { | |
0aa1113d TH |
1733 | struct ata_eh_context *ehc = &link->eh_context; |
1734 | int rc; | |
1735 | ||
1736 | rc = ata_std_prereset(link, deadline); | |
1737 | if (rc) | |
1738 | return rc; | |
1739 | ||
1740 | /* if we're about to do hardreset, nothing more to do */ | |
1741 | if (ehc->i.action & ATA_EH_HARDRESET) | |
1742 | return 0; | |
1743 | ||
1744 | /* wait for !BSY if we don't know that no device is attached */ | |
1745 | if (!ata_link_offline(link)) { | |
705e76be | 1746 | rc = ata_sff_wait_ready(link, deadline); |
0aa1113d | 1747 | if (rc && rc != -ENODEV) { |
a9a79dfe JP |
1748 | ata_link_warn(link, |
1749 | "device not ready (errno=%d), forcing hardreset\n", | |
1750 | rc); | |
0aa1113d TH |
1751 | ehc->i.action |= ATA_EH_HARDRESET; |
1752 | } | |
1753 | } | |
1754 | ||
1755 | return 0; | |
1756 | } | |
0fe40ff8 | 1757 | EXPORT_SYMBOL_GPL(ata_sff_prereset); |
0aa1113d | 1758 | |
90088bb4 | 1759 | /** |
624d5c51 TH |
1760 | * ata_devchk - PATA device presence detection |
1761 | * @ap: ATA channel to examine | |
1762 | * @device: Device to examine (starting at zero) | |
90088bb4 | 1763 | * |
624d5c51 TH |
1764 | * This technique was originally described in |
1765 | * Hale Landis's ATADRVR (www.ata-atapi.com), and | |
1766 | * later found its way into the ATA/ATAPI spec. | |
1767 | * | |
1768 | * Write a pattern to the ATA shadow registers, | |
1769 | * and if a device is present, it will respond by | |
1770 | * correctly storing and echoing back the | |
1771 | * ATA shadow register contents. | |
90088bb4 TH |
1772 | * |
1773 | * LOCKING: | |
624d5c51 | 1774 | * caller. |
90088bb4 | 1775 | */ |
624d5c51 | 1776 | static unsigned int ata_devchk(struct ata_port *ap, unsigned int device) |
90088bb4 TH |
1777 | { |
1778 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
624d5c51 | 1779 | u8 nsect, lbal; |
90088bb4 | 1780 | |
5682ed33 | 1781 | ap->ops->sff_dev_select(ap, device); |
90088bb4 | 1782 | |
624d5c51 TH |
1783 | iowrite8(0x55, ioaddr->nsect_addr); |
1784 | iowrite8(0xaa, ioaddr->lbal_addr); | |
90088bb4 | 1785 | |
624d5c51 TH |
1786 | iowrite8(0xaa, ioaddr->nsect_addr); |
1787 | iowrite8(0x55, ioaddr->lbal_addr); | |
90088bb4 | 1788 | |
624d5c51 TH |
1789 | iowrite8(0x55, ioaddr->nsect_addr); |
1790 | iowrite8(0xaa, ioaddr->lbal_addr); | |
1791 | ||
1792 | nsect = ioread8(ioaddr->nsect_addr); | |
1793 | lbal = ioread8(ioaddr->lbal_addr); | |
1794 | ||
1795 | if ((nsect == 0x55) && (lbal == 0xaa)) | |
1796 | return 1; /* we found a device */ | |
1797 | ||
1798 | return 0; /* nothing found */ | |
90088bb4 TH |
1799 | } |
1800 | ||
272f7884 | 1801 | /** |
9363c382 | 1802 | * ata_sff_dev_classify - Parse returned ATA device signature |
624d5c51 TH |
1803 | * @dev: ATA device to classify (starting at zero) |
1804 | * @present: device seems present | |
1805 | * @r_err: Value of error register on completion | |
272f7884 | 1806 | * |
624d5c51 TH |
1807 | * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs, |
1808 | * an ATA/ATAPI-defined set of values is placed in the ATA | |
1809 | * shadow registers, indicating the results of device detection | |
1810 | * and diagnostics. | |
272f7884 | 1811 | * |
624d5c51 TH |
1812 | * Select the ATA device, and read the values from the ATA shadow |
1813 | * registers. Then parse according to the Error register value, | |
1814 | * and the spec-defined values examined by ata_dev_classify(). | |
272f7884 TH |
1815 | * |
1816 | * LOCKING: | |
624d5c51 TH |
1817 | * caller. |
1818 | * | |
1819 | * RETURNS: | |
1820 | * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE. | |
272f7884 | 1821 | */ |
9363c382 | 1822 | unsigned int ata_sff_dev_classify(struct ata_device *dev, int present, |
624d5c51 | 1823 | u8 *r_err) |
272f7884 | 1824 | { |
624d5c51 TH |
1825 | struct ata_port *ap = dev->link->ap; |
1826 | struct ata_taskfile tf; | |
1827 | unsigned int class; | |
1828 | u8 err; | |
1829 | ||
5682ed33 | 1830 | ap->ops->sff_dev_select(ap, dev->devno); |
624d5c51 TH |
1831 | |
1832 | memset(&tf, 0, sizeof(tf)); | |
1833 | ||
5682ed33 | 1834 | ap->ops->sff_tf_read(ap, &tf); |
624d5c51 TH |
1835 | err = tf.feature; |
1836 | if (r_err) | |
1837 | *r_err = err; | |
1838 | ||
1839 | /* see if device passed diags: continue and warn later */ | |
1840 | if (err == 0) | |
1841 | /* diagnostic fail : do nothing _YET_ */ | |
1842 | dev->horkage |= ATA_HORKAGE_DIAGNOSTIC; | |
1843 | else if (err == 1) | |
1844 | /* do nothing */ ; | |
1845 | else if ((dev->devno == 0) && (err == 0x81)) | |
1846 | /* do nothing */ ; | |
1847 | else | |
1848 | return ATA_DEV_NONE; | |
272f7884 | 1849 | |
624d5c51 TH |
1850 | /* determine if device is ATA or ATAPI */ |
1851 | class = ata_dev_classify(&tf); | |
272f7884 | 1852 | |
624d5c51 TH |
1853 | if (class == ATA_DEV_UNKNOWN) { |
1854 | /* If the device failed diagnostic, it's likely to | |
1855 | * have reported incorrect device signature too. | |
1856 | * Assume ATA device if the device seems present but | |
1857 | * device signature is invalid with diagnostic | |
1858 | * failure. | |
1859 | */ | |
1860 | if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC)) | |
1861 | class = ATA_DEV_ATA; | |
1862 | else | |
1863 | class = ATA_DEV_NONE; | |
5682ed33 TH |
1864 | } else if ((class == ATA_DEV_ATA) && |
1865 | (ap->ops->sff_check_status(ap) == 0)) | |
624d5c51 TH |
1866 | class = ATA_DEV_NONE; |
1867 | ||
1868 | return class; | |
272f7884 | 1869 | } |
0fe40ff8 | 1870 | EXPORT_SYMBOL_GPL(ata_sff_dev_classify); |
272f7884 | 1871 | |
705e76be TH |
1872 | /** |
1873 | * ata_sff_wait_after_reset - wait for devices to become ready after reset | |
1874 | * @link: SFF link which is just reset | |
1875 | * @devmask: mask of present devices | |
1876 | * @deadline: deadline jiffies for the operation | |
1877 | * | |
1878 | * Wait devices attached to SFF @link to become ready after | |
1879 | * reset. It contains preceding 150ms wait to avoid accessing TF | |
1880 | * status register too early. | |
1881 | * | |
1882 | * LOCKING: | |
1883 | * Kernel thread context (may sleep). | |
1884 | * | |
1885 | * RETURNS: | |
1886 | * 0 on success, -ENODEV if some or all of devices in @devmask | |
1887 | * don't seem to exist. -errno on other errors. | |
1888 | */ | |
1889 | int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask, | |
1890 | unsigned long deadline) | |
1fdffbce | 1891 | { |
705e76be | 1892 | struct ata_port *ap = link->ap; |
1fdffbce | 1893 | struct ata_ioports *ioaddr = &ap->ioaddr; |
624d5c51 TH |
1894 | unsigned int dev0 = devmask & (1 << 0); |
1895 | unsigned int dev1 = devmask & (1 << 1); | |
1896 | int rc, ret = 0; | |
1fdffbce | 1897 | |
97750ceb | 1898 | ata_msleep(ap, ATA_WAIT_AFTER_RESET); |
705e76be TH |
1899 | |
1900 | /* always check readiness of the master device */ | |
1901 | rc = ata_sff_wait_ready(link, deadline); | |
1902 | /* -ENODEV means the odd clown forgot the D7 pulldown resistor | |
1903 | * and TF status is 0xff, bail out on it too. | |
624d5c51 | 1904 | */ |
705e76be TH |
1905 | if (rc) |
1906 | return rc; | |
1fdffbce | 1907 | |
624d5c51 TH |
1908 | /* if device 1 was found in ata_devchk, wait for register |
1909 | * access briefly, then wait for BSY to clear. | |
1910 | */ | |
1911 | if (dev1) { | |
1912 | int i; | |
1fdffbce | 1913 | |
5682ed33 | 1914 | ap->ops->sff_dev_select(ap, 1); |
1fdffbce | 1915 | |
624d5c51 TH |
1916 | /* Wait for register access. Some ATAPI devices fail |
1917 | * to set nsect/lbal after reset, so don't waste too | |
1918 | * much time on it. We're gonna wait for !BSY anyway. | |
1919 | */ | |
1920 | for (i = 0; i < 2; i++) { | |
1921 | u8 nsect, lbal; | |
1922 | ||
1923 | nsect = ioread8(ioaddr->nsect_addr); | |
1924 | lbal = ioread8(ioaddr->lbal_addr); | |
1925 | if ((nsect == 1) && (lbal == 1)) | |
1926 | break; | |
97750ceb | 1927 | ata_msleep(ap, 50); /* give drive a breather */ |
624d5c51 TH |
1928 | } |
1929 | ||
705e76be | 1930 | rc = ata_sff_wait_ready(link, deadline); |
624d5c51 TH |
1931 | if (rc) { |
1932 | if (rc != -ENODEV) | |
1933 | return rc; | |
1934 | ret = rc; | |
1935 | } | |
1fdffbce JG |
1936 | } |
1937 | ||
624d5c51 | 1938 | /* is all this really necessary? */ |
5682ed33 | 1939 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 | 1940 | if (dev1) |
5682ed33 | 1941 | ap->ops->sff_dev_select(ap, 1); |
624d5c51 | 1942 | if (dev0) |
5682ed33 | 1943 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
1944 | |
1945 | return ret; | |
1fdffbce | 1946 | } |
0fe40ff8 | 1947 | EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset); |
1fdffbce | 1948 | |
624d5c51 TH |
1949 | static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask, |
1950 | unsigned long deadline) | |
2cc432ee | 1951 | { |
624d5c51 | 1952 | struct ata_ioports *ioaddr = &ap->ioaddr; |
2cc432ee | 1953 | |
624d5c51 TH |
1954 | DPRINTK("ata%u: bus reset via SRST\n", ap->print_id); |
1955 | ||
6d8ca28f OZ |
1956 | if (ap->ioaddr.ctl_addr) { |
1957 | /* software reset. causes dev0 to be selected */ | |
1958 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
1959 | udelay(20); /* FIXME: flush */ | |
1960 | iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr); | |
1961 | udelay(20); /* FIXME: flush */ | |
1962 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
1963 | ap->last_ctl = ap->ctl; | |
1964 | } | |
624d5c51 | 1965 | |
705e76be TH |
1966 | /* wait the port to become ready */ |
1967 | return ata_sff_wait_after_reset(&ap->link, devmask, deadline); | |
2cc432ee JG |
1968 | } |
1969 | ||
6d97dbd7 | 1970 | /** |
9363c382 | 1971 | * ata_sff_softreset - reset host port via ATA SRST |
624d5c51 TH |
1972 | * @link: ATA link to reset |
1973 | * @classes: resulting classes of attached devices | |
1974 | * @deadline: deadline jiffies for the operation | |
6d97dbd7 | 1975 | * |
624d5c51 | 1976 | * Reset host port using ATA SRST. |
6d97dbd7 TH |
1977 | * |
1978 | * LOCKING: | |
624d5c51 TH |
1979 | * Kernel thread context (may sleep) |
1980 | * | |
1981 | * RETURNS: | |
1982 | * 0 on success, -errno otherwise. | |
6d97dbd7 | 1983 | */ |
9363c382 | 1984 | int ata_sff_softreset(struct ata_link *link, unsigned int *classes, |
624d5c51 | 1985 | unsigned long deadline) |
6d97dbd7 | 1986 | { |
624d5c51 TH |
1987 | struct ata_port *ap = link->ap; |
1988 | unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; | |
1989 | unsigned int devmask = 0; | |
1990 | int rc; | |
1991 | u8 err; | |
6d97dbd7 | 1992 | |
624d5c51 | 1993 | DPRINTK("ENTER\n"); |
6d97dbd7 | 1994 | |
624d5c51 TH |
1995 | /* determine if device 0/1 are present */ |
1996 | if (ata_devchk(ap, 0)) | |
1997 | devmask |= (1 << 0); | |
1998 | if (slave_possible && ata_devchk(ap, 1)) | |
1999 | devmask |= (1 << 1); | |
2000 | ||
2001 | /* select device 0 again */ | |
5682ed33 | 2002 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
2003 | |
2004 | /* issue bus reset */ | |
2005 | DPRINTK("about to softreset, devmask=%x\n", devmask); | |
2006 | rc = ata_bus_softreset(ap, devmask, deadline); | |
2007 | /* if link is occupied, -ENODEV too is an error */ | |
2008 | if (rc && (rc != -ENODEV || sata_scr_valid(link))) { | |
a9a79dfe | 2009 | ata_link_err(link, "SRST failed (errno=%d)\n", rc); |
624d5c51 TH |
2010 | return rc; |
2011 | } | |
0f0a3ad3 | 2012 | |
624d5c51 | 2013 | /* determine by signature whether we have ATA or ATAPI devices */ |
9363c382 | 2014 | classes[0] = ata_sff_dev_classify(&link->device[0], |
624d5c51 TH |
2015 | devmask & (1 << 0), &err); |
2016 | if (slave_possible && err != 0x81) | |
9363c382 | 2017 | classes[1] = ata_sff_dev_classify(&link->device[1], |
624d5c51 TH |
2018 | devmask & (1 << 1), &err); |
2019 | ||
624d5c51 TH |
2020 | DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]); |
2021 | return 0; | |
6d97dbd7 | 2022 | } |
0fe40ff8 | 2023 | EXPORT_SYMBOL_GPL(ata_sff_softreset); |
6d97dbd7 TH |
2024 | |
2025 | /** | |
9363c382 | 2026 | * sata_sff_hardreset - reset host port via SATA phy reset |
624d5c51 TH |
2027 | * @link: link to reset |
2028 | * @class: resulting class of attached device | |
2029 | * @deadline: deadline jiffies for the operation | |
6d97dbd7 | 2030 | * |
624d5c51 TH |
2031 | * SATA phy-reset host port using DET bits of SControl register, |
2032 | * wait for !BSY and classify the attached device. | |
6d97dbd7 TH |
2033 | * |
2034 | * LOCKING: | |
624d5c51 TH |
2035 | * Kernel thread context (may sleep) |
2036 | * | |
2037 | * RETURNS: | |
2038 | * 0 on success, -errno otherwise. | |
6d97dbd7 | 2039 | */ |
9363c382 | 2040 | int sata_sff_hardreset(struct ata_link *link, unsigned int *class, |
624d5c51 | 2041 | unsigned long deadline) |
6d97dbd7 | 2042 | { |
9dadd45b TH |
2043 | struct ata_eh_context *ehc = &link->eh_context; |
2044 | const unsigned long *timing = sata_ehc_deb_timing(ehc); | |
2045 | bool online; | |
624d5c51 TH |
2046 | int rc; |
2047 | ||
9dadd45b TH |
2048 | rc = sata_link_hardreset(link, timing, deadline, &online, |
2049 | ata_sff_check_ready); | |
9dadd45b TH |
2050 | if (online) |
2051 | *class = ata_sff_dev_classify(link->device, 1, NULL); | |
624d5c51 TH |
2052 | |
2053 | DPRINTK("EXIT, class=%u\n", *class); | |
9dadd45b | 2054 | return rc; |
6d97dbd7 | 2055 | } |
0fe40ff8 | 2056 | EXPORT_SYMBOL_GPL(sata_sff_hardreset); |
6d97dbd7 | 2057 | |
203c75b8 TH |
2058 | /** |
2059 | * ata_sff_postreset - SFF postreset callback | |
2060 | * @link: the target SFF ata_link | |
2061 | * @classes: classes of attached devices | |
2062 | * | |
2063 | * This function is invoked after a successful reset. It first | |
2064 | * calls ata_std_postreset() and performs SFF specific postreset | |
2065 | * processing. | |
2066 | * | |
2067 | * LOCKING: | |
2068 | * Kernel thread context (may sleep) | |
2069 | */ | |
2070 | void ata_sff_postreset(struct ata_link *link, unsigned int *classes) | |
2071 | { | |
2072 | struct ata_port *ap = link->ap; | |
2073 | ||
2074 | ata_std_postreset(link, classes); | |
2075 | ||
2076 | /* is double-select really necessary? */ | |
2077 | if (classes[0] != ATA_DEV_NONE) | |
2078 | ap->ops->sff_dev_select(ap, 1); | |
2079 | if (classes[1] != ATA_DEV_NONE) | |
2080 | ap->ops->sff_dev_select(ap, 0); | |
2081 | ||
2082 | /* bail out if no device is present */ | |
2083 | if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) { | |
2084 | DPRINTK("EXIT, no device\n"); | |
2085 | return; | |
2086 | } | |
2087 | ||
2088 | /* set up device control */ | |
41dec29b SS |
2089 | if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) { |
2090 | ata_sff_set_devctl(ap, ap->ctl); | |
e3e4385f SM |
2091 | ap->last_ctl = ap->ctl; |
2092 | } | |
203c75b8 | 2093 | } |
0fe40ff8 | 2094 | EXPORT_SYMBOL_GPL(ata_sff_postreset); |
203c75b8 | 2095 | |
3d47aa8e AC |
2096 | /** |
2097 | * ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers | |
2098 | * @qc: command | |
2099 | * | |
2100 | * Drain the FIFO and device of any stuck data following a command | |
3ad2f3fb | 2101 | * failing to complete. In some cases this is necessary before a |
3d47aa8e AC |
2102 | * reset will recover the device. |
2103 | * | |
2104 | */ | |
2105 | ||
2106 | void ata_sff_drain_fifo(struct ata_queued_cmd *qc) | |
2107 | { | |
2108 | int count; | |
2109 | struct ata_port *ap; | |
2110 | ||
2111 | /* We only need to flush incoming data when a command was running */ | |
2112 | if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE) | |
2113 | return; | |
2114 | ||
2115 | ap = qc->ap; | |
2116 | /* Drain up to 64K of data before we give up this recovery method */ | |
2117 | for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) | |
9a8fd68b | 2118 | && count < 65536; count += 2) |
3d47aa8e AC |
2119 | ioread16(ap->ioaddr.data_addr); |
2120 | ||
2121 | /* Can become DEBUG later */ | |
2122 | if (count) | |
a9a79dfe | 2123 | ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count); |
3d47aa8e AC |
2124 | |
2125 | } | |
2126 | EXPORT_SYMBOL_GPL(ata_sff_drain_fifo); | |
2127 | ||
6d97dbd7 | 2128 | /** |
fe06e5f9 | 2129 | * ata_sff_error_handler - Stock error handler for SFF controller |
6d97dbd7 | 2130 | * @ap: port to handle error for |
6d97dbd7 | 2131 | * |
9363c382 | 2132 | * Stock error handler for SFF controller. It can handle both |
6d97dbd7 TH |
2133 | * PATA and SATA controllers. Many controllers should be able to |
2134 | * use this EH as-is or with some added handling before and | |
2135 | * after. | |
2136 | * | |
6d97dbd7 TH |
2137 | * LOCKING: |
2138 | * Kernel thread context (may sleep) | |
2139 | */ | |
9363c382 | 2140 | void ata_sff_error_handler(struct ata_port *ap) |
6d97dbd7 | 2141 | { |
a1efdaba TH |
2142 | ata_reset_fn_t softreset = ap->ops->softreset; |
2143 | ata_reset_fn_t hardreset = ap->ops->hardreset; | |
6d97dbd7 TH |
2144 | struct ata_queued_cmd *qc; |
2145 | unsigned long flags; | |
6d97dbd7 | 2146 | |
9af5c9c9 | 2147 | qc = __ata_qc_from_tag(ap, ap->link.active_tag); |
6d97dbd7 TH |
2148 | if (qc && !(qc->flags & ATA_QCFLAG_FAILED)) |
2149 | qc = NULL; | |
2150 | ||
ba6a1308 | 2151 | spin_lock_irqsave(ap->lock, flags); |
6d97dbd7 | 2152 | |
fe06e5f9 TH |
2153 | /* |
2154 | * We *MUST* do FIFO draining before we issue a reset as | |
2155 | * several devices helpfully clear their internal state and | |
2156 | * will lock solid if we touch the data port post reset. Pass | |
2157 | * qc in case anyone wants to do different PIO/DMA recovery or | |
2158 | * has per command fixups | |
3d47aa8e | 2159 | */ |
8244cd05 TH |
2160 | if (ap->ops->sff_drain_fifo) |
2161 | ap->ops->sff_drain_fifo(qc); | |
6d97dbd7 | 2162 | |
ba6a1308 | 2163 | spin_unlock_irqrestore(ap->lock, flags); |
6d97dbd7 | 2164 | |
fe06e5f9 TH |
2165 | /* ignore built-in hardresets if SCR access is not available */ |
2166 | if ((hardreset == sata_std_hardreset || | |
2167 | hardreset == sata_sff_hardreset) && !sata_scr_valid(&ap->link)) | |
a1efdaba | 2168 | hardreset = NULL; |
6d97dbd7 | 2169 | |
a1efdaba TH |
2170 | ata_do_eh(ap, ap->ops->prereset, softreset, hardreset, |
2171 | ap->ops->postreset); | |
6d97dbd7 | 2172 | } |
0fe40ff8 | 2173 | EXPORT_SYMBOL_GPL(ata_sff_error_handler); |
6d97dbd7 | 2174 | |
624d5c51 | 2175 | /** |
9363c382 | 2176 | * ata_sff_std_ports - initialize ioaddr with standard port offsets. |
624d5c51 TH |
2177 | * @ioaddr: IO address structure to be initialized |
2178 | * | |
2179 | * Utility function which initializes data_addr, error_addr, | |
2180 | * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr, | |
2181 | * device_addr, status_addr, and command_addr to standard offsets | |
2182 | * relative to cmd_addr. | |
2183 | * | |
2184 | * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr. | |
2185 | */ | |
9363c382 | 2186 | void ata_sff_std_ports(struct ata_ioports *ioaddr) |
624d5c51 TH |
2187 | { |
2188 | ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA; | |
2189 | ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR; | |
2190 | ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE; | |
2191 | ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT; | |
2192 | ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL; | |
2193 | ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM; | |
2194 | ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH; | |
2195 | ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE; | |
2196 | ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS; | |
2197 | ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD; | |
2198 | } | |
0fe40ff8 | 2199 | EXPORT_SYMBOL_GPL(ata_sff_std_ports); |
624d5c51 | 2200 | |
1fdffbce | 2201 | #ifdef CONFIG_PCI |
4112e16a | 2202 | |
272f7884 TH |
2203 | static int ata_resources_present(struct pci_dev *pdev, int port) |
2204 | { | |
2205 | int i; | |
2206 | ||
2207 | /* Check the PCI resources for this channel are enabled */ | |
2208 | port = port * 2; | |
0fe40ff8 | 2209 | for (i = 0; i < 2; i++) { |
272f7884 TH |
2210 | if (pci_resource_start(pdev, port + i) == 0 || |
2211 | pci_resource_len(pdev, port + i) == 0) | |
2212 | return 0; | |
2213 | } | |
2214 | return 1; | |
2215 | } | |
2216 | ||
d491b27b | 2217 | /** |
9363c382 | 2218 | * ata_pci_sff_init_host - acquire native PCI ATA resources and init host |
d491b27b | 2219 | * @host: target ATA host |
d491b27b | 2220 | * |
1626aeb8 TH |
2221 | * Acquire native PCI ATA resources for @host and initialize the |
2222 | * first two ports of @host accordingly. Ports marked dummy are | |
2223 | * skipped and allocation failure makes the port dummy. | |
d491b27b | 2224 | * |
d583bc18 TH |
2225 | * Note that native PCI resources are valid even for legacy hosts |
2226 | * as we fix up pdev resources array early in boot, so this | |
2227 | * function can be used for both native and legacy SFF hosts. | |
2228 | * | |
d491b27b TH |
2229 | * LOCKING: |
2230 | * Inherited from calling layer (may sleep). | |
2231 | * | |
2232 | * RETURNS: | |
1626aeb8 TH |
2233 | * 0 if at least one port is initialized, -ENODEV if no port is |
2234 | * available. | |
d491b27b | 2235 | */ |
9363c382 | 2236 | int ata_pci_sff_init_host(struct ata_host *host) |
d491b27b TH |
2237 | { |
2238 | struct device *gdev = host->dev; | |
2239 | struct pci_dev *pdev = to_pci_dev(gdev); | |
1626aeb8 | 2240 | unsigned int mask = 0; |
d491b27b TH |
2241 | int i, rc; |
2242 | ||
d491b27b TH |
2243 | /* request, iomap BARs and init port addresses accordingly */ |
2244 | for (i = 0; i < 2; i++) { | |
2245 | struct ata_port *ap = host->ports[i]; | |
2246 | int base = i * 2; | |
2247 | void __iomem * const *iomap; | |
2248 | ||
1626aeb8 TH |
2249 | if (ata_port_is_dummy(ap)) |
2250 | continue; | |
2251 | ||
2252 | /* Discard disabled ports. Some controllers show | |
2253 | * their unused channels this way. Disabled ports are | |
2254 | * made dummy. | |
2255 | */ | |
2256 | if (!ata_resources_present(pdev, i)) { | |
2257 | ap->ops = &ata_dummy_port_ops; | |
d491b27b | 2258 | continue; |
1626aeb8 | 2259 | } |
d491b27b | 2260 | |
35a10a80 TH |
2261 | rc = pcim_iomap_regions(pdev, 0x3 << base, |
2262 | dev_driver_string(gdev)); | |
d491b27b | 2263 | if (rc) { |
a44fec1f JP |
2264 | dev_warn(gdev, |
2265 | "failed to request/iomap BARs for port %d (errno=%d)\n", | |
2266 | i, rc); | |
d491b27b TH |
2267 | if (rc == -EBUSY) |
2268 | pcim_pin_device(pdev); | |
1626aeb8 TH |
2269 | ap->ops = &ata_dummy_port_ops; |
2270 | continue; | |
d491b27b TH |
2271 | } |
2272 | host->iomap = iomap = pcim_iomap_table(pdev); | |
2273 | ||
2274 | ap->ioaddr.cmd_addr = iomap[base]; | |
2275 | ap->ioaddr.altstatus_addr = | |
2276 | ap->ioaddr.ctl_addr = (void __iomem *) | |
2277 | ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS); | |
9363c382 | 2278 | ata_sff_std_ports(&ap->ioaddr); |
1626aeb8 | 2279 | |
cbcdd875 TH |
2280 | ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx", |
2281 | (unsigned long long)pci_resource_start(pdev, base), | |
2282 | (unsigned long long)pci_resource_start(pdev, base + 1)); | |
2283 | ||
1626aeb8 TH |
2284 | mask |= 1 << i; |
2285 | } | |
2286 | ||
2287 | if (!mask) { | |
a44fec1f | 2288 | dev_err(gdev, "no available native port\n"); |
1626aeb8 | 2289 | return -ENODEV; |
d491b27b TH |
2290 | } |
2291 | ||
2292 | return 0; | |
2293 | } | |
0fe40ff8 | 2294 | EXPORT_SYMBOL_GPL(ata_pci_sff_init_host); |
d491b27b | 2295 | |
21b0ad4f | 2296 | /** |
1c5afdf7 | 2297 | * ata_pci_sff_prepare_host - helper to prepare PCI PIO-only SFF ATA host |
21b0ad4f | 2298 | * @pdev: target PCI device |
1626aeb8 | 2299 | * @ppi: array of port_info, must be enough for two ports |
21b0ad4f TH |
2300 | * @r_host: out argument for the initialized ATA host |
2301 | * | |
1c5afdf7 TH |
2302 | * Helper to allocate PIO-only SFF ATA host for @pdev, acquire |
2303 | * all PCI resources and initialize it accordingly in one go. | |
21b0ad4f TH |
2304 | * |
2305 | * LOCKING: | |
2306 | * Inherited from calling layer (may sleep). | |
2307 | * | |
2308 | * RETURNS: | |
2309 | * 0 on success, -errno otherwise. | |
2310 | */ | |
9363c382 | 2311 | int ata_pci_sff_prepare_host(struct pci_dev *pdev, |
0fe40ff8 | 2312 | const struct ata_port_info * const *ppi, |
d583bc18 | 2313 | struct ata_host **r_host) |
21b0ad4f TH |
2314 | { |
2315 | struct ata_host *host; | |
21b0ad4f TH |
2316 | int rc; |
2317 | ||
2318 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) | |
2319 | return -ENOMEM; | |
2320 | ||
2321 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); | |
2322 | if (!host) { | |
a44fec1f | 2323 | dev_err(&pdev->dev, "failed to allocate ATA host\n"); |
21b0ad4f TH |
2324 | rc = -ENOMEM; |
2325 | goto err_out; | |
2326 | } | |
2327 | ||
9363c382 | 2328 | rc = ata_pci_sff_init_host(host); |
21b0ad4f TH |
2329 | if (rc) |
2330 | goto err_out; | |
2331 | ||
21b0ad4f TH |
2332 | devres_remove_group(&pdev->dev, NULL); |
2333 | *r_host = host; | |
2334 | return 0; | |
2335 | ||
0fe40ff8 | 2336 | err_out: |
21b0ad4f TH |
2337 | devres_release_group(&pdev->dev, NULL); |
2338 | return rc; | |
2339 | } | |
0fe40ff8 | 2340 | EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host); |
21b0ad4f | 2341 | |
4e6b79fa | 2342 | /** |
9363c382 | 2343 | * ata_pci_sff_activate_host - start SFF host, request IRQ and register it |
4e6b79fa TH |
2344 | * @host: target SFF ATA host |
2345 | * @irq_handler: irq_handler used when requesting IRQ(s) | |
2346 | * @sht: scsi_host_template to use when registering the host | |
2347 | * | |
2348 | * This is the counterpart of ata_host_activate() for SFF ATA | |
2349 | * hosts. This separate helper is necessary because SFF hosts | |
2350 | * use two separate interrupts in legacy mode. | |
2351 | * | |
2352 | * LOCKING: | |
2353 | * Inherited from calling layer (may sleep). | |
2354 | * | |
2355 | * RETURNS: | |
2356 | * 0 on success, -errno otherwise. | |
2357 | */ | |
9363c382 | 2358 | int ata_pci_sff_activate_host(struct ata_host *host, |
4e6b79fa TH |
2359 | irq_handler_t irq_handler, |
2360 | struct scsi_host_template *sht) | |
2361 | { | |
2362 | struct device *dev = host->dev; | |
2363 | struct pci_dev *pdev = to_pci_dev(dev); | |
2364 | const char *drv_name = dev_driver_string(host->dev); | |
2365 | int legacy_mode = 0, rc; | |
2366 | ||
2367 | rc = ata_host_start(host); | |
2368 | if (rc) | |
2369 | return rc; | |
2370 | ||
2371 | if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) { | |
589d5726 | 2372 | u8 tmp8, mask = 0; |
4e6b79fa | 2373 | |
589d5726 DS |
2374 | /* |
2375 | * ATA spec says we should use legacy mode when one | |
2376 | * port is in legacy mode, but disabled ports on some | |
2377 | * PCI hosts appear as fixed legacy ports, e.g SB600/700 | |
2378 | * on which the secondary port is not wired, so | |
2379 | * ignore ports that are marked as 'dummy' during | |
2380 | * this check | |
2381 | */ | |
4e6b79fa | 2382 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8); |
589d5726 DS |
2383 | if (!ata_port_is_dummy(host->ports[0])) |
2384 | mask |= (1 << 0); | |
2385 | if (!ata_port_is_dummy(host->ports[1])) | |
2386 | mask |= (1 << 2); | |
4e6b79fa TH |
2387 | if ((tmp8 & mask) != mask) |
2388 | legacy_mode = 1; | |
4e6b79fa TH |
2389 | } |
2390 | ||
2391 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) | |
2392 | return -ENOMEM; | |
2393 | ||
2394 | if (!legacy_mode && pdev->irq) { | |
af649a1b JB |
2395 | int i; |
2396 | ||
4e6b79fa TH |
2397 | rc = devm_request_irq(dev, pdev->irq, irq_handler, |
2398 | IRQF_SHARED, drv_name, host); | |
2399 | if (rc) | |
2400 | goto out; | |
2401 | ||
af649a1b JB |
2402 | for (i = 0; i < 2; i++) { |
2403 | if (ata_port_is_dummy(host->ports[i])) | |
2404 | continue; | |
2405 | ata_port_desc(host->ports[i], "irq %d", pdev->irq); | |
2406 | } | |
4e6b79fa TH |
2407 | } else if (legacy_mode) { |
2408 | if (!ata_port_is_dummy(host->ports[0])) { | |
2409 | rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev), | |
2410 | irq_handler, IRQF_SHARED, | |
2411 | drv_name, host); | |
2412 | if (rc) | |
2413 | goto out; | |
2414 | ||
2415 | ata_port_desc(host->ports[0], "irq %d", | |
2416 | ATA_PRIMARY_IRQ(pdev)); | |
2417 | } | |
2418 | ||
2419 | if (!ata_port_is_dummy(host->ports[1])) { | |
2420 | rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev), | |
2421 | irq_handler, IRQF_SHARED, | |
2422 | drv_name, host); | |
2423 | if (rc) | |
2424 | goto out; | |
2425 | ||
2426 | ata_port_desc(host->ports[1], "irq %d", | |
2427 | ATA_SECONDARY_IRQ(pdev)); | |
2428 | } | |
2429 | } | |
2430 | ||
2431 | rc = ata_host_register(host, sht); | |
0fe40ff8 | 2432 | out: |
4e6b79fa TH |
2433 | if (rc == 0) |
2434 | devres_remove_group(dev, NULL); | |
2435 | else | |
2436 | devres_release_group(dev, NULL); | |
2437 | ||
2438 | return rc; | |
2439 | } | |
0fe40ff8 | 2440 | EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host); |
4e6b79fa | 2441 | |
1c5afdf7 TH |
2442 | static const struct ata_port_info *ata_sff_find_valid_pi( |
2443 | const struct ata_port_info * const *ppi) | |
2444 | { | |
2445 | int i; | |
2446 | ||
2447 | /* look up the first valid port_info */ | |
2448 | for (i = 0; i < 2 && ppi[i]; i++) | |
2449 | if (ppi[i]->port_ops != &ata_dummy_port_ops) | |
2450 | return ppi[i]; | |
2451 | ||
2452 | return NULL; | |
2453 | } | |
2454 | ||
c2036033 BZ |
2455 | static int ata_pci_init_one(struct pci_dev *pdev, |
2456 | const struct ata_port_info * const *ppi, | |
2457 | struct scsi_host_template *sht, void *host_priv, | |
2458 | int hflags, bool bmdma) | |
1fdffbce | 2459 | { |
f0d36efd | 2460 | struct device *dev = &pdev->dev; |
1c5afdf7 | 2461 | const struct ata_port_info *pi; |
0f834de3 | 2462 | struct ata_host *host = NULL; |
1c5afdf7 | 2463 | int rc; |
1fdffbce JG |
2464 | |
2465 | DPRINTK("ENTER\n"); | |
2466 | ||
1c5afdf7 | 2467 | pi = ata_sff_find_valid_pi(ppi); |
1626aeb8 | 2468 | if (!pi) { |
a44fec1f | 2469 | dev_err(&pdev->dev, "no valid port_info specified\n"); |
1626aeb8 TH |
2470 | return -EINVAL; |
2471 | } | |
c791c306 | 2472 | |
1626aeb8 TH |
2473 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) |
2474 | return -ENOMEM; | |
1fdffbce | 2475 | |
f0d36efd | 2476 | rc = pcim_enable_device(pdev); |
1fdffbce | 2477 | if (rc) |
4e6b79fa | 2478 | goto out; |
1fdffbce | 2479 | |
aab94404 | 2480 | #ifdef CONFIG_ATA_BMDMA |
c2036033 BZ |
2481 | if (bmdma) |
2482 | /* prepare and activate BMDMA host */ | |
2483 | rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host); | |
2484 | else | |
aab94404 | 2485 | #endif |
c2036033 BZ |
2486 | /* prepare and activate SFF host */ |
2487 | rc = ata_pci_sff_prepare_host(pdev, ppi, &host); | |
d583bc18 | 2488 | if (rc) |
4e6b79fa | 2489 | goto out; |
887125e3 | 2490 | host->private_data = host_priv; |
c2036033 | 2491 | host->flags |= hflags; |
d491b27b | 2492 | |
aab94404 | 2493 | #ifdef CONFIG_ATA_BMDMA |
c2036033 BZ |
2494 | if (bmdma) { |
2495 | pci_set_master(pdev); | |
2496 | rc = ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht); | |
2497 | } else | |
aab94404 | 2498 | #endif |
c2036033 | 2499 | rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht); |
0fe40ff8 | 2500 | out: |
4e6b79fa TH |
2501 | if (rc == 0) |
2502 | devres_remove_group(&pdev->dev, NULL); | |
2503 | else | |
2504 | devres_release_group(&pdev->dev, NULL); | |
d491b27b | 2505 | |
1fdffbce JG |
2506 | return rc; |
2507 | } | |
c2036033 BZ |
2508 | |
2509 | /** | |
2510 | * ata_pci_sff_init_one - Initialize/register PIO-only PCI IDE controller | |
2511 | * @pdev: Controller to be initialized | |
2512 | * @ppi: array of port_info, must be enough for two ports | |
2513 | * @sht: scsi_host_template to use when registering the host | |
2514 | * @host_priv: host private_data | |
2515 | * @hflag: host flags | |
2516 | * | |
2517 | * This is a helper function which can be called from a driver's | |
2518 | * xxx_init_one() probe function if the hardware uses traditional | |
2519 | * IDE taskfile registers and is PIO only. | |
2520 | * | |
2521 | * ASSUMPTION: | |
2522 | * Nobody makes a single channel controller that appears solely as | |
2523 | * the secondary legacy port on PCI. | |
2524 | * | |
2525 | * LOCKING: | |
2526 | * Inherited from PCI layer (may sleep). | |
2527 | * | |
2528 | * RETURNS: | |
2529 | * Zero on success, negative on errno-based value on error. | |
2530 | */ | |
2531 | int ata_pci_sff_init_one(struct pci_dev *pdev, | |
2532 | const struct ata_port_info * const *ppi, | |
2533 | struct scsi_host_template *sht, void *host_priv, int hflag) | |
2534 | { | |
2535 | return ata_pci_init_one(pdev, ppi, sht, host_priv, hflag, 0); | |
2536 | } | |
0fe40ff8 | 2537 | EXPORT_SYMBOL_GPL(ata_pci_sff_init_one); |
1fdffbce JG |
2538 | |
2539 | #endif /* CONFIG_PCI */ | |
9f2f7210 | 2540 | |
9a7780c9 TH |
2541 | /* |
2542 | * BMDMA support | |
2543 | */ | |
2544 | ||
2545 | #ifdef CONFIG_ATA_BMDMA | |
2546 | ||
9f2f7210 TH |
2547 | const struct ata_port_operations ata_bmdma_port_ops = { |
2548 | .inherits = &ata_sff_port_ops, | |
2549 | ||
fe06e5f9 TH |
2550 | .error_handler = ata_bmdma_error_handler, |
2551 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
2552 | ||
f47451c4 | 2553 | .qc_prep = ata_bmdma_qc_prep, |
360ff783 | 2554 | .qc_issue = ata_bmdma_qc_issue, |
f47451c4 | 2555 | |
37f65b8b | 2556 | .sff_irq_clear = ata_bmdma_irq_clear, |
9f2f7210 TH |
2557 | .bmdma_setup = ata_bmdma_setup, |
2558 | .bmdma_start = ata_bmdma_start, | |
2559 | .bmdma_stop = ata_bmdma_stop, | |
2560 | .bmdma_status = ata_bmdma_status, | |
c7087652 TH |
2561 | |
2562 | .port_start = ata_bmdma_port_start, | |
9f2f7210 TH |
2563 | }; |
2564 | EXPORT_SYMBOL_GPL(ata_bmdma_port_ops); | |
2565 | ||
2566 | const struct ata_port_operations ata_bmdma32_port_ops = { | |
2567 | .inherits = &ata_bmdma_port_ops, | |
2568 | ||
2569 | .sff_data_xfer = ata_sff_data_xfer32, | |
c7087652 | 2570 | .port_start = ata_bmdma_port_start32, |
9f2f7210 TH |
2571 | }; |
2572 | EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops); | |
2573 | ||
f47451c4 TH |
2574 | /** |
2575 | * ata_bmdma_fill_sg - Fill PCI IDE PRD table | |
2576 | * @qc: Metadata associated with taskfile to be transferred | |
2577 | * | |
2578 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
2579 | * associated with the current disk command. | |
2580 | * | |
2581 | * LOCKING: | |
2582 | * spin_lock_irqsave(host lock) | |
2583 | * | |
2584 | */ | |
2585 | static void ata_bmdma_fill_sg(struct ata_queued_cmd *qc) | |
2586 | { | |
2587 | struct ata_port *ap = qc->ap; | |
f60d7011 | 2588 | struct ata_bmdma_prd *prd = ap->bmdma_prd; |
f47451c4 TH |
2589 | struct scatterlist *sg; |
2590 | unsigned int si, pi; | |
2591 | ||
2592 | pi = 0; | |
2593 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
2594 | u32 addr, offset; | |
2595 | u32 sg_len, len; | |
2596 | ||
2597 | /* determine if physical DMA addr spans 64K boundary. | |
2598 | * Note h/w doesn't support 64-bit, so we unconditionally | |
2599 | * truncate dma_addr_t to u32. | |
2600 | */ | |
2601 | addr = (u32) sg_dma_address(sg); | |
2602 | sg_len = sg_dma_len(sg); | |
2603 | ||
2604 | while (sg_len) { | |
2605 | offset = addr & 0xffff; | |
2606 | len = sg_len; | |
2607 | if ((offset + sg_len) > 0x10000) | |
2608 | len = 0x10000 - offset; | |
2609 | ||
f60d7011 TH |
2610 | prd[pi].addr = cpu_to_le32(addr); |
2611 | prd[pi].flags_len = cpu_to_le32(len & 0xffff); | |
f47451c4 TH |
2612 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); |
2613 | ||
2614 | pi++; | |
2615 | sg_len -= len; | |
2616 | addr += len; | |
2617 | } | |
2618 | } | |
2619 | ||
f60d7011 | 2620 | prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); |
f47451c4 TH |
2621 | } |
2622 | ||
2623 | /** | |
2624 | * ata_bmdma_fill_sg_dumb - Fill PCI IDE PRD table | |
2625 | * @qc: Metadata associated with taskfile to be transferred | |
2626 | * | |
2627 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
2628 | * associated with the current disk command. Perform the fill | |
2629 | * so that we avoid writing any length 64K records for | |
2630 | * controllers that don't follow the spec. | |
2631 | * | |
2632 | * LOCKING: | |
2633 | * spin_lock_irqsave(host lock) | |
2634 | * | |
2635 | */ | |
2636 | static void ata_bmdma_fill_sg_dumb(struct ata_queued_cmd *qc) | |
2637 | { | |
2638 | struct ata_port *ap = qc->ap; | |
f60d7011 | 2639 | struct ata_bmdma_prd *prd = ap->bmdma_prd; |
f47451c4 TH |
2640 | struct scatterlist *sg; |
2641 | unsigned int si, pi; | |
2642 | ||
2643 | pi = 0; | |
2644 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
2645 | u32 addr, offset; | |
2646 | u32 sg_len, len, blen; | |
2647 | ||
2648 | /* determine if physical DMA addr spans 64K boundary. | |
2649 | * Note h/w doesn't support 64-bit, so we unconditionally | |
2650 | * truncate dma_addr_t to u32. | |
2651 | */ | |
2652 | addr = (u32) sg_dma_address(sg); | |
2653 | sg_len = sg_dma_len(sg); | |
2654 | ||
2655 | while (sg_len) { | |
2656 | offset = addr & 0xffff; | |
2657 | len = sg_len; | |
2658 | if ((offset + sg_len) > 0x10000) | |
2659 | len = 0x10000 - offset; | |
2660 | ||
2661 | blen = len & 0xffff; | |
f60d7011 | 2662 | prd[pi].addr = cpu_to_le32(addr); |
f47451c4 TH |
2663 | if (blen == 0) { |
2664 | /* Some PATA chipsets like the CS5530 can't | |
2665 | cope with 0x0000 meaning 64K as the spec | |
2666 | says */ | |
f60d7011 | 2667 | prd[pi].flags_len = cpu_to_le32(0x8000); |
f47451c4 | 2668 | blen = 0x8000; |
f60d7011 | 2669 | prd[++pi].addr = cpu_to_le32(addr + 0x8000); |
f47451c4 | 2670 | } |
f60d7011 | 2671 | prd[pi].flags_len = cpu_to_le32(blen); |
f47451c4 TH |
2672 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); |
2673 | ||
2674 | pi++; | |
2675 | sg_len -= len; | |
2676 | addr += len; | |
2677 | } | |
2678 | } | |
2679 | ||
f60d7011 | 2680 | prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); |
f47451c4 TH |
2681 | } |
2682 | ||
2683 | /** | |
2684 | * ata_bmdma_qc_prep - Prepare taskfile for submission | |
2685 | * @qc: Metadata associated with taskfile to be prepared | |
2686 | * | |
2687 | * Prepare ATA taskfile for submission. | |
2688 | * | |
2689 | * LOCKING: | |
2690 | * spin_lock_irqsave(host lock) | |
2691 | */ | |
2692 | void ata_bmdma_qc_prep(struct ata_queued_cmd *qc) | |
2693 | { | |
2694 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
2695 | return; | |
2696 | ||
2697 | ata_bmdma_fill_sg(qc); | |
2698 | } | |
2699 | EXPORT_SYMBOL_GPL(ata_bmdma_qc_prep); | |
2700 | ||
2701 | /** | |
2702 | * ata_bmdma_dumb_qc_prep - Prepare taskfile for submission | |
2703 | * @qc: Metadata associated with taskfile to be prepared | |
2704 | * | |
2705 | * Prepare ATA taskfile for submission. | |
2706 | * | |
2707 | * LOCKING: | |
2708 | * spin_lock_irqsave(host lock) | |
2709 | */ | |
2710 | void ata_bmdma_dumb_qc_prep(struct ata_queued_cmd *qc) | |
2711 | { | |
2712 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
2713 | return; | |
2714 | ||
2715 | ata_bmdma_fill_sg_dumb(qc); | |
2716 | } | |
2717 | EXPORT_SYMBOL_GPL(ata_bmdma_dumb_qc_prep); | |
2718 | ||
360ff783 TH |
2719 | /** |
2720 | * ata_bmdma_qc_issue - issue taskfile to a BMDMA controller | |
2721 | * @qc: command to issue to device | |
2722 | * | |
2723 | * This function issues a PIO, NODATA or DMA command to a | |
2724 | * SFF/BMDMA controller. PIO and NODATA are handled by | |
2725 | * ata_sff_qc_issue(). | |
2726 | * | |
2727 | * LOCKING: | |
2728 | * spin_lock_irqsave(host lock) | |
2729 | * | |
2730 | * RETURNS: | |
2731 | * Zero on success, AC_ERR_* mask on failure | |
2732 | */ | |
2733 | unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd *qc) | |
2734 | { | |
2735 | struct ata_port *ap = qc->ap; | |
ea3c6450 | 2736 | struct ata_link *link = qc->dev->link; |
360ff783 | 2737 | |
360ff783 TH |
2738 | /* defer PIO handling to sff_qc_issue */ |
2739 | if (!ata_is_dma(qc->tf.protocol)) | |
2740 | return ata_sff_qc_issue(qc); | |
2741 | ||
2742 | /* select the device */ | |
2743 | ata_dev_select(ap, qc->dev->devno, 1, 0); | |
2744 | ||
2745 | /* start the command */ | |
2746 | switch (qc->tf.protocol) { | |
2747 | case ATA_PROT_DMA: | |
2748 | WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING); | |
2749 | ||
2750 | ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ | |
2751 | ap->ops->bmdma_setup(qc); /* set up bmdma */ | |
2752 | ap->ops->bmdma_start(qc); /* initiate bmdma */ | |
2753 | ap->hsm_task_state = HSM_ST_LAST; | |
2754 | break; | |
2755 | ||
2756 | case ATAPI_PROT_DMA: | |
2757 | WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING); | |
2758 | ||
2759 | ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ | |
2760 | ap->ops->bmdma_setup(qc); /* set up bmdma */ | |
2761 | ap->hsm_task_state = HSM_ST_FIRST; | |
2762 | ||
2763 | /* send cdb by polling if no cdb interrupt */ | |
2764 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
ea3c6450 | 2765 | ata_sff_queue_pio_task(link, 0); |
360ff783 TH |
2766 | break; |
2767 | ||
2768 | default: | |
2769 | WARN_ON(1); | |
2770 | return AC_ERR_SYSTEM; | |
2771 | } | |
2772 | ||
2773 | return 0; | |
2774 | } | |
2775 | EXPORT_SYMBOL_GPL(ata_bmdma_qc_issue); | |
2776 | ||
c3b28894 TH |
2777 | /** |
2778 | * ata_bmdma_port_intr - Handle BMDMA port interrupt | |
2779 | * @ap: Port on which interrupt arrived (possibly...) | |
2780 | * @qc: Taskfile currently active in engine | |
2781 | * | |
2782 | * Handle port interrupt for given queued command. | |
2783 | * | |
2784 | * LOCKING: | |
2785 | * spin_lock_irqsave(host lock) | |
2786 | * | |
2787 | * RETURNS: | |
2788 | * One if interrupt was handled, zero if not (shared irq). | |
2789 | */ | |
2790 | unsigned int ata_bmdma_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc) | |
2791 | { | |
2792 | struct ata_eh_info *ehi = &ap->link.eh_info; | |
2793 | u8 host_stat = 0; | |
2794 | bool bmdma_stopped = false; | |
2795 | unsigned int handled; | |
2796 | ||
2797 | if (ap->hsm_task_state == HSM_ST_LAST && ata_is_dma(qc->tf.protocol)) { | |
2798 | /* check status of DMA engine */ | |
2799 | host_stat = ap->ops->bmdma_status(ap); | |
2800 | VPRINTK("ata%u: host_stat 0x%X\n", ap->print_id, host_stat); | |
2801 | ||
2802 | /* if it's not our irq... */ | |
2803 | if (!(host_stat & ATA_DMA_INTR)) | |
2804 | return ata_sff_idle_irq(ap); | |
2805 | ||
2806 | /* before we do anything else, clear DMA-Start bit */ | |
2807 | ap->ops->bmdma_stop(qc); | |
2808 | bmdma_stopped = true; | |
2809 | ||
2810 | if (unlikely(host_stat & ATA_DMA_ERR)) { | |
25985edc | 2811 | /* error when transferring data to/from memory */ |
c3b28894 TH |
2812 | qc->err_mask |= AC_ERR_HOST_BUS; |
2813 | ap->hsm_task_state = HSM_ST_ERR; | |
2814 | } | |
2815 | } | |
2816 | ||
2817 | handled = __ata_sff_port_intr(ap, qc, bmdma_stopped); | |
2818 | ||
2819 | if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol)) | |
2820 | ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat); | |
2821 | ||
2822 | return handled; | |
2823 | } | |
2824 | EXPORT_SYMBOL_GPL(ata_bmdma_port_intr); | |
2825 | ||
2826 | /** | |
2827 | * ata_bmdma_interrupt - Default BMDMA ATA host interrupt handler | |
2828 | * @irq: irq line (unused) | |
2829 | * @dev_instance: pointer to our ata_host information structure | |
2830 | * | |
2831 | * Default interrupt handler for PCI IDE devices. Calls | |
2832 | * ata_bmdma_port_intr() for each port that is not disabled. | |
2833 | * | |
2834 | * LOCKING: | |
2835 | * Obtains host lock during operation. | |
2836 | * | |
2837 | * RETURNS: | |
2838 | * IRQ_NONE or IRQ_HANDLED. | |
2839 | */ | |
2840 | irqreturn_t ata_bmdma_interrupt(int irq, void *dev_instance) | |
2841 | { | |
2842 | return __ata_sff_interrupt(irq, dev_instance, ata_bmdma_port_intr); | |
2843 | } | |
2844 | EXPORT_SYMBOL_GPL(ata_bmdma_interrupt); | |
2845 | ||
fe06e5f9 TH |
2846 | /** |
2847 | * ata_bmdma_error_handler - Stock error handler for BMDMA controller | |
2848 | * @ap: port to handle error for | |
2849 | * | |
2850 | * Stock error handler for BMDMA controller. It can handle both | |
2851 | * PATA and SATA controllers. Most BMDMA controllers should be | |
2852 | * able to use this EH as-is or with some added handling before | |
2853 | * and after. | |
2854 | * | |
2855 | * LOCKING: | |
2856 | * Kernel thread context (may sleep) | |
2857 | */ | |
2858 | void ata_bmdma_error_handler(struct ata_port *ap) | |
2859 | { | |
2860 | struct ata_queued_cmd *qc; | |
2861 | unsigned long flags; | |
2862 | bool thaw = false; | |
2863 | ||
2864 | qc = __ata_qc_from_tag(ap, ap->link.active_tag); | |
2865 | if (qc && !(qc->flags & ATA_QCFLAG_FAILED)) | |
2866 | qc = NULL; | |
2867 | ||
2868 | /* reset PIO HSM and stop DMA engine */ | |
2869 | spin_lock_irqsave(ap->lock, flags); | |
2870 | ||
2871 | if (qc && ata_is_dma(qc->tf.protocol)) { | |
2872 | u8 host_stat; | |
2873 | ||
2874 | host_stat = ap->ops->bmdma_status(ap); | |
2875 | ||
2876 | /* BMDMA controllers indicate host bus error by | |
2877 | * setting DMA_ERR bit and timing out. As it wasn't | |
2878 | * really a timeout event, adjust error mask and | |
2879 | * cancel frozen state. | |
2880 | */ | |
2881 | if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) { | |
2882 | qc->err_mask = AC_ERR_HOST_BUS; | |
2883 | thaw = true; | |
2884 | } | |
2885 | ||
2886 | ap->ops->bmdma_stop(qc); | |
2887 | ||
2888 | /* if we're gonna thaw, make sure IRQ is clear */ | |
2889 | if (thaw) { | |
2890 | ap->ops->sff_check_status(ap); | |
37f65b8b TH |
2891 | if (ap->ops->sff_irq_clear) |
2892 | ap->ops->sff_irq_clear(ap); | |
fe06e5f9 TH |
2893 | } |
2894 | } | |
2895 | ||
2896 | spin_unlock_irqrestore(ap->lock, flags); | |
2897 | ||
2898 | if (thaw) | |
2899 | ata_eh_thaw_port(ap); | |
2900 | ||
2901 | ata_sff_error_handler(ap); | |
2902 | } | |
2903 | EXPORT_SYMBOL_GPL(ata_bmdma_error_handler); | |
2904 | ||
2905 | /** | |
2906 | * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for BMDMA | |
2907 | * @qc: internal command to clean up | |
2908 | * | |
2909 | * LOCKING: | |
2910 | * Kernel thread context (may sleep) | |
2911 | */ | |
2912 | void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc) | |
2913 | { | |
2914 | struct ata_port *ap = qc->ap; | |
2915 | unsigned long flags; | |
2916 | ||
2917 | if (ata_is_dma(qc->tf.protocol)) { | |
2918 | spin_lock_irqsave(ap->lock, flags); | |
2919 | ap->ops->bmdma_stop(qc); | |
2920 | spin_unlock_irqrestore(ap->lock, flags); | |
2921 | } | |
2922 | } | |
2923 | EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd); | |
2924 | ||
37f65b8b TH |
2925 | /** |
2926 | * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt. | |
2927 | * @ap: Port associated with this ATA transaction. | |
2928 | * | |
2929 | * Clear interrupt and error flags in DMA status register. | |
2930 | * | |
2931 | * May be used as the irq_clear() entry in ata_port_operations. | |
2932 | * | |
2933 | * LOCKING: | |
2934 | * spin_lock_irqsave(host lock) | |
2935 | */ | |
2936 | void ata_bmdma_irq_clear(struct ata_port *ap) | |
2937 | { | |
2938 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
2939 | ||
2940 | if (!mmio) | |
2941 | return; | |
2942 | ||
2943 | iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS); | |
2944 | } | |
2945 | EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear); | |
2946 | ||
9f2f7210 TH |
2947 | /** |
2948 | * ata_bmdma_setup - Set up PCI IDE BMDMA transaction | |
2949 | * @qc: Info associated with this ATA transaction. | |
2950 | * | |
2951 | * LOCKING: | |
2952 | * spin_lock_irqsave(host lock) | |
2953 | */ | |
2954 | void ata_bmdma_setup(struct ata_queued_cmd *qc) | |
2955 | { | |
2956 | struct ata_port *ap = qc->ap; | |
2957 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
2958 | u8 dmactl; | |
2959 | ||
2960 | /* load PRD table addr. */ | |
2961 | mb(); /* make sure PRD table writes are visible to controller */ | |
f60d7011 | 2962 | iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); |
9f2f7210 TH |
2963 | |
2964 | /* specify data direction, triple-check start bit is clear */ | |
2965 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2966 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | |
2967 | if (!rw) | |
2968 | dmactl |= ATA_DMA_WR; | |
2969 | iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2970 | ||
2971 | /* issue r/w command */ | |
2972 | ap->ops->sff_exec_command(ap, &qc->tf); | |
2973 | } | |
2974 | EXPORT_SYMBOL_GPL(ata_bmdma_setup); | |
2975 | ||
2976 | /** | |
2977 | * ata_bmdma_start - Start a PCI IDE BMDMA transaction | |
2978 | * @qc: Info associated with this ATA transaction. | |
2979 | * | |
2980 | * LOCKING: | |
2981 | * spin_lock_irqsave(host lock) | |
2982 | */ | |
2983 | void ata_bmdma_start(struct ata_queued_cmd *qc) | |
2984 | { | |
2985 | struct ata_port *ap = qc->ap; | |
2986 | u8 dmactl; | |
2987 | ||
2988 | /* start host DMA transaction */ | |
2989 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2990 | iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2991 | ||
2992 | /* Strictly, one may wish to issue an ioread8() here, to | |
2993 | * flush the mmio write. However, control also passes | |
2994 | * to the hardware at this point, and it will interrupt | |
2995 | * us when we are to resume control. So, in effect, | |
2996 | * we don't care when the mmio write flushes. | |
2997 | * Further, a read of the DMA status register _immediately_ | |
2998 | * following the write may not be what certain flaky hardware | |
2999 | * is expected, so I think it is best to not add a readb() | |
3000 | * without first all the MMIO ATA cards/mobos. | |
3001 | * Or maybe I'm just being paranoid. | |
3002 | * | |
3003 | * FIXME: The posting of this write means I/O starts are | |
25985edc | 3004 | * unnecessarily delayed for MMIO |
9f2f7210 TH |
3005 | */ |
3006 | } | |
3007 | EXPORT_SYMBOL_GPL(ata_bmdma_start); | |
3008 | ||
3009 | /** | |
3010 | * ata_bmdma_stop - Stop PCI IDE BMDMA transfer | |
3011 | * @qc: Command we are ending DMA for | |
3012 | * | |
3013 | * Clears the ATA_DMA_START flag in the dma control register | |
3014 | * | |
3015 | * May be used as the bmdma_stop() entry in ata_port_operations. | |
3016 | * | |
3017 | * LOCKING: | |
3018 | * spin_lock_irqsave(host lock) | |
3019 | */ | |
3020 | void ata_bmdma_stop(struct ata_queued_cmd *qc) | |
3021 | { | |
3022 | struct ata_port *ap = qc->ap; | |
3023 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
3024 | ||
3025 | /* clear start/stop bit */ | |
3026 | iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, | |
3027 | mmio + ATA_DMA_CMD); | |
3028 | ||
3029 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | |
3030 | ata_sff_dma_pause(ap); | |
3031 | } | |
3032 | EXPORT_SYMBOL_GPL(ata_bmdma_stop); | |
3033 | ||
3034 | /** | |
3035 | * ata_bmdma_status - Read PCI IDE BMDMA status | |
3036 | * @ap: Port associated with this ATA transaction. | |
3037 | * | |
3038 | * Read and return BMDMA status register. | |
3039 | * | |
3040 | * May be used as the bmdma_status() entry in ata_port_operations. | |
3041 | * | |
3042 | * LOCKING: | |
3043 | * spin_lock_irqsave(host lock) | |
3044 | */ | |
3045 | u8 ata_bmdma_status(struct ata_port *ap) | |
3046 | { | |
3047 | return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); | |
3048 | } | |
3049 | EXPORT_SYMBOL_GPL(ata_bmdma_status); | |
3050 | ||
c7087652 TH |
3051 | |
3052 | /** | |
3053 | * ata_bmdma_port_start - Set port up for bmdma. | |
3054 | * @ap: Port to initialize | |
3055 | * | |
3056 | * Called just after data structures for each port are | |
3057 | * initialized. Allocates space for PRD table. | |
3058 | * | |
3059 | * May be used as the port_start() entry in ata_port_operations. | |
3060 | * | |
3061 | * LOCKING: | |
3062 | * Inherited from caller. | |
3063 | */ | |
3064 | int ata_bmdma_port_start(struct ata_port *ap) | |
3065 | { | |
3066 | if (ap->mwdma_mask || ap->udma_mask) { | |
f60d7011 TH |
3067 | ap->bmdma_prd = |
3068 | dmam_alloc_coherent(ap->host->dev, ATA_PRD_TBL_SZ, | |
3069 | &ap->bmdma_prd_dma, GFP_KERNEL); | |
3070 | if (!ap->bmdma_prd) | |
c7087652 TH |
3071 | return -ENOMEM; |
3072 | } | |
3073 | ||
3074 | return 0; | |
3075 | } | |
3076 | EXPORT_SYMBOL_GPL(ata_bmdma_port_start); | |
3077 | ||
3078 | /** | |
3079 | * ata_bmdma_port_start32 - Set port up for dma. | |
3080 | * @ap: Port to initialize | |
3081 | * | |
3082 | * Called just after data structures for each port are | |
3083 | * initialized. Enables 32bit PIO and allocates space for PRD | |
3084 | * table. | |
3085 | * | |
3086 | * May be used as the port_start() entry in ata_port_operations for | |
3087 | * devices that are capable of 32bit PIO. | |
3088 | * | |
3089 | * LOCKING: | |
3090 | * Inherited from caller. | |
3091 | */ | |
3092 | int ata_bmdma_port_start32(struct ata_port *ap) | |
3093 | { | |
3094 | ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE; | |
3095 | return ata_bmdma_port_start(ap); | |
3096 | } | |
3097 | EXPORT_SYMBOL_GPL(ata_bmdma_port_start32); | |
3098 | ||
9f2f7210 TH |
3099 | #ifdef CONFIG_PCI |
3100 | ||
3101 | /** | |
3102 | * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex | |
3103 | * @pdev: PCI device | |
3104 | * | |
3105 | * Some PCI ATA devices report simplex mode but in fact can be told to | |
3106 | * enter non simplex mode. This implements the necessary logic to | |
3107 | * perform the task on such devices. Calling it on other devices will | |
3108 | * have -undefined- behaviour. | |
3109 | */ | |
3110 | int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev) | |
3111 | { | |
3112 | unsigned long bmdma = pci_resource_start(pdev, 4); | |
3113 | u8 simplex; | |
3114 | ||
3115 | if (bmdma == 0) | |
3116 | return -ENOENT; | |
3117 | ||
3118 | simplex = inb(bmdma + 0x02); | |
3119 | outb(simplex & 0x60, bmdma + 0x02); | |
3120 | simplex = inb(bmdma + 0x02); | |
3121 | if (simplex & 0x80) | |
3122 | return -EOPNOTSUPP; | |
3123 | return 0; | |
3124 | } | |
3125 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex); | |
3126 | ||
c7087652 TH |
3127 | static void ata_bmdma_nodma(struct ata_host *host, const char *reason) |
3128 | { | |
3129 | int i; | |
3130 | ||
a44fec1f | 3131 | dev_err(host->dev, "BMDMA: %s, falling back to PIO\n", reason); |
c7087652 TH |
3132 | |
3133 | for (i = 0; i < 2; i++) { | |
3134 | host->ports[i]->mwdma_mask = 0; | |
3135 | host->ports[i]->udma_mask = 0; | |
3136 | } | |
3137 | } | |
3138 | ||
9f2f7210 TH |
3139 | /** |
3140 | * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host | |
3141 | * @host: target ATA host | |
3142 | * | |
3143 | * Acquire PCI BMDMA resources and initialize @host accordingly. | |
3144 | * | |
3145 | * LOCKING: | |
3146 | * Inherited from calling layer (may sleep). | |
9f2f7210 | 3147 | */ |
c7087652 | 3148 | void ata_pci_bmdma_init(struct ata_host *host) |
9f2f7210 TH |
3149 | { |
3150 | struct device *gdev = host->dev; | |
3151 | struct pci_dev *pdev = to_pci_dev(gdev); | |
3152 | int i, rc; | |
3153 | ||
3154 | /* No BAR4 allocation: No DMA */ | |
c7087652 TH |
3155 | if (pci_resource_start(pdev, 4) == 0) { |
3156 | ata_bmdma_nodma(host, "BAR4 is zero"); | |
3157 | return; | |
3158 | } | |
9f2f7210 | 3159 | |
c7087652 TH |
3160 | /* |
3161 | * Some controllers require BMDMA region to be initialized | |
3162 | * even if DMA is not in use to clear IRQ status via | |
3163 | * ->sff_irq_clear method. Try to initialize bmdma_addr | |
3164 | * regardless of dma masks. | |
3165 | */ | |
c54c719b | 3166 | rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK); |
9f2f7210 | 3167 | if (rc) |
c7087652 TH |
3168 | ata_bmdma_nodma(host, "failed to set dma mask"); |
3169 | if (!rc) { | |
c54c719b | 3170 | rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK); |
c7087652 TH |
3171 | if (rc) |
3172 | ata_bmdma_nodma(host, | |
3173 | "failed to set consistent dma mask"); | |
3174 | } | |
9f2f7210 TH |
3175 | |
3176 | /* request and iomap DMA region */ | |
3177 | rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev)); | |
3178 | if (rc) { | |
c7087652 TH |
3179 | ata_bmdma_nodma(host, "failed to request/iomap BAR4"); |
3180 | return; | |
9f2f7210 TH |
3181 | } |
3182 | host->iomap = pcim_iomap_table(pdev); | |
3183 | ||
3184 | for (i = 0; i < 2; i++) { | |
3185 | struct ata_port *ap = host->ports[i]; | |
3186 | void __iomem *bmdma = host->iomap[4] + 8 * i; | |
3187 | ||
3188 | if (ata_port_is_dummy(ap)) | |
3189 | continue; | |
3190 | ||
3191 | ap->ioaddr.bmdma_addr = bmdma; | |
3192 | if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) && | |
3193 | (ioread8(bmdma + 2) & 0x80)) | |
3194 | host->flags |= ATA_HOST_SIMPLEX; | |
3195 | ||
3196 | ata_port_desc(ap, "bmdma 0x%llx", | |
3197 | (unsigned long long)pci_resource_start(pdev, 4) + 8 * i); | |
3198 | } | |
9f2f7210 TH |
3199 | } |
3200 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_init); | |
3201 | ||
1c5afdf7 TH |
3202 | /** |
3203 | * ata_pci_bmdma_prepare_host - helper to prepare PCI BMDMA ATA host | |
3204 | * @pdev: target PCI device | |
3205 | * @ppi: array of port_info, must be enough for two ports | |
3206 | * @r_host: out argument for the initialized ATA host | |
3207 | * | |
3208 | * Helper to allocate BMDMA ATA host for @pdev, acquire all PCI | |
3209 | * resources and initialize it accordingly in one go. | |
3210 | * | |
3211 | * LOCKING: | |
3212 | * Inherited from calling layer (may sleep). | |
3213 | * | |
3214 | * RETURNS: | |
3215 | * 0 on success, -errno otherwise. | |
3216 | */ | |
3217 | int ata_pci_bmdma_prepare_host(struct pci_dev *pdev, | |
3218 | const struct ata_port_info * const * ppi, | |
3219 | struct ata_host **r_host) | |
3220 | { | |
3221 | int rc; | |
3222 | ||
3223 | rc = ata_pci_sff_prepare_host(pdev, ppi, r_host); | |
3224 | if (rc) | |
3225 | return rc; | |
3226 | ||
3227 | ata_pci_bmdma_init(*r_host); | |
3228 | return 0; | |
3229 | } | |
3230 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_prepare_host); | |
3231 | ||
3232 | /** | |
3233 | * ata_pci_bmdma_init_one - Initialize/register BMDMA PCI IDE controller | |
3234 | * @pdev: Controller to be initialized | |
3235 | * @ppi: array of port_info, must be enough for two ports | |
3236 | * @sht: scsi_host_template to use when registering the host | |
3237 | * @host_priv: host private_data | |
3238 | * @hflags: host flags | |
3239 | * | |
3240 | * This function is similar to ata_pci_sff_init_one() but also | |
3241 | * takes care of BMDMA initialization. | |
3242 | * | |
3243 | * LOCKING: | |
3244 | * Inherited from PCI layer (may sleep). | |
3245 | * | |
3246 | * RETURNS: | |
3247 | * Zero on success, negative on errno-based value on error. | |
3248 | */ | |
3249 | int ata_pci_bmdma_init_one(struct pci_dev *pdev, | |
3250 | const struct ata_port_info * const * ppi, | |
3251 | struct scsi_host_template *sht, void *host_priv, | |
3252 | int hflags) | |
3253 | { | |
c2036033 | 3254 | return ata_pci_init_one(pdev, ppi, sht, host_priv, hflags, 1); |
1c5afdf7 TH |
3255 | } |
3256 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_init_one); | |
3257 | ||
9f2f7210 | 3258 | #endif /* CONFIG_PCI */ |
9a7780c9 | 3259 | #endif /* CONFIG_ATA_BMDMA */ |
270390e1 TH |
3260 | |
3261 | /** | |
3262 | * ata_sff_port_init - Initialize SFF/BMDMA ATA port | |
3263 | * @ap: Port to initialize | |
3264 | * | |
3265 | * Called on port allocation to initialize SFF/BMDMA specific | |
3266 | * fields. | |
3267 | * | |
3268 | * LOCKING: | |
3269 | * None. | |
3270 | */ | |
3271 | void ata_sff_port_init(struct ata_port *ap) | |
3272 | { | |
c429137a | 3273 | INIT_DELAYED_WORK(&ap->sff_pio_task, ata_sff_pio_task); |
5fe7454a TH |
3274 | ap->ctl = ATA_DEVCTL_OBS; |
3275 | ap->last_ctl = 0xFF; | |
270390e1 TH |
3276 | } |
3277 | ||
3278 | int __init ata_sff_init(void) | |
3279 | { | |
6370a6ad | 3280 | ata_sff_wq = alloc_workqueue("ata_sff", WQ_MEM_RECLAIM, WQ_MAX_ACTIVE); |
c429137a TH |
3281 | if (!ata_sff_wq) |
3282 | return -ENOMEM; | |
3283 | ||
270390e1 TH |
3284 | return 0; |
3285 | } | |
3286 | ||
c43d559f | 3287 | void ata_sff_exit(void) |
270390e1 | 3288 | { |
c429137a | 3289 | destroy_workqueue(ata_sff_wq); |
270390e1 | 3290 | } |