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c82ee6d3 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1fdffbce | 2 | /* |
f3a03b09 | 3 | * libata-sff.c - helper library for PCI IDE BMDMA |
1fdffbce | 4 | * |
1fdffbce JG |
5 | * Copyright 2003-2006 Red Hat, Inc. All rights reserved. |
6 | * Copyright 2003-2006 Jeff Garzik | |
7 | * | |
1fdffbce | 8 | * libata documentation is available via 'make {ps|pdf}docs', |
9bb9a39c | 9 | * as Documentation/driver-api/libata.rst |
1fdffbce JG |
10 | * |
11 | * Hardware documentation available from http://www.t13.org/ and | |
12 | * http://www.sata-io.org/ | |
1fdffbce JG |
13 | */ |
14 | ||
1fdffbce | 15 | #include <linux/kernel.h> |
5a0e3ad6 | 16 | #include <linux/gfp.h> |
1fdffbce | 17 | #include <linux/pci.h> |
bff7832d | 18 | #include <linux/module.h> |
1fdffbce | 19 | #include <linux/libata.h> |
624d5c51 | 20 | #include <linux/highmem.h> |
c206a389 | 21 | #include <trace/events/libata.h> |
1fdffbce JG |
22 | #include "libata.h" |
23 | ||
c429137a TH |
24 | static struct workqueue_struct *ata_sff_wq; |
25 | ||
624d5c51 TH |
26 | const struct ata_port_operations ata_sff_port_ops = { |
27 | .inherits = &ata_base_port_ops, | |
28 | ||
f47451c4 | 29 | .qc_prep = ata_noop_qc_prep, |
9363c382 | 30 | .qc_issue = ata_sff_qc_issue, |
4c9bf4e7 | 31 | .qc_fill_rtf = ata_sff_qc_fill_rtf, |
9363c382 TH |
32 | |
33 | .freeze = ata_sff_freeze, | |
34 | .thaw = ata_sff_thaw, | |
0aa1113d | 35 | .prereset = ata_sff_prereset, |
9363c382 | 36 | .softreset = ata_sff_softreset, |
57c9efdf | 37 | .hardreset = sata_sff_hardreset, |
203c75b8 | 38 | .postreset = ata_sff_postreset, |
9363c382 | 39 | .error_handler = ata_sff_error_handler, |
9363c382 | 40 | |
5682ed33 TH |
41 | .sff_dev_select = ata_sff_dev_select, |
42 | .sff_check_status = ata_sff_check_status, | |
43 | .sff_tf_load = ata_sff_tf_load, | |
44 | .sff_tf_read = ata_sff_tf_read, | |
45 | .sff_exec_command = ata_sff_exec_command, | |
46 | .sff_data_xfer = ata_sff_data_xfer, | |
8244cd05 | 47 | .sff_drain_fifo = ata_sff_drain_fifo, |
624d5c51 | 48 | |
c96f1732 | 49 | .lost_interrupt = ata_sff_lost_interrupt, |
624d5c51 | 50 | }; |
0fe40ff8 | 51 | EXPORT_SYMBOL_GPL(ata_sff_port_ops); |
624d5c51 | 52 | |
272f7884 | 53 | /** |
9363c382 | 54 | * ata_sff_check_status - Read device status reg & clear interrupt |
272f7884 TH |
55 | * @ap: port where the device is |
56 | * | |
57 | * Reads ATA taskfile status register for currently-selected device | |
58 | * and return its value. This also clears pending interrupts | |
59 | * from this device | |
60 | * | |
61 | * LOCKING: | |
62 | * Inherited from caller. | |
63 | */ | |
9363c382 | 64 | u8 ata_sff_check_status(struct ata_port *ap) |
272f7884 TH |
65 | { |
66 | return ioread8(ap->ioaddr.status_addr); | |
67 | } | |
0fe40ff8 | 68 | EXPORT_SYMBOL_GPL(ata_sff_check_status); |
272f7884 TH |
69 | |
70 | /** | |
9363c382 | 71 | * ata_sff_altstatus - Read device alternate status reg |
272f7884 | 72 | * @ap: port where the device is |
03c0e84f | 73 | * @status: pointer to a status value |
272f7884 | 74 | * |
03c0e84f SS |
75 | * Reads ATA alternate status register for currently-selected device |
76 | * and return its value. | |
272f7884 | 77 | * |
03c0e84f SS |
78 | * RETURN: |
79 | * true if the register exists, false if not. | |
272f7884 TH |
80 | * |
81 | * LOCKING: | |
82 | * Inherited from caller. | |
83 | */ | |
03c0e84f | 84 | static bool ata_sff_altstatus(struct ata_port *ap, u8 *status) |
624d5c51 | 85 | { |
03c0e84f SS |
86 | u8 tmp; |
87 | ||
88 | if (ap->ops->sff_check_altstatus) { | |
89 | tmp = ap->ops->sff_check_altstatus(ap); | |
90 | goto read; | |
91 | } | |
92 | if (ap->ioaddr.altstatus_addr) { | |
93 | tmp = ioread8(ap->ioaddr.altstatus_addr); | |
94 | goto read; | |
95 | } | |
96 | return false; | |
624d5c51 | 97 | |
03c0e84f SS |
98 | read: |
99 | if (status) | |
100 | *status = tmp; | |
101 | return true; | |
624d5c51 TH |
102 | } |
103 | ||
a57c1bad AC |
104 | /** |
105 | * ata_sff_irq_status - Check if the device is busy | |
106 | * @ap: port where the device is | |
107 | * | |
108 | * Determine if the port is currently busy. Uses altstatus | |
109 | * if available in order to avoid clearing shared IRQ status | |
110 | * when finding an IRQ source. Non ctl capable devices don't | |
111 | * share interrupt lines fortunately for us. | |
112 | * | |
113 | * LOCKING: | |
114 | * Inherited from caller. | |
115 | */ | |
116 | static u8 ata_sff_irq_status(struct ata_port *ap) | |
117 | { | |
118 | u8 status; | |
119 | ||
03c0e84f SS |
120 | /* Not us: We are busy */ |
121 | if (ata_sff_altstatus(ap, &status) && (status & ATA_BUSY)) | |
122 | return status; | |
a57c1bad | 123 | /* Clear INTRQ latch */ |
6311c90a | 124 | status = ap->ops->sff_check_status(ap); |
a57c1bad AC |
125 | return status; |
126 | } | |
127 | ||
128 | /** | |
129 | * ata_sff_sync - Flush writes | |
130 | * @ap: Port to wait for. | |
131 | * | |
132 | * CAUTION: | |
133 | * If we have an mmio device with no ctl and no altstatus | |
134 | * method this will fail. No such devices are known to exist. | |
135 | * | |
136 | * LOCKING: | |
137 | * Inherited from caller. | |
138 | */ | |
139 | ||
140 | static void ata_sff_sync(struct ata_port *ap) | |
141 | { | |
03c0e84f | 142 | ata_sff_altstatus(ap, NULL); |
a57c1bad AC |
143 | } |
144 | ||
145 | /** | |
146 | * ata_sff_pause - Flush writes and wait 400nS | |
147 | * @ap: Port to pause for. | |
148 | * | |
149 | * CAUTION: | |
150 | * If we have an mmio device with no ctl and no altstatus | |
151 | * method this will fail. No such devices are known to exist. | |
152 | * | |
153 | * LOCKING: | |
154 | * Inherited from caller. | |
155 | */ | |
156 | ||
157 | void ata_sff_pause(struct ata_port *ap) | |
158 | { | |
159 | ata_sff_sync(ap); | |
160 | ndelay(400); | |
161 | } | |
0fe40ff8 | 162 | EXPORT_SYMBOL_GPL(ata_sff_pause); |
a57c1bad AC |
163 | |
164 | /** | |
165 | * ata_sff_dma_pause - Pause before commencing DMA | |
166 | * @ap: Port to pause for. | |
167 | * | |
168 | * Perform I/O fencing and ensure sufficient cycle delays occur | |
169 | * for the HDMA1:0 transition | |
170 | */ | |
0fe40ff8 | 171 | |
a57c1bad AC |
172 | void ata_sff_dma_pause(struct ata_port *ap) |
173 | { | |
03c0e84f SS |
174 | /* |
175 | * An altstatus read will cause the needed delay without | |
176 | * messing up the IRQ status | |
177 | */ | |
178 | if (ata_sff_altstatus(ap, NULL)) | |
a57c1bad | 179 | return; |
a57c1bad AC |
180 | /* There are no DMA controllers without ctl. BUG here to ensure |
181 | we never violate the HDMA1:0 transition timing and risk | |
182 | corruption. */ | |
183 | BUG(); | |
184 | } | |
0fe40ff8 | 185 | EXPORT_SYMBOL_GPL(ata_sff_dma_pause); |
a57c1bad | 186 | |
aa2731ad TH |
187 | static int ata_sff_check_ready(struct ata_link *link) |
188 | { | |
189 | u8 status = link->ap->ops->sff_check_status(link->ap); | |
190 | ||
78ab88f0 | 191 | return ata_check_ready(status); |
aa2731ad TH |
192 | } |
193 | ||
624d5c51 | 194 | /** |
9363c382 | 195 | * ata_sff_wait_ready - sleep until BSY clears, or timeout |
705e76be | 196 | * @link: SFF link to wait ready status for |
624d5c51 TH |
197 | * @deadline: deadline jiffies for the operation |
198 | * | |
199 | * Sleep until ATA Status register bit BSY clears, or timeout | |
200 | * occurs. | |
201 | * | |
202 | * LOCKING: | |
203 | * Kernel thread context (may sleep). | |
204 | * | |
205 | * RETURNS: | |
206 | * 0 on success, -errno otherwise. | |
207 | */ | |
705e76be | 208 | int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline) |
624d5c51 | 209 | { |
aa2731ad | 210 | return ata_wait_ready(link, deadline, ata_sff_check_ready); |
624d5c51 | 211 | } |
0fe40ff8 | 212 | EXPORT_SYMBOL_GPL(ata_sff_wait_ready); |
624d5c51 | 213 | |
41dec29b SS |
214 | /** |
215 | * ata_sff_set_devctl - Write device control reg | |
216 | * @ap: port where the device is | |
217 | * @ctl: value to write | |
218 | * | |
4fc5f0aa | 219 | * Writes ATA device control register. |
41dec29b | 220 | * |
4fc5f0aa SS |
221 | * RETURN: |
222 | * true if the register exists, false if not. | |
41dec29b SS |
223 | * |
224 | * LOCKING: | |
225 | * Inherited from caller. | |
226 | */ | |
4fc5f0aa | 227 | static bool ata_sff_set_devctl(struct ata_port *ap, u8 ctl) |
41dec29b | 228 | { |
4fc5f0aa | 229 | if (ap->ops->sff_set_devctl) { |
41dec29b | 230 | ap->ops->sff_set_devctl(ap, ctl); |
4fc5f0aa SS |
231 | return true; |
232 | } | |
233 | if (ap->ioaddr.ctl_addr) { | |
41dec29b | 234 | iowrite8(ctl, ap->ioaddr.ctl_addr); |
4fc5f0aa SS |
235 | return true; |
236 | } | |
237 | ||
238 | return false; | |
41dec29b SS |
239 | } |
240 | ||
624d5c51 | 241 | /** |
9363c382 | 242 | * ata_sff_dev_select - Select device 0/1 on ATA bus |
624d5c51 TH |
243 | * @ap: ATA channel to manipulate |
244 | * @device: ATA device (numbered from zero) to select | |
245 | * | |
246 | * Use the method defined in the ATA specification to | |
247 | * make either device 0, or device 1, active on the | |
248 | * ATA channel. Works with both PIO and MMIO. | |
249 | * | |
250 | * May be used as the dev_select() entry in ata_port_operations. | |
251 | * | |
252 | * LOCKING: | |
253 | * caller. | |
254 | */ | |
9363c382 | 255 | void ata_sff_dev_select(struct ata_port *ap, unsigned int device) |
624d5c51 TH |
256 | { |
257 | u8 tmp; | |
258 | ||
259 | if (device == 0) | |
260 | tmp = ATA_DEVICE_OBS; | |
261 | else | |
262 | tmp = ATA_DEVICE_OBS | ATA_DEV1; | |
263 | ||
264 | iowrite8(tmp, ap->ioaddr.device_addr); | |
9363c382 | 265 | ata_sff_pause(ap); /* needed; also flushes, for mmio */ |
624d5c51 | 266 | } |
0fe40ff8 | 267 | EXPORT_SYMBOL_GPL(ata_sff_dev_select); |
624d5c51 TH |
268 | |
269 | /** | |
270 | * ata_dev_select - Select device 0/1 on ATA bus | |
271 | * @ap: ATA channel to manipulate | |
272 | * @device: ATA device (numbered from zero) to select | |
273 | * @wait: non-zero to wait for Status register BSY bit to clear | |
274 | * @can_sleep: non-zero if context allows sleeping | |
275 | * | |
276 | * Use the method defined in the ATA specification to | |
277 | * make either device 0, or device 1, active on the | |
278 | * ATA channel. | |
279 | * | |
9363c382 TH |
280 | * This is a high-level version of ata_sff_dev_select(), which |
281 | * additionally provides the services of inserting the proper | |
282 | * pauses and status polling, where needed. | |
624d5c51 TH |
283 | * |
284 | * LOCKING: | |
285 | * caller. | |
286 | */ | |
c7a8209f | 287 | static void ata_dev_select(struct ata_port *ap, unsigned int device, |
624d5c51 TH |
288 | unsigned int wait, unsigned int can_sleep) |
289 | { | |
624d5c51 TH |
290 | if (wait) |
291 | ata_wait_idle(ap); | |
292 | ||
5682ed33 | 293 | ap->ops->sff_dev_select(ap, device); |
624d5c51 TH |
294 | |
295 | if (wait) { | |
296 | if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI) | |
97750ceb | 297 | ata_msleep(ap, 150); |
624d5c51 TH |
298 | ata_wait_idle(ap); |
299 | } | |
300 | } | |
301 | ||
302 | /** | |
9363c382 | 303 | * ata_sff_irq_on - Enable interrupts on a port. |
624d5c51 TH |
304 | * @ap: Port on which interrupts are enabled. |
305 | * | |
306 | * Enable interrupts on a legacy IDE device using MMIO or PIO, | |
307 | * wait for idle, clear any pending interrupts. | |
308 | * | |
e42a542b SS |
309 | * Note: may NOT be used as the sff_irq_on() entry in |
310 | * ata_port_operations. | |
311 | * | |
624d5c51 TH |
312 | * LOCKING: |
313 | * Inherited from caller. | |
314 | */ | |
e42a542b | 315 | void ata_sff_irq_on(struct ata_port *ap) |
624d5c51 | 316 | { |
e42a542b SS |
317 | if (ap->ops->sff_irq_on) { |
318 | ap->ops->sff_irq_on(ap); | |
319 | return; | |
320 | } | |
624d5c51 TH |
321 | |
322 | ap->ctl &= ~ATA_NIEN; | |
323 | ap->last_ctl = ap->ctl; | |
324 | ||
4fc5f0aa | 325 | ata_sff_set_devctl(ap, ap->ctl); |
e42a542b | 326 | ata_wait_idle(ap); |
624d5c51 | 327 | |
37f65b8b TH |
328 | if (ap->ops->sff_irq_clear) |
329 | ap->ops->sff_irq_clear(ap); | |
624d5c51 | 330 | } |
0fe40ff8 | 331 | EXPORT_SYMBOL_GPL(ata_sff_irq_on); |
624d5c51 | 332 | |
624d5c51 | 333 | /** |
9363c382 | 334 | * ata_sff_tf_load - send taskfile registers to host controller |
624d5c51 TH |
335 | * @ap: Port to which output is sent |
336 | * @tf: ATA taskfile register set | |
337 | * | |
338 | * Outputs ATA taskfile to standard ATA host controller. | |
339 | * | |
340 | * LOCKING: | |
341 | * Inherited from caller. | |
342 | */ | |
9363c382 | 343 | void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
624d5c51 TH |
344 | { |
345 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
346 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
347 | ||
348 | if (tf->ctl != ap->last_ctl) { | |
349 | if (ioaddr->ctl_addr) | |
350 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
351 | ap->last_ctl = tf->ctl; | |
40c60230 | 352 | ata_wait_idle(ap); |
624d5c51 TH |
353 | } |
354 | ||
355 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
efcb3cf7 | 356 | WARN_ON_ONCE(!ioaddr->ctl_addr); |
624d5c51 TH |
357 | iowrite8(tf->hob_feature, ioaddr->feature_addr); |
358 | iowrite8(tf->hob_nsect, ioaddr->nsect_addr); | |
359 | iowrite8(tf->hob_lbal, ioaddr->lbal_addr); | |
360 | iowrite8(tf->hob_lbam, ioaddr->lbam_addr); | |
361 | iowrite8(tf->hob_lbah, ioaddr->lbah_addr); | |
624d5c51 TH |
362 | } |
363 | ||
364 | if (is_addr) { | |
365 | iowrite8(tf->feature, ioaddr->feature_addr); | |
366 | iowrite8(tf->nsect, ioaddr->nsect_addr); | |
367 | iowrite8(tf->lbal, ioaddr->lbal_addr); | |
368 | iowrite8(tf->lbam, ioaddr->lbam_addr); | |
369 | iowrite8(tf->lbah, ioaddr->lbah_addr); | |
624d5c51 TH |
370 | } |
371 | ||
c206a389 | 372 | if (tf->flags & ATA_TFLAG_DEVICE) |
624d5c51 | 373 | iowrite8(tf->device, ioaddr->device_addr); |
40c60230 TH |
374 | |
375 | ata_wait_idle(ap); | |
624d5c51 | 376 | } |
0fe40ff8 | 377 | EXPORT_SYMBOL_GPL(ata_sff_tf_load); |
624d5c51 TH |
378 | |
379 | /** | |
9363c382 | 380 | * ata_sff_tf_read - input device's ATA taskfile shadow registers |
624d5c51 TH |
381 | * @ap: Port from which input is read |
382 | * @tf: ATA taskfile register set for storing input | |
383 | * | |
384 | * Reads ATA taskfile registers for currently-selected device | |
385 | * into @tf. Assumes the device has a fully SFF compliant task file | |
386 | * layout and behaviour. If you device does not (eg has a different | |
387 | * status method) then you will need to provide a replacement tf_read | |
388 | * | |
389 | * LOCKING: | |
390 | * Inherited from caller. | |
391 | */ | |
9363c382 | 392 | void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
624d5c51 TH |
393 | { |
394 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
395 | ||
efcef265 SS |
396 | tf->status = ata_sff_check_status(ap); |
397 | tf->error = ioread8(ioaddr->error_addr); | |
624d5c51 TH |
398 | tf->nsect = ioread8(ioaddr->nsect_addr); |
399 | tf->lbal = ioread8(ioaddr->lbal_addr); | |
400 | tf->lbam = ioread8(ioaddr->lbam_addr); | |
401 | tf->lbah = ioread8(ioaddr->lbah_addr); | |
402 | tf->device = ioread8(ioaddr->device_addr); | |
403 | ||
404 | if (tf->flags & ATA_TFLAG_LBA48) { | |
405 | if (likely(ioaddr->ctl_addr)) { | |
406 | iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); | |
407 | tf->hob_feature = ioread8(ioaddr->error_addr); | |
408 | tf->hob_nsect = ioread8(ioaddr->nsect_addr); | |
409 | tf->hob_lbal = ioread8(ioaddr->lbal_addr); | |
410 | tf->hob_lbam = ioread8(ioaddr->lbam_addr); | |
411 | tf->hob_lbah = ioread8(ioaddr->lbah_addr); | |
412 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
413 | ap->last_ctl = tf->ctl; | |
414 | } else | |
efcb3cf7 | 415 | WARN_ON_ONCE(1); |
624d5c51 TH |
416 | } |
417 | } | |
0fe40ff8 | 418 | EXPORT_SYMBOL_GPL(ata_sff_tf_read); |
624d5c51 TH |
419 | |
420 | /** | |
9363c382 | 421 | * ata_sff_exec_command - issue ATA command to host controller |
624d5c51 TH |
422 | * @ap: port to which command is being issued |
423 | * @tf: ATA taskfile register set | |
424 | * | |
425 | * Issues ATA command, with proper synchronization with interrupt | |
426 | * handler / other threads. | |
427 | * | |
428 | * LOCKING: | |
429 | * spin_lock_irqsave(host lock) | |
430 | */ | |
9363c382 | 431 | void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) |
624d5c51 | 432 | { |
624d5c51 | 433 | iowrite8(tf->command, ap->ioaddr.command_addr); |
9363c382 | 434 | ata_sff_pause(ap); |
624d5c51 | 435 | } |
0fe40ff8 | 436 | EXPORT_SYMBOL_GPL(ata_sff_exec_command); |
624d5c51 TH |
437 | |
438 | /** | |
439 | * ata_tf_to_host - issue ATA taskfile to host controller | |
440 | * @ap: port to which command is being issued | |
441 | * @tf: ATA taskfile register set | |
c206a389 | 442 | * @tag: tag of the associated command |
624d5c51 TH |
443 | * |
444 | * Issues ATA taskfile register set to ATA host controller, | |
445 | * with proper synchronization with interrupt handler and | |
446 | * other threads. | |
447 | * | |
448 | * LOCKING: | |
449 | * spin_lock_irqsave(host lock) | |
450 | */ | |
451 | static inline void ata_tf_to_host(struct ata_port *ap, | |
c206a389 HR |
452 | const struct ata_taskfile *tf, |
453 | unsigned int tag) | |
624d5c51 | 454 | { |
c206a389 | 455 | trace_ata_tf_load(ap, tf); |
5682ed33 | 456 | ap->ops->sff_tf_load(ap, tf); |
c206a389 | 457 | trace_ata_exec_command(ap, tf, tag); |
5682ed33 | 458 | ap->ops->sff_exec_command(ap, tf); |
624d5c51 TH |
459 | } |
460 | ||
461 | /** | |
9363c382 | 462 | * ata_sff_data_xfer - Transfer data by PIO |
989e0aac | 463 | * @qc: queued command |
624d5c51 TH |
464 | * @buf: data buffer |
465 | * @buflen: buffer length | |
466 | * @rw: read/write | |
467 | * | |
468 | * Transfer data from/to the device data register by PIO. | |
469 | * | |
470 | * LOCKING: | |
471 | * Inherited from caller. | |
472 | * | |
473 | * RETURNS: | |
474 | * Bytes consumed. | |
475 | */ | |
989e0aac | 476 | unsigned int ata_sff_data_xfer(struct ata_queued_cmd *qc, unsigned char *buf, |
9363c382 | 477 | unsigned int buflen, int rw) |
624d5c51 | 478 | { |
989e0aac | 479 | struct ata_port *ap = qc->dev->link->ap; |
624d5c51 TH |
480 | void __iomem *data_addr = ap->ioaddr.data_addr; |
481 | unsigned int words = buflen >> 1; | |
482 | ||
483 | /* Transfer multiple of 2 bytes */ | |
484 | if (rw == READ) | |
485 | ioread16_rep(data_addr, buf, words); | |
486 | else | |
487 | iowrite16_rep(data_addr, buf, words); | |
488 | ||
2102d749 | 489 | /* Transfer trailing byte, if any. */ |
624d5c51 | 490 | if (unlikely(buflen & 0x01)) { |
21dba244 | 491 | unsigned char pad[2] = { }; |
624d5c51 | 492 | |
2102d749 SS |
493 | /* Point buf to the tail of buffer */ |
494 | buf += buflen - 1; | |
495 | ||
496 | /* | |
497 | * Use io*16_rep() accessors here as well to avoid pointlessly | |
972b94ff | 498 | * swapping bytes to and from on the big endian machines... |
2102d749 | 499 | */ |
624d5c51 | 500 | if (rw == READ) { |
2102d749 SS |
501 | ioread16_rep(data_addr, pad, 1); |
502 | *buf = pad[0]; | |
624d5c51 | 503 | } else { |
2102d749 SS |
504 | pad[0] = *buf; |
505 | iowrite16_rep(data_addr, pad, 1); | |
624d5c51 TH |
506 | } |
507 | words++; | |
508 | } | |
509 | ||
510 | return words << 1; | |
511 | } | |
0fe40ff8 | 512 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer); |
624d5c51 | 513 | |
871af121 AC |
514 | /** |
515 | * ata_sff_data_xfer32 - Transfer data by PIO | |
989e0aac | 516 | * @qc: queued command |
871af121 AC |
517 | * @buf: data buffer |
518 | * @buflen: buffer length | |
519 | * @rw: read/write | |
520 | * | |
521 | * Transfer data from/to the device data register by PIO using 32bit | |
522 | * I/O operations. | |
523 | * | |
524 | * LOCKING: | |
525 | * Inherited from caller. | |
526 | * | |
527 | * RETURNS: | |
528 | * Bytes consumed. | |
529 | */ | |
530 | ||
989e0aac | 531 | unsigned int ata_sff_data_xfer32(struct ata_queued_cmd *qc, unsigned char *buf, |
871af121 AC |
532 | unsigned int buflen, int rw) |
533 | { | |
989e0aac | 534 | struct ata_device *dev = qc->dev; |
871af121 AC |
535 | struct ata_port *ap = dev->link->ap; |
536 | void __iomem *data_addr = ap->ioaddr.data_addr; | |
537 | unsigned int words = buflen >> 2; | |
538 | int slop = buflen & 3; | |
972b94ff | 539 | |
e3cf95dd | 540 | if (!(ap->pflags & ATA_PFLAG_PIO32)) |
989e0aac | 541 | return ata_sff_data_xfer(qc, buf, buflen, rw); |
871af121 AC |
542 | |
543 | /* Transfer multiple of 4 bytes */ | |
544 | if (rw == READ) | |
545 | ioread32_rep(data_addr, buf, words); | |
546 | else | |
547 | iowrite32_rep(data_addr, buf, words); | |
548 | ||
d1b3525b | 549 | /* Transfer trailing bytes, if any */ |
871af121 | 550 | if (unlikely(slop)) { |
21dba244 | 551 | unsigned char pad[4] = { }; |
d1b3525b SS |
552 | |
553 | /* Point buf to the tail of buffer */ | |
554 | buf += buflen - slop; | |
555 | ||
556 | /* | |
557 | * Use io*_rep() accessors here as well to avoid pointlessly | |
972b94ff | 558 | * swapping bytes to and from on the big endian machines... |
d1b3525b | 559 | */ |
871af121 | 560 | if (rw == READ) { |
d1b3525b SS |
561 | if (slop < 3) |
562 | ioread16_rep(data_addr, pad, 1); | |
563 | else | |
564 | ioread32_rep(data_addr, pad, 1); | |
565 | memcpy(buf, pad, slop); | |
871af121 | 566 | } else { |
d1b3525b SS |
567 | memcpy(pad, buf, slop); |
568 | if (slop < 3) | |
569 | iowrite16_rep(data_addr, pad, 1); | |
570 | else | |
571 | iowrite32_rep(data_addr, pad, 1); | |
871af121 | 572 | } |
871af121 | 573 | } |
d1b3525b | 574 | return (buflen + 1) & ~1; |
871af121 AC |
575 | } |
576 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer32); | |
577 | ||
ecef6a9e CH |
578 | static void ata_pio_xfer(struct ata_queued_cmd *qc, struct page *page, |
579 | unsigned int offset, size_t xfer_size) | |
580 | { | |
581 | bool do_write = (qc->tf.flags & ATA_TFLAG_WRITE); | |
582 | unsigned char *buf; | |
583 | ||
584 | buf = kmap_atomic(page); | |
585 | qc->ap->ops->sff_data_xfer(qc, buf + offset, xfer_size, do_write); | |
586 | kunmap_atomic(buf); | |
587 | ||
588 | if (!do_write && !PageSlab(page)) | |
589 | flush_dcache_page(page); | |
590 | } | |
591 | ||
624d5c51 TH |
592 | /** |
593 | * ata_pio_sector - Transfer a sector of data. | |
594 | * @qc: Command on going | |
595 | * | |
596 | * Transfer qc->sect_size bytes of data from/to the ATA device. | |
597 | * | |
598 | * LOCKING: | |
599 | * Inherited from caller. | |
600 | */ | |
601 | static void ata_pio_sector(struct ata_queued_cmd *qc) | |
602 | { | |
624d5c51 TH |
603 | struct ata_port *ap = qc->ap; |
604 | struct page *page; | |
605 | unsigned int offset; | |
624d5c51 | 606 | |
752ead44 JA |
607 | if (!qc->cursg) { |
608 | qc->curbytes = qc->nbytes; | |
609 | return; | |
610 | } | |
624d5c51 TH |
611 | if (qc->curbytes == qc->nbytes - qc->sect_size) |
612 | ap->hsm_task_state = HSM_ST_LAST; | |
613 | ||
614 | page = sg_page(qc->cursg); | |
615 | offset = qc->cursg->offset + qc->cursg_ofs; | |
616 | ||
617 | /* get the current page and offset */ | |
618 | page = nth_page(page, (offset >> PAGE_SHIFT)); | |
619 | offset %= PAGE_SIZE; | |
620 | ||
7fad6ad6 | 621 | trace_ata_sff_pio_transfer_data(qc, offset, qc->sect_size); |
624d5c51 | 622 | |
ecef6a9e CH |
623 | /* |
624 | * Split the transfer when it splits a page boundary. Note that the | |
625 | * split still has to be dword aligned like all ATA data transfers. | |
626 | */ | |
627 | WARN_ON_ONCE(offset % 4); | |
628 | if (offset + qc->sect_size > PAGE_SIZE) { | |
629 | unsigned int split_len = PAGE_SIZE - offset; | |
630 | ||
631 | ata_pio_xfer(qc, page, offset, split_len); | |
632 | ata_pio_xfer(qc, nth_page(page, 1), 0, | |
633 | qc->sect_size - split_len); | |
634 | } else { | |
635 | ata_pio_xfer(qc, page, offset, qc->sect_size); | |
636 | } | |
2d68b7fe | 637 | |
624d5c51 TH |
638 | qc->curbytes += qc->sect_size; |
639 | qc->cursg_ofs += qc->sect_size; | |
640 | ||
641 | if (qc->cursg_ofs == qc->cursg->length) { | |
642 | qc->cursg = sg_next(qc->cursg); | |
752ead44 JA |
643 | if (!qc->cursg) |
644 | ap->hsm_task_state = HSM_ST_LAST; | |
624d5c51 TH |
645 | qc->cursg_ofs = 0; |
646 | } | |
647 | } | |
648 | ||
649 | /** | |
650 | * ata_pio_sectors - Transfer one or many sectors. | |
651 | * @qc: Command on going | |
652 | * | |
653 | * Transfer one or many sectors of data from/to the | |
654 | * ATA device for the DRQ request. | |
655 | * | |
656 | * LOCKING: | |
657 | * Inherited from caller. | |
658 | */ | |
659 | static void ata_pio_sectors(struct ata_queued_cmd *qc) | |
660 | { | |
661 | if (is_multi_taskfile(&qc->tf)) { | |
662 | /* READ/WRITE MULTIPLE */ | |
663 | unsigned int nsect; | |
664 | ||
efcb3cf7 | 665 | WARN_ON_ONCE(qc->dev->multi_count == 0); |
624d5c51 TH |
666 | |
667 | nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size, | |
668 | qc->dev->multi_count); | |
669 | while (nsect--) | |
670 | ata_pio_sector(qc); | |
671 | } else | |
672 | ata_pio_sector(qc); | |
673 | ||
a57c1bad | 674 | ata_sff_sync(qc->ap); /* flush */ |
624d5c51 TH |
675 | } |
676 | ||
677 | /** | |
678 | * atapi_send_cdb - Write CDB bytes to hardware | |
679 | * @ap: Port to which ATAPI device is attached. | |
680 | * @qc: Taskfile currently active | |
681 | * | |
682 | * When device has indicated its readiness to accept | |
683 | * a CDB, this function is called. Send the CDB. | |
684 | * | |
685 | * LOCKING: | |
686 | * caller. | |
687 | */ | |
688 | static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc) | |
689 | { | |
690 | /* send SCSI cdb */ | |
7fad6ad6 | 691 | trace_atapi_send_cdb(qc, 0, qc->dev->cdb_len); |
efcb3cf7 | 692 | WARN_ON_ONCE(qc->dev->cdb_len < 12); |
624d5c51 | 693 | |
989e0aac | 694 | ap->ops->sff_data_xfer(qc, qc->cdb, qc->dev->cdb_len, 1); |
a57c1bad AC |
695 | ata_sff_sync(ap); |
696 | /* FIXME: If the CDB is for DMA do we need to do the transition delay | |
697 | or is bmdma_start guaranteed to do it ? */ | |
624d5c51 TH |
698 | switch (qc->tf.protocol) { |
699 | case ATAPI_PROT_PIO: | |
700 | ap->hsm_task_state = HSM_ST; | |
701 | break; | |
702 | case ATAPI_PROT_NODATA: | |
703 | ap->hsm_task_state = HSM_ST_LAST; | |
704 | break; | |
9a7780c9 | 705 | #ifdef CONFIG_ATA_BMDMA |
624d5c51 TH |
706 | case ATAPI_PROT_DMA: |
707 | ap->hsm_task_state = HSM_ST_LAST; | |
708 | /* initiate bmdma */ | |
c206a389 | 709 | trace_ata_bmdma_start(ap, &qc->tf, qc->tag); |
624d5c51 TH |
710 | ap->ops->bmdma_start(qc); |
711 | break; | |
9a7780c9 TH |
712 | #endif /* CONFIG_ATA_BMDMA */ |
713 | default: | |
714 | BUG(); | |
624d5c51 TH |
715 | } |
716 | } | |
717 | ||
718 | /** | |
719 | * __atapi_pio_bytes - Transfer data from/to the ATAPI device. | |
720 | * @qc: Command on going | |
721 | * @bytes: number of bytes | |
722 | * | |
03070458 | 723 | * Transfer data from/to the ATAPI device. |
624d5c51 TH |
724 | * |
725 | * LOCKING: | |
726 | * Inherited from caller. | |
727 | * | |
728 | */ | |
729 | static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes) | |
730 | { | |
731 | int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ; | |
732 | struct ata_port *ap = qc->ap; | |
733 | struct ata_device *dev = qc->dev; | |
734 | struct ata_eh_info *ehi = &dev->link->eh_info; | |
735 | struct scatterlist *sg; | |
736 | struct page *page; | |
737 | unsigned char *buf; | |
738 | unsigned int offset, count, consumed; | |
739 | ||
740 | next_sg: | |
741 | sg = qc->cursg; | |
742 | if (unlikely(!sg)) { | |
743 | ata_ehi_push_desc(ehi, "unexpected or too much trailing data " | |
744 | "buf=%u cur=%u bytes=%u", | |
745 | qc->nbytes, qc->curbytes, bytes); | |
746 | return -1; | |
747 | } | |
748 | ||
749 | page = sg_page(sg); | |
750 | offset = sg->offset + qc->cursg_ofs; | |
751 | ||
752 | /* get the current page and offset */ | |
753 | page = nth_page(page, (offset >> PAGE_SHIFT)); | |
754 | offset %= PAGE_SIZE; | |
755 | ||
756 | /* don't overrun current sg */ | |
757 | count = min(sg->length - qc->cursg_ofs, bytes); | |
758 | ||
759 | /* don't cross page boundaries */ | |
760 | count = min(count, (unsigned int)PAGE_SIZE - offset); | |
761 | ||
7fad6ad6 | 762 | trace_atapi_pio_transfer_data(qc, offset, count); |
624d5c51 | 763 | |
5d7a288c TA |
764 | /* do the actual data transfer */ |
765 | buf = kmap_atomic(page); | |
766 | consumed = ap->ops->sff_data_xfer(qc, buf + offset, count, rw); | |
767 | kunmap_atomic(buf); | |
624d5c51 TH |
768 | |
769 | bytes -= min(bytes, consumed); | |
770 | qc->curbytes += count; | |
771 | qc->cursg_ofs += count; | |
772 | ||
773 | if (qc->cursg_ofs == sg->length) { | |
774 | qc->cursg = sg_next(qc->cursg); | |
775 | qc->cursg_ofs = 0; | |
776 | } | |
777 | ||
a0f79f7a CB |
778 | /* |
779 | * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed); | |
780 | * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN | |
781 | * check correctly as it doesn't know if it is the last request being | |
782 | * made. Somebody should implement a proper sanity check. | |
783 | */ | |
624d5c51 TH |
784 | if (bytes) |
785 | goto next_sg; | |
786 | return 0; | |
787 | } | |
788 | ||
789 | /** | |
790 | * atapi_pio_bytes - Transfer data from/to the ATAPI device. | |
791 | * @qc: Command on going | |
792 | * | |
793 | * Transfer Transfer data from/to the ATAPI device. | |
794 | * | |
795 | * LOCKING: | |
796 | * Inherited from caller. | |
797 | */ | |
798 | static void atapi_pio_bytes(struct ata_queued_cmd *qc) | |
799 | { | |
800 | struct ata_port *ap = qc->ap; | |
801 | struct ata_device *dev = qc->dev; | |
802 | struct ata_eh_info *ehi = &dev->link->eh_info; | |
803 | unsigned int ireason, bc_lo, bc_hi, bytes; | |
804 | int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0; | |
805 | ||
806 | /* Abuse qc->result_tf for temp storage of intermediate TF | |
807 | * here to save some kernel stack usage. | |
808 | * For normal completion, qc->result_tf is not relevant. For | |
809 | * error, qc->result_tf is later overwritten by ata_qc_complete(). | |
810 | * So, the correctness of qc->result_tf is not affected. | |
811 | */ | |
5682ed33 | 812 | ap->ops->sff_tf_read(ap, &qc->result_tf); |
624d5c51 TH |
813 | ireason = qc->result_tf.nsect; |
814 | bc_lo = qc->result_tf.lbam; | |
815 | bc_hi = qc->result_tf.lbah; | |
816 | bytes = (bc_hi << 8) | bc_lo; | |
817 | ||
818 | /* shall be cleared to zero, indicating xfer of data */ | |
002ae084 | 819 | if (unlikely(ireason & ATAPI_COD)) |
624d5c51 TH |
820 | goto atapi_check; |
821 | ||
822 | /* make sure transfer direction matches expected */ | |
002ae084 | 823 | i_write = ((ireason & ATAPI_IO) == 0) ? 1 : 0; |
624d5c51 TH |
824 | if (unlikely(do_write != i_write)) |
825 | goto atapi_check; | |
826 | ||
827 | if (unlikely(!bytes)) | |
828 | goto atapi_check; | |
829 | ||
624d5c51 TH |
830 | if (unlikely(__atapi_pio_bytes(qc, bytes))) |
831 | goto err_out; | |
a57c1bad | 832 | ata_sff_sync(ap); /* flush */ |
624d5c51 TH |
833 | |
834 | return; | |
835 | ||
836 | atapi_check: | |
837 | ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)", | |
838 | ireason, bytes); | |
839 | err_out: | |
840 | qc->err_mask |= AC_ERR_HSM; | |
841 | ap->hsm_task_state = HSM_ST_ERR; | |
842 | } | |
843 | ||
844 | /** | |
845 | * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue. | |
846 | * @ap: the target ata_port | |
847 | * @qc: qc on going | |
848 | * | |
849 | * RETURNS: | |
850 | * 1 if ok in workqueue, 0 otherwise. | |
851 | */ | |
0fe40ff8 AC |
852 | static inline int ata_hsm_ok_in_wq(struct ata_port *ap, |
853 | struct ata_queued_cmd *qc) | |
624d5c51 TH |
854 | { |
855 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
856 | return 1; | |
857 | ||
858 | if (ap->hsm_task_state == HSM_ST_FIRST) { | |
859 | if (qc->tf.protocol == ATA_PROT_PIO && | |
0fe40ff8 | 860 | (qc->tf.flags & ATA_TFLAG_WRITE)) |
624d5c51 TH |
861 | return 1; |
862 | ||
863 | if (ata_is_atapi(qc->tf.protocol) && | |
0fe40ff8 | 864 | !(qc->dev->flags & ATA_DFLAG_CDB_INTR)) |
624d5c51 TH |
865 | return 1; |
866 | } | |
867 | ||
868 | return 0; | |
869 | } | |
870 | ||
871 | /** | |
872 | * ata_hsm_qc_complete - finish a qc running on standard HSM | |
873 | * @qc: Command to complete | |
874 | * @in_wq: 1 if called from workqueue, 0 otherwise | |
875 | * | |
876 | * Finish @qc which is running on standard HSM. | |
877 | * | |
878 | * LOCKING: | |
879 | * If @in_wq is zero, spin_lock_irqsave(host lock). | |
880 | * Otherwise, none on entry and grabs host lock. | |
881 | */ | |
882 | static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq) | |
883 | { | |
884 | struct ata_port *ap = qc->ap; | |
624d5c51 TH |
885 | |
886 | if (ap->ops->error_handler) { | |
887 | if (in_wq) { | |
624d5c51 TH |
888 | /* EH might have kicked in while host lock is |
889 | * released. | |
890 | */ | |
891 | qc = ata_qc_from_tag(ap, qc->tag); | |
892 | if (qc) { | |
893 | if (likely(!(qc->err_mask & AC_ERR_HSM))) { | |
e42a542b | 894 | ata_sff_irq_on(ap); |
624d5c51 TH |
895 | ata_qc_complete(qc); |
896 | } else | |
897 | ata_port_freeze(ap); | |
898 | } | |
624d5c51 TH |
899 | } else { |
900 | if (likely(!(qc->err_mask & AC_ERR_HSM))) | |
901 | ata_qc_complete(qc); | |
902 | else | |
903 | ata_port_freeze(ap); | |
904 | } | |
905 | } else { | |
906 | if (in_wq) { | |
e42a542b | 907 | ata_sff_irq_on(ap); |
624d5c51 | 908 | ata_qc_complete(qc); |
624d5c51 TH |
909 | } else |
910 | ata_qc_complete(qc); | |
911 | } | |
912 | } | |
913 | ||
914 | /** | |
9363c382 | 915 | * ata_sff_hsm_move - move the HSM to the next state. |
624d5c51 TH |
916 | * @ap: the target ata_port |
917 | * @qc: qc on going | |
918 | * @status: current device status | |
919 | * @in_wq: 1 if called from workqueue, 0 otherwise | |
920 | * | |
921 | * RETURNS: | |
922 | * 1 when poll next status needed, 0 otherwise. | |
923 | */ | |
9363c382 TH |
924 | int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc, |
925 | u8 status, int in_wq) | |
624d5c51 | 926 | { |
ea3c6450 GG |
927 | struct ata_link *link = qc->dev->link; |
928 | struct ata_eh_info *ehi = &link->eh_info; | |
624d5c51 TH |
929 | int poll_next; |
930 | ||
8eee1d3e TH |
931 | lockdep_assert_held(ap->lock); |
932 | ||
efcb3cf7 | 933 | WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0); |
624d5c51 | 934 | |
9363c382 | 935 | /* Make sure ata_sff_qc_issue() does not throw things |
624d5c51 TH |
936 | * like DMA polling into the workqueue. Notice that |
937 | * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING). | |
938 | */ | |
efcb3cf7 | 939 | WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc)); |
624d5c51 TH |
940 | |
941 | fsm_start: | |
7fad6ad6 | 942 | trace_ata_sff_hsm_state(qc, status); |
624d5c51 TH |
943 | |
944 | switch (ap->hsm_task_state) { | |
945 | case HSM_ST_FIRST: | |
946 | /* Send first data block or PACKET CDB */ | |
947 | ||
948 | /* If polling, we will stay in the work queue after | |
949 | * sending the data. Otherwise, interrupt handler | |
950 | * takes over after sending the data. | |
951 | */ | |
952 | poll_next = (qc->tf.flags & ATA_TFLAG_POLLING); | |
953 | ||
954 | /* check device status */ | |
955 | if (unlikely((status & ATA_DRQ) == 0)) { | |
956 | /* handle BSY=0, DRQ=0 as error */ | |
957 | if (likely(status & (ATA_ERR | ATA_DF))) | |
958 | /* device stops HSM for abort/error */ | |
959 | qc->err_mask |= AC_ERR_DEV; | |
a836d3e8 | 960 | else { |
624d5c51 | 961 | /* HSM violation. Let EH handle this */ |
a836d3e8 TH |
962 | ata_ehi_push_desc(ehi, |
963 | "ST_FIRST: !(DRQ|ERR|DF)"); | |
624d5c51 | 964 | qc->err_mask |= AC_ERR_HSM; |
a836d3e8 | 965 | } |
624d5c51 TH |
966 | |
967 | ap->hsm_task_state = HSM_ST_ERR; | |
968 | goto fsm_start; | |
969 | } | |
970 | ||
971 | /* Device should not ask for data transfer (DRQ=1) | |
972 | * when it finds something wrong. | |
973 | * We ignore DRQ here and stop the HSM by | |
974 | * changing hsm_task_state to HSM_ST_ERR and | |
975 | * let the EH abort the command or reset the device. | |
976 | */ | |
977 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
978 | /* Some ATAPI tape drives forget to clear the ERR bit | |
979 | * when doing the next command (mostly request sense). | |
980 | * We ignore ERR here to workaround and proceed sending | |
981 | * the CDB. | |
982 | */ | |
983 | if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) { | |
a836d3e8 TH |
984 | ata_ehi_push_desc(ehi, "ST_FIRST: " |
985 | "DRQ=1 with device error, " | |
986 | "dev_stat 0x%X", status); | |
624d5c51 TH |
987 | qc->err_mask |= AC_ERR_HSM; |
988 | ap->hsm_task_state = HSM_ST_ERR; | |
989 | goto fsm_start; | |
990 | } | |
991 | } | |
992 | ||
624d5c51 TH |
993 | if (qc->tf.protocol == ATA_PROT_PIO) { |
994 | /* PIO data out protocol. | |
995 | * send first data block. | |
996 | */ | |
997 | ||
998 | /* ata_pio_sectors() might change the state | |
999 | * to HSM_ST_LAST. so, the state is changed here | |
1000 | * before ata_pio_sectors(). | |
1001 | */ | |
1002 | ap->hsm_task_state = HSM_ST; | |
1003 | ata_pio_sectors(qc); | |
1004 | } else | |
1005 | /* send CDB */ | |
1006 | atapi_send_cdb(ap, qc); | |
1007 | ||
c429137a | 1008 | /* if polling, ata_sff_pio_task() handles the rest. |
624d5c51 TH |
1009 | * otherwise, interrupt handler takes over from here. |
1010 | */ | |
1011 | break; | |
1012 | ||
1013 | case HSM_ST: | |
1014 | /* complete command or read/write the data register */ | |
1015 | if (qc->tf.protocol == ATAPI_PROT_PIO) { | |
1016 | /* ATAPI PIO protocol */ | |
1017 | if ((status & ATA_DRQ) == 0) { | |
1018 | /* No more data to transfer or device error. | |
1019 | * Device error will be tagged in HSM_ST_LAST. | |
1020 | */ | |
1021 | ap->hsm_task_state = HSM_ST_LAST; | |
1022 | goto fsm_start; | |
1023 | } | |
1024 | ||
1025 | /* Device should not ask for data transfer (DRQ=1) | |
1026 | * when it finds something wrong. | |
1027 | * We ignore DRQ here and stop the HSM by | |
1028 | * changing hsm_task_state to HSM_ST_ERR and | |
1029 | * let the EH abort the command or reset the device. | |
1030 | */ | |
1031 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
a836d3e8 TH |
1032 | ata_ehi_push_desc(ehi, "ST-ATAPI: " |
1033 | "DRQ=1 with device error, " | |
1034 | "dev_stat 0x%X", status); | |
624d5c51 TH |
1035 | qc->err_mask |= AC_ERR_HSM; |
1036 | ap->hsm_task_state = HSM_ST_ERR; | |
1037 | goto fsm_start; | |
1038 | } | |
1039 | ||
1040 | atapi_pio_bytes(qc); | |
1041 | ||
1042 | if (unlikely(ap->hsm_task_state == HSM_ST_ERR)) | |
1043 | /* bad ireason reported by device */ | |
1044 | goto fsm_start; | |
1045 | ||
1046 | } else { | |
1047 | /* ATA PIO protocol */ | |
1048 | if (unlikely((status & ATA_DRQ) == 0)) { | |
1049 | /* handle BSY=0, DRQ=0 as error */ | |
6a6b97d3 | 1050 | if (likely(status & (ATA_ERR | ATA_DF))) { |
624d5c51 TH |
1051 | /* device stops HSM for abort/error */ |
1052 | qc->err_mask |= AC_ERR_DEV; | |
6a6b97d3 TH |
1053 | |
1054 | /* If diagnostic failed and this is | |
1055 | * IDENTIFY, it's likely a phantom | |
1056 | * device. Mark hint. | |
1057 | */ | |
1058 | if (qc->dev->horkage & | |
1059 | ATA_HORKAGE_DIAGNOSTIC) | |
1060 | qc->err_mask |= | |
1061 | AC_ERR_NODEV_HINT; | |
1062 | } else { | |
624d5c51 TH |
1063 | /* HSM violation. Let EH handle this. |
1064 | * Phantom devices also trigger this | |
1065 | * condition. Mark hint. | |
1066 | */ | |
a836d3e8 | 1067 | ata_ehi_push_desc(ehi, "ST-ATA: " |
80ee6f54 | 1068 | "DRQ=0 without device error, " |
a836d3e8 | 1069 | "dev_stat 0x%X", status); |
624d5c51 TH |
1070 | qc->err_mask |= AC_ERR_HSM | |
1071 | AC_ERR_NODEV_HINT; | |
a836d3e8 | 1072 | } |
624d5c51 TH |
1073 | |
1074 | ap->hsm_task_state = HSM_ST_ERR; | |
1075 | goto fsm_start; | |
1076 | } | |
1077 | ||
1078 | /* For PIO reads, some devices may ask for | |
1079 | * data transfer (DRQ=1) alone with ERR=1. | |
1080 | * We respect DRQ here and transfer one | |
1081 | * block of junk data before changing the | |
1082 | * hsm_task_state to HSM_ST_ERR. | |
1083 | * | |
1084 | * For PIO writes, ERR=1 DRQ=1 doesn't make | |
1085 | * sense since the data block has been | |
1086 | * transferred to the device. | |
1087 | */ | |
1088 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
1089 | /* data might be corrputed */ | |
1090 | qc->err_mask |= AC_ERR_DEV; | |
1091 | ||
1092 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) { | |
1093 | ata_pio_sectors(qc); | |
1094 | status = ata_wait_idle(ap); | |
1095 | } | |
1096 | ||
a836d3e8 TH |
1097 | if (status & (ATA_BUSY | ATA_DRQ)) { |
1098 | ata_ehi_push_desc(ehi, "ST-ATA: " | |
1099 | "BUSY|DRQ persists on ERR|DF, " | |
1100 | "dev_stat 0x%X", status); | |
624d5c51 | 1101 | qc->err_mask |= AC_ERR_HSM; |
a836d3e8 | 1102 | } |
624d5c51 | 1103 | |
b919930c TH |
1104 | /* There are oddball controllers with |
1105 | * status register stuck at 0x7f and | |
1106 | * lbal/m/h at zero which makes it | |
1107 | * pass all other presence detection | |
1108 | * mechanisms we have. Set NODEV_HINT | |
1109 | * for it. Kernel bz#7241. | |
1110 | */ | |
1111 | if (status == 0x7f) | |
1112 | qc->err_mask |= AC_ERR_NODEV_HINT; | |
1113 | ||
624d5c51 TH |
1114 | /* ata_pio_sectors() might change the |
1115 | * state to HSM_ST_LAST. so, the state | |
1116 | * is changed after ata_pio_sectors(). | |
1117 | */ | |
1118 | ap->hsm_task_state = HSM_ST_ERR; | |
1119 | goto fsm_start; | |
1120 | } | |
1121 | ||
1122 | ata_pio_sectors(qc); | |
1123 | ||
1124 | if (ap->hsm_task_state == HSM_ST_LAST && | |
1125 | (!(qc->tf.flags & ATA_TFLAG_WRITE))) { | |
1126 | /* all data read */ | |
1127 | status = ata_wait_idle(ap); | |
1128 | goto fsm_start; | |
1129 | } | |
1130 | } | |
1131 | ||
1132 | poll_next = 1; | |
1133 | break; | |
1134 | ||
1135 | case HSM_ST_LAST: | |
1136 | if (unlikely(!ata_ok(status))) { | |
1137 | qc->err_mask |= __ac_err_mask(status); | |
1138 | ap->hsm_task_state = HSM_ST_ERR; | |
1139 | goto fsm_start; | |
1140 | } | |
1141 | ||
1142 | /* no more data to transfer */ | |
7fad6ad6 | 1143 | trace_ata_sff_hsm_command_complete(qc, status); |
624d5c51 | 1144 | |
efcb3cf7 | 1145 | WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM)); |
624d5c51 TH |
1146 | |
1147 | ap->hsm_task_state = HSM_ST_IDLE; | |
1148 | ||
1149 | /* complete taskfile transaction */ | |
1150 | ata_hsm_qc_complete(qc, in_wq); | |
1151 | ||
1152 | poll_next = 0; | |
1153 | break; | |
1154 | ||
1155 | case HSM_ST_ERR: | |
624d5c51 TH |
1156 | ap->hsm_task_state = HSM_ST_IDLE; |
1157 | ||
1158 | /* complete taskfile transaction */ | |
1159 | ata_hsm_qc_complete(qc, in_wq); | |
1160 | ||
1161 | poll_next = 0; | |
1162 | break; | |
1163 | default: | |
1164 | poll_next = 0; | |
a588afc9 TH |
1165 | WARN(true, "ata%d: SFF host state machine in invalid state %d", |
1166 | ap->print_id, ap->hsm_task_state); | |
624d5c51 TH |
1167 | } |
1168 | ||
1169 | return poll_next; | |
1170 | } | |
0fe40ff8 | 1171 | EXPORT_SYMBOL_GPL(ata_sff_hsm_move); |
624d5c51 | 1172 | |
64b97594 VK |
1173 | void ata_sff_queue_work(struct work_struct *work) |
1174 | { | |
1175 | queue_work(ata_sff_wq, work); | |
1176 | } | |
1177 | EXPORT_SYMBOL_GPL(ata_sff_queue_work); | |
1178 | ||
1179 | void ata_sff_queue_delayed_work(struct delayed_work *dwork, unsigned long delay) | |
1180 | { | |
1181 | queue_delayed_work(ata_sff_wq, dwork, delay); | |
1182 | } | |
1183 | EXPORT_SYMBOL_GPL(ata_sff_queue_delayed_work); | |
1184 | ||
ea3c6450 | 1185 | void ata_sff_queue_pio_task(struct ata_link *link, unsigned long delay) |
c429137a | 1186 | { |
ea3c6450 GG |
1187 | struct ata_port *ap = link->ap; |
1188 | ||
1189 | WARN_ON((ap->sff_pio_task_link != NULL) && | |
1190 | (ap->sff_pio_task_link != link)); | |
1191 | ap->sff_pio_task_link = link; | |
1192 | ||
c429137a | 1193 | /* may fail if ata_sff_flush_pio_task() in progress */ |
64b97594 | 1194 | ata_sff_queue_delayed_work(&ap->sff_pio_task, msecs_to_jiffies(delay)); |
c429137a TH |
1195 | } |
1196 | EXPORT_SYMBOL_GPL(ata_sff_queue_pio_task); | |
1197 | ||
1198 | void ata_sff_flush_pio_task(struct ata_port *ap) | |
1199 | { | |
7fad6ad6 | 1200 | trace_ata_sff_flush_pio_task(ap); |
c429137a | 1201 | |
afe2c511 | 1202 | cancel_delayed_work_sync(&ap->sff_pio_task); |
ce751452 DJ |
1203 | |
1204 | /* | |
1205 | * We wanna reset the HSM state to IDLE. If we do so without | |
1206 | * grabbing the port lock, critical sections protected by it which | |
1207 | * expect the HSM state to stay stable may get surprised. For | |
1208 | * example, we may set IDLE in between the time | |
1209 | * __ata_sff_port_intr() checks for HSM_ST_IDLE and before it calls | |
1210 | * ata_sff_hsm_move() causing ata_sff_hsm_move() to BUG(). | |
1211 | */ | |
1212 | spin_lock_irq(ap->lock); | |
c429137a | 1213 | ap->hsm_task_state = HSM_ST_IDLE; |
ce751452 DJ |
1214 | spin_unlock_irq(ap->lock); |
1215 | ||
d4d8eaff | 1216 | ap->sff_pio_task_link = NULL; |
c429137a TH |
1217 | } |
1218 | ||
1219 | static void ata_sff_pio_task(struct work_struct *work) | |
624d5c51 TH |
1220 | { |
1221 | struct ata_port *ap = | |
c429137a | 1222 | container_of(work, struct ata_port, sff_pio_task.work); |
ea3c6450 | 1223 | struct ata_link *link = ap->sff_pio_task_link; |
c429137a | 1224 | struct ata_queued_cmd *qc; |
624d5c51 TH |
1225 | u8 status; |
1226 | int poll_next; | |
1227 | ||
8eee1d3e TH |
1228 | spin_lock_irq(ap->lock); |
1229 | ||
4fca377f | 1230 | BUG_ON(ap->sff_pio_task_link == NULL); |
c429137a | 1231 | /* qc can be NULL if timeout occurred */ |
ea3c6450 GG |
1232 | qc = ata_qc_from_tag(ap, link->active_tag); |
1233 | if (!qc) { | |
1234 | ap->sff_pio_task_link = NULL; | |
8eee1d3e | 1235 | goto out_unlock; |
ea3c6450 | 1236 | } |
c429137a | 1237 | |
624d5c51 | 1238 | fsm_start: |
efcb3cf7 | 1239 | WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE); |
624d5c51 TH |
1240 | |
1241 | /* | |
1242 | * This is purely heuristic. This is a fast path. | |
1243 | * Sometimes when we enter, BSY will be cleared in | |
1244 | * a chk-status or two. If not, the drive is probably seeking | |
1245 | * or something. Snooze for a couple msecs, then | |
1246 | * chk-status again. If still busy, queue delayed work. | |
1247 | */ | |
9363c382 | 1248 | status = ata_sff_busy_wait(ap, ATA_BUSY, 5); |
624d5c51 | 1249 | if (status & ATA_BUSY) { |
8eee1d3e | 1250 | spin_unlock_irq(ap->lock); |
97750ceb | 1251 | ata_msleep(ap, 2); |
8eee1d3e TH |
1252 | spin_lock_irq(ap->lock); |
1253 | ||
9363c382 | 1254 | status = ata_sff_busy_wait(ap, ATA_BUSY, 10); |
624d5c51 | 1255 | if (status & ATA_BUSY) { |
ea3c6450 | 1256 | ata_sff_queue_pio_task(link, ATA_SHORT_PAUSE); |
8eee1d3e | 1257 | goto out_unlock; |
624d5c51 TH |
1258 | } |
1259 | } | |
1260 | ||
ea3c6450 GG |
1261 | /* |
1262 | * hsm_move() may trigger another command to be processed. | |
1263 | * clean the link beforehand. | |
1264 | */ | |
1265 | ap->sff_pio_task_link = NULL; | |
624d5c51 | 1266 | /* move the HSM */ |
9363c382 | 1267 | poll_next = ata_sff_hsm_move(ap, qc, status, 1); |
624d5c51 TH |
1268 | |
1269 | /* another command or interrupt handler | |
1270 | * may be running at this point. | |
1271 | */ | |
1272 | if (poll_next) | |
1273 | goto fsm_start; | |
8eee1d3e TH |
1274 | out_unlock: |
1275 | spin_unlock_irq(ap->lock); | |
624d5c51 TH |
1276 | } |
1277 | ||
1278 | /** | |
360ff783 | 1279 | * ata_sff_qc_issue - issue taskfile to a SFF controller |
624d5c51 TH |
1280 | * @qc: command to issue to device |
1281 | * | |
360ff783 TH |
1282 | * This function issues a PIO or NODATA command to a SFF |
1283 | * controller. | |
624d5c51 TH |
1284 | * |
1285 | * LOCKING: | |
1286 | * spin_lock_irqsave(host lock) | |
1287 | * | |
1288 | * RETURNS: | |
1289 | * Zero on success, AC_ERR_* mask on failure | |
1290 | */ | |
9363c382 | 1291 | unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc) |
624d5c51 TH |
1292 | { |
1293 | struct ata_port *ap = qc->ap; | |
ea3c6450 | 1294 | struct ata_link *link = qc->dev->link; |
624d5c51 TH |
1295 | |
1296 | /* Use polling pio if the LLD doesn't handle | |
1297 | * interrupt driven pio and atapi CDB interrupt. | |
1298 | */ | |
360ff783 TH |
1299 | if (ap->flags & ATA_FLAG_PIO_POLLING) |
1300 | qc->tf.flags |= ATA_TFLAG_POLLING; | |
624d5c51 TH |
1301 | |
1302 | /* select the device */ | |
1303 | ata_dev_select(ap, qc->dev->devno, 1, 0); | |
1304 | ||
1305 | /* start the command */ | |
1306 | switch (qc->tf.protocol) { | |
1307 | case ATA_PROT_NODATA: | |
1308 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1309 | ata_qc_set_polling(qc); | |
1310 | ||
c206a389 | 1311 | ata_tf_to_host(ap, &qc->tf, qc->tag); |
624d5c51 TH |
1312 | ap->hsm_task_state = HSM_ST_LAST; |
1313 | ||
1314 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
ea3c6450 | 1315 | ata_sff_queue_pio_task(link, 0); |
624d5c51 TH |
1316 | |
1317 | break; | |
1318 | ||
624d5c51 TH |
1319 | case ATA_PROT_PIO: |
1320 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1321 | ata_qc_set_polling(qc); | |
1322 | ||
c206a389 | 1323 | ata_tf_to_host(ap, &qc->tf, qc->tag); |
624d5c51 TH |
1324 | |
1325 | if (qc->tf.flags & ATA_TFLAG_WRITE) { | |
1326 | /* PIO data out protocol */ | |
1327 | ap->hsm_task_state = HSM_ST_FIRST; | |
ea3c6450 | 1328 | ata_sff_queue_pio_task(link, 0); |
624d5c51 | 1329 | |
c429137a TH |
1330 | /* always send first data block using the |
1331 | * ata_sff_pio_task() codepath. | |
624d5c51 TH |
1332 | */ |
1333 | } else { | |
1334 | /* PIO data in protocol */ | |
1335 | ap->hsm_task_state = HSM_ST; | |
1336 | ||
1337 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
ea3c6450 | 1338 | ata_sff_queue_pio_task(link, 0); |
624d5c51 | 1339 | |
c429137a TH |
1340 | /* if polling, ata_sff_pio_task() handles the |
1341 | * rest. otherwise, interrupt handler takes | |
1342 | * over from here. | |
624d5c51 TH |
1343 | */ |
1344 | } | |
1345 | ||
1346 | break; | |
1347 | ||
1348 | case ATAPI_PROT_PIO: | |
1349 | case ATAPI_PROT_NODATA: | |
1350 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1351 | ata_qc_set_polling(qc); | |
1352 | ||
c206a389 | 1353 | ata_tf_to_host(ap, &qc->tf, qc->tag); |
624d5c51 TH |
1354 | |
1355 | ap->hsm_task_state = HSM_ST_FIRST; | |
1356 | ||
1357 | /* send cdb by polling if no cdb interrupt */ | |
1358 | if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) || | |
1359 | (qc->tf.flags & ATA_TFLAG_POLLING)) | |
ea3c6450 | 1360 | ata_sff_queue_pio_task(link, 0); |
624d5c51 TH |
1361 | break; |
1362 | ||
624d5c51 | 1363 | default: |
624d5c51 TH |
1364 | return AC_ERR_SYSTEM; |
1365 | } | |
1366 | ||
1367 | return 0; | |
1368 | } | |
0fe40ff8 | 1369 | EXPORT_SYMBOL_GPL(ata_sff_qc_issue); |
624d5c51 | 1370 | |
22183bf5 TH |
1371 | /** |
1372 | * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read | |
1373 | * @qc: qc to fill result TF for | |
1374 | * | |
1375 | * @qc is finished and result TF needs to be filled. Fill it | |
1376 | * using ->sff_tf_read. | |
1377 | * | |
1378 | * LOCKING: | |
1379 | * spin_lock_irqsave(host lock) | |
22183bf5 | 1380 | */ |
931139af | 1381 | void ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc) |
22183bf5 TH |
1382 | { |
1383 | qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf); | |
22183bf5 | 1384 | } |
0fe40ff8 | 1385 | EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf); |
22183bf5 | 1386 | |
c3b28894 | 1387 | static unsigned int ata_sff_idle_irq(struct ata_port *ap) |
624d5c51 | 1388 | { |
c3b28894 TH |
1389 | ap->stats.idle_irq++; |
1390 | ||
1391 | #ifdef ATA_IRQ_TRAP | |
1392 | if ((ap->stats.idle_irq % 1000) == 0) { | |
1393 | ap->ops->sff_check_status(ap); | |
1394 | if (ap->ops->sff_irq_clear) | |
1395 | ap->ops->sff_irq_clear(ap); | |
a9a79dfe | 1396 | ata_port_warn(ap, "irq trap\n"); |
c3b28894 TH |
1397 | return 1; |
1398 | } | |
1399 | #endif | |
1400 | return 0; /* irq not handled */ | |
1401 | } | |
1402 | ||
1403 | static unsigned int __ata_sff_port_intr(struct ata_port *ap, | |
1404 | struct ata_queued_cmd *qc, | |
1405 | bool hsmv_on_idle) | |
1406 | { | |
1407 | u8 status; | |
624d5c51 | 1408 | |
7fad6ad6 | 1409 | trace_ata_sff_port_intr(qc, hsmv_on_idle); |
624d5c51 TH |
1410 | |
1411 | /* Check whether we are expecting interrupt in this state */ | |
1412 | switch (ap->hsm_task_state) { | |
1413 | case HSM_ST_FIRST: | |
1414 | /* Some pre-ATAPI-4 devices assert INTRQ | |
1415 | * at this state when ready to receive CDB. | |
1416 | */ | |
1417 | ||
1418 | /* Check the ATA_DFLAG_CDB_INTR flag is enough here. | |
1419 | * The flag was turned on only for atapi devices. No | |
1420 | * need to check ata_is_atapi(qc->tf.protocol) again. | |
1421 | */ | |
1422 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
c3b28894 | 1423 | return ata_sff_idle_irq(ap); |
624d5c51 | 1424 | break; |
687a9933 | 1425 | case HSM_ST_IDLE: |
c3b28894 | 1426 | return ata_sff_idle_irq(ap); |
687a9933 TH |
1427 | default: |
1428 | break; | |
624d5c51 TH |
1429 | } |
1430 | ||
a57c1bad AC |
1431 | /* check main status, clearing INTRQ if needed */ |
1432 | status = ata_sff_irq_status(ap); | |
332ac7ff | 1433 | if (status & ATA_BUSY) { |
c3b28894 | 1434 | if (hsmv_on_idle) { |
332ac7ff TH |
1435 | /* BMDMA engine is already stopped, we're screwed */ |
1436 | qc->err_mask |= AC_ERR_HSM; | |
1437 | ap->hsm_task_state = HSM_ST_ERR; | |
1438 | } else | |
c3b28894 | 1439 | return ata_sff_idle_irq(ap); |
332ac7ff | 1440 | } |
624d5c51 | 1441 | |
9f2f7210 | 1442 | /* clear irq events */ |
37f65b8b TH |
1443 | if (ap->ops->sff_irq_clear) |
1444 | ap->ops->sff_irq_clear(ap); | |
624d5c51 | 1445 | |
9363c382 | 1446 | ata_sff_hsm_move(ap, qc, status, 0); |
624d5c51 | 1447 | |
624d5c51 | 1448 | return 1; /* irq handled */ |
624d5c51 TH |
1449 | } |
1450 | ||
1451 | /** | |
c3b28894 TH |
1452 | * ata_sff_port_intr - Handle SFF port interrupt |
1453 | * @ap: Port on which interrupt arrived (possibly...) | |
1454 | * @qc: Taskfile currently active in engine | |
624d5c51 | 1455 | * |
c3b28894 | 1456 | * Handle port interrupt for given queued command. |
624d5c51 TH |
1457 | * |
1458 | * LOCKING: | |
c3b28894 | 1459 | * spin_lock_irqsave(host lock) |
624d5c51 TH |
1460 | * |
1461 | * RETURNS: | |
c3b28894 | 1462 | * One if interrupt was handled, zero if not (shared irq). |
624d5c51 | 1463 | */ |
c3b28894 TH |
1464 | unsigned int ata_sff_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc) |
1465 | { | |
1466 | return __ata_sff_port_intr(ap, qc, false); | |
1467 | } | |
1468 | EXPORT_SYMBOL_GPL(ata_sff_port_intr); | |
1469 | ||
1470 | static inline irqreturn_t __ata_sff_interrupt(int irq, void *dev_instance, | |
1471 | unsigned int (*port_intr)(struct ata_port *, struct ata_queued_cmd *)) | |
624d5c51 TH |
1472 | { |
1473 | struct ata_host *host = dev_instance; | |
332ac7ff | 1474 | bool retried = false; |
624d5c51 | 1475 | unsigned int i; |
332ac7ff | 1476 | unsigned int handled, idle, polling; |
624d5c51 TH |
1477 | unsigned long flags; |
1478 | ||
1479 | /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */ | |
1480 | spin_lock_irqsave(&host->lock, flags); | |
1481 | ||
332ac7ff TH |
1482 | retry: |
1483 | handled = idle = polling = 0; | |
624d5c51 | 1484 | for (i = 0; i < host->n_ports; i++) { |
d88ec2e5 TH |
1485 | struct ata_port *ap = host->ports[i]; |
1486 | struct ata_queued_cmd *qc; | |
624d5c51 | 1487 | |
d88ec2e5 | 1488 | qc = ata_qc_from_tag(ap, ap->link.active_tag); |
27943620 TH |
1489 | if (qc) { |
1490 | if (!(qc->tf.flags & ATA_TFLAG_POLLING)) | |
c3b28894 | 1491 | handled |= port_intr(ap, qc); |
27943620 TH |
1492 | else |
1493 | polling |= 1 << i; | |
332ac7ff TH |
1494 | } else |
1495 | idle |= 1 << i; | |
27943620 TH |
1496 | } |
1497 | ||
1498 | /* | |
1499 | * If no port was expecting IRQ but the controller is actually | |
1500 | * asserting IRQ line, nobody cared will ensue. Check IRQ | |
1501 | * pending status if available and clear spurious IRQ. | |
1502 | */ | |
332ac7ff TH |
1503 | if (!handled && !retried) { |
1504 | bool retry = false; | |
1505 | ||
27943620 TH |
1506 | for (i = 0; i < host->n_ports; i++) { |
1507 | struct ata_port *ap = host->ports[i]; | |
1508 | ||
1509 | if (polling & (1 << i)) | |
1510 | continue; | |
1511 | ||
1512 | if (!ap->ops->sff_irq_check || | |
1513 | !ap->ops->sff_irq_check(ap)) | |
1514 | continue; | |
1515 | ||
332ac7ff TH |
1516 | if (idle & (1 << i)) { |
1517 | ap->ops->sff_check_status(ap); | |
37f65b8b TH |
1518 | if (ap->ops->sff_irq_clear) |
1519 | ap->ops->sff_irq_clear(ap); | |
332ac7ff TH |
1520 | } else { |
1521 | /* clear INTRQ and check if BUSY cleared */ | |
1522 | if (!(ap->ops->sff_check_status(ap) & ATA_BUSY)) | |
1523 | retry |= true; | |
1524 | /* | |
1525 | * With command in flight, we can't do | |
1526 | * sff_irq_clear() w/o racing with completion. | |
1527 | */ | |
1528 | } | |
1529 | } | |
1530 | ||
1531 | if (retry) { | |
1532 | retried = true; | |
1533 | goto retry; | |
27943620 | 1534 | } |
624d5c51 TH |
1535 | } |
1536 | ||
1537 | spin_unlock_irqrestore(&host->lock, flags); | |
1538 | ||
1539 | return IRQ_RETVAL(handled); | |
1540 | } | |
c3b28894 TH |
1541 | |
1542 | /** | |
1543 | * ata_sff_interrupt - Default SFF ATA host interrupt handler | |
1544 | * @irq: irq line (unused) | |
1545 | * @dev_instance: pointer to our ata_host information structure | |
1546 | * | |
1547 | * Default interrupt handler for PCI IDE devices. Calls | |
1548 | * ata_sff_port_intr() for each port that is not disabled. | |
1549 | * | |
1550 | * LOCKING: | |
1551 | * Obtains host lock during operation. | |
1552 | * | |
1553 | * RETURNS: | |
1554 | * IRQ_NONE or IRQ_HANDLED. | |
1555 | */ | |
1556 | irqreturn_t ata_sff_interrupt(int irq, void *dev_instance) | |
1557 | { | |
1558 | return __ata_sff_interrupt(irq, dev_instance, ata_sff_port_intr); | |
1559 | } | |
0fe40ff8 | 1560 | EXPORT_SYMBOL_GPL(ata_sff_interrupt); |
624d5c51 | 1561 | |
c96f1732 AC |
1562 | /** |
1563 | * ata_sff_lost_interrupt - Check for an apparent lost interrupt | |
1564 | * @ap: port that appears to have timed out | |
1565 | * | |
1566 | * Called from the libata error handlers when the core code suspects | |
1567 | * an interrupt has been lost. If it has complete anything we can and | |
1568 | * then return. Interface must support altstatus for this faster | |
1569 | * recovery to occur. | |
1570 | * | |
1571 | * Locking: | |
1572 | * Caller holds host lock | |
1573 | */ | |
1574 | ||
1575 | void ata_sff_lost_interrupt(struct ata_port *ap) | |
1576 | { | |
76ed2f61 | 1577 | u8 status = 0; |
c96f1732 AC |
1578 | struct ata_queued_cmd *qc; |
1579 | ||
1580 | /* Only one outstanding command per SFF channel */ | |
1581 | qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
3e4ec344 TH |
1582 | /* We cannot lose an interrupt on a non-existent or polled command */ |
1583 | if (!qc || qc->tf.flags & ATA_TFLAG_POLLING) | |
c96f1732 AC |
1584 | return; |
1585 | /* See if the controller thinks it is still busy - if so the command | |
1586 | isn't a lost IRQ but is still in progress */ | |
03c0e84f SS |
1587 | if (WARN_ON_ONCE(!ata_sff_altstatus(ap, &status))) |
1588 | return; | |
c96f1732 AC |
1589 | if (status & ATA_BUSY) |
1590 | return; | |
1591 | ||
1592 | /* There was a command running, we are no longer busy and we have | |
1593 | no interrupt. */ | |
03c0e84f | 1594 | ata_port_warn(ap, "lost interrupt (Status 0x%x)\n", status); |
c96f1732 AC |
1595 | /* Run the host interrupt logic as if the interrupt had not been |
1596 | lost */ | |
c3b28894 | 1597 | ata_sff_port_intr(ap, qc); |
c96f1732 AC |
1598 | } |
1599 | EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt); | |
1600 | ||
624d5c51 | 1601 | /** |
9363c382 | 1602 | * ata_sff_freeze - Freeze SFF controller port |
624d5c51 TH |
1603 | * @ap: port to freeze |
1604 | * | |
9f2f7210 | 1605 | * Freeze SFF controller port. |
624d5c51 TH |
1606 | * |
1607 | * LOCKING: | |
1608 | * Inherited from caller. | |
1609 | */ | |
9363c382 | 1610 | void ata_sff_freeze(struct ata_port *ap) |
624d5c51 | 1611 | { |
624d5c51 TH |
1612 | ap->ctl |= ATA_NIEN; |
1613 | ap->last_ctl = ap->ctl; | |
1614 | ||
4fc5f0aa | 1615 | ata_sff_set_devctl(ap, ap->ctl); |
624d5c51 TH |
1616 | |
1617 | /* Under certain circumstances, some controllers raise IRQ on | |
1618 | * ATA_NIEN manipulation. Also, many controllers fail to mask | |
1619 | * previously pending IRQ on ATA_NIEN assertion. Clear it. | |
1620 | */ | |
5682ed33 | 1621 | ap->ops->sff_check_status(ap); |
624d5c51 | 1622 | |
37f65b8b TH |
1623 | if (ap->ops->sff_irq_clear) |
1624 | ap->ops->sff_irq_clear(ap); | |
624d5c51 | 1625 | } |
0fe40ff8 | 1626 | EXPORT_SYMBOL_GPL(ata_sff_freeze); |
624d5c51 TH |
1627 | |
1628 | /** | |
9363c382 | 1629 | * ata_sff_thaw - Thaw SFF controller port |
624d5c51 TH |
1630 | * @ap: port to thaw |
1631 | * | |
9363c382 | 1632 | * Thaw SFF controller port. |
624d5c51 TH |
1633 | * |
1634 | * LOCKING: | |
1635 | * Inherited from caller. | |
1636 | */ | |
9363c382 | 1637 | void ata_sff_thaw(struct ata_port *ap) |
272f7884 | 1638 | { |
624d5c51 | 1639 | /* clear & re-enable interrupts */ |
5682ed33 | 1640 | ap->ops->sff_check_status(ap); |
37f65b8b TH |
1641 | if (ap->ops->sff_irq_clear) |
1642 | ap->ops->sff_irq_clear(ap); | |
e42a542b | 1643 | ata_sff_irq_on(ap); |
272f7884 | 1644 | } |
0fe40ff8 | 1645 | EXPORT_SYMBOL_GPL(ata_sff_thaw); |
272f7884 | 1646 | |
0aa1113d TH |
1647 | /** |
1648 | * ata_sff_prereset - prepare SFF link for reset | |
1649 | * @link: SFF link to be reset | |
1650 | * @deadline: deadline jiffies for the operation | |
1651 | * | |
1652 | * SFF link @link is about to be reset. Initialize it. It first | |
1653 | * calls ata_std_prereset() and wait for !BSY if the port is | |
1654 | * being softreset. | |
1655 | * | |
1656 | * LOCKING: | |
1657 | * Kernel thread context (may sleep) | |
1658 | * | |
1659 | * RETURNS: | |
ac1eb665 | 1660 | * Always 0. |
0aa1113d TH |
1661 | */ |
1662 | int ata_sff_prereset(struct ata_link *link, unsigned long deadline) | |
1663 | { | |
0aa1113d TH |
1664 | struct ata_eh_context *ehc = &link->eh_context; |
1665 | int rc; | |
1666 | ||
ac1eb665 SS |
1667 | /* The standard prereset is best-effort and always returns 0 */ |
1668 | ata_std_prereset(link, deadline); | |
0aa1113d TH |
1669 | |
1670 | /* if we're about to do hardreset, nothing more to do */ | |
1671 | if (ehc->i.action & ATA_EH_HARDRESET) | |
1672 | return 0; | |
1673 | ||
1674 | /* wait for !BSY if we don't know that no device is attached */ | |
1675 | if (!ata_link_offline(link)) { | |
705e76be | 1676 | rc = ata_sff_wait_ready(link, deadline); |
0aa1113d | 1677 | if (rc && rc != -ENODEV) { |
a9a79dfe JP |
1678 | ata_link_warn(link, |
1679 | "device not ready (errno=%d), forcing hardreset\n", | |
1680 | rc); | |
0aa1113d TH |
1681 | ehc->i.action |= ATA_EH_HARDRESET; |
1682 | } | |
1683 | } | |
1684 | ||
1685 | return 0; | |
1686 | } | |
0fe40ff8 | 1687 | EXPORT_SYMBOL_GPL(ata_sff_prereset); |
0aa1113d | 1688 | |
90088bb4 | 1689 | /** |
624d5c51 TH |
1690 | * ata_devchk - PATA device presence detection |
1691 | * @ap: ATA channel to examine | |
1692 | * @device: Device to examine (starting at zero) | |
90088bb4 | 1693 | * |
624d5c51 TH |
1694 | * This technique was originally described in |
1695 | * Hale Landis's ATADRVR (www.ata-atapi.com), and | |
1696 | * later found its way into the ATA/ATAPI spec. | |
1697 | * | |
1698 | * Write a pattern to the ATA shadow registers, | |
1699 | * and if a device is present, it will respond by | |
1700 | * correctly storing and echoing back the | |
1701 | * ATA shadow register contents. | |
90088bb4 | 1702 | * |
1336aa88 SS |
1703 | * RETURN: |
1704 | * true if device is present, false if not. | |
1705 | * | |
90088bb4 | 1706 | * LOCKING: |
624d5c51 | 1707 | * caller. |
90088bb4 | 1708 | */ |
1336aa88 | 1709 | static bool ata_devchk(struct ata_port *ap, unsigned int device) |
90088bb4 TH |
1710 | { |
1711 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
624d5c51 | 1712 | u8 nsect, lbal; |
90088bb4 | 1713 | |
5682ed33 | 1714 | ap->ops->sff_dev_select(ap, device); |
90088bb4 | 1715 | |
624d5c51 TH |
1716 | iowrite8(0x55, ioaddr->nsect_addr); |
1717 | iowrite8(0xaa, ioaddr->lbal_addr); | |
90088bb4 | 1718 | |
624d5c51 TH |
1719 | iowrite8(0xaa, ioaddr->nsect_addr); |
1720 | iowrite8(0x55, ioaddr->lbal_addr); | |
90088bb4 | 1721 | |
624d5c51 TH |
1722 | iowrite8(0x55, ioaddr->nsect_addr); |
1723 | iowrite8(0xaa, ioaddr->lbal_addr); | |
1724 | ||
1725 | nsect = ioread8(ioaddr->nsect_addr); | |
1726 | lbal = ioread8(ioaddr->lbal_addr); | |
1727 | ||
1728 | if ((nsect == 0x55) && (lbal == 0xaa)) | |
1336aa88 | 1729 | return true; /* we found a device */ |
624d5c51 | 1730 | |
1336aa88 | 1731 | return false; /* nothing found */ |
90088bb4 TH |
1732 | } |
1733 | ||
272f7884 | 1734 | /** |
9363c382 | 1735 | * ata_sff_dev_classify - Parse returned ATA device signature |
624d5c51 TH |
1736 | * @dev: ATA device to classify (starting at zero) |
1737 | * @present: device seems present | |
1738 | * @r_err: Value of error register on completion | |
272f7884 | 1739 | * |
624d5c51 TH |
1740 | * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs, |
1741 | * an ATA/ATAPI-defined set of values is placed in the ATA | |
1742 | * shadow registers, indicating the results of device detection | |
1743 | * and diagnostics. | |
272f7884 | 1744 | * |
624d5c51 TH |
1745 | * Select the ATA device, and read the values from the ATA shadow |
1746 | * registers. Then parse according to the Error register value, | |
1747 | * and the spec-defined values examined by ata_dev_classify(). | |
272f7884 TH |
1748 | * |
1749 | * LOCKING: | |
624d5c51 TH |
1750 | * caller. |
1751 | * | |
1752 | * RETURNS: | |
1753 | * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE. | |
272f7884 | 1754 | */ |
9363c382 | 1755 | unsigned int ata_sff_dev_classify(struct ata_device *dev, int present, |
624d5c51 | 1756 | u8 *r_err) |
272f7884 | 1757 | { |
624d5c51 TH |
1758 | struct ata_port *ap = dev->link->ap; |
1759 | struct ata_taskfile tf; | |
1760 | unsigned int class; | |
1761 | u8 err; | |
1762 | ||
5682ed33 | 1763 | ap->ops->sff_dev_select(ap, dev->devno); |
624d5c51 TH |
1764 | |
1765 | memset(&tf, 0, sizeof(tf)); | |
1766 | ||
5682ed33 | 1767 | ap->ops->sff_tf_read(ap, &tf); |
efcef265 | 1768 | err = tf.error; |
624d5c51 TH |
1769 | if (r_err) |
1770 | *r_err = err; | |
1771 | ||
1772 | /* see if device passed diags: continue and warn later */ | |
1773 | if (err == 0) | |
1774 | /* diagnostic fail : do nothing _YET_ */ | |
1775 | dev->horkage |= ATA_HORKAGE_DIAGNOSTIC; | |
1776 | else if (err == 1) | |
1777 | /* do nothing */ ; | |
1778 | else if ((dev->devno == 0) && (err == 0x81)) | |
1779 | /* do nothing */ ; | |
1780 | else | |
1781 | return ATA_DEV_NONE; | |
272f7884 | 1782 | |
624d5c51 | 1783 | /* determine if device is ATA or ATAPI */ |
6c952a0d | 1784 | class = ata_port_classify(ap, &tf); |
ffa92a74 SS |
1785 | switch (class) { |
1786 | case ATA_DEV_UNKNOWN: | |
1787 | /* | |
1788 | * If the device failed diagnostic, it's likely to | |
624d5c51 TH |
1789 | * have reported incorrect device signature too. |
1790 | * Assume ATA device if the device seems present but | |
1791 | * device signature is invalid with diagnostic | |
1792 | * failure. | |
1793 | */ | |
1794 | if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC)) | |
1795 | class = ATA_DEV_ATA; | |
1796 | else | |
1797 | class = ATA_DEV_NONE; | |
ffa92a74 SS |
1798 | break; |
1799 | case ATA_DEV_ATA: | |
1800 | if (ap->ops->sff_check_status(ap) == 0) | |
1801 | class = ATA_DEV_NONE; | |
1802 | break; | |
1803 | } | |
624d5c51 | 1804 | return class; |
272f7884 | 1805 | } |
0fe40ff8 | 1806 | EXPORT_SYMBOL_GPL(ata_sff_dev_classify); |
272f7884 | 1807 | |
705e76be TH |
1808 | /** |
1809 | * ata_sff_wait_after_reset - wait for devices to become ready after reset | |
1810 | * @link: SFF link which is just reset | |
1811 | * @devmask: mask of present devices | |
1812 | * @deadline: deadline jiffies for the operation | |
1813 | * | |
1814 | * Wait devices attached to SFF @link to become ready after | |
1815 | * reset. It contains preceding 150ms wait to avoid accessing TF | |
1816 | * status register too early. | |
1817 | * | |
1818 | * LOCKING: | |
1819 | * Kernel thread context (may sleep). | |
1820 | * | |
1821 | * RETURNS: | |
1822 | * 0 on success, -ENODEV if some or all of devices in @devmask | |
1823 | * don't seem to exist. -errno on other errors. | |
1824 | */ | |
1825 | int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask, | |
1826 | unsigned long deadline) | |
1fdffbce | 1827 | { |
705e76be | 1828 | struct ata_port *ap = link->ap; |
1fdffbce | 1829 | struct ata_ioports *ioaddr = &ap->ioaddr; |
624d5c51 TH |
1830 | unsigned int dev0 = devmask & (1 << 0); |
1831 | unsigned int dev1 = devmask & (1 << 1); | |
1832 | int rc, ret = 0; | |
1fdffbce | 1833 | |
97750ceb | 1834 | ata_msleep(ap, ATA_WAIT_AFTER_RESET); |
705e76be TH |
1835 | |
1836 | /* always check readiness of the master device */ | |
1837 | rc = ata_sff_wait_ready(link, deadline); | |
1838 | /* -ENODEV means the odd clown forgot the D7 pulldown resistor | |
1839 | * and TF status is 0xff, bail out on it too. | |
624d5c51 | 1840 | */ |
705e76be TH |
1841 | if (rc) |
1842 | return rc; | |
1fdffbce | 1843 | |
624d5c51 TH |
1844 | /* if device 1 was found in ata_devchk, wait for register |
1845 | * access briefly, then wait for BSY to clear. | |
1846 | */ | |
1847 | if (dev1) { | |
1848 | int i; | |
1fdffbce | 1849 | |
5682ed33 | 1850 | ap->ops->sff_dev_select(ap, 1); |
1fdffbce | 1851 | |
624d5c51 TH |
1852 | /* Wait for register access. Some ATAPI devices fail |
1853 | * to set nsect/lbal after reset, so don't waste too | |
1854 | * much time on it. We're gonna wait for !BSY anyway. | |
1855 | */ | |
1856 | for (i = 0; i < 2; i++) { | |
1857 | u8 nsect, lbal; | |
1858 | ||
1859 | nsect = ioread8(ioaddr->nsect_addr); | |
1860 | lbal = ioread8(ioaddr->lbal_addr); | |
1861 | if ((nsect == 1) && (lbal == 1)) | |
1862 | break; | |
97750ceb | 1863 | ata_msleep(ap, 50); /* give drive a breather */ |
624d5c51 TH |
1864 | } |
1865 | ||
705e76be | 1866 | rc = ata_sff_wait_ready(link, deadline); |
624d5c51 TH |
1867 | if (rc) { |
1868 | if (rc != -ENODEV) | |
1869 | return rc; | |
1870 | ret = rc; | |
1871 | } | |
1fdffbce JG |
1872 | } |
1873 | ||
624d5c51 | 1874 | /* is all this really necessary? */ |
5682ed33 | 1875 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 | 1876 | if (dev1) |
5682ed33 | 1877 | ap->ops->sff_dev_select(ap, 1); |
624d5c51 | 1878 | if (dev0) |
5682ed33 | 1879 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
1880 | |
1881 | return ret; | |
1fdffbce | 1882 | } |
0fe40ff8 | 1883 | EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset); |
1fdffbce | 1884 | |
624d5c51 TH |
1885 | static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask, |
1886 | unsigned long deadline) | |
2cc432ee | 1887 | { |
624d5c51 | 1888 | struct ata_ioports *ioaddr = &ap->ioaddr; |
2cc432ee | 1889 | |
6d8ca28f OZ |
1890 | if (ap->ioaddr.ctl_addr) { |
1891 | /* software reset. causes dev0 to be selected */ | |
1892 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
1893 | udelay(20); /* FIXME: flush */ | |
1894 | iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr); | |
1895 | udelay(20); /* FIXME: flush */ | |
1896 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
1897 | ap->last_ctl = ap->ctl; | |
1898 | } | |
624d5c51 | 1899 | |
705e76be TH |
1900 | /* wait the port to become ready */ |
1901 | return ata_sff_wait_after_reset(&ap->link, devmask, deadline); | |
2cc432ee JG |
1902 | } |
1903 | ||
6d97dbd7 | 1904 | /** |
9363c382 | 1905 | * ata_sff_softreset - reset host port via ATA SRST |
624d5c51 TH |
1906 | * @link: ATA link to reset |
1907 | * @classes: resulting classes of attached devices | |
1908 | * @deadline: deadline jiffies for the operation | |
6d97dbd7 | 1909 | * |
624d5c51 | 1910 | * Reset host port using ATA SRST. |
6d97dbd7 TH |
1911 | * |
1912 | * LOCKING: | |
624d5c51 TH |
1913 | * Kernel thread context (may sleep) |
1914 | * | |
1915 | * RETURNS: | |
1916 | * 0 on success, -errno otherwise. | |
6d97dbd7 | 1917 | */ |
9363c382 | 1918 | int ata_sff_softreset(struct ata_link *link, unsigned int *classes, |
624d5c51 | 1919 | unsigned long deadline) |
6d97dbd7 | 1920 | { |
624d5c51 TH |
1921 | struct ata_port *ap = link->ap; |
1922 | unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; | |
1923 | unsigned int devmask = 0; | |
1924 | int rc; | |
1925 | u8 err; | |
6d97dbd7 | 1926 | |
624d5c51 TH |
1927 | /* determine if device 0/1 are present */ |
1928 | if (ata_devchk(ap, 0)) | |
1929 | devmask |= (1 << 0); | |
1930 | if (slave_possible && ata_devchk(ap, 1)) | |
1931 | devmask |= (1 << 1); | |
1932 | ||
1933 | /* select device 0 again */ | |
5682ed33 | 1934 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
1935 | |
1936 | /* issue bus reset */ | |
624d5c51 TH |
1937 | rc = ata_bus_softreset(ap, devmask, deadline); |
1938 | /* if link is occupied, -ENODEV too is an error */ | |
1939 | if (rc && (rc != -ENODEV || sata_scr_valid(link))) { | |
a9a79dfe | 1940 | ata_link_err(link, "SRST failed (errno=%d)\n", rc); |
624d5c51 TH |
1941 | return rc; |
1942 | } | |
0f0a3ad3 | 1943 | |
624d5c51 | 1944 | /* determine by signature whether we have ATA or ATAPI devices */ |
9363c382 | 1945 | classes[0] = ata_sff_dev_classify(&link->device[0], |
624d5c51 TH |
1946 | devmask & (1 << 0), &err); |
1947 | if (slave_possible && err != 0x81) | |
9363c382 | 1948 | classes[1] = ata_sff_dev_classify(&link->device[1], |
624d5c51 TH |
1949 | devmask & (1 << 1), &err); |
1950 | ||
624d5c51 | 1951 | return 0; |
6d97dbd7 | 1952 | } |
0fe40ff8 | 1953 | EXPORT_SYMBOL_GPL(ata_sff_softreset); |
6d97dbd7 TH |
1954 | |
1955 | /** | |
9363c382 | 1956 | * sata_sff_hardreset - reset host port via SATA phy reset |
624d5c51 TH |
1957 | * @link: link to reset |
1958 | * @class: resulting class of attached device | |
1959 | * @deadline: deadline jiffies for the operation | |
6d97dbd7 | 1960 | * |
624d5c51 TH |
1961 | * SATA phy-reset host port using DET bits of SControl register, |
1962 | * wait for !BSY and classify the attached device. | |
6d97dbd7 TH |
1963 | * |
1964 | * LOCKING: | |
624d5c51 TH |
1965 | * Kernel thread context (may sleep) |
1966 | * | |
1967 | * RETURNS: | |
1968 | * 0 on success, -errno otherwise. | |
6d97dbd7 | 1969 | */ |
9363c382 | 1970 | int sata_sff_hardreset(struct ata_link *link, unsigned int *class, |
624d5c51 | 1971 | unsigned long deadline) |
6d97dbd7 | 1972 | { |
9dadd45b TH |
1973 | struct ata_eh_context *ehc = &link->eh_context; |
1974 | const unsigned long *timing = sata_ehc_deb_timing(ehc); | |
1975 | bool online; | |
624d5c51 TH |
1976 | int rc; |
1977 | ||
9dadd45b TH |
1978 | rc = sata_link_hardreset(link, timing, deadline, &online, |
1979 | ata_sff_check_ready); | |
9dadd45b TH |
1980 | if (online) |
1981 | *class = ata_sff_dev_classify(link->device, 1, NULL); | |
624d5c51 | 1982 | |
9dadd45b | 1983 | return rc; |
6d97dbd7 | 1984 | } |
0fe40ff8 | 1985 | EXPORT_SYMBOL_GPL(sata_sff_hardreset); |
6d97dbd7 | 1986 | |
203c75b8 TH |
1987 | /** |
1988 | * ata_sff_postreset - SFF postreset callback | |
1989 | * @link: the target SFF ata_link | |
1990 | * @classes: classes of attached devices | |
1991 | * | |
1992 | * This function is invoked after a successful reset. It first | |
1993 | * calls ata_std_postreset() and performs SFF specific postreset | |
1994 | * processing. | |
1995 | * | |
1996 | * LOCKING: | |
1997 | * Kernel thread context (may sleep) | |
1998 | */ | |
1999 | void ata_sff_postreset(struct ata_link *link, unsigned int *classes) | |
2000 | { | |
2001 | struct ata_port *ap = link->ap; | |
2002 | ||
2003 | ata_std_postreset(link, classes); | |
2004 | ||
2005 | /* is double-select really necessary? */ | |
2006 | if (classes[0] != ATA_DEV_NONE) | |
2007 | ap->ops->sff_dev_select(ap, 1); | |
2008 | if (classes[1] != ATA_DEV_NONE) | |
2009 | ap->ops->sff_dev_select(ap, 0); | |
2010 | ||
2011 | /* bail out if no device is present */ | |
f8ec26d0 | 2012 | if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) |
203c75b8 | 2013 | return; |
203c75b8 TH |
2014 | |
2015 | /* set up device control */ | |
4fc5f0aa | 2016 | if (ata_sff_set_devctl(ap, ap->ctl)) |
e3e4385f | 2017 | ap->last_ctl = ap->ctl; |
203c75b8 | 2018 | } |
0fe40ff8 | 2019 | EXPORT_SYMBOL_GPL(ata_sff_postreset); |
203c75b8 | 2020 | |
3d47aa8e AC |
2021 | /** |
2022 | * ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers | |
2023 | * @qc: command | |
2024 | * | |
2025 | * Drain the FIFO and device of any stuck data following a command | |
3ad2f3fb | 2026 | * failing to complete. In some cases this is necessary before a |
3d47aa8e AC |
2027 | * reset will recover the device. |
2028 | * | |
2029 | */ | |
2030 | ||
2031 | void ata_sff_drain_fifo(struct ata_queued_cmd *qc) | |
2032 | { | |
2033 | int count; | |
2034 | struct ata_port *ap; | |
2035 | ||
2036 | /* We only need to flush incoming data when a command was running */ | |
2037 | if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE) | |
2038 | return; | |
2039 | ||
2040 | ap = qc->ap; | |
2041 | /* Drain up to 64K of data before we give up this recovery method */ | |
2042 | for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) | |
9a8fd68b | 2043 | && count < 65536; count += 2) |
3d47aa8e AC |
2044 | ioread16(ap->ioaddr.data_addr); |
2045 | ||
3d47aa8e | 2046 | if (count) |
a9a79dfe | 2047 | ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count); |
3d47aa8e AC |
2048 | |
2049 | } | |
2050 | EXPORT_SYMBOL_GPL(ata_sff_drain_fifo); | |
2051 | ||
6d97dbd7 | 2052 | /** |
fe06e5f9 | 2053 | * ata_sff_error_handler - Stock error handler for SFF controller |
6d97dbd7 | 2054 | * @ap: port to handle error for |
6d97dbd7 | 2055 | * |
9363c382 | 2056 | * Stock error handler for SFF controller. It can handle both |
6d97dbd7 TH |
2057 | * PATA and SATA controllers. Many controllers should be able to |
2058 | * use this EH as-is or with some added handling before and | |
2059 | * after. | |
2060 | * | |
6d97dbd7 TH |
2061 | * LOCKING: |
2062 | * Kernel thread context (may sleep) | |
2063 | */ | |
9363c382 | 2064 | void ata_sff_error_handler(struct ata_port *ap) |
6d97dbd7 | 2065 | { |
a1efdaba TH |
2066 | ata_reset_fn_t softreset = ap->ops->softreset; |
2067 | ata_reset_fn_t hardreset = ap->ops->hardreset; | |
6d97dbd7 TH |
2068 | struct ata_queued_cmd *qc; |
2069 | unsigned long flags; | |
6d97dbd7 | 2070 | |
9af5c9c9 | 2071 | qc = __ata_qc_from_tag(ap, ap->link.active_tag); |
87629312 | 2072 | if (qc && !(qc->flags & ATA_QCFLAG_EH)) |
6d97dbd7 TH |
2073 | qc = NULL; |
2074 | ||
ba6a1308 | 2075 | spin_lock_irqsave(ap->lock, flags); |
6d97dbd7 | 2076 | |
fe06e5f9 TH |
2077 | /* |
2078 | * We *MUST* do FIFO draining before we issue a reset as | |
2079 | * several devices helpfully clear their internal state and | |
2080 | * will lock solid if we touch the data port post reset. Pass | |
2081 | * qc in case anyone wants to do different PIO/DMA recovery or | |
2082 | * has per command fixups | |
3d47aa8e | 2083 | */ |
8244cd05 TH |
2084 | if (ap->ops->sff_drain_fifo) |
2085 | ap->ops->sff_drain_fifo(qc); | |
6d97dbd7 | 2086 | |
ba6a1308 | 2087 | spin_unlock_irqrestore(ap->lock, flags); |
6d97dbd7 | 2088 | |
fe06e5f9 TH |
2089 | /* ignore built-in hardresets if SCR access is not available */ |
2090 | if ((hardreset == sata_std_hardreset || | |
2091 | hardreset == sata_sff_hardreset) && !sata_scr_valid(&ap->link)) | |
a1efdaba | 2092 | hardreset = NULL; |
6d97dbd7 | 2093 | |
a1efdaba TH |
2094 | ata_do_eh(ap, ap->ops->prereset, softreset, hardreset, |
2095 | ap->ops->postreset); | |
6d97dbd7 | 2096 | } |
0fe40ff8 | 2097 | EXPORT_SYMBOL_GPL(ata_sff_error_handler); |
6d97dbd7 | 2098 | |
624d5c51 | 2099 | /** |
9363c382 | 2100 | * ata_sff_std_ports - initialize ioaddr with standard port offsets. |
624d5c51 TH |
2101 | * @ioaddr: IO address structure to be initialized |
2102 | * | |
2103 | * Utility function which initializes data_addr, error_addr, | |
2104 | * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr, | |
2105 | * device_addr, status_addr, and command_addr to standard offsets | |
2106 | * relative to cmd_addr. | |
2107 | * | |
2108 | * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr. | |
2109 | */ | |
9363c382 | 2110 | void ata_sff_std_ports(struct ata_ioports *ioaddr) |
624d5c51 TH |
2111 | { |
2112 | ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA; | |
2113 | ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR; | |
2114 | ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE; | |
2115 | ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT; | |
2116 | ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL; | |
2117 | ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM; | |
2118 | ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH; | |
2119 | ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE; | |
2120 | ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS; | |
2121 | ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD; | |
2122 | } | |
0fe40ff8 | 2123 | EXPORT_SYMBOL_GPL(ata_sff_std_ports); |
624d5c51 | 2124 | |
1fdffbce | 2125 | #ifdef CONFIG_PCI |
4112e16a | 2126 | |
b51aa532 | 2127 | static bool ata_resources_present(struct pci_dev *pdev, int port) |
272f7884 TH |
2128 | { |
2129 | int i; | |
2130 | ||
2131 | /* Check the PCI resources for this channel are enabled */ | |
b51aa532 | 2132 | port *= 2; |
0fe40ff8 | 2133 | for (i = 0; i < 2; i++) { |
272f7884 TH |
2134 | if (pci_resource_start(pdev, port + i) == 0 || |
2135 | pci_resource_len(pdev, port + i) == 0) | |
b51aa532 | 2136 | return false; |
272f7884 | 2137 | } |
b51aa532 | 2138 | return true; |
272f7884 TH |
2139 | } |
2140 | ||
d491b27b | 2141 | /** |
9363c382 | 2142 | * ata_pci_sff_init_host - acquire native PCI ATA resources and init host |
d491b27b | 2143 | * @host: target ATA host |
d491b27b | 2144 | * |
1626aeb8 TH |
2145 | * Acquire native PCI ATA resources for @host and initialize the |
2146 | * first two ports of @host accordingly. Ports marked dummy are | |
2147 | * skipped and allocation failure makes the port dummy. | |
d491b27b | 2148 | * |
d583bc18 TH |
2149 | * Note that native PCI resources are valid even for legacy hosts |
2150 | * as we fix up pdev resources array early in boot, so this | |
2151 | * function can be used for both native and legacy SFF hosts. | |
2152 | * | |
d491b27b TH |
2153 | * LOCKING: |
2154 | * Inherited from calling layer (may sleep). | |
2155 | * | |
2156 | * RETURNS: | |
1626aeb8 TH |
2157 | * 0 if at least one port is initialized, -ENODEV if no port is |
2158 | * available. | |
d491b27b | 2159 | */ |
9363c382 | 2160 | int ata_pci_sff_init_host(struct ata_host *host) |
d491b27b TH |
2161 | { |
2162 | struct device *gdev = host->dev; | |
2163 | struct pci_dev *pdev = to_pci_dev(gdev); | |
1626aeb8 | 2164 | unsigned int mask = 0; |
d491b27b TH |
2165 | int i, rc; |
2166 | ||
d491b27b TH |
2167 | /* request, iomap BARs and init port addresses accordingly */ |
2168 | for (i = 0; i < 2; i++) { | |
2169 | struct ata_port *ap = host->ports[i]; | |
2170 | int base = i * 2; | |
2171 | void __iomem * const *iomap; | |
2172 | ||
1626aeb8 TH |
2173 | if (ata_port_is_dummy(ap)) |
2174 | continue; | |
2175 | ||
2176 | /* Discard disabled ports. Some controllers show | |
2177 | * their unused channels this way. Disabled ports are | |
2178 | * made dummy. | |
2179 | */ | |
2180 | if (!ata_resources_present(pdev, i)) { | |
2181 | ap->ops = &ata_dummy_port_ops; | |
d491b27b | 2182 | continue; |
1626aeb8 | 2183 | } |
d491b27b | 2184 | |
35a10a80 TH |
2185 | rc = pcim_iomap_regions(pdev, 0x3 << base, |
2186 | dev_driver_string(gdev)); | |
d491b27b | 2187 | if (rc) { |
a44fec1f JP |
2188 | dev_warn(gdev, |
2189 | "failed to request/iomap BARs for port %d (errno=%d)\n", | |
2190 | i, rc); | |
d491b27b TH |
2191 | if (rc == -EBUSY) |
2192 | pcim_pin_device(pdev); | |
1626aeb8 TH |
2193 | ap->ops = &ata_dummy_port_ops; |
2194 | continue; | |
d491b27b TH |
2195 | } |
2196 | host->iomap = iomap = pcim_iomap_table(pdev); | |
2197 | ||
2198 | ap->ioaddr.cmd_addr = iomap[base]; | |
2199 | ap->ioaddr.altstatus_addr = | |
2200 | ap->ioaddr.ctl_addr = (void __iomem *) | |
2201 | ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS); | |
9363c382 | 2202 | ata_sff_std_ports(&ap->ioaddr); |
1626aeb8 | 2203 | |
cbcdd875 TH |
2204 | ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx", |
2205 | (unsigned long long)pci_resource_start(pdev, base), | |
2206 | (unsigned long long)pci_resource_start(pdev, base + 1)); | |
2207 | ||
1626aeb8 TH |
2208 | mask |= 1 << i; |
2209 | } | |
2210 | ||
2211 | if (!mask) { | |
a44fec1f | 2212 | dev_err(gdev, "no available native port\n"); |
1626aeb8 | 2213 | return -ENODEV; |
d491b27b TH |
2214 | } |
2215 | ||
2216 | return 0; | |
2217 | } | |
0fe40ff8 | 2218 | EXPORT_SYMBOL_GPL(ata_pci_sff_init_host); |
d491b27b | 2219 | |
21b0ad4f | 2220 | /** |
1c5afdf7 | 2221 | * ata_pci_sff_prepare_host - helper to prepare PCI PIO-only SFF ATA host |
21b0ad4f | 2222 | * @pdev: target PCI device |
1626aeb8 | 2223 | * @ppi: array of port_info, must be enough for two ports |
21b0ad4f TH |
2224 | * @r_host: out argument for the initialized ATA host |
2225 | * | |
1c5afdf7 TH |
2226 | * Helper to allocate PIO-only SFF ATA host for @pdev, acquire |
2227 | * all PCI resources and initialize it accordingly in one go. | |
21b0ad4f TH |
2228 | * |
2229 | * LOCKING: | |
2230 | * Inherited from calling layer (may sleep). | |
2231 | * | |
2232 | * RETURNS: | |
2233 | * 0 on success, -errno otherwise. | |
2234 | */ | |
9363c382 | 2235 | int ata_pci_sff_prepare_host(struct pci_dev *pdev, |
0fe40ff8 | 2236 | const struct ata_port_info * const *ppi, |
d583bc18 | 2237 | struct ata_host **r_host) |
21b0ad4f TH |
2238 | { |
2239 | struct ata_host *host; | |
21b0ad4f TH |
2240 | int rc; |
2241 | ||
2242 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) | |
2243 | return -ENOMEM; | |
2244 | ||
2245 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); | |
2246 | if (!host) { | |
a44fec1f | 2247 | dev_err(&pdev->dev, "failed to allocate ATA host\n"); |
21b0ad4f TH |
2248 | rc = -ENOMEM; |
2249 | goto err_out; | |
2250 | } | |
2251 | ||
9363c382 | 2252 | rc = ata_pci_sff_init_host(host); |
21b0ad4f TH |
2253 | if (rc) |
2254 | goto err_out; | |
2255 | ||
21b0ad4f TH |
2256 | devres_remove_group(&pdev->dev, NULL); |
2257 | *r_host = host; | |
2258 | return 0; | |
2259 | ||
0fe40ff8 | 2260 | err_out: |
21b0ad4f TH |
2261 | devres_release_group(&pdev->dev, NULL); |
2262 | return rc; | |
2263 | } | |
0fe40ff8 | 2264 | EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host); |
21b0ad4f | 2265 | |
4e6b79fa | 2266 | /** |
9363c382 | 2267 | * ata_pci_sff_activate_host - start SFF host, request IRQ and register it |
4e6b79fa TH |
2268 | * @host: target SFF ATA host |
2269 | * @irq_handler: irq_handler used when requesting IRQ(s) | |
2270 | * @sht: scsi_host_template to use when registering the host | |
2271 | * | |
2272 | * This is the counterpart of ata_host_activate() for SFF ATA | |
2273 | * hosts. This separate helper is necessary because SFF hosts | |
2274 | * use two separate interrupts in legacy mode. | |
2275 | * | |
2276 | * LOCKING: | |
2277 | * Inherited from calling layer (may sleep). | |
2278 | * | |
2279 | * RETURNS: | |
2280 | * 0 on success, -errno otherwise. | |
2281 | */ | |
9363c382 | 2282 | int ata_pci_sff_activate_host(struct ata_host *host, |
4e6b79fa | 2283 | irq_handler_t irq_handler, |
25df73d9 | 2284 | const struct scsi_host_template *sht) |
4e6b79fa TH |
2285 | { |
2286 | struct device *dev = host->dev; | |
2287 | struct pci_dev *pdev = to_pci_dev(dev); | |
2288 | const char *drv_name = dev_driver_string(host->dev); | |
2289 | int legacy_mode = 0, rc; | |
2290 | ||
2291 | rc = ata_host_start(host); | |
2292 | if (rc) | |
2293 | return rc; | |
2294 | ||
2295 | if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) { | |
589d5726 | 2296 | u8 tmp8, mask = 0; |
4e6b79fa | 2297 | |
589d5726 DS |
2298 | /* |
2299 | * ATA spec says we should use legacy mode when one | |
2300 | * port is in legacy mode, but disabled ports on some | |
2301 | * PCI hosts appear as fixed legacy ports, e.g SB600/700 | |
2302 | * on which the secondary port is not wired, so | |
2303 | * ignore ports that are marked as 'dummy' during | |
2304 | * this check | |
2305 | */ | |
4e6b79fa | 2306 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8); |
589d5726 DS |
2307 | if (!ata_port_is_dummy(host->ports[0])) |
2308 | mask |= (1 << 0); | |
2309 | if (!ata_port_is_dummy(host->ports[1])) | |
2310 | mask |= (1 << 2); | |
4e6b79fa TH |
2311 | if ((tmp8 & mask) != mask) |
2312 | legacy_mode = 1; | |
4e6b79fa TH |
2313 | } |
2314 | ||
2315 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) | |
2316 | return -ENOMEM; | |
2317 | ||
2318 | if (!legacy_mode && pdev->irq) { | |
af649a1b JB |
2319 | int i; |
2320 | ||
4e6b79fa TH |
2321 | rc = devm_request_irq(dev, pdev->irq, irq_handler, |
2322 | IRQF_SHARED, drv_name, host); | |
2323 | if (rc) | |
2324 | goto out; | |
2325 | ||
af649a1b JB |
2326 | for (i = 0; i < 2; i++) { |
2327 | if (ata_port_is_dummy(host->ports[i])) | |
2328 | continue; | |
2329 | ata_port_desc(host->ports[i], "irq %d", pdev->irq); | |
2330 | } | |
4e6b79fa TH |
2331 | } else if (legacy_mode) { |
2332 | if (!ata_port_is_dummy(host->ports[0])) { | |
2333 | rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev), | |
2334 | irq_handler, IRQF_SHARED, | |
2335 | drv_name, host); | |
2336 | if (rc) | |
2337 | goto out; | |
2338 | ||
2339 | ata_port_desc(host->ports[0], "irq %d", | |
2340 | ATA_PRIMARY_IRQ(pdev)); | |
2341 | } | |
2342 | ||
2343 | if (!ata_port_is_dummy(host->ports[1])) { | |
2344 | rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev), | |
2345 | irq_handler, IRQF_SHARED, | |
2346 | drv_name, host); | |
2347 | if (rc) | |
2348 | goto out; | |
2349 | ||
2350 | ata_port_desc(host->ports[1], "irq %d", | |
2351 | ATA_SECONDARY_IRQ(pdev)); | |
2352 | } | |
2353 | } | |
2354 | ||
2355 | rc = ata_host_register(host, sht); | |
0fe40ff8 | 2356 | out: |
4e6b79fa TH |
2357 | if (rc == 0) |
2358 | devres_remove_group(dev, NULL); | |
2359 | else | |
2360 | devres_release_group(dev, NULL); | |
2361 | ||
2362 | return rc; | |
2363 | } | |
0fe40ff8 | 2364 | EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host); |
4e6b79fa | 2365 | |
1c5afdf7 TH |
2366 | static const struct ata_port_info *ata_sff_find_valid_pi( |
2367 | const struct ata_port_info * const *ppi) | |
2368 | { | |
2369 | int i; | |
2370 | ||
2371 | /* look up the first valid port_info */ | |
2372 | for (i = 0; i < 2 && ppi[i]; i++) | |
2373 | if (ppi[i]->port_ops != &ata_dummy_port_ops) | |
2374 | return ppi[i]; | |
2375 | ||
2376 | return NULL; | |
2377 | } | |
2378 | ||
c2036033 BZ |
2379 | static int ata_pci_init_one(struct pci_dev *pdev, |
2380 | const struct ata_port_info * const *ppi, | |
25df73d9 | 2381 | const struct scsi_host_template *sht, void *host_priv, |
c2036033 | 2382 | int hflags, bool bmdma) |
1fdffbce | 2383 | { |
f0d36efd | 2384 | struct device *dev = &pdev->dev; |
1c5afdf7 | 2385 | const struct ata_port_info *pi; |
0f834de3 | 2386 | struct ata_host *host = NULL; |
1c5afdf7 | 2387 | int rc; |
1fdffbce | 2388 | |
1c5afdf7 | 2389 | pi = ata_sff_find_valid_pi(ppi); |
1626aeb8 | 2390 | if (!pi) { |
a44fec1f | 2391 | dev_err(&pdev->dev, "no valid port_info specified\n"); |
1626aeb8 TH |
2392 | return -EINVAL; |
2393 | } | |
c791c306 | 2394 | |
1626aeb8 TH |
2395 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) |
2396 | return -ENOMEM; | |
1fdffbce | 2397 | |
f0d36efd | 2398 | rc = pcim_enable_device(pdev); |
1fdffbce | 2399 | if (rc) |
4e6b79fa | 2400 | goto out; |
1fdffbce | 2401 | |
aab94404 | 2402 | #ifdef CONFIG_ATA_BMDMA |
c2036033 BZ |
2403 | if (bmdma) |
2404 | /* prepare and activate BMDMA host */ | |
2405 | rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host); | |
2406 | else | |
aab94404 | 2407 | #endif |
c2036033 BZ |
2408 | /* prepare and activate SFF host */ |
2409 | rc = ata_pci_sff_prepare_host(pdev, ppi, &host); | |
d583bc18 | 2410 | if (rc) |
4e6b79fa | 2411 | goto out; |
887125e3 | 2412 | host->private_data = host_priv; |
c2036033 | 2413 | host->flags |= hflags; |
d491b27b | 2414 | |
aab94404 | 2415 | #ifdef CONFIG_ATA_BMDMA |
c2036033 BZ |
2416 | if (bmdma) { |
2417 | pci_set_master(pdev); | |
2418 | rc = ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht); | |
2419 | } else | |
aab94404 | 2420 | #endif |
c2036033 | 2421 | rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht); |
0fe40ff8 | 2422 | out: |
4e6b79fa TH |
2423 | if (rc == 0) |
2424 | devres_remove_group(&pdev->dev, NULL); | |
2425 | else | |
2426 | devres_release_group(&pdev->dev, NULL); | |
d491b27b | 2427 | |
1fdffbce JG |
2428 | return rc; |
2429 | } | |
c2036033 BZ |
2430 | |
2431 | /** | |
2432 | * ata_pci_sff_init_one - Initialize/register PIO-only PCI IDE controller | |
2433 | * @pdev: Controller to be initialized | |
2434 | * @ppi: array of port_info, must be enough for two ports | |
2435 | * @sht: scsi_host_template to use when registering the host | |
2436 | * @host_priv: host private_data | |
2437 | * @hflag: host flags | |
2438 | * | |
2439 | * This is a helper function which can be called from a driver's | |
2440 | * xxx_init_one() probe function if the hardware uses traditional | |
2441 | * IDE taskfile registers and is PIO only. | |
2442 | * | |
2443 | * ASSUMPTION: | |
2444 | * Nobody makes a single channel controller that appears solely as | |
2445 | * the secondary legacy port on PCI. | |
2446 | * | |
2447 | * LOCKING: | |
2448 | * Inherited from PCI layer (may sleep). | |
2449 | * | |
2450 | * RETURNS: | |
2451 | * Zero on success, negative on errno-based value on error. | |
2452 | */ | |
2453 | int ata_pci_sff_init_one(struct pci_dev *pdev, | |
2454 | const struct ata_port_info * const *ppi, | |
25df73d9 | 2455 | const struct scsi_host_template *sht, void *host_priv, int hflag) |
c2036033 BZ |
2456 | { |
2457 | return ata_pci_init_one(pdev, ppi, sht, host_priv, hflag, 0); | |
2458 | } | |
0fe40ff8 | 2459 | EXPORT_SYMBOL_GPL(ata_pci_sff_init_one); |
1fdffbce JG |
2460 | |
2461 | #endif /* CONFIG_PCI */ | |
9f2f7210 | 2462 | |
9a7780c9 TH |
2463 | /* |
2464 | * BMDMA support | |
2465 | */ | |
2466 | ||
2467 | #ifdef CONFIG_ATA_BMDMA | |
2468 | ||
9f2f7210 TH |
2469 | const struct ata_port_operations ata_bmdma_port_ops = { |
2470 | .inherits = &ata_sff_port_ops, | |
2471 | ||
fe06e5f9 TH |
2472 | .error_handler = ata_bmdma_error_handler, |
2473 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
2474 | ||
f47451c4 | 2475 | .qc_prep = ata_bmdma_qc_prep, |
360ff783 | 2476 | .qc_issue = ata_bmdma_qc_issue, |
f47451c4 | 2477 | |
37f65b8b | 2478 | .sff_irq_clear = ata_bmdma_irq_clear, |
9f2f7210 TH |
2479 | .bmdma_setup = ata_bmdma_setup, |
2480 | .bmdma_start = ata_bmdma_start, | |
2481 | .bmdma_stop = ata_bmdma_stop, | |
2482 | .bmdma_status = ata_bmdma_status, | |
c7087652 TH |
2483 | |
2484 | .port_start = ata_bmdma_port_start, | |
9f2f7210 TH |
2485 | }; |
2486 | EXPORT_SYMBOL_GPL(ata_bmdma_port_ops); | |
2487 | ||
2488 | const struct ata_port_operations ata_bmdma32_port_ops = { | |
2489 | .inherits = &ata_bmdma_port_ops, | |
2490 | ||
2491 | .sff_data_xfer = ata_sff_data_xfer32, | |
c7087652 | 2492 | .port_start = ata_bmdma_port_start32, |
9f2f7210 TH |
2493 | }; |
2494 | EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops); | |
2495 | ||
f47451c4 TH |
2496 | /** |
2497 | * ata_bmdma_fill_sg - Fill PCI IDE PRD table | |
2498 | * @qc: Metadata associated with taskfile to be transferred | |
2499 | * | |
2500 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
2501 | * associated with the current disk command. | |
2502 | * | |
2503 | * LOCKING: | |
2504 | * spin_lock_irqsave(host lock) | |
2505 | * | |
2506 | */ | |
2507 | static void ata_bmdma_fill_sg(struct ata_queued_cmd *qc) | |
2508 | { | |
2509 | struct ata_port *ap = qc->ap; | |
f60d7011 | 2510 | struct ata_bmdma_prd *prd = ap->bmdma_prd; |
f47451c4 TH |
2511 | struct scatterlist *sg; |
2512 | unsigned int si, pi; | |
2513 | ||
2514 | pi = 0; | |
2515 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
2516 | u32 addr, offset; | |
2517 | u32 sg_len, len; | |
2518 | ||
2519 | /* determine if physical DMA addr spans 64K boundary. | |
2520 | * Note h/w doesn't support 64-bit, so we unconditionally | |
2521 | * truncate dma_addr_t to u32. | |
2522 | */ | |
2523 | addr = (u32) sg_dma_address(sg); | |
2524 | sg_len = sg_dma_len(sg); | |
2525 | ||
2526 | while (sg_len) { | |
2527 | offset = addr & 0xffff; | |
2528 | len = sg_len; | |
2529 | if ((offset + sg_len) > 0x10000) | |
2530 | len = 0x10000 - offset; | |
2531 | ||
f60d7011 TH |
2532 | prd[pi].addr = cpu_to_le32(addr); |
2533 | prd[pi].flags_len = cpu_to_le32(len & 0xffff); | |
f47451c4 TH |
2534 | |
2535 | pi++; | |
2536 | sg_len -= len; | |
2537 | addr += len; | |
2538 | } | |
2539 | } | |
2540 | ||
f60d7011 | 2541 | prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); |
f47451c4 TH |
2542 | } |
2543 | ||
2544 | /** | |
2545 | * ata_bmdma_fill_sg_dumb - Fill PCI IDE PRD table | |
2546 | * @qc: Metadata associated with taskfile to be transferred | |
2547 | * | |
2548 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
2549 | * associated with the current disk command. Perform the fill | |
2550 | * so that we avoid writing any length 64K records for | |
2551 | * controllers that don't follow the spec. | |
2552 | * | |
2553 | * LOCKING: | |
2554 | * spin_lock_irqsave(host lock) | |
2555 | * | |
2556 | */ | |
2557 | static void ata_bmdma_fill_sg_dumb(struct ata_queued_cmd *qc) | |
2558 | { | |
2559 | struct ata_port *ap = qc->ap; | |
f60d7011 | 2560 | struct ata_bmdma_prd *prd = ap->bmdma_prd; |
f47451c4 TH |
2561 | struct scatterlist *sg; |
2562 | unsigned int si, pi; | |
2563 | ||
2564 | pi = 0; | |
2565 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
2566 | u32 addr, offset; | |
2567 | u32 sg_len, len, blen; | |
2568 | ||
2569 | /* determine if physical DMA addr spans 64K boundary. | |
2570 | * Note h/w doesn't support 64-bit, so we unconditionally | |
2571 | * truncate dma_addr_t to u32. | |
2572 | */ | |
2573 | addr = (u32) sg_dma_address(sg); | |
2574 | sg_len = sg_dma_len(sg); | |
2575 | ||
2576 | while (sg_len) { | |
2577 | offset = addr & 0xffff; | |
2578 | len = sg_len; | |
2579 | if ((offset + sg_len) > 0x10000) | |
2580 | len = 0x10000 - offset; | |
2581 | ||
2582 | blen = len & 0xffff; | |
f60d7011 | 2583 | prd[pi].addr = cpu_to_le32(addr); |
f47451c4 TH |
2584 | if (blen == 0) { |
2585 | /* Some PATA chipsets like the CS5530 can't | |
2586 | cope with 0x0000 meaning 64K as the spec | |
2587 | says */ | |
f60d7011 | 2588 | prd[pi].flags_len = cpu_to_le32(0x8000); |
f47451c4 | 2589 | blen = 0x8000; |
f60d7011 | 2590 | prd[++pi].addr = cpu_to_le32(addr + 0x8000); |
f47451c4 | 2591 | } |
f60d7011 | 2592 | prd[pi].flags_len = cpu_to_le32(blen); |
f47451c4 TH |
2593 | |
2594 | pi++; | |
2595 | sg_len -= len; | |
2596 | addr += len; | |
2597 | } | |
2598 | } | |
2599 | ||
f60d7011 | 2600 | prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); |
f47451c4 TH |
2601 | } |
2602 | ||
2603 | /** | |
2604 | * ata_bmdma_qc_prep - Prepare taskfile for submission | |
2605 | * @qc: Metadata associated with taskfile to be prepared | |
2606 | * | |
2607 | * Prepare ATA taskfile for submission. | |
2608 | * | |
2609 | * LOCKING: | |
2610 | * spin_lock_irqsave(host lock) | |
2611 | */ | |
95364f36 | 2612 | enum ata_completion_errors ata_bmdma_qc_prep(struct ata_queued_cmd *qc) |
f47451c4 TH |
2613 | { |
2614 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
95364f36 | 2615 | return AC_ERR_OK; |
f47451c4 TH |
2616 | |
2617 | ata_bmdma_fill_sg(qc); | |
95364f36 JS |
2618 | |
2619 | return AC_ERR_OK; | |
f47451c4 TH |
2620 | } |
2621 | EXPORT_SYMBOL_GPL(ata_bmdma_qc_prep); | |
2622 | ||
2623 | /** | |
2624 | * ata_bmdma_dumb_qc_prep - Prepare taskfile for submission | |
2625 | * @qc: Metadata associated with taskfile to be prepared | |
2626 | * | |
2627 | * Prepare ATA taskfile for submission. | |
2628 | * | |
2629 | * LOCKING: | |
2630 | * spin_lock_irqsave(host lock) | |
2631 | */ | |
95364f36 | 2632 | enum ata_completion_errors ata_bmdma_dumb_qc_prep(struct ata_queued_cmd *qc) |
f47451c4 TH |
2633 | { |
2634 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
95364f36 | 2635 | return AC_ERR_OK; |
f47451c4 TH |
2636 | |
2637 | ata_bmdma_fill_sg_dumb(qc); | |
95364f36 JS |
2638 | |
2639 | return AC_ERR_OK; | |
f47451c4 TH |
2640 | } |
2641 | EXPORT_SYMBOL_GPL(ata_bmdma_dumb_qc_prep); | |
2642 | ||
360ff783 TH |
2643 | /** |
2644 | * ata_bmdma_qc_issue - issue taskfile to a BMDMA controller | |
2645 | * @qc: command to issue to device | |
2646 | * | |
2647 | * This function issues a PIO, NODATA or DMA command to a | |
2648 | * SFF/BMDMA controller. PIO and NODATA are handled by | |
2649 | * ata_sff_qc_issue(). | |
2650 | * | |
2651 | * LOCKING: | |
2652 | * spin_lock_irqsave(host lock) | |
2653 | * | |
2654 | * RETURNS: | |
2655 | * Zero on success, AC_ERR_* mask on failure | |
2656 | */ | |
2657 | unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd *qc) | |
2658 | { | |
2659 | struct ata_port *ap = qc->ap; | |
ea3c6450 | 2660 | struct ata_link *link = qc->dev->link; |
360ff783 | 2661 | |
360ff783 TH |
2662 | /* defer PIO handling to sff_qc_issue */ |
2663 | if (!ata_is_dma(qc->tf.protocol)) | |
2664 | return ata_sff_qc_issue(qc); | |
2665 | ||
2666 | /* select the device */ | |
2667 | ata_dev_select(ap, qc->dev->devno, 1, 0); | |
2668 | ||
2669 | /* start the command */ | |
2670 | switch (qc->tf.protocol) { | |
2671 | case ATA_PROT_DMA: | |
2672 | WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING); | |
2673 | ||
c206a389 | 2674 | trace_ata_tf_load(ap, &qc->tf); |
360ff783 | 2675 | ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ |
c206a389 | 2676 | trace_ata_bmdma_setup(ap, &qc->tf, qc->tag); |
360ff783 | 2677 | ap->ops->bmdma_setup(qc); /* set up bmdma */ |
c206a389 | 2678 | trace_ata_bmdma_start(ap, &qc->tf, qc->tag); |
360ff783 TH |
2679 | ap->ops->bmdma_start(qc); /* initiate bmdma */ |
2680 | ap->hsm_task_state = HSM_ST_LAST; | |
2681 | break; | |
2682 | ||
2683 | case ATAPI_PROT_DMA: | |
2684 | WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING); | |
2685 | ||
c206a389 | 2686 | trace_ata_tf_load(ap, &qc->tf); |
360ff783 | 2687 | ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ |
c206a389 | 2688 | trace_ata_bmdma_setup(ap, &qc->tf, qc->tag); |
360ff783 TH |
2689 | ap->ops->bmdma_setup(qc); /* set up bmdma */ |
2690 | ap->hsm_task_state = HSM_ST_FIRST; | |
2691 | ||
2692 | /* send cdb by polling if no cdb interrupt */ | |
2693 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
ea3c6450 | 2694 | ata_sff_queue_pio_task(link, 0); |
360ff783 TH |
2695 | break; |
2696 | ||
2697 | default: | |
2698 | WARN_ON(1); | |
2699 | return AC_ERR_SYSTEM; | |
2700 | } | |
2701 | ||
2702 | return 0; | |
2703 | } | |
2704 | EXPORT_SYMBOL_GPL(ata_bmdma_qc_issue); | |
2705 | ||
c3b28894 TH |
2706 | /** |
2707 | * ata_bmdma_port_intr - Handle BMDMA port interrupt | |
2708 | * @ap: Port on which interrupt arrived (possibly...) | |
2709 | * @qc: Taskfile currently active in engine | |
2710 | * | |
2711 | * Handle port interrupt for given queued command. | |
2712 | * | |
2713 | * LOCKING: | |
2714 | * spin_lock_irqsave(host lock) | |
2715 | * | |
2716 | * RETURNS: | |
2717 | * One if interrupt was handled, zero if not (shared irq). | |
2718 | */ | |
2719 | unsigned int ata_bmdma_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc) | |
2720 | { | |
2721 | struct ata_eh_info *ehi = &ap->link.eh_info; | |
2722 | u8 host_stat = 0; | |
2723 | bool bmdma_stopped = false; | |
2724 | unsigned int handled; | |
2725 | ||
2726 | if (ap->hsm_task_state == HSM_ST_LAST && ata_is_dma(qc->tf.protocol)) { | |
2727 | /* check status of DMA engine */ | |
2728 | host_stat = ap->ops->bmdma_status(ap); | |
c206a389 | 2729 | trace_ata_bmdma_status(ap, host_stat); |
c3b28894 TH |
2730 | |
2731 | /* if it's not our irq... */ | |
2732 | if (!(host_stat & ATA_DMA_INTR)) | |
2733 | return ata_sff_idle_irq(ap); | |
2734 | ||
2735 | /* before we do anything else, clear DMA-Start bit */ | |
c206a389 | 2736 | trace_ata_bmdma_stop(ap, &qc->tf, qc->tag); |
c3b28894 TH |
2737 | ap->ops->bmdma_stop(qc); |
2738 | bmdma_stopped = true; | |
2739 | ||
2740 | if (unlikely(host_stat & ATA_DMA_ERR)) { | |
25985edc | 2741 | /* error when transferring data to/from memory */ |
c3b28894 TH |
2742 | qc->err_mask |= AC_ERR_HOST_BUS; |
2743 | ap->hsm_task_state = HSM_ST_ERR; | |
2744 | } | |
2745 | } | |
2746 | ||
2747 | handled = __ata_sff_port_intr(ap, qc, bmdma_stopped); | |
2748 | ||
2749 | if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol)) | |
2750 | ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat); | |
2751 | ||
2752 | return handled; | |
2753 | } | |
2754 | EXPORT_SYMBOL_GPL(ata_bmdma_port_intr); | |
2755 | ||
2756 | /** | |
2757 | * ata_bmdma_interrupt - Default BMDMA ATA host interrupt handler | |
2758 | * @irq: irq line (unused) | |
2759 | * @dev_instance: pointer to our ata_host information structure | |
2760 | * | |
2761 | * Default interrupt handler for PCI IDE devices. Calls | |
2762 | * ata_bmdma_port_intr() for each port that is not disabled. | |
2763 | * | |
2764 | * LOCKING: | |
2765 | * Obtains host lock during operation. | |
2766 | * | |
2767 | * RETURNS: | |
2768 | * IRQ_NONE or IRQ_HANDLED. | |
2769 | */ | |
2770 | irqreturn_t ata_bmdma_interrupt(int irq, void *dev_instance) | |
2771 | { | |
2772 | return __ata_sff_interrupt(irq, dev_instance, ata_bmdma_port_intr); | |
2773 | } | |
2774 | EXPORT_SYMBOL_GPL(ata_bmdma_interrupt); | |
2775 | ||
fe06e5f9 TH |
2776 | /** |
2777 | * ata_bmdma_error_handler - Stock error handler for BMDMA controller | |
2778 | * @ap: port to handle error for | |
2779 | * | |
2780 | * Stock error handler for BMDMA controller. It can handle both | |
2781 | * PATA and SATA controllers. Most BMDMA controllers should be | |
2782 | * able to use this EH as-is or with some added handling before | |
2783 | * and after. | |
2784 | * | |
2785 | * LOCKING: | |
2786 | * Kernel thread context (may sleep) | |
2787 | */ | |
2788 | void ata_bmdma_error_handler(struct ata_port *ap) | |
2789 | { | |
2790 | struct ata_queued_cmd *qc; | |
2791 | unsigned long flags; | |
2792 | bool thaw = false; | |
2793 | ||
2794 | qc = __ata_qc_from_tag(ap, ap->link.active_tag); | |
87629312 | 2795 | if (qc && !(qc->flags & ATA_QCFLAG_EH)) |
fe06e5f9 TH |
2796 | qc = NULL; |
2797 | ||
2798 | /* reset PIO HSM and stop DMA engine */ | |
2799 | spin_lock_irqsave(ap->lock, flags); | |
2800 | ||
2801 | if (qc && ata_is_dma(qc->tf.protocol)) { | |
2802 | u8 host_stat; | |
2803 | ||
2804 | host_stat = ap->ops->bmdma_status(ap); | |
c206a389 | 2805 | trace_ata_bmdma_status(ap, host_stat); |
fe06e5f9 TH |
2806 | |
2807 | /* BMDMA controllers indicate host bus error by | |
2808 | * setting DMA_ERR bit and timing out. As it wasn't | |
2809 | * really a timeout event, adjust error mask and | |
2810 | * cancel frozen state. | |
2811 | */ | |
2812 | if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) { | |
2813 | qc->err_mask = AC_ERR_HOST_BUS; | |
2814 | thaw = true; | |
2815 | } | |
2816 | ||
c206a389 | 2817 | trace_ata_bmdma_stop(ap, &qc->tf, qc->tag); |
fe06e5f9 TH |
2818 | ap->ops->bmdma_stop(qc); |
2819 | ||
2820 | /* if we're gonna thaw, make sure IRQ is clear */ | |
2821 | if (thaw) { | |
2822 | ap->ops->sff_check_status(ap); | |
37f65b8b TH |
2823 | if (ap->ops->sff_irq_clear) |
2824 | ap->ops->sff_irq_clear(ap); | |
fe06e5f9 TH |
2825 | } |
2826 | } | |
2827 | ||
2828 | spin_unlock_irqrestore(ap->lock, flags); | |
2829 | ||
2830 | if (thaw) | |
2831 | ata_eh_thaw_port(ap); | |
2832 | ||
2833 | ata_sff_error_handler(ap); | |
2834 | } | |
2835 | EXPORT_SYMBOL_GPL(ata_bmdma_error_handler); | |
2836 | ||
2837 | /** | |
2838 | * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for BMDMA | |
2839 | * @qc: internal command to clean up | |
2840 | * | |
2841 | * LOCKING: | |
2842 | * Kernel thread context (may sleep) | |
2843 | */ | |
2844 | void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc) | |
2845 | { | |
2846 | struct ata_port *ap = qc->ap; | |
2847 | unsigned long flags; | |
2848 | ||
2849 | if (ata_is_dma(qc->tf.protocol)) { | |
2850 | spin_lock_irqsave(ap->lock, flags); | |
c206a389 | 2851 | trace_ata_bmdma_stop(ap, &qc->tf, qc->tag); |
fe06e5f9 TH |
2852 | ap->ops->bmdma_stop(qc); |
2853 | spin_unlock_irqrestore(ap->lock, flags); | |
2854 | } | |
2855 | } | |
2856 | EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd); | |
2857 | ||
37f65b8b TH |
2858 | /** |
2859 | * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt. | |
2860 | * @ap: Port associated with this ATA transaction. | |
2861 | * | |
2862 | * Clear interrupt and error flags in DMA status register. | |
2863 | * | |
2864 | * May be used as the irq_clear() entry in ata_port_operations. | |
2865 | * | |
2866 | * LOCKING: | |
2867 | * spin_lock_irqsave(host lock) | |
2868 | */ | |
2869 | void ata_bmdma_irq_clear(struct ata_port *ap) | |
2870 | { | |
2871 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
2872 | ||
2873 | if (!mmio) | |
2874 | return; | |
2875 | ||
2876 | iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS); | |
2877 | } | |
2878 | EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear); | |
2879 | ||
9f2f7210 TH |
2880 | /** |
2881 | * ata_bmdma_setup - Set up PCI IDE BMDMA transaction | |
2882 | * @qc: Info associated with this ATA transaction. | |
2883 | * | |
2884 | * LOCKING: | |
2885 | * spin_lock_irqsave(host lock) | |
2886 | */ | |
2887 | void ata_bmdma_setup(struct ata_queued_cmd *qc) | |
2888 | { | |
2889 | struct ata_port *ap = qc->ap; | |
2890 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
2891 | u8 dmactl; | |
2892 | ||
2893 | /* load PRD table addr. */ | |
2894 | mb(); /* make sure PRD table writes are visible to controller */ | |
f60d7011 | 2895 | iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); |
9f2f7210 TH |
2896 | |
2897 | /* specify data direction, triple-check start bit is clear */ | |
2898 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2899 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | |
2900 | if (!rw) | |
2901 | dmactl |= ATA_DMA_WR; | |
2902 | iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2903 | ||
2904 | /* issue r/w command */ | |
2905 | ap->ops->sff_exec_command(ap, &qc->tf); | |
2906 | } | |
2907 | EXPORT_SYMBOL_GPL(ata_bmdma_setup); | |
2908 | ||
2909 | /** | |
2910 | * ata_bmdma_start - Start a PCI IDE BMDMA transaction | |
2911 | * @qc: Info associated with this ATA transaction. | |
2912 | * | |
2913 | * LOCKING: | |
2914 | * spin_lock_irqsave(host lock) | |
2915 | */ | |
2916 | void ata_bmdma_start(struct ata_queued_cmd *qc) | |
2917 | { | |
2918 | struct ata_port *ap = qc->ap; | |
2919 | u8 dmactl; | |
2920 | ||
2921 | /* start host DMA transaction */ | |
2922 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2923 | iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2924 | ||
2925 | /* Strictly, one may wish to issue an ioread8() here, to | |
2926 | * flush the mmio write. However, control also passes | |
2927 | * to the hardware at this point, and it will interrupt | |
2928 | * us when we are to resume control. So, in effect, | |
2929 | * we don't care when the mmio write flushes. | |
2930 | * Further, a read of the DMA status register _immediately_ | |
2931 | * following the write may not be what certain flaky hardware | |
2932 | * is expected, so I think it is best to not add a readb() | |
2933 | * without first all the MMIO ATA cards/mobos. | |
2934 | * Or maybe I'm just being paranoid. | |
2935 | * | |
2936 | * FIXME: The posting of this write means I/O starts are | |
25985edc | 2937 | * unnecessarily delayed for MMIO |
9f2f7210 TH |
2938 | */ |
2939 | } | |
2940 | EXPORT_SYMBOL_GPL(ata_bmdma_start); | |
2941 | ||
2942 | /** | |
2943 | * ata_bmdma_stop - Stop PCI IDE BMDMA transfer | |
2944 | * @qc: Command we are ending DMA for | |
2945 | * | |
2946 | * Clears the ATA_DMA_START flag in the dma control register | |
2947 | * | |
2948 | * May be used as the bmdma_stop() entry in ata_port_operations. | |
2949 | * | |
2950 | * LOCKING: | |
2951 | * spin_lock_irqsave(host lock) | |
2952 | */ | |
2953 | void ata_bmdma_stop(struct ata_queued_cmd *qc) | |
2954 | { | |
2955 | struct ata_port *ap = qc->ap; | |
2956 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
2957 | ||
2958 | /* clear start/stop bit */ | |
2959 | iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, | |
2960 | mmio + ATA_DMA_CMD); | |
2961 | ||
2962 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | |
2963 | ata_sff_dma_pause(ap); | |
2964 | } | |
2965 | EXPORT_SYMBOL_GPL(ata_bmdma_stop); | |
2966 | ||
2967 | /** | |
2968 | * ata_bmdma_status - Read PCI IDE BMDMA status | |
2969 | * @ap: Port associated with this ATA transaction. | |
2970 | * | |
2971 | * Read and return BMDMA status register. | |
2972 | * | |
2973 | * May be used as the bmdma_status() entry in ata_port_operations. | |
2974 | * | |
2975 | * LOCKING: | |
2976 | * spin_lock_irqsave(host lock) | |
2977 | */ | |
2978 | u8 ata_bmdma_status(struct ata_port *ap) | |
2979 | { | |
2980 | return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); | |
2981 | } | |
2982 | EXPORT_SYMBOL_GPL(ata_bmdma_status); | |
2983 | ||
c7087652 TH |
2984 | |
2985 | /** | |
2986 | * ata_bmdma_port_start - Set port up for bmdma. | |
2987 | * @ap: Port to initialize | |
2988 | * | |
2989 | * Called just after data structures for each port are | |
2990 | * initialized. Allocates space for PRD table. | |
2991 | * | |
2992 | * May be used as the port_start() entry in ata_port_operations. | |
2993 | * | |
2994 | * LOCKING: | |
2995 | * Inherited from caller. | |
2996 | */ | |
2997 | int ata_bmdma_port_start(struct ata_port *ap) | |
2998 | { | |
2999 | if (ap->mwdma_mask || ap->udma_mask) { | |
f60d7011 TH |
3000 | ap->bmdma_prd = |
3001 | dmam_alloc_coherent(ap->host->dev, ATA_PRD_TBL_SZ, | |
3002 | &ap->bmdma_prd_dma, GFP_KERNEL); | |
3003 | if (!ap->bmdma_prd) | |
c7087652 TH |
3004 | return -ENOMEM; |
3005 | } | |
3006 | ||
3007 | return 0; | |
3008 | } | |
3009 | EXPORT_SYMBOL_GPL(ata_bmdma_port_start); | |
3010 | ||
3011 | /** | |
3012 | * ata_bmdma_port_start32 - Set port up for dma. | |
3013 | * @ap: Port to initialize | |
3014 | * | |
3015 | * Called just after data structures for each port are | |
3016 | * initialized. Enables 32bit PIO and allocates space for PRD | |
3017 | * table. | |
3018 | * | |
3019 | * May be used as the port_start() entry in ata_port_operations for | |
3020 | * devices that are capable of 32bit PIO. | |
3021 | * | |
3022 | * LOCKING: | |
3023 | * Inherited from caller. | |
3024 | */ | |
3025 | int ata_bmdma_port_start32(struct ata_port *ap) | |
3026 | { | |
3027 | ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE; | |
3028 | return ata_bmdma_port_start(ap); | |
3029 | } | |
3030 | EXPORT_SYMBOL_GPL(ata_bmdma_port_start32); | |
3031 | ||
9f2f7210 TH |
3032 | #ifdef CONFIG_PCI |
3033 | ||
3034 | /** | |
3035 | * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex | |
3036 | * @pdev: PCI device | |
3037 | * | |
3038 | * Some PCI ATA devices report simplex mode but in fact can be told to | |
3039 | * enter non simplex mode. This implements the necessary logic to | |
3040 | * perform the task on such devices. Calling it on other devices will | |
3041 | * have -undefined- behaviour. | |
3042 | */ | |
3043 | int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev) | |
3044 | { | |
3045 | unsigned long bmdma = pci_resource_start(pdev, 4); | |
3046 | u8 simplex; | |
3047 | ||
3048 | if (bmdma == 0) | |
3049 | return -ENOENT; | |
3050 | ||
3051 | simplex = inb(bmdma + 0x02); | |
3052 | outb(simplex & 0x60, bmdma + 0x02); | |
3053 | simplex = inb(bmdma + 0x02); | |
3054 | if (simplex & 0x80) | |
3055 | return -EOPNOTSUPP; | |
3056 | return 0; | |
3057 | } | |
3058 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex); | |
3059 | ||
c7087652 TH |
3060 | static void ata_bmdma_nodma(struct ata_host *host, const char *reason) |
3061 | { | |
3062 | int i; | |
3063 | ||
a44fec1f | 3064 | dev_err(host->dev, "BMDMA: %s, falling back to PIO\n", reason); |
c7087652 TH |
3065 | |
3066 | for (i = 0; i < 2; i++) { | |
3067 | host->ports[i]->mwdma_mask = 0; | |
3068 | host->ports[i]->udma_mask = 0; | |
3069 | } | |
3070 | } | |
3071 | ||
9f2f7210 TH |
3072 | /** |
3073 | * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host | |
3074 | * @host: target ATA host | |
3075 | * | |
3076 | * Acquire PCI BMDMA resources and initialize @host accordingly. | |
3077 | * | |
3078 | * LOCKING: | |
3079 | * Inherited from calling layer (may sleep). | |
9f2f7210 | 3080 | */ |
c7087652 | 3081 | void ata_pci_bmdma_init(struct ata_host *host) |
9f2f7210 TH |
3082 | { |
3083 | struct device *gdev = host->dev; | |
3084 | struct pci_dev *pdev = to_pci_dev(gdev); | |
3085 | int i, rc; | |
3086 | ||
3087 | /* No BAR4 allocation: No DMA */ | |
c7087652 TH |
3088 | if (pci_resource_start(pdev, 4) == 0) { |
3089 | ata_bmdma_nodma(host, "BAR4 is zero"); | |
3090 | return; | |
3091 | } | |
9f2f7210 | 3092 | |
c7087652 TH |
3093 | /* |
3094 | * Some controllers require BMDMA region to be initialized | |
3095 | * even if DMA is not in use to clear IRQ status via | |
3096 | * ->sff_irq_clear method. Try to initialize bmdma_addr | |
3097 | * regardless of dma masks. | |
3098 | */ | |
b5e55556 | 3099 | rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK); |
9f2f7210 | 3100 | if (rc) |
c7087652 | 3101 | ata_bmdma_nodma(host, "failed to set dma mask"); |
9f2f7210 TH |
3102 | |
3103 | /* request and iomap DMA region */ | |
3104 | rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev)); | |
3105 | if (rc) { | |
c7087652 TH |
3106 | ata_bmdma_nodma(host, "failed to request/iomap BAR4"); |
3107 | return; | |
9f2f7210 TH |
3108 | } |
3109 | host->iomap = pcim_iomap_table(pdev); | |
3110 | ||
3111 | for (i = 0; i < 2; i++) { | |
3112 | struct ata_port *ap = host->ports[i]; | |
3113 | void __iomem *bmdma = host->iomap[4] + 8 * i; | |
3114 | ||
3115 | if (ata_port_is_dummy(ap)) | |
3116 | continue; | |
3117 | ||
3118 | ap->ioaddr.bmdma_addr = bmdma; | |
3119 | if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) && | |
3120 | (ioread8(bmdma + 2) & 0x80)) | |
3121 | host->flags |= ATA_HOST_SIMPLEX; | |
3122 | ||
3123 | ata_port_desc(ap, "bmdma 0x%llx", | |
3124 | (unsigned long long)pci_resource_start(pdev, 4) + 8 * i); | |
3125 | } | |
9f2f7210 TH |
3126 | } |
3127 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_init); | |
3128 | ||
1c5afdf7 TH |
3129 | /** |
3130 | * ata_pci_bmdma_prepare_host - helper to prepare PCI BMDMA ATA host | |
3131 | * @pdev: target PCI device | |
3132 | * @ppi: array of port_info, must be enough for two ports | |
3133 | * @r_host: out argument for the initialized ATA host | |
3134 | * | |
3135 | * Helper to allocate BMDMA ATA host for @pdev, acquire all PCI | |
3136 | * resources and initialize it accordingly in one go. | |
3137 | * | |
3138 | * LOCKING: | |
3139 | * Inherited from calling layer (may sleep). | |
3140 | * | |
3141 | * RETURNS: | |
3142 | * 0 on success, -errno otherwise. | |
3143 | */ | |
3144 | int ata_pci_bmdma_prepare_host(struct pci_dev *pdev, | |
3145 | const struct ata_port_info * const * ppi, | |
3146 | struct ata_host **r_host) | |
3147 | { | |
3148 | int rc; | |
3149 | ||
3150 | rc = ata_pci_sff_prepare_host(pdev, ppi, r_host); | |
3151 | if (rc) | |
3152 | return rc; | |
3153 | ||
3154 | ata_pci_bmdma_init(*r_host); | |
3155 | return 0; | |
3156 | } | |
3157 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_prepare_host); | |
3158 | ||
3159 | /** | |
3160 | * ata_pci_bmdma_init_one - Initialize/register BMDMA PCI IDE controller | |
3161 | * @pdev: Controller to be initialized | |
3162 | * @ppi: array of port_info, must be enough for two ports | |
3163 | * @sht: scsi_host_template to use when registering the host | |
3164 | * @host_priv: host private_data | |
3165 | * @hflags: host flags | |
3166 | * | |
3167 | * This function is similar to ata_pci_sff_init_one() but also | |
3168 | * takes care of BMDMA initialization. | |
3169 | * | |
3170 | * LOCKING: | |
3171 | * Inherited from PCI layer (may sleep). | |
3172 | * | |
3173 | * RETURNS: | |
3174 | * Zero on success, negative on errno-based value on error. | |
3175 | */ | |
3176 | int ata_pci_bmdma_init_one(struct pci_dev *pdev, | |
3177 | const struct ata_port_info * const * ppi, | |
25df73d9 | 3178 | const struct scsi_host_template *sht, void *host_priv, |
1c5afdf7 TH |
3179 | int hflags) |
3180 | { | |
c2036033 | 3181 | return ata_pci_init_one(pdev, ppi, sht, host_priv, hflags, 1); |
1c5afdf7 TH |
3182 | } |
3183 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_init_one); | |
3184 | ||
9f2f7210 | 3185 | #endif /* CONFIG_PCI */ |
9a7780c9 | 3186 | #endif /* CONFIG_ATA_BMDMA */ |
270390e1 TH |
3187 | |
3188 | /** | |
3189 | * ata_sff_port_init - Initialize SFF/BMDMA ATA port | |
3190 | * @ap: Port to initialize | |
3191 | * | |
3192 | * Called on port allocation to initialize SFF/BMDMA specific | |
3193 | * fields. | |
3194 | * | |
3195 | * LOCKING: | |
3196 | * None. | |
3197 | */ | |
3198 | void ata_sff_port_init(struct ata_port *ap) | |
3199 | { | |
c429137a | 3200 | INIT_DELAYED_WORK(&ap->sff_pio_task, ata_sff_pio_task); |
5fe7454a TH |
3201 | ap->ctl = ATA_DEVCTL_OBS; |
3202 | ap->last_ctl = 0xFF; | |
270390e1 TH |
3203 | } |
3204 | ||
3205 | int __init ata_sff_init(void) | |
3206 | { | |
6370a6ad | 3207 | ata_sff_wq = alloc_workqueue("ata_sff", WQ_MEM_RECLAIM, WQ_MAX_ACTIVE); |
c429137a TH |
3208 | if (!ata_sff_wq) |
3209 | return -ENOMEM; | |
3210 | ||
270390e1 TH |
3211 | return 0; |
3212 | } | |
3213 | ||
c43d559f | 3214 | void ata_sff_exit(void) |
270390e1 | 3215 | { |
c429137a | 3216 | destroy_workqueue(ata_sff_wq); |
270390e1 | 3217 | } |