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c82ee6d3 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1fdffbce | 2 | /* |
f3a03b09 | 3 | * libata-sff.c - helper library for PCI IDE BMDMA |
1fdffbce | 4 | * |
8c3d3d4b | 5 | * Maintained by: Tejun Heo <tj@kernel.org> |
1fdffbce JG |
6 | * Please ALWAYS copy linux-ide@vger.kernel.org |
7 | * on emails. | |
8 | * | |
9 | * Copyright 2003-2006 Red Hat, Inc. All rights reserved. | |
10 | * Copyright 2003-2006 Jeff Garzik | |
11 | * | |
1fdffbce | 12 | * libata documentation is available via 'make {ps|pdf}docs', |
9bb9a39c | 13 | * as Documentation/driver-api/libata.rst |
1fdffbce JG |
14 | * |
15 | * Hardware documentation available from http://www.t13.org/ and | |
16 | * http://www.sata-io.org/ | |
1fdffbce JG |
17 | */ |
18 | ||
1fdffbce | 19 | #include <linux/kernel.h> |
5a0e3ad6 | 20 | #include <linux/gfp.h> |
1fdffbce | 21 | #include <linux/pci.h> |
bff7832d | 22 | #include <linux/module.h> |
1fdffbce | 23 | #include <linux/libata.h> |
624d5c51 | 24 | #include <linux/highmem.h> |
1fdffbce JG |
25 | |
26 | #include "libata.h" | |
27 | ||
c429137a TH |
28 | static struct workqueue_struct *ata_sff_wq; |
29 | ||
624d5c51 TH |
30 | const struct ata_port_operations ata_sff_port_ops = { |
31 | .inherits = &ata_base_port_ops, | |
32 | ||
f47451c4 | 33 | .qc_prep = ata_noop_qc_prep, |
9363c382 | 34 | .qc_issue = ata_sff_qc_issue, |
4c9bf4e7 | 35 | .qc_fill_rtf = ata_sff_qc_fill_rtf, |
9363c382 TH |
36 | |
37 | .freeze = ata_sff_freeze, | |
38 | .thaw = ata_sff_thaw, | |
0aa1113d | 39 | .prereset = ata_sff_prereset, |
9363c382 | 40 | .softreset = ata_sff_softreset, |
57c9efdf | 41 | .hardreset = sata_sff_hardreset, |
203c75b8 | 42 | .postreset = ata_sff_postreset, |
9363c382 | 43 | .error_handler = ata_sff_error_handler, |
9363c382 | 44 | |
5682ed33 TH |
45 | .sff_dev_select = ata_sff_dev_select, |
46 | .sff_check_status = ata_sff_check_status, | |
47 | .sff_tf_load = ata_sff_tf_load, | |
48 | .sff_tf_read = ata_sff_tf_read, | |
49 | .sff_exec_command = ata_sff_exec_command, | |
50 | .sff_data_xfer = ata_sff_data_xfer, | |
8244cd05 | 51 | .sff_drain_fifo = ata_sff_drain_fifo, |
624d5c51 | 52 | |
c96f1732 | 53 | .lost_interrupt = ata_sff_lost_interrupt, |
624d5c51 | 54 | }; |
0fe40ff8 | 55 | EXPORT_SYMBOL_GPL(ata_sff_port_ops); |
624d5c51 | 56 | |
272f7884 | 57 | /** |
9363c382 | 58 | * ata_sff_check_status - Read device status reg & clear interrupt |
272f7884 TH |
59 | * @ap: port where the device is |
60 | * | |
61 | * Reads ATA taskfile status register for currently-selected device | |
62 | * and return its value. This also clears pending interrupts | |
63 | * from this device | |
64 | * | |
65 | * LOCKING: | |
66 | * Inherited from caller. | |
67 | */ | |
9363c382 | 68 | u8 ata_sff_check_status(struct ata_port *ap) |
272f7884 TH |
69 | { |
70 | return ioread8(ap->ioaddr.status_addr); | |
71 | } | |
0fe40ff8 | 72 | EXPORT_SYMBOL_GPL(ata_sff_check_status); |
272f7884 TH |
73 | |
74 | /** | |
9363c382 | 75 | * ata_sff_altstatus - Read device alternate status reg |
272f7884 TH |
76 | * @ap: port where the device is |
77 | * | |
78 | * Reads ATA taskfile alternate status register for | |
79 | * currently-selected device and return its value. | |
80 | * | |
81 | * Note: may NOT be used as the check_altstatus() entry in | |
82 | * ata_port_operations. | |
83 | * | |
84 | * LOCKING: | |
85 | * Inherited from caller. | |
86 | */ | |
a57c1bad | 87 | static u8 ata_sff_altstatus(struct ata_port *ap) |
624d5c51 | 88 | { |
5682ed33 TH |
89 | if (ap->ops->sff_check_altstatus) |
90 | return ap->ops->sff_check_altstatus(ap); | |
624d5c51 TH |
91 | |
92 | return ioread8(ap->ioaddr.altstatus_addr); | |
93 | } | |
94 | ||
a57c1bad AC |
95 | /** |
96 | * ata_sff_irq_status - Check if the device is busy | |
97 | * @ap: port where the device is | |
98 | * | |
99 | * Determine if the port is currently busy. Uses altstatus | |
100 | * if available in order to avoid clearing shared IRQ status | |
101 | * when finding an IRQ source. Non ctl capable devices don't | |
102 | * share interrupt lines fortunately for us. | |
103 | * | |
104 | * LOCKING: | |
105 | * Inherited from caller. | |
106 | */ | |
107 | static u8 ata_sff_irq_status(struct ata_port *ap) | |
108 | { | |
109 | u8 status; | |
110 | ||
111 | if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) { | |
112 | status = ata_sff_altstatus(ap); | |
113 | /* Not us: We are busy */ | |
114 | if (status & ATA_BUSY) | |
0fe40ff8 | 115 | return status; |
a57c1bad AC |
116 | } |
117 | /* Clear INTRQ latch */ | |
6311c90a | 118 | status = ap->ops->sff_check_status(ap); |
a57c1bad AC |
119 | return status; |
120 | } | |
121 | ||
122 | /** | |
123 | * ata_sff_sync - Flush writes | |
124 | * @ap: Port to wait for. | |
125 | * | |
126 | * CAUTION: | |
127 | * If we have an mmio device with no ctl and no altstatus | |
128 | * method this will fail. No such devices are known to exist. | |
129 | * | |
130 | * LOCKING: | |
131 | * Inherited from caller. | |
132 | */ | |
133 | ||
134 | static void ata_sff_sync(struct ata_port *ap) | |
135 | { | |
136 | if (ap->ops->sff_check_altstatus) | |
137 | ap->ops->sff_check_altstatus(ap); | |
138 | else if (ap->ioaddr.altstatus_addr) | |
139 | ioread8(ap->ioaddr.altstatus_addr); | |
140 | } | |
141 | ||
142 | /** | |
143 | * ata_sff_pause - Flush writes and wait 400nS | |
144 | * @ap: Port to pause for. | |
145 | * | |
146 | * CAUTION: | |
147 | * If we have an mmio device with no ctl and no altstatus | |
148 | * method this will fail. No such devices are known to exist. | |
149 | * | |
150 | * LOCKING: | |
151 | * Inherited from caller. | |
152 | */ | |
153 | ||
154 | void ata_sff_pause(struct ata_port *ap) | |
155 | { | |
156 | ata_sff_sync(ap); | |
157 | ndelay(400); | |
158 | } | |
0fe40ff8 | 159 | EXPORT_SYMBOL_GPL(ata_sff_pause); |
a57c1bad AC |
160 | |
161 | /** | |
162 | * ata_sff_dma_pause - Pause before commencing DMA | |
163 | * @ap: Port to pause for. | |
164 | * | |
165 | * Perform I/O fencing and ensure sufficient cycle delays occur | |
166 | * for the HDMA1:0 transition | |
167 | */ | |
0fe40ff8 | 168 | |
a57c1bad AC |
169 | void ata_sff_dma_pause(struct ata_port *ap) |
170 | { | |
171 | if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) { | |
172 | /* An altstatus read will cause the needed delay without | |
173 | messing up the IRQ status */ | |
174 | ata_sff_altstatus(ap); | |
175 | return; | |
176 | } | |
177 | /* There are no DMA controllers without ctl. BUG here to ensure | |
178 | we never violate the HDMA1:0 transition timing and risk | |
179 | corruption. */ | |
180 | BUG(); | |
181 | } | |
0fe40ff8 | 182 | EXPORT_SYMBOL_GPL(ata_sff_dma_pause); |
a57c1bad | 183 | |
624d5c51 | 184 | /** |
9363c382 | 185 | * ata_sff_busy_sleep - sleep until BSY clears, or timeout |
624d5c51 | 186 | * @ap: port containing status register to be polled |
341c2c95 TH |
187 | * @tmout_pat: impatience timeout in msecs |
188 | * @tmout: overall timeout in msecs | |
624d5c51 TH |
189 | * |
190 | * Sleep until ATA Status register bit BSY clears, | |
191 | * or a timeout occurs. | |
192 | * | |
193 | * LOCKING: | |
194 | * Kernel thread context (may sleep). | |
195 | * | |
196 | * RETURNS: | |
197 | * 0 on success, -errno otherwise. | |
198 | */ | |
9363c382 TH |
199 | int ata_sff_busy_sleep(struct ata_port *ap, |
200 | unsigned long tmout_pat, unsigned long tmout) | |
624d5c51 TH |
201 | { |
202 | unsigned long timer_start, timeout; | |
203 | u8 status; | |
204 | ||
9363c382 | 205 | status = ata_sff_busy_wait(ap, ATA_BUSY, 300); |
624d5c51 | 206 | timer_start = jiffies; |
341c2c95 | 207 | timeout = ata_deadline(timer_start, tmout_pat); |
624d5c51 TH |
208 | while (status != 0xff && (status & ATA_BUSY) && |
209 | time_before(jiffies, timeout)) { | |
97750ceb | 210 | ata_msleep(ap, 50); |
9363c382 | 211 | status = ata_sff_busy_wait(ap, ATA_BUSY, 3); |
624d5c51 TH |
212 | } |
213 | ||
214 | if (status != 0xff && (status & ATA_BUSY)) | |
a9a79dfe JP |
215 | ata_port_warn(ap, |
216 | "port is slow to respond, please be patient (Status 0x%x)\n", | |
217 | status); | |
624d5c51 | 218 | |
341c2c95 | 219 | timeout = ata_deadline(timer_start, tmout); |
624d5c51 TH |
220 | while (status != 0xff && (status & ATA_BUSY) && |
221 | time_before(jiffies, timeout)) { | |
97750ceb | 222 | ata_msleep(ap, 50); |
5682ed33 | 223 | status = ap->ops->sff_check_status(ap); |
624d5c51 TH |
224 | } |
225 | ||
226 | if (status == 0xff) | |
227 | return -ENODEV; | |
228 | ||
229 | if (status & ATA_BUSY) { | |
a9a79dfe JP |
230 | ata_port_err(ap, |
231 | "port failed to respond (%lu secs, Status 0x%x)\n", | |
232 | DIV_ROUND_UP(tmout, 1000), status); | |
624d5c51 TH |
233 | return -EBUSY; |
234 | } | |
235 | ||
236 | return 0; | |
237 | } | |
0fe40ff8 | 238 | EXPORT_SYMBOL_GPL(ata_sff_busy_sleep); |
624d5c51 | 239 | |
aa2731ad TH |
240 | static int ata_sff_check_ready(struct ata_link *link) |
241 | { | |
242 | u8 status = link->ap->ops->sff_check_status(link->ap); | |
243 | ||
78ab88f0 | 244 | return ata_check_ready(status); |
aa2731ad TH |
245 | } |
246 | ||
624d5c51 | 247 | /** |
9363c382 | 248 | * ata_sff_wait_ready - sleep until BSY clears, or timeout |
705e76be | 249 | * @link: SFF link to wait ready status for |
624d5c51 TH |
250 | * @deadline: deadline jiffies for the operation |
251 | * | |
252 | * Sleep until ATA Status register bit BSY clears, or timeout | |
253 | * occurs. | |
254 | * | |
255 | * LOCKING: | |
256 | * Kernel thread context (may sleep). | |
257 | * | |
258 | * RETURNS: | |
259 | * 0 on success, -errno otherwise. | |
260 | */ | |
705e76be | 261 | int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline) |
624d5c51 | 262 | { |
aa2731ad | 263 | return ata_wait_ready(link, deadline, ata_sff_check_ready); |
624d5c51 | 264 | } |
0fe40ff8 | 265 | EXPORT_SYMBOL_GPL(ata_sff_wait_ready); |
624d5c51 | 266 | |
41dec29b SS |
267 | /** |
268 | * ata_sff_set_devctl - Write device control reg | |
269 | * @ap: port where the device is | |
270 | * @ctl: value to write | |
271 | * | |
272 | * Writes ATA taskfile device control register. | |
273 | * | |
274 | * Note: may NOT be used as the sff_set_devctl() entry in | |
275 | * ata_port_operations. | |
276 | * | |
277 | * LOCKING: | |
278 | * Inherited from caller. | |
279 | */ | |
280 | static void ata_sff_set_devctl(struct ata_port *ap, u8 ctl) | |
281 | { | |
282 | if (ap->ops->sff_set_devctl) | |
283 | ap->ops->sff_set_devctl(ap, ctl); | |
284 | else | |
285 | iowrite8(ctl, ap->ioaddr.ctl_addr); | |
286 | } | |
287 | ||
624d5c51 | 288 | /** |
9363c382 | 289 | * ata_sff_dev_select - Select device 0/1 on ATA bus |
624d5c51 TH |
290 | * @ap: ATA channel to manipulate |
291 | * @device: ATA device (numbered from zero) to select | |
292 | * | |
293 | * Use the method defined in the ATA specification to | |
294 | * make either device 0, or device 1, active on the | |
295 | * ATA channel. Works with both PIO and MMIO. | |
296 | * | |
297 | * May be used as the dev_select() entry in ata_port_operations. | |
298 | * | |
299 | * LOCKING: | |
300 | * caller. | |
301 | */ | |
9363c382 | 302 | void ata_sff_dev_select(struct ata_port *ap, unsigned int device) |
624d5c51 TH |
303 | { |
304 | u8 tmp; | |
305 | ||
306 | if (device == 0) | |
307 | tmp = ATA_DEVICE_OBS; | |
308 | else | |
309 | tmp = ATA_DEVICE_OBS | ATA_DEV1; | |
310 | ||
311 | iowrite8(tmp, ap->ioaddr.device_addr); | |
9363c382 | 312 | ata_sff_pause(ap); /* needed; also flushes, for mmio */ |
624d5c51 | 313 | } |
0fe40ff8 | 314 | EXPORT_SYMBOL_GPL(ata_sff_dev_select); |
624d5c51 TH |
315 | |
316 | /** | |
317 | * ata_dev_select - Select device 0/1 on ATA bus | |
318 | * @ap: ATA channel to manipulate | |
319 | * @device: ATA device (numbered from zero) to select | |
320 | * @wait: non-zero to wait for Status register BSY bit to clear | |
321 | * @can_sleep: non-zero if context allows sleeping | |
322 | * | |
323 | * Use the method defined in the ATA specification to | |
324 | * make either device 0, or device 1, active on the | |
325 | * ATA channel. | |
326 | * | |
9363c382 TH |
327 | * This is a high-level version of ata_sff_dev_select(), which |
328 | * additionally provides the services of inserting the proper | |
329 | * pauses and status polling, where needed. | |
624d5c51 TH |
330 | * |
331 | * LOCKING: | |
332 | * caller. | |
333 | */ | |
c7a8209f | 334 | static void ata_dev_select(struct ata_port *ap, unsigned int device, |
624d5c51 TH |
335 | unsigned int wait, unsigned int can_sleep) |
336 | { | |
337 | if (ata_msg_probe(ap)) | |
a9a79dfe JP |
338 | ata_port_info(ap, "ata_dev_select: ENTER, device %u, wait %u\n", |
339 | device, wait); | |
624d5c51 TH |
340 | |
341 | if (wait) | |
342 | ata_wait_idle(ap); | |
343 | ||
5682ed33 | 344 | ap->ops->sff_dev_select(ap, device); |
624d5c51 TH |
345 | |
346 | if (wait) { | |
347 | if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI) | |
97750ceb | 348 | ata_msleep(ap, 150); |
624d5c51 TH |
349 | ata_wait_idle(ap); |
350 | } | |
351 | } | |
352 | ||
353 | /** | |
9363c382 | 354 | * ata_sff_irq_on - Enable interrupts on a port. |
624d5c51 TH |
355 | * @ap: Port on which interrupts are enabled. |
356 | * | |
357 | * Enable interrupts on a legacy IDE device using MMIO or PIO, | |
358 | * wait for idle, clear any pending interrupts. | |
359 | * | |
e42a542b SS |
360 | * Note: may NOT be used as the sff_irq_on() entry in |
361 | * ata_port_operations. | |
362 | * | |
624d5c51 TH |
363 | * LOCKING: |
364 | * Inherited from caller. | |
365 | */ | |
e42a542b | 366 | void ata_sff_irq_on(struct ata_port *ap) |
624d5c51 TH |
367 | { |
368 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
e42a542b SS |
369 | |
370 | if (ap->ops->sff_irq_on) { | |
371 | ap->ops->sff_irq_on(ap); | |
372 | return; | |
373 | } | |
624d5c51 TH |
374 | |
375 | ap->ctl &= ~ATA_NIEN; | |
376 | ap->last_ctl = ap->ctl; | |
377 | ||
e42a542b SS |
378 | if (ap->ops->sff_set_devctl || ioaddr->ctl_addr) |
379 | ata_sff_set_devctl(ap, ap->ctl); | |
380 | ata_wait_idle(ap); | |
624d5c51 | 381 | |
37f65b8b TH |
382 | if (ap->ops->sff_irq_clear) |
383 | ap->ops->sff_irq_clear(ap); | |
624d5c51 | 384 | } |
0fe40ff8 | 385 | EXPORT_SYMBOL_GPL(ata_sff_irq_on); |
624d5c51 | 386 | |
624d5c51 | 387 | /** |
9363c382 | 388 | * ata_sff_tf_load - send taskfile registers to host controller |
624d5c51 TH |
389 | * @ap: Port to which output is sent |
390 | * @tf: ATA taskfile register set | |
391 | * | |
392 | * Outputs ATA taskfile to standard ATA host controller. | |
393 | * | |
394 | * LOCKING: | |
395 | * Inherited from caller. | |
396 | */ | |
9363c382 | 397 | void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
624d5c51 TH |
398 | { |
399 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
400 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
401 | ||
402 | if (tf->ctl != ap->last_ctl) { | |
403 | if (ioaddr->ctl_addr) | |
404 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
405 | ap->last_ctl = tf->ctl; | |
40c60230 | 406 | ata_wait_idle(ap); |
624d5c51 TH |
407 | } |
408 | ||
409 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
efcb3cf7 | 410 | WARN_ON_ONCE(!ioaddr->ctl_addr); |
624d5c51 TH |
411 | iowrite8(tf->hob_feature, ioaddr->feature_addr); |
412 | iowrite8(tf->hob_nsect, ioaddr->nsect_addr); | |
413 | iowrite8(tf->hob_lbal, ioaddr->lbal_addr); | |
414 | iowrite8(tf->hob_lbam, ioaddr->lbam_addr); | |
415 | iowrite8(tf->hob_lbah, ioaddr->lbah_addr); | |
416 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", | |
417 | tf->hob_feature, | |
418 | tf->hob_nsect, | |
419 | tf->hob_lbal, | |
420 | tf->hob_lbam, | |
421 | tf->hob_lbah); | |
422 | } | |
423 | ||
424 | if (is_addr) { | |
425 | iowrite8(tf->feature, ioaddr->feature_addr); | |
426 | iowrite8(tf->nsect, ioaddr->nsect_addr); | |
427 | iowrite8(tf->lbal, ioaddr->lbal_addr); | |
428 | iowrite8(tf->lbam, ioaddr->lbam_addr); | |
429 | iowrite8(tf->lbah, ioaddr->lbah_addr); | |
430 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", | |
431 | tf->feature, | |
432 | tf->nsect, | |
433 | tf->lbal, | |
434 | tf->lbam, | |
435 | tf->lbah); | |
436 | } | |
437 | ||
438 | if (tf->flags & ATA_TFLAG_DEVICE) { | |
439 | iowrite8(tf->device, ioaddr->device_addr); | |
440 | VPRINTK("device 0x%X\n", tf->device); | |
441 | } | |
40c60230 TH |
442 | |
443 | ata_wait_idle(ap); | |
624d5c51 | 444 | } |
0fe40ff8 | 445 | EXPORT_SYMBOL_GPL(ata_sff_tf_load); |
624d5c51 TH |
446 | |
447 | /** | |
9363c382 | 448 | * ata_sff_tf_read - input device's ATA taskfile shadow registers |
624d5c51 TH |
449 | * @ap: Port from which input is read |
450 | * @tf: ATA taskfile register set for storing input | |
451 | * | |
452 | * Reads ATA taskfile registers for currently-selected device | |
453 | * into @tf. Assumes the device has a fully SFF compliant task file | |
454 | * layout and behaviour. If you device does not (eg has a different | |
455 | * status method) then you will need to provide a replacement tf_read | |
456 | * | |
457 | * LOCKING: | |
458 | * Inherited from caller. | |
459 | */ | |
9363c382 | 460 | void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
624d5c51 TH |
461 | { |
462 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
463 | ||
9363c382 | 464 | tf->command = ata_sff_check_status(ap); |
624d5c51 TH |
465 | tf->feature = ioread8(ioaddr->error_addr); |
466 | tf->nsect = ioread8(ioaddr->nsect_addr); | |
467 | tf->lbal = ioread8(ioaddr->lbal_addr); | |
468 | tf->lbam = ioread8(ioaddr->lbam_addr); | |
469 | tf->lbah = ioread8(ioaddr->lbah_addr); | |
470 | tf->device = ioread8(ioaddr->device_addr); | |
471 | ||
472 | if (tf->flags & ATA_TFLAG_LBA48) { | |
473 | if (likely(ioaddr->ctl_addr)) { | |
474 | iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); | |
475 | tf->hob_feature = ioread8(ioaddr->error_addr); | |
476 | tf->hob_nsect = ioread8(ioaddr->nsect_addr); | |
477 | tf->hob_lbal = ioread8(ioaddr->lbal_addr); | |
478 | tf->hob_lbam = ioread8(ioaddr->lbam_addr); | |
479 | tf->hob_lbah = ioread8(ioaddr->lbah_addr); | |
480 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
481 | ap->last_ctl = tf->ctl; | |
482 | } else | |
efcb3cf7 | 483 | WARN_ON_ONCE(1); |
624d5c51 TH |
484 | } |
485 | } | |
0fe40ff8 | 486 | EXPORT_SYMBOL_GPL(ata_sff_tf_read); |
624d5c51 TH |
487 | |
488 | /** | |
9363c382 | 489 | * ata_sff_exec_command - issue ATA command to host controller |
624d5c51 TH |
490 | * @ap: port to which command is being issued |
491 | * @tf: ATA taskfile register set | |
492 | * | |
493 | * Issues ATA command, with proper synchronization with interrupt | |
494 | * handler / other threads. | |
495 | * | |
496 | * LOCKING: | |
497 | * spin_lock_irqsave(host lock) | |
498 | */ | |
9363c382 | 499 | void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) |
624d5c51 TH |
500 | { |
501 | DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); | |
502 | ||
503 | iowrite8(tf->command, ap->ioaddr.command_addr); | |
9363c382 | 504 | ata_sff_pause(ap); |
624d5c51 | 505 | } |
0fe40ff8 | 506 | EXPORT_SYMBOL_GPL(ata_sff_exec_command); |
624d5c51 TH |
507 | |
508 | /** | |
509 | * ata_tf_to_host - issue ATA taskfile to host controller | |
510 | * @ap: port to which command is being issued | |
511 | * @tf: ATA taskfile register set | |
512 | * | |
513 | * Issues ATA taskfile register set to ATA host controller, | |
514 | * with proper synchronization with interrupt handler and | |
515 | * other threads. | |
516 | * | |
517 | * LOCKING: | |
518 | * spin_lock_irqsave(host lock) | |
519 | */ | |
520 | static inline void ata_tf_to_host(struct ata_port *ap, | |
521 | const struct ata_taskfile *tf) | |
522 | { | |
5682ed33 TH |
523 | ap->ops->sff_tf_load(ap, tf); |
524 | ap->ops->sff_exec_command(ap, tf); | |
624d5c51 TH |
525 | } |
526 | ||
527 | /** | |
9363c382 | 528 | * ata_sff_data_xfer - Transfer data by PIO |
989e0aac | 529 | * @qc: queued command |
624d5c51 TH |
530 | * @buf: data buffer |
531 | * @buflen: buffer length | |
532 | * @rw: read/write | |
533 | * | |
534 | * Transfer data from/to the device data register by PIO. | |
535 | * | |
536 | * LOCKING: | |
537 | * Inherited from caller. | |
538 | * | |
539 | * RETURNS: | |
540 | * Bytes consumed. | |
541 | */ | |
989e0aac | 542 | unsigned int ata_sff_data_xfer(struct ata_queued_cmd *qc, unsigned char *buf, |
9363c382 | 543 | unsigned int buflen, int rw) |
624d5c51 | 544 | { |
989e0aac | 545 | struct ata_port *ap = qc->dev->link->ap; |
624d5c51 TH |
546 | void __iomem *data_addr = ap->ioaddr.data_addr; |
547 | unsigned int words = buflen >> 1; | |
548 | ||
549 | /* Transfer multiple of 2 bytes */ | |
550 | if (rw == READ) | |
551 | ioread16_rep(data_addr, buf, words); | |
552 | else | |
553 | iowrite16_rep(data_addr, buf, words); | |
554 | ||
2102d749 | 555 | /* Transfer trailing byte, if any. */ |
624d5c51 | 556 | if (unlikely(buflen & 0x01)) { |
21dba244 | 557 | unsigned char pad[2] = { }; |
624d5c51 | 558 | |
2102d749 SS |
559 | /* Point buf to the tail of buffer */ |
560 | buf += buflen - 1; | |
561 | ||
562 | /* | |
563 | * Use io*16_rep() accessors here as well to avoid pointlessly | |
972b94ff | 564 | * swapping bytes to and from on the big endian machines... |
2102d749 | 565 | */ |
624d5c51 | 566 | if (rw == READ) { |
2102d749 SS |
567 | ioread16_rep(data_addr, pad, 1); |
568 | *buf = pad[0]; | |
624d5c51 | 569 | } else { |
2102d749 SS |
570 | pad[0] = *buf; |
571 | iowrite16_rep(data_addr, pad, 1); | |
624d5c51 TH |
572 | } |
573 | words++; | |
574 | } | |
575 | ||
576 | return words << 1; | |
577 | } | |
0fe40ff8 | 578 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer); |
624d5c51 | 579 | |
871af121 AC |
580 | /** |
581 | * ata_sff_data_xfer32 - Transfer data by PIO | |
989e0aac | 582 | * @qc: queued command |
871af121 AC |
583 | * @buf: data buffer |
584 | * @buflen: buffer length | |
585 | * @rw: read/write | |
586 | * | |
587 | * Transfer data from/to the device data register by PIO using 32bit | |
588 | * I/O operations. | |
589 | * | |
590 | * LOCKING: | |
591 | * Inherited from caller. | |
592 | * | |
593 | * RETURNS: | |
594 | * Bytes consumed. | |
595 | */ | |
596 | ||
989e0aac | 597 | unsigned int ata_sff_data_xfer32(struct ata_queued_cmd *qc, unsigned char *buf, |
871af121 AC |
598 | unsigned int buflen, int rw) |
599 | { | |
989e0aac | 600 | struct ata_device *dev = qc->dev; |
871af121 AC |
601 | struct ata_port *ap = dev->link->ap; |
602 | void __iomem *data_addr = ap->ioaddr.data_addr; | |
603 | unsigned int words = buflen >> 2; | |
604 | int slop = buflen & 3; | |
972b94ff | 605 | |
e3cf95dd | 606 | if (!(ap->pflags & ATA_PFLAG_PIO32)) |
989e0aac | 607 | return ata_sff_data_xfer(qc, buf, buflen, rw); |
871af121 AC |
608 | |
609 | /* Transfer multiple of 4 bytes */ | |
610 | if (rw == READ) | |
611 | ioread32_rep(data_addr, buf, words); | |
612 | else | |
613 | iowrite32_rep(data_addr, buf, words); | |
614 | ||
d1b3525b | 615 | /* Transfer trailing bytes, if any */ |
871af121 | 616 | if (unlikely(slop)) { |
21dba244 | 617 | unsigned char pad[4] = { }; |
d1b3525b SS |
618 | |
619 | /* Point buf to the tail of buffer */ | |
620 | buf += buflen - slop; | |
621 | ||
622 | /* | |
623 | * Use io*_rep() accessors here as well to avoid pointlessly | |
972b94ff | 624 | * swapping bytes to and from on the big endian machines... |
d1b3525b | 625 | */ |
871af121 | 626 | if (rw == READ) { |
d1b3525b SS |
627 | if (slop < 3) |
628 | ioread16_rep(data_addr, pad, 1); | |
629 | else | |
630 | ioread32_rep(data_addr, pad, 1); | |
631 | memcpy(buf, pad, slop); | |
871af121 | 632 | } else { |
d1b3525b SS |
633 | memcpy(pad, buf, slop); |
634 | if (slop < 3) | |
635 | iowrite16_rep(data_addr, pad, 1); | |
636 | else | |
637 | iowrite32_rep(data_addr, pad, 1); | |
871af121 | 638 | } |
871af121 | 639 | } |
d1b3525b | 640 | return (buflen + 1) & ~1; |
871af121 AC |
641 | } |
642 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer32); | |
643 | ||
624d5c51 TH |
644 | /** |
645 | * ata_pio_sector - Transfer a sector of data. | |
646 | * @qc: Command on going | |
647 | * | |
648 | * Transfer qc->sect_size bytes of data from/to the ATA device. | |
649 | * | |
650 | * LOCKING: | |
651 | * Inherited from caller. | |
652 | */ | |
653 | static void ata_pio_sector(struct ata_queued_cmd *qc) | |
654 | { | |
655 | int do_write = (qc->tf.flags & ATA_TFLAG_WRITE); | |
656 | struct ata_port *ap = qc->ap; | |
657 | struct page *page; | |
658 | unsigned int offset; | |
659 | unsigned char *buf; | |
660 | ||
661 | if (qc->curbytes == qc->nbytes - qc->sect_size) | |
662 | ap->hsm_task_state = HSM_ST_LAST; | |
663 | ||
664 | page = sg_page(qc->cursg); | |
665 | offset = qc->cursg->offset + qc->cursg_ofs; | |
666 | ||
667 | /* get the current page and offset */ | |
668 | page = nth_page(page, (offset >> PAGE_SHIFT)); | |
669 | offset %= PAGE_SIZE; | |
670 | ||
671 | DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); | |
672 | ||
5d7a288c TA |
673 | /* do the actual data transfer */ |
674 | buf = kmap_atomic(page); | |
675 | ap->ops->sff_data_xfer(qc, buf + offset, qc->sect_size, do_write); | |
676 | kunmap_atomic(buf); | |
624d5c51 | 677 | |
3842e835 | 678 | if (!do_write && !PageSlab(page)) |
2d68b7fe CM |
679 | flush_dcache_page(page); |
680 | ||
624d5c51 TH |
681 | qc->curbytes += qc->sect_size; |
682 | qc->cursg_ofs += qc->sect_size; | |
683 | ||
684 | if (qc->cursg_ofs == qc->cursg->length) { | |
685 | qc->cursg = sg_next(qc->cursg); | |
686 | qc->cursg_ofs = 0; | |
687 | } | |
688 | } | |
689 | ||
690 | /** | |
691 | * ata_pio_sectors - Transfer one or many sectors. | |
692 | * @qc: Command on going | |
693 | * | |
694 | * Transfer one or many sectors of data from/to the | |
695 | * ATA device for the DRQ request. | |
696 | * | |
697 | * LOCKING: | |
698 | * Inherited from caller. | |
699 | */ | |
700 | static void ata_pio_sectors(struct ata_queued_cmd *qc) | |
701 | { | |
702 | if (is_multi_taskfile(&qc->tf)) { | |
703 | /* READ/WRITE MULTIPLE */ | |
704 | unsigned int nsect; | |
705 | ||
efcb3cf7 | 706 | WARN_ON_ONCE(qc->dev->multi_count == 0); |
624d5c51 TH |
707 | |
708 | nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size, | |
709 | qc->dev->multi_count); | |
710 | while (nsect--) | |
711 | ata_pio_sector(qc); | |
712 | } else | |
713 | ata_pio_sector(qc); | |
714 | ||
a57c1bad | 715 | ata_sff_sync(qc->ap); /* flush */ |
624d5c51 TH |
716 | } |
717 | ||
718 | /** | |
719 | * atapi_send_cdb - Write CDB bytes to hardware | |
720 | * @ap: Port to which ATAPI device is attached. | |
721 | * @qc: Taskfile currently active | |
722 | * | |
723 | * When device has indicated its readiness to accept | |
724 | * a CDB, this function is called. Send the CDB. | |
725 | * | |
726 | * LOCKING: | |
727 | * caller. | |
728 | */ | |
729 | static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc) | |
730 | { | |
731 | /* send SCSI cdb */ | |
732 | DPRINTK("send cdb\n"); | |
efcb3cf7 | 733 | WARN_ON_ONCE(qc->dev->cdb_len < 12); |
624d5c51 | 734 | |
989e0aac | 735 | ap->ops->sff_data_xfer(qc, qc->cdb, qc->dev->cdb_len, 1); |
a57c1bad AC |
736 | ata_sff_sync(ap); |
737 | /* FIXME: If the CDB is for DMA do we need to do the transition delay | |
738 | or is bmdma_start guaranteed to do it ? */ | |
624d5c51 TH |
739 | switch (qc->tf.protocol) { |
740 | case ATAPI_PROT_PIO: | |
741 | ap->hsm_task_state = HSM_ST; | |
742 | break; | |
743 | case ATAPI_PROT_NODATA: | |
744 | ap->hsm_task_state = HSM_ST_LAST; | |
745 | break; | |
9a7780c9 | 746 | #ifdef CONFIG_ATA_BMDMA |
624d5c51 TH |
747 | case ATAPI_PROT_DMA: |
748 | ap->hsm_task_state = HSM_ST_LAST; | |
749 | /* initiate bmdma */ | |
750 | ap->ops->bmdma_start(qc); | |
751 | break; | |
9a7780c9 TH |
752 | #endif /* CONFIG_ATA_BMDMA */ |
753 | default: | |
754 | BUG(); | |
624d5c51 TH |
755 | } |
756 | } | |
757 | ||
758 | /** | |
759 | * __atapi_pio_bytes - Transfer data from/to the ATAPI device. | |
760 | * @qc: Command on going | |
761 | * @bytes: number of bytes | |
762 | * | |
763 | * Transfer Transfer data from/to the ATAPI device. | |
764 | * | |
765 | * LOCKING: | |
766 | * Inherited from caller. | |
767 | * | |
768 | */ | |
769 | static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes) | |
770 | { | |
771 | int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ; | |
772 | struct ata_port *ap = qc->ap; | |
773 | struct ata_device *dev = qc->dev; | |
774 | struct ata_eh_info *ehi = &dev->link->eh_info; | |
775 | struct scatterlist *sg; | |
776 | struct page *page; | |
777 | unsigned char *buf; | |
778 | unsigned int offset, count, consumed; | |
779 | ||
780 | next_sg: | |
781 | sg = qc->cursg; | |
782 | if (unlikely(!sg)) { | |
783 | ata_ehi_push_desc(ehi, "unexpected or too much trailing data " | |
784 | "buf=%u cur=%u bytes=%u", | |
785 | qc->nbytes, qc->curbytes, bytes); | |
786 | return -1; | |
787 | } | |
788 | ||
789 | page = sg_page(sg); | |
790 | offset = sg->offset + qc->cursg_ofs; | |
791 | ||
792 | /* get the current page and offset */ | |
793 | page = nth_page(page, (offset >> PAGE_SHIFT)); | |
794 | offset %= PAGE_SIZE; | |
795 | ||
796 | /* don't overrun current sg */ | |
797 | count = min(sg->length - qc->cursg_ofs, bytes); | |
798 | ||
799 | /* don't cross page boundaries */ | |
800 | count = min(count, (unsigned int)PAGE_SIZE - offset); | |
801 | ||
802 | DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); | |
803 | ||
5d7a288c TA |
804 | /* do the actual data transfer */ |
805 | buf = kmap_atomic(page); | |
806 | consumed = ap->ops->sff_data_xfer(qc, buf + offset, count, rw); | |
807 | kunmap_atomic(buf); | |
624d5c51 TH |
808 | |
809 | bytes -= min(bytes, consumed); | |
810 | qc->curbytes += count; | |
811 | qc->cursg_ofs += count; | |
812 | ||
813 | if (qc->cursg_ofs == sg->length) { | |
814 | qc->cursg = sg_next(qc->cursg); | |
815 | qc->cursg_ofs = 0; | |
816 | } | |
817 | ||
a0f79f7a CB |
818 | /* |
819 | * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed); | |
820 | * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN | |
821 | * check correctly as it doesn't know if it is the last request being | |
822 | * made. Somebody should implement a proper sanity check. | |
823 | */ | |
624d5c51 TH |
824 | if (bytes) |
825 | goto next_sg; | |
826 | return 0; | |
827 | } | |
828 | ||
829 | /** | |
830 | * atapi_pio_bytes - Transfer data from/to the ATAPI device. | |
831 | * @qc: Command on going | |
832 | * | |
833 | * Transfer Transfer data from/to the ATAPI device. | |
834 | * | |
835 | * LOCKING: | |
836 | * Inherited from caller. | |
837 | */ | |
838 | static void atapi_pio_bytes(struct ata_queued_cmd *qc) | |
839 | { | |
840 | struct ata_port *ap = qc->ap; | |
841 | struct ata_device *dev = qc->dev; | |
842 | struct ata_eh_info *ehi = &dev->link->eh_info; | |
843 | unsigned int ireason, bc_lo, bc_hi, bytes; | |
844 | int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0; | |
845 | ||
846 | /* Abuse qc->result_tf for temp storage of intermediate TF | |
847 | * here to save some kernel stack usage. | |
848 | * For normal completion, qc->result_tf is not relevant. For | |
849 | * error, qc->result_tf is later overwritten by ata_qc_complete(). | |
850 | * So, the correctness of qc->result_tf is not affected. | |
851 | */ | |
5682ed33 | 852 | ap->ops->sff_tf_read(ap, &qc->result_tf); |
624d5c51 TH |
853 | ireason = qc->result_tf.nsect; |
854 | bc_lo = qc->result_tf.lbam; | |
855 | bc_hi = qc->result_tf.lbah; | |
856 | bytes = (bc_hi << 8) | bc_lo; | |
857 | ||
858 | /* shall be cleared to zero, indicating xfer of data */ | |
002ae084 | 859 | if (unlikely(ireason & ATAPI_COD)) |
624d5c51 TH |
860 | goto atapi_check; |
861 | ||
862 | /* make sure transfer direction matches expected */ | |
002ae084 | 863 | i_write = ((ireason & ATAPI_IO) == 0) ? 1 : 0; |
624d5c51 TH |
864 | if (unlikely(do_write != i_write)) |
865 | goto atapi_check; | |
866 | ||
867 | if (unlikely(!bytes)) | |
868 | goto atapi_check; | |
869 | ||
870 | VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes); | |
871 | ||
872 | if (unlikely(__atapi_pio_bytes(qc, bytes))) | |
873 | goto err_out; | |
a57c1bad | 874 | ata_sff_sync(ap); /* flush */ |
624d5c51 TH |
875 | |
876 | return; | |
877 | ||
878 | atapi_check: | |
879 | ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)", | |
880 | ireason, bytes); | |
881 | err_out: | |
882 | qc->err_mask |= AC_ERR_HSM; | |
883 | ap->hsm_task_state = HSM_ST_ERR; | |
884 | } | |
885 | ||
886 | /** | |
887 | * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue. | |
888 | * @ap: the target ata_port | |
889 | * @qc: qc on going | |
890 | * | |
891 | * RETURNS: | |
892 | * 1 if ok in workqueue, 0 otherwise. | |
893 | */ | |
0fe40ff8 AC |
894 | static inline int ata_hsm_ok_in_wq(struct ata_port *ap, |
895 | struct ata_queued_cmd *qc) | |
624d5c51 TH |
896 | { |
897 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
898 | return 1; | |
899 | ||
900 | if (ap->hsm_task_state == HSM_ST_FIRST) { | |
901 | if (qc->tf.protocol == ATA_PROT_PIO && | |
0fe40ff8 | 902 | (qc->tf.flags & ATA_TFLAG_WRITE)) |
624d5c51 TH |
903 | return 1; |
904 | ||
905 | if (ata_is_atapi(qc->tf.protocol) && | |
0fe40ff8 | 906 | !(qc->dev->flags & ATA_DFLAG_CDB_INTR)) |
624d5c51 TH |
907 | return 1; |
908 | } | |
909 | ||
910 | return 0; | |
911 | } | |
912 | ||
913 | /** | |
914 | * ata_hsm_qc_complete - finish a qc running on standard HSM | |
915 | * @qc: Command to complete | |
916 | * @in_wq: 1 if called from workqueue, 0 otherwise | |
917 | * | |
918 | * Finish @qc which is running on standard HSM. | |
919 | * | |
920 | * LOCKING: | |
921 | * If @in_wq is zero, spin_lock_irqsave(host lock). | |
922 | * Otherwise, none on entry and grabs host lock. | |
923 | */ | |
924 | static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq) | |
925 | { | |
926 | struct ata_port *ap = qc->ap; | |
624d5c51 TH |
927 | |
928 | if (ap->ops->error_handler) { | |
929 | if (in_wq) { | |
624d5c51 TH |
930 | /* EH might have kicked in while host lock is |
931 | * released. | |
932 | */ | |
933 | qc = ata_qc_from_tag(ap, qc->tag); | |
934 | if (qc) { | |
935 | if (likely(!(qc->err_mask & AC_ERR_HSM))) { | |
e42a542b | 936 | ata_sff_irq_on(ap); |
624d5c51 TH |
937 | ata_qc_complete(qc); |
938 | } else | |
939 | ata_port_freeze(ap); | |
940 | } | |
624d5c51 TH |
941 | } else { |
942 | if (likely(!(qc->err_mask & AC_ERR_HSM))) | |
943 | ata_qc_complete(qc); | |
944 | else | |
945 | ata_port_freeze(ap); | |
946 | } | |
947 | } else { | |
948 | if (in_wq) { | |
e42a542b | 949 | ata_sff_irq_on(ap); |
624d5c51 | 950 | ata_qc_complete(qc); |
624d5c51 TH |
951 | } else |
952 | ata_qc_complete(qc); | |
953 | } | |
954 | } | |
955 | ||
956 | /** | |
9363c382 | 957 | * ata_sff_hsm_move - move the HSM to the next state. |
624d5c51 TH |
958 | * @ap: the target ata_port |
959 | * @qc: qc on going | |
960 | * @status: current device status | |
961 | * @in_wq: 1 if called from workqueue, 0 otherwise | |
962 | * | |
963 | * RETURNS: | |
964 | * 1 when poll next status needed, 0 otherwise. | |
965 | */ | |
9363c382 TH |
966 | int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc, |
967 | u8 status, int in_wq) | |
624d5c51 | 968 | { |
ea3c6450 GG |
969 | struct ata_link *link = qc->dev->link; |
970 | struct ata_eh_info *ehi = &link->eh_info; | |
624d5c51 TH |
971 | int poll_next; |
972 | ||
8eee1d3e TH |
973 | lockdep_assert_held(ap->lock); |
974 | ||
efcb3cf7 | 975 | WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0); |
624d5c51 | 976 | |
9363c382 | 977 | /* Make sure ata_sff_qc_issue() does not throw things |
624d5c51 TH |
978 | * like DMA polling into the workqueue. Notice that |
979 | * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING). | |
980 | */ | |
efcb3cf7 | 981 | WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc)); |
624d5c51 TH |
982 | |
983 | fsm_start: | |
984 | DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n", | |
985 | ap->print_id, qc->tf.protocol, ap->hsm_task_state, status); | |
986 | ||
987 | switch (ap->hsm_task_state) { | |
988 | case HSM_ST_FIRST: | |
989 | /* Send first data block or PACKET CDB */ | |
990 | ||
991 | /* If polling, we will stay in the work queue after | |
992 | * sending the data. Otherwise, interrupt handler | |
993 | * takes over after sending the data. | |
994 | */ | |
995 | poll_next = (qc->tf.flags & ATA_TFLAG_POLLING); | |
996 | ||
997 | /* check device status */ | |
998 | if (unlikely((status & ATA_DRQ) == 0)) { | |
999 | /* handle BSY=0, DRQ=0 as error */ | |
1000 | if (likely(status & (ATA_ERR | ATA_DF))) | |
1001 | /* device stops HSM for abort/error */ | |
1002 | qc->err_mask |= AC_ERR_DEV; | |
a836d3e8 | 1003 | else { |
624d5c51 | 1004 | /* HSM violation. Let EH handle this */ |
a836d3e8 TH |
1005 | ata_ehi_push_desc(ehi, |
1006 | "ST_FIRST: !(DRQ|ERR|DF)"); | |
624d5c51 | 1007 | qc->err_mask |= AC_ERR_HSM; |
a836d3e8 | 1008 | } |
624d5c51 TH |
1009 | |
1010 | ap->hsm_task_state = HSM_ST_ERR; | |
1011 | goto fsm_start; | |
1012 | } | |
1013 | ||
1014 | /* Device should not ask for data transfer (DRQ=1) | |
1015 | * when it finds something wrong. | |
1016 | * We ignore DRQ here and stop the HSM by | |
1017 | * changing hsm_task_state to HSM_ST_ERR and | |
1018 | * let the EH abort the command or reset the device. | |
1019 | */ | |
1020 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
1021 | /* Some ATAPI tape drives forget to clear the ERR bit | |
1022 | * when doing the next command (mostly request sense). | |
1023 | * We ignore ERR here to workaround and proceed sending | |
1024 | * the CDB. | |
1025 | */ | |
1026 | if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) { | |
a836d3e8 TH |
1027 | ata_ehi_push_desc(ehi, "ST_FIRST: " |
1028 | "DRQ=1 with device error, " | |
1029 | "dev_stat 0x%X", status); | |
624d5c51 TH |
1030 | qc->err_mask |= AC_ERR_HSM; |
1031 | ap->hsm_task_state = HSM_ST_ERR; | |
1032 | goto fsm_start; | |
1033 | } | |
1034 | } | |
1035 | ||
624d5c51 TH |
1036 | if (qc->tf.protocol == ATA_PROT_PIO) { |
1037 | /* PIO data out protocol. | |
1038 | * send first data block. | |
1039 | */ | |
1040 | ||
1041 | /* ata_pio_sectors() might change the state | |
1042 | * to HSM_ST_LAST. so, the state is changed here | |
1043 | * before ata_pio_sectors(). | |
1044 | */ | |
1045 | ap->hsm_task_state = HSM_ST; | |
1046 | ata_pio_sectors(qc); | |
1047 | } else | |
1048 | /* send CDB */ | |
1049 | atapi_send_cdb(ap, qc); | |
1050 | ||
c429137a | 1051 | /* if polling, ata_sff_pio_task() handles the rest. |
624d5c51 TH |
1052 | * otherwise, interrupt handler takes over from here. |
1053 | */ | |
1054 | break; | |
1055 | ||
1056 | case HSM_ST: | |
1057 | /* complete command or read/write the data register */ | |
1058 | if (qc->tf.protocol == ATAPI_PROT_PIO) { | |
1059 | /* ATAPI PIO protocol */ | |
1060 | if ((status & ATA_DRQ) == 0) { | |
1061 | /* No more data to transfer or device error. | |
1062 | * Device error will be tagged in HSM_ST_LAST. | |
1063 | */ | |
1064 | ap->hsm_task_state = HSM_ST_LAST; | |
1065 | goto fsm_start; | |
1066 | } | |
1067 | ||
1068 | /* Device should not ask for data transfer (DRQ=1) | |
1069 | * when it finds something wrong. | |
1070 | * We ignore DRQ here and stop the HSM by | |
1071 | * changing hsm_task_state to HSM_ST_ERR and | |
1072 | * let the EH abort the command or reset the device. | |
1073 | */ | |
1074 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
a836d3e8 TH |
1075 | ata_ehi_push_desc(ehi, "ST-ATAPI: " |
1076 | "DRQ=1 with device error, " | |
1077 | "dev_stat 0x%X", status); | |
624d5c51 TH |
1078 | qc->err_mask |= AC_ERR_HSM; |
1079 | ap->hsm_task_state = HSM_ST_ERR; | |
1080 | goto fsm_start; | |
1081 | } | |
1082 | ||
1083 | atapi_pio_bytes(qc); | |
1084 | ||
1085 | if (unlikely(ap->hsm_task_state == HSM_ST_ERR)) | |
1086 | /* bad ireason reported by device */ | |
1087 | goto fsm_start; | |
1088 | ||
1089 | } else { | |
1090 | /* ATA PIO protocol */ | |
1091 | if (unlikely((status & ATA_DRQ) == 0)) { | |
1092 | /* handle BSY=0, DRQ=0 as error */ | |
6a6b97d3 | 1093 | if (likely(status & (ATA_ERR | ATA_DF))) { |
624d5c51 TH |
1094 | /* device stops HSM for abort/error */ |
1095 | qc->err_mask |= AC_ERR_DEV; | |
6a6b97d3 TH |
1096 | |
1097 | /* If diagnostic failed and this is | |
1098 | * IDENTIFY, it's likely a phantom | |
1099 | * device. Mark hint. | |
1100 | */ | |
1101 | if (qc->dev->horkage & | |
1102 | ATA_HORKAGE_DIAGNOSTIC) | |
1103 | qc->err_mask |= | |
1104 | AC_ERR_NODEV_HINT; | |
1105 | } else { | |
624d5c51 TH |
1106 | /* HSM violation. Let EH handle this. |
1107 | * Phantom devices also trigger this | |
1108 | * condition. Mark hint. | |
1109 | */ | |
a836d3e8 | 1110 | ata_ehi_push_desc(ehi, "ST-ATA: " |
80ee6f54 | 1111 | "DRQ=0 without device error, " |
a836d3e8 | 1112 | "dev_stat 0x%X", status); |
624d5c51 TH |
1113 | qc->err_mask |= AC_ERR_HSM | |
1114 | AC_ERR_NODEV_HINT; | |
a836d3e8 | 1115 | } |
624d5c51 TH |
1116 | |
1117 | ap->hsm_task_state = HSM_ST_ERR; | |
1118 | goto fsm_start; | |
1119 | } | |
1120 | ||
1121 | /* For PIO reads, some devices may ask for | |
1122 | * data transfer (DRQ=1) alone with ERR=1. | |
1123 | * We respect DRQ here and transfer one | |
1124 | * block of junk data before changing the | |
1125 | * hsm_task_state to HSM_ST_ERR. | |
1126 | * | |
1127 | * For PIO writes, ERR=1 DRQ=1 doesn't make | |
1128 | * sense since the data block has been | |
1129 | * transferred to the device. | |
1130 | */ | |
1131 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
1132 | /* data might be corrputed */ | |
1133 | qc->err_mask |= AC_ERR_DEV; | |
1134 | ||
1135 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) { | |
1136 | ata_pio_sectors(qc); | |
1137 | status = ata_wait_idle(ap); | |
1138 | } | |
1139 | ||
a836d3e8 TH |
1140 | if (status & (ATA_BUSY | ATA_DRQ)) { |
1141 | ata_ehi_push_desc(ehi, "ST-ATA: " | |
1142 | "BUSY|DRQ persists on ERR|DF, " | |
1143 | "dev_stat 0x%X", status); | |
624d5c51 | 1144 | qc->err_mask |= AC_ERR_HSM; |
a836d3e8 | 1145 | } |
624d5c51 | 1146 | |
b919930c TH |
1147 | /* There are oddball controllers with |
1148 | * status register stuck at 0x7f and | |
1149 | * lbal/m/h at zero which makes it | |
1150 | * pass all other presence detection | |
1151 | * mechanisms we have. Set NODEV_HINT | |
1152 | * for it. Kernel bz#7241. | |
1153 | */ | |
1154 | if (status == 0x7f) | |
1155 | qc->err_mask |= AC_ERR_NODEV_HINT; | |
1156 | ||
624d5c51 TH |
1157 | /* ata_pio_sectors() might change the |
1158 | * state to HSM_ST_LAST. so, the state | |
1159 | * is changed after ata_pio_sectors(). | |
1160 | */ | |
1161 | ap->hsm_task_state = HSM_ST_ERR; | |
1162 | goto fsm_start; | |
1163 | } | |
1164 | ||
1165 | ata_pio_sectors(qc); | |
1166 | ||
1167 | if (ap->hsm_task_state == HSM_ST_LAST && | |
1168 | (!(qc->tf.flags & ATA_TFLAG_WRITE))) { | |
1169 | /* all data read */ | |
1170 | status = ata_wait_idle(ap); | |
1171 | goto fsm_start; | |
1172 | } | |
1173 | } | |
1174 | ||
1175 | poll_next = 1; | |
1176 | break; | |
1177 | ||
1178 | case HSM_ST_LAST: | |
1179 | if (unlikely(!ata_ok(status))) { | |
1180 | qc->err_mask |= __ac_err_mask(status); | |
1181 | ap->hsm_task_state = HSM_ST_ERR; | |
1182 | goto fsm_start; | |
1183 | } | |
1184 | ||
1185 | /* no more data to transfer */ | |
1186 | DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n", | |
1187 | ap->print_id, qc->dev->devno, status); | |
1188 | ||
efcb3cf7 | 1189 | WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM)); |
624d5c51 TH |
1190 | |
1191 | ap->hsm_task_state = HSM_ST_IDLE; | |
1192 | ||
1193 | /* complete taskfile transaction */ | |
1194 | ata_hsm_qc_complete(qc, in_wq); | |
1195 | ||
1196 | poll_next = 0; | |
1197 | break; | |
1198 | ||
1199 | case HSM_ST_ERR: | |
624d5c51 TH |
1200 | ap->hsm_task_state = HSM_ST_IDLE; |
1201 | ||
1202 | /* complete taskfile transaction */ | |
1203 | ata_hsm_qc_complete(qc, in_wq); | |
1204 | ||
1205 | poll_next = 0; | |
1206 | break; | |
1207 | default: | |
1208 | poll_next = 0; | |
a588afc9 TH |
1209 | WARN(true, "ata%d: SFF host state machine in invalid state %d", |
1210 | ap->print_id, ap->hsm_task_state); | |
624d5c51 TH |
1211 | } |
1212 | ||
1213 | return poll_next; | |
1214 | } | |
0fe40ff8 | 1215 | EXPORT_SYMBOL_GPL(ata_sff_hsm_move); |
624d5c51 | 1216 | |
64b97594 VK |
1217 | void ata_sff_queue_work(struct work_struct *work) |
1218 | { | |
1219 | queue_work(ata_sff_wq, work); | |
1220 | } | |
1221 | EXPORT_SYMBOL_GPL(ata_sff_queue_work); | |
1222 | ||
1223 | void ata_sff_queue_delayed_work(struct delayed_work *dwork, unsigned long delay) | |
1224 | { | |
1225 | queue_delayed_work(ata_sff_wq, dwork, delay); | |
1226 | } | |
1227 | EXPORT_SYMBOL_GPL(ata_sff_queue_delayed_work); | |
1228 | ||
ea3c6450 | 1229 | void ata_sff_queue_pio_task(struct ata_link *link, unsigned long delay) |
c429137a | 1230 | { |
ea3c6450 GG |
1231 | struct ata_port *ap = link->ap; |
1232 | ||
1233 | WARN_ON((ap->sff_pio_task_link != NULL) && | |
1234 | (ap->sff_pio_task_link != link)); | |
1235 | ap->sff_pio_task_link = link; | |
1236 | ||
c429137a | 1237 | /* may fail if ata_sff_flush_pio_task() in progress */ |
64b97594 | 1238 | ata_sff_queue_delayed_work(&ap->sff_pio_task, msecs_to_jiffies(delay)); |
c429137a TH |
1239 | } |
1240 | EXPORT_SYMBOL_GPL(ata_sff_queue_pio_task); | |
1241 | ||
1242 | void ata_sff_flush_pio_task(struct ata_port *ap) | |
1243 | { | |
1244 | DPRINTK("ENTER\n"); | |
1245 | ||
afe2c511 | 1246 | cancel_delayed_work_sync(&ap->sff_pio_task); |
ce751452 DJ |
1247 | |
1248 | /* | |
1249 | * We wanna reset the HSM state to IDLE. If we do so without | |
1250 | * grabbing the port lock, critical sections protected by it which | |
1251 | * expect the HSM state to stay stable may get surprised. For | |
1252 | * example, we may set IDLE in between the time | |
1253 | * __ata_sff_port_intr() checks for HSM_ST_IDLE and before it calls | |
1254 | * ata_sff_hsm_move() causing ata_sff_hsm_move() to BUG(). | |
1255 | */ | |
1256 | spin_lock_irq(ap->lock); | |
c429137a | 1257 | ap->hsm_task_state = HSM_ST_IDLE; |
ce751452 DJ |
1258 | spin_unlock_irq(ap->lock); |
1259 | ||
d4d8eaff | 1260 | ap->sff_pio_task_link = NULL; |
c429137a TH |
1261 | |
1262 | if (ata_msg_ctl(ap)) | |
a9a79dfe | 1263 | ata_port_dbg(ap, "%s: EXIT\n", __func__); |
c429137a TH |
1264 | } |
1265 | ||
1266 | static void ata_sff_pio_task(struct work_struct *work) | |
624d5c51 TH |
1267 | { |
1268 | struct ata_port *ap = | |
c429137a | 1269 | container_of(work, struct ata_port, sff_pio_task.work); |
ea3c6450 | 1270 | struct ata_link *link = ap->sff_pio_task_link; |
c429137a | 1271 | struct ata_queued_cmd *qc; |
624d5c51 TH |
1272 | u8 status; |
1273 | int poll_next; | |
1274 | ||
8eee1d3e TH |
1275 | spin_lock_irq(ap->lock); |
1276 | ||
4fca377f | 1277 | BUG_ON(ap->sff_pio_task_link == NULL); |
c429137a | 1278 | /* qc can be NULL if timeout occurred */ |
ea3c6450 GG |
1279 | qc = ata_qc_from_tag(ap, link->active_tag); |
1280 | if (!qc) { | |
1281 | ap->sff_pio_task_link = NULL; | |
8eee1d3e | 1282 | goto out_unlock; |
ea3c6450 | 1283 | } |
c429137a | 1284 | |
624d5c51 | 1285 | fsm_start: |
efcb3cf7 | 1286 | WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE); |
624d5c51 TH |
1287 | |
1288 | /* | |
1289 | * This is purely heuristic. This is a fast path. | |
1290 | * Sometimes when we enter, BSY will be cleared in | |
1291 | * a chk-status or two. If not, the drive is probably seeking | |
1292 | * or something. Snooze for a couple msecs, then | |
1293 | * chk-status again. If still busy, queue delayed work. | |
1294 | */ | |
9363c382 | 1295 | status = ata_sff_busy_wait(ap, ATA_BUSY, 5); |
624d5c51 | 1296 | if (status & ATA_BUSY) { |
8eee1d3e | 1297 | spin_unlock_irq(ap->lock); |
97750ceb | 1298 | ata_msleep(ap, 2); |
8eee1d3e TH |
1299 | spin_lock_irq(ap->lock); |
1300 | ||
9363c382 | 1301 | status = ata_sff_busy_wait(ap, ATA_BUSY, 10); |
624d5c51 | 1302 | if (status & ATA_BUSY) { |
ea3c6450 | 1303 | ata_sff_queue_pio_task(link, ATA_SHORT_PAUSE); |
8eee1d3e | 1304 | goto out_unlock; |
624d5c51 TH |
1305 | } |
1306 | } | |
1307 | ||
ea3c6450 GG |
1308 | /* |
1309 | * hsm_move() may trigger another command to be processed. | |
1310 | * clean the link beforehand. | |
1311 | */ | |
1312 | ap->sff_pio_task_link = NULL; | |
624d5c51 | 1313 | /* move the HSM */ |
9363c382 | 1314 | poll_next = ata_sff_hsm_move(ap, qc, status, 1); |
624d5c51 TH |
1315 | |
1316 | /* another command or interrupt handler | |
1317 | * may be running at this point. | |
1318 | */ | |
1319 | if (poll_next) | |
1320 | goto fsm_start; | |
8eee1d3e TH |
1321 | out_unlock: |
1322 | spin_unlock_irq(ap->lock); | |
624d5c51 TH |
1323 | } |
1324 | ||
1325 | /** | |
360ff783 | 1326 | * ata_sff_qc_issue - issue taskfile to a SFF controller |
624d5c51 TH |
1327 | * @qc: command to issue to device |
1328 | * | |
360ff783 TH |
1329 | * This function issues a PIO or NODATA command to a SFF |
1330 | * controller. | |
624d5c51 TH |
1331 | * |
1332 | * LOCKING: | |
1333 | * spin_lock_irqsave(host lock) | |
1334 | * | |
1335 | * RETURNS: | |
1336 | * Zero on success, AC_ERR_* mask on failure | |
1337 | */ | |
9363c382 | 1338 | unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc) |
624d5c51 TH |
1339 | { |
1340 | struct ata_port *ap = qc->ap; | |
ea3c6450 | 1341 | struct ata_link *link = qc->dev->link; |
624d5c51 TH |
1342 | |
1343 | /* Use polling pio if the LLD doesn't handle | |
1344 | * interrupt driven pio and atapi CDB interrupt. | |
1345 | */ | |
360ff783 TH |
1346 | if (ap->flags & ATA_FLAG_PIO_POLLING) |
1347 | qc->tf.flags |= ATA_TFLAG_POLLING; | |
624d5c51 TH |
1348 | |
1349 | /* select the device */ | |
1350 | ata_dev_select(ap, qc->dev->devno, 1, 0); | |
1351 | ||
1352 | /* start the command */ | |
1353 | switch (qc->tf.protocol) { | |
1354 | case ATA_PROT_NODATA: | |
1355 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1356 | ata_qc_set_polling(qc); | |
1357 | ||
1358 | ata_tf_to_host(ap, &qc->tf); | |
1359 | ap->hsm_task_state = HSM_ST_LAST; | |
1360 | ||
1361 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
ea3c6450 | 1362 | ata_sff_queue_pio_task(link, 0); |
624d5c51 TH |
1363 | |
1364 | break; | |
1365 | ||
624d5c51 TH |
1366 | case ATA_PROT_PIO: |
1367 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1368 | ata_qc_set_polling(qc); | |
1369 | ||
1370 | ata_tf_to_host(ap, &qc->tf); | |
1371 | ||
1372 | if (qc->tf.flags & ATA_TFLAG_WRITE) { | |
1373 | /* PIO data out protocol */ | |
1374 | ap->hsm_task_state = HSM_ST_FIRST; | |
ea3c6450 | 1375 | ata_sff_queue_pio_task(link, 0); |
624d5c51 | 1376 | |
c429137a TH |
1377 | /* always send first data block using the |
1378 | * ata_sff_pio_task() codepath. | |
624d5c51 TH |
1379 | */ |
1380 | } else { | |
1381 | /* PIO data in protocol */ | |
1382 | ap->hsm_task_state = HSM_ST; | |
1383 | ||
1384 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
ea3c6450 | 1385 | ata_sff_queue_pio_task(link, 0); |
624d5c51 | 1386 | |
c429137a TH |
1387 | /* if polling, ata_sff_pio_task() handles the |
1388 | * rest. otherwise, interrupt handler takes | |
1389 | * over from here. | |
624d5c51 TH |
1390 | */ |
1391 | } | |
1392 | ||
1393 | break; | |
1394 | ||
1395 | case ATAPI_PROT_PIO: | |
1396 | case ATAPI_PROT_NODATA: | |
1397 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1398 | ata_qc_set_polling(qc); | |
1399 | ||
1400 | ata_tf_to_host(ap, &qc->tf); | |
1401 | ||
1402 | ap->hsm_task_state = HSM_ST_FIRST; | |
1403 | ||
1404 | /* send cdb by polling if no cdb interrupt */ | |
1405 | if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) || | |
1406 | (qc->tf.flags & ATA_TFLAG_POLLING)) | |
ea3c6450 | 1407 | ata_sff_queue_pio_task(link, 0); |
624d5c51 TH |
1408 | break; |
1409 | ||
624d5c51 | 1410 | default: |
624d5c51 TH |
1411 | return AC_ERR_SYSTEM; |
1412 | } | |
1413 | ||
1414 | return 0; | |
1415 | } | |
0fe40ff8 | 1416 | EXPORT_SYMBOL_GPL(ata_sff_qc_issue); |
624d5c51 | 1417 | |
22183bf5 TH |
1418 | /** |
1419 | * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read | |
1420 | * @qc: qc to fill result TF for | |
1421 | * | |
1422 | * @qc is finished and result TF needs to be filled. Fill it | |
1423 | * using ->sff_tf_read. | |
1424 | * | |
1425 | * LOCKING: | |
1426 | * spin_lock_irqsave(host lock) | |
1427 | * | |
1428 | * RETURNS: | |
1429 | * true indicating that result TF is successfully filled. | |
1430 | */ | |
1431 | bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc) | |
1432 | { | |
1433 | qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf); | |
1434 | return true; | |
1435 | } | |
0fe40ff8 | 1436 | EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf); |
22183bf5 | 1437 | |
c3b28894 | 1438 | static unsigned int ata_sff_idle_irq(struct ata_port *ap) |
624d5c51 | 1439 | { |
c3b28894 TH |
1440 | ap->stats.idle_irq++; |
1441 | ||
1442 | #ifdef ATA_IRQ_TRAP | |
1443 | if ((ap->stats.idle_irq % 1000) == 0) { | |
1444 | ap->ops->sff_check_status(ap); | |
1445 | if (ap->ops->sff_irq_clear) | |
1446 | ap->ops->sff_irq_clear(ap); | |
a9a79dfe | 1447 | ata_port_warn(ap, "irq trap\n"); |
c3b28894 TH |
1448 | return 1; |
1449 | } | |
1450 | #endif | |
1451 | return 0; /* irq not handled */ | |
1452 | } | |
1453 | ||
1454 | static unsigned int __ata_sff_port_intr(struct ata_port *ap, | |
1455 | struct ata_queued_cmd *qc, | |
1456 | bool hsmv_on_idle) | |
1457 | { | |
1458 | u8 status; | |
624d5c51 TH |
1459 | |
1460 | VPRINTK("ata%u: protocol %d task_state %d\n", | |
1461 | ap->print_id, qc->tf.protocol, ap->hsm_task_state); | |
1462 | ||
1463 | /* Check whether we are expecting interrupt in this state */ | |
1464 | switch (ap->hsm_task_state) { | |
1465 | case HSM_ST_FIRST: | |
1466 | /* Some pre-ATAPI-4 devices assert INTRQ | |
1467 | * at this state when ready to receive CDB. | |
1468 | */ | |
1469 | ||
1470 | /* Check the ATA_DFLAG_CDB_INTR flag is enough here. | |
1471 | * The flag was turned on only for atapi devices. No | |
1472 | * need to check ata_is_atapi(qc->tf.protocol) again. | |
1473 | */ | |
1474 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
c3b28894 | 1475 | return ata_sff_idle_irq(ap); |
624d5c51 | 1476 | break; |
687a9933 | 1477 | case HSM_ST_IDLE: |
c3b28894 | 1478 | return ata_sff_idle_irq(ap); |
687a9933 TH |
1479 | default: |
1480 | break; | |
624d5c51 TH |
1481 | } |
1482 | ||
a57c1bad AC |
1483 | /* check main status, clearing INTRQ if needed */ |
1484 | status = ata_sff_irq_status(ap); | |
332ac7ff | 1485 | if (status & ATA_BUSY) { |
c3b28894 | 1486 | if (hsmv_on_idle) { |
332ac7ff TH |
1487 | /* BMDMA engine is already stopped, we're screwed */ |
1488 | qc->err_mask |= AC_ERR_HSM; | |
1489 | ap->hsm_task_state = HSM_ST_ERR; | |
1490 | } else | |
c3b28894 | 1491 | return ata_sff_idle_irq(ap); |
332ac7ff | 1492 | } |
624d5c51 | 1493 | |
9f2f7210 | 1494 | /* clear irq events */ |
37f65b8b TH |
1495 | if (ap->ops->sff_irq_clear) |
1496 | ap->ops->sff_irq_clear(ap); | |
624d5c51 | 1497 | |
9363c382 | 1498 | ata_sff_hsm_move(ap, qc, status, 0); |
624d5c51 | 1499 | |
624d5c51 | 1500 | return 1; /* irq handled */ |
624d5c51 TH |
1501 | } |
1502 | ||
1503 | /** | |
c3b28894 TH |
1504 | * ata_sff_port_intr - Handle SFF port interrupt |
1505 | * @ap: Port on which interrupt arrived (possibly...) | |
1506 | * @qc: Taskfile currently active in engine | |
624d5c51 | 1507 | * |
c3b28894 | 1508 | * Handle port interrupt for given queued command. |
624d5c51 TH |
1509 | * |
1510 | * LOCKING: | |
c3b28894 | 1511 | * spin_lock_irqsave(host lock) |
624d5c51 TH |
1512 | * |
1513 | * RETURNS: | |
c3b28894 | 1514 | * One if interrupt was handled, zero if not (shared irq). |
624d5c51 | 1515 | */ |
c3b28894 TH |
1516 | unsigned int ata_sff_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc) |
1517 | { | |
1518 | return __ata_sff_port_intr(ap, qc, false); | |
1519 | } | |
1520 | EXPORT_SYMBOL_GPL(ata_sff_port_intr); | |
1521 | ||
1522 | static inline irqreturn_t __ata_sff_interrupt(int irq, void *dev_instance, | |
1523 | unsigned int (*port_intr)(struct ata_port *, struct ata_queued_cmd *)) | |
624d5c51 TH |
1524 | { |
1525 | struct ata_host *host = dev_instance; | |
332ac7ff | 1526 | bool retried = false; |
624d5c51 | 1527 | unsigned int i; |
332ac7ff | 1528 | unsigned int handled, idle, polling; |
624d5c51 TH |
1529 | unsigned long flags; |
1530 | ||
1531 | /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */ | |
1532 | spin_lock_irqsave(&host->lock, flags); | |
1533 | ||
332ac7ff TH |
1534 | retry: |
1535 | handled = idle = polling = 0; | |
624d5c51 | 1536 | for (i = 0; i < host->n_ports; i++) { |
d88ec2e5 TH |
1537 | struct ata_port *ap = host->ports[i]; |
1538 | struct ata_queued_cmd *qc; | |
624d5c51 | 1539 | |
d88ec2e5 | 1540 | qc = ata_qc_from_tag(ap, ap->link.active_tag); |
27943620 TH |
1541 | if (qc) { |
1542 | if (!(qc->tf.flags & ATA_TFLAG_POLLING)) | |
c3b28894 | 1543 | handled |= port_intr(ap, qc); |
27943620 TH |
1544 | else |
1545 | polling |= 1 << i; | |
332ac7ff TH |
1546 | } else |
1547 | idle |= 1 << i; | |
27943620 TH |
1548 | } |
1549 | ||
1550 | /* | |
1551 | * If no port was expecting IRQ but the controller is actually | |
1552 | * asserting IRQ line, nobody cared will ensue. Check IRQ | |
1553 | * pending status if available and clear spurious IRQ. | |
1554 | */ | |
332ac7ff TH |
1555 | if (!handled && !retried) { |
1556 | bool retry = false; | |
1557 | ||
27943620 TH |
1558 | for (i = 0; i < host->n_ports; i++) { |
1559 | struct ata_port *ap = host->ports[i]; | |
1560 | ||
1561 | if (polling & (1 << i)) | |
1562 | continue; | |
1563 | ||
1564 | if (!ap->ops->sff_irq_check || | |
1565 | !ap->ops->sff_irq_check(ap)) | |
1566 | continue; | |
1567 | ||
332ac7ff TH |
1568 | if (idle & (1 << i)) { |
1569 | ap->ops->sff_check_status(ap); | |
37f65b8b TH |
1570 | if (ap->ops->sff_irq_clear) |
1571 | ap->ops->sff_irq_clear(ap); | |
332ac7ff TH |
1572 | } else { |
1573 | /* clear INTRQ and check if BUSY cleared */ | |
1574 | if (!(ap->ops->sff_check_status(ap) & ATA_BUSY)) | |
1575 | retry |= true; | |
1576 | /* | |
1577 | * With command in flight, we can't do | |
1578 | * sff_irq_clear() w/o racing with completion. | |
1579 | */ | |
1580 | } | |
1581 | } | |
1582 | ||
1583 | if (retry) { | |
1584 | retried = true; | |
1585 | goto retry; | |
27943620 | 1586 | } |
624d5c51 TH |
1587 | } |
1588 | ||
1589 | spin_unlock_irqrestore(&host->lock, flags); | |
1590 | ||
1591 | return IRQ_RETVAL(handled); | |
1592 | } | |
c3b28894 TH |
1593 | |
1594 | /** | |
1595 | * ata_sff_interrupt - Default SFF ATA host interrupt handler | |
1596 | * @irq: irq line (unused) | |
1597 | * @dev_instance: pointer to our ata_host information structure | |
1598 | * | |
1599 | * Default interrupt handler for PCI IDE devices. Calls | |
1600 | * ata_sff_port_intr() for each port that is not disabled. | |
1601 | * | |
1602 | * LOCKING: | |
1603 | * Obtains host lock during operation. | |
1604 | * | |
1605 | * RETURNS: | |
1606 | * IRQ_NONE or IRQ_HANDLED. | |
1607 | */ | |
1608 | irqreturn_t ata_sff_interrupt(int irq, void *dev_instance) | |
1609 | { | |
1610 | return __ata_sff_interrupt(irq, dev_instance, ata_sff_port_intr); | |
1611 | } | |
0fe40ff8 | 1612 | EXPORT_SYMBOL_GPL(ata_sff_interrupt); |
624d5c51 | 1613 | |
c96f1732 AC |
1614 | /** |
1615 | * ata_sff_lost_interrupt - Check for an apparent lost interrupt | |
1616 | * @ap: port that appears to have timed out | |
1617 | * | |
1618 | * Called from the libata error handlers when the core code suspects | |
1619 | * an interrupt has been lost. If it has complete anything we can and | |
1620 | * then return. Interface must support altstatus for this faster | |
1621 | * recovery to occur. | |
1622 | * | |
1623 | * Locking: | |
1624 | * Caller holds host lock | |
1625 | */ | |
1626 | ||
1627 | void ata_sff_lost_interrupt(struct ata_port *ap) | |
1628 | { | |
1629 | u8 status; | |
1630 | struct ata_queued_cmd *qc; | |
1631 | ||
1632 | /* Only one outstanding command per SFF channel */ | |
1633 | qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
3e4ec344 TH |
1634 | /* We cannot lose an interrupt on a non-existent or polled command */ |
1635 | if (!qc || qc->tf.flags & ATA_TFLAG_POLLING) | |
c96f1732 AC |
1636 | return; |
1637 | /* See if the controller thinks it is still busy - if so the command | |
1638 | isn't a lost IRQ but is still in progress */ | |
1639 | status = ata_sff_altstatus(ap); | |
1640 | if (status & ATA_BUSY) | |
1641 | return; | |
1642 | ||
1643 | /* There was a command running, we are no longer busy and we have | |
1644 | no interrupt. */ | |
a9a79dfe | 1645 | ata_port_warn(ap, "lost interrupt (Status 0x%x)\n", |
c96f1732 AC |
1646 | status); |
1647 | /* Run the host interrupt logic as if the interrupt had not been | |
1648 | lost */ | |
c3b28894 | 1649 | ata_sff_port_intr(ap, qc); |
c96f1732 AC |
1650 | } |
1651 | EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt); | |
1652 | ||
624d5c51 | 1653 | /** |
9363c382 | 1654 | * ata_sff_freeze - Freeze SFF controller port |
624d5c51 TH |
1655 | * @ap: port to freeze |
1656 | * | |
9f2f7210 | 1657 | * Freeze SFF controller port. |
624d5c51 TH |
1658 | * |
1659 | * LOCKING: | |
1660 | * Inherited from caller. | |
1661 | */ | |
9363c382 | 1662 | void ata_sff_freeze(struct ata_port *ap) |
624d5c51 | 1663 | { |
624d5c51 TH |
1664 | ap->ctl |= ATA_NIEN; |
1665 | ap->last_ctl = ap->ctl; | |
1666 | ||
41dec29b SS |
1667 | if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) |
1668 | ata_sff_set_devctl(ap, ap->ctl); | |
624d5c51 TH |
1669 | |
1670 | /* Under certain circumstances, some controllers raise IRQ on | |
1671 | * ATA_NIEN manipulation. Also, many controllers fail to mask | |
1672 | * previously pending IRQ on ATA_NIEN assertion. Clear it. | |
1673 | */ | |
5682ed33 | 1674 | ap->ops->sff_check_status(ap); |
624d5c51 | 1675 | |
37f65b8b TH |
1676 | if (ap->ops->sff_irq_clear) |
1677 | ap->ops->sff_irq_clear(ap); | |
624d5c51 | 1678 | } |
0fe40ff8 | 1679 | EXPORT_SYMBOL_GPL(ata_sff_freeze); |
624d5c51 TH |
1680 | |
1681 | /** | |
9363c382 | 1682 | * ata_sff_thaw - Thaw SFF controller port |
624d5c51 TH |
1683 | * @ap: port to thaw |
1684 | * | |
9363c382 | 1685 | * Thaw SFF controller port. |
624d5c51 TH |
1686 | * |
1687 | * LOCKING: | |
1688 | * Inherited from caller. | |
1689 | */ | |
9363c382 | 1690 | void ata_sff_thaw(struct ata_port *ap) |
272f7884 | 1691 | { |
624d5c51 | 1692 | /* clear & re-enable interrupts */ |
5682ed33 | 1693 | ap->ops->sff_check_status(ap); |
37f65b8b TH |
1694 | if (ap->ops->sff_irq_clear) |
1695 | ap->ops->sff_irq_clear(ap); | |
e42a542b | 1696 | ata_sff_irq_on(ap); |
272f7884 | 1697 | } |
0fe40ff8 | 1698 | EXPORT_SYMBOL_GPL(ata_sff_thaw); |
272f7884 | 1699 | |
0aa1113d TH |
1700 | /** |
1701 | * ata_sff_prereset - prepare SFF link for reset | |
1702 | * @link: SFF link to be reset | |
1703 | * @deadline: deadline jiffies for the operation | |
1704 | * | |
1705 | * SFF link @link is about to be reset. Initialize it. It first | |
1706 | * calls ata_std_prereset() and wait for !BSY if the port is | |
1707 | * being softreset. | |
1708 | * | |
1709 | * LOCKING: | |
1710 | * Kernel thread context (may sleep) | |
1711 | * | |
1712 | * RETURNS: | |
1713 | * 0 on success, -errno otherwise. | |
1714 | */ | |
1715 | int ata_sff_prereset(struct ata_link *link, unsigned long deadline) | |
1716 | { | |
0aa1113d TH |
1717 | struct ata_eh_context *ehc = &link->eh_context; |
1718 | int rc; | |
1719 | ||
1720 | rc = ata_std_prereset(link, deadline); | |
1721 | if (rc) | |
1722 | return rc; | |
1723 | ||
1724 | /* if we're about to do hardreset, nothing more to do */ | |
1725 | if (ehc->i.action & ATA_EH_HARDRESET) | |
1726 | return 0; | |
1727 | ||
1728 | /* wait for !BSY if we don't know that no device is attached */ | |
1729 | if (!ata_link_offline(link)) { | |
705e76be | 1730 | rc = ata_sff_wait_ready(link, deadline); |
0aa1113d | 1731 | if (rc && rc != -ENODEV) { |
a9a79dfe JP |
1732 | ata_link_warn(link, |
1733 | "device not ready (errno=%d), forcing hardreset\n", | |
1734 | rc); | |
0aa1113d TH |
1735 | ehc->i.action |= ATA_EH_HARDRESET; |
1736 | } | |
1737 | } | |
1738 | ||
1739 | return 0; | |
1740 | } | |
0fe40ff8 | 1741 | EXPORT_SYMBOL_GPL(ata_sff_prereset); |
0aa1113d | 1742 | |
90088bb4 | 1743 | /** |
624d5c51 TH |
1744 | * ata_devchk - PATA device presence detection |
1745 | * @ap: ATA channel to examine | |
1746 | * @device: Device to examine (starting at zero) | |
90088bb4 | 1747 | * |
624d5c51 TH |
1748 | * This technique was originally described in |
1749 | * Hale Landis's ATADRVR (www.ata-atapi.com), and | |
1750 | * later found its way into the ATA/ATAPI spec. | |
1751 | * | |
1752 | * Write a pattern to the ATA shadow registers, | |
1753 | * and if a device is present, it will respond by | |
1754 | * correctly storing and echoing back the | |
1755 | * ATA shadow register contents. | |
90088bb4 TH |
1756 | * |
1757 | * LOCKING: | |
624d5c51 | 1758 | * caller. |
90088bb4 | 1759 | */ |
624d5c51 | 1760 | static unsigned int ata_devchk(struct ata_port *ap, unsigned int device) |
90088bb4 TH |
1761 | { |
1762 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
624d5c51 | 1763 | u8 nsect, lbal; |
90088bb4 | 1764 | |
5682ed33 | 1765 | ap->ops->sff_dev_select(ap, device); |
90088bb4 | 1766 | |
624d5c51 TH |
1767 | iowrite8(0x55, ioaddr->nsect_addr); |
1768 | iowrite8(0xaa, ioaddr->lbal_addr); | |
90088bb4 | 1769 | |
624d5c51 TH |
1770 | iowrite8(0xaa, ioaddr->nsect_addr); |
1771 | iowrite8(0x55, ioaddr->lbal_addr); | |
90088bb4 | 1772 | |
624d5c51 TH |
1773 | iowrite8(0x55, ioaddr->nsect_addr); |
1774 | iowrite8(0xaa, ioaddr->lbal_addr); | |
1775 | ||
1776 | nsect = ioread8(ioaddr->nsect_addr); | |
1777 | lbal = ioread8(ioaddr->lbal_addr); | |
1778 | ||
1779 | if ((nsect == 0x55) && (lbal == 0xaa)) | |
1780 | return 1; /* we found a device */ | |
1781 | ||
1782 | return 0; /* nothing found */ | |
90088bb4 TH |
1783 | } |
1784 | ||
272f7884 | 1785 | /** |
9363c382 | 1786 | * ata_sff_dev_classify - Parse returned ATA device signature |
624d5c51 TH |
1787 | * @dev: ATA device to classify (starting at zero) |
1788 | * @present: device seems present | |
1789 | * @r_err: Value of error register on completion | |
272f7884 | 1790 | * |
624d5c51 TH |
1791 | * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs, |
1792 | * an ATA/ATAPI-defined set of values is placed in the ATA | |
1793 | * shadow registers, indicating the results of device detection | |
1794 | * and diagnostics. | |
272f7884 | 1795 | * |
624d5c51 TH |
1796 | * Select the ATA device, and read the values from the ATA shadow |
1797 | * registers. Then parse according to the Error register value, | |
1798 | * and the spec-defined values examined by ata_dev_classify(). | |
272f7884 TH |
1799 | * |
1800 | * LOCKING: | |
624d5c51 TH |
1801 | * caller. |
1802 | * | |
1803 | * RETURNS: | |
1804 | * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE. | |
272f7884 | 1805 | */ |
9363c382 | 1806 | unsigned int ata_sff_dev_classify(struct ata_device *dev, int present, |
624d5c51 | 1807 | u8 *r_err) |
272f7884 | 1808 | { |
624d5c51 TH |
1809 | struct ata_port *ap = dev->link->ap; |
1810 | struct ata_taskfile tf; | |
1811 | unsigned int class; | |
1812 | u8 err; | |
1813 | ||
5682ed33 | 1814 | ap->ops->sff_dev_select(ap, dev->devno); |
624d5c51 TH |
1815 | |
1816 | memset(&tf, 0, sizeof(tf)); | |
1817 | ||
5682ed33 | 1818 | ap->ops->sff_tf_read(ap, &tf); |
624d5c51 TH |
1819 | err = tf.feature; |
1820 | if (r_err) | |
1821 | *r_err = err; | |
1822 | ||
1823 | /* see if device passed diags: continue and warn later */ | |
1824 | if (err == 0) | |
1825 | /* diagnostic fail : do nothing _YET_ */ | |
1826 | dev->horkage |= ATA_HORKAGE_DIAGNOSTIC; | |
1827 | else if (err == 1) | |
1828 | /* do nothing */ ; | |
1829 | else if ((dev->devno == 0) && (err == 0x81)) | |
1830 | /* do nothing */ ; | |
1831 | else | |
1832 | return ATA_DEV_NONE; | |
272f7884 | 1833 | |
624d5c51 TH |
1834 | /* determine if device is ATA or ATAPI */ |
1835 | class = ata_dev_classify(&tf); | |
272f7884 | 1836 | |
624d5c51 TH |
1837 | if (class == ATA_DEV_UNKNOWN) { |
1838 | /* If the device failed diagnostic, it's likely to | |
1839 | * have reported incorrect device signature too. | |
1840 | * Assume ATA device if the device seems present but | |
1841 | * device signature is invalid with diagnostic | |
1842 | * failure. | |
1843 | */ | |
1844 | if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC)) | |
1845 | class = ATA_DEV_ATA; | |
1846 | else | |
1847 | class = ATA_DEV_NONE; | |
5682ed33 TH |
1848 | } else if ((class == ATA_DEV_ATA) && |
1849 | (ap->ops->sff_check_status(ap) == 0)) | |
624d5c51 TH |
1850 | class = ATA_DEV_NONE; |
1851 | ||
1852 | return class; | |
272f7884 | 1853 | } |
0fe40ff8 | 1854 | EXPORT_SYMBOL_GPL(ata_sff_dev_classify); |
272f7884 | 1855 | |
705e76be TH |
1856 | /** |
1857 | * ata_sff_wait_after_reset - wait for devices to become ready after reset | |
1858 | * @link: SFF link which is just reset | |
1859 | * @devmask: mask of present devices | |
1860 | * @deadline: deadline jiffies for the operation | |
1861 | * | |
1862 | * Wait devices attached to SFF @link to become ready after | |
1863 | * reset. It contains preceding 150ms wait to avoid accessing TF | |
1864 | * status register too early. | |
1865 | * | |
1866 | * LOCKING: | |
1867 | * Kernel thread context (may sleep). | |
1868 | * | |
1869 | * RETURNS: | |
1870 | * 0 on success, -ENODEV if some or all of devices in @devmask | |
1871 | * don't seem to exist. -errno on other errors. | |
1872 | */ | |
1873 | int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask, | |
1874 | unsigned long deadline) | |
1fdffbce | 1875 | { |
705e76be | 1876 | struct ata_port *ap = link->ap; |
1fdffbce | 1877 | struct ata_ioports *ioaddr = &ap->ioaddr; |
624d5c51 TH |
1878 | unsigned int dev0 = devmask & (1 << 0); |
1879 | unsigned int dev1 = devmask & (1 << 1); | |
1880 | int rc, ret = 0; | |
1fdffbce | 1881 | |
97750ceb | 1882 | ata_msleep(ap, ATA_WAIT_AFTER_RESET); |
705e76be TH |
1883 | |
1884 | /* always check readiness of the master device */ | |
1885 | rc = ata_sff_wait_ready(link, deadline); | |
1886 | /* -ENODEV means the odd clown forgot the D7 pulldown resistor | |
1887 | * and TF status is 0xff, bail out on it too. | |
624d5c51 | 1888 | */ |
705e76be TH |
1889 | if (rc) |
1890 | return rc; | |
1fdffbce | 1891 | |
624d5c51 TH |
1892 | /* if device 1 was found in ata_devchk, wait for register |
1893 | * access briefly, then wait for BSY to clear. | |
1894 | */ | |
1895 | if (dev1) { | |
1896 | int i; | |
1fdffbce | 1897 | |
5682ed33 | 1898 | ap->ops->sff_dev_select(ap, 1); |
1fdffbce | 1899 | |
624d5c51 TH |
1900 | /* Wait for register access. Some ATAPI devices fail |
1901 | * to set nsect/lbal after reset, so don't waste too | |
1902 | * much time on it. We're gonna wait for !BSY anyway. | |
1903 | */ | |
1904 | for (i = 0; i < 2; i++) { | |
1905 | u8 nsect, lbal; | |
1906 | ||
1907 | nsect = ioread8(ioaddr->nsect_addr); | |
1908 | lbal = ioread8(ioaddr->lbal_addr); | |
1909 | if ((nsect == 1) && (lbal == 1)) | |
1910 | break; | |
97750ceb | 1911 | ata_msleep(ap, 50); /* give drive a breather */ |
624d5c51 TH |
1912 | } |
1913 | ||
705e76be | 1914 | rc = ata_sff_wait_ready(link, deadline); |
624d5c51 TH |
1915 | if (rc) { |
1916 | if (rc != -ENODEV) | |
1917 | return rc; | |
1918 | ret = rc; | |
1919 | } | |
1fdffbce JG |
1920 | } |
1921 | ||
624d5c51 | 1922 | /* is all this really necessary? */ |
5682ed33 | 1923 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 | 1924 | if (dev1) |
5682ed33 | 1925 | ap->ops->sff_dev_select(ap, 1); |
624d5c51 | 1926 | if (dev0) |
5682ed33 | 1927 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
1928 | |
1929 | return ret; | |
1fdffbce | 1930 | } |
0fe40ff8 | 1931 | EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset); |
1fdffbce | 1932 | |
624d5c51 TH |
1933 | static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask, |
1934 | unsigned long deadline) | |
2cc432ee | 1935 | { |
624d5c51 | 1936 | struct ata_ioports *ioaddr = &ap->ioaddr; |
2cc432ee | 1937 | |
624d5c51 TH |
1938 | DPRINTK("ata%u: bus reset via SRST\n", ap->print_id); |
1939 | ||
6d8ca28f OZ |
1940 | if (ap->ioaddr.ctl_addr) { |
1941 | /* software reset. causes dev0 to be selected */ | |
1942 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
1943 | udelay(20); /* FIXME: flush */ | |
1944 | iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr); | |
1945 | udelay(20); /* FIXME: flush */ | |
1946 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
1947 | ap->last_ctl = ap->ctl; | |
1948 | } | |
624d5c51 | 1949 | |
705e76be TH |
1950 | /* wait the port to become ready */ |
1951 | return ata_sff_wait_after_reset(&ap->link, devmask, deadline); | |
2cc432ee JG |
1952 | } |
1953 | ||
6d97dbd7 | 1954 | /** |
9363c382 | 1955 | * ata_sff_softreset - reset host port via ATA SRST |
624d5c51 TH |
1956 | * @link: ATA link to reset |
1957 | * @classes: resulting classes of attached devices | |
1958 | * @deadline: deadline jiffies for the operation | |
6d97dbd7 | 1959 | * |
624d5c51 | 1960 | * Reset host port using ATA SRST. |
6d97dbd7 TH |
1961 | * |
1962 | * LOCKING: | |
624d5c51 TH |
1963 | * Kernel thread context (may sleep) |
1964 | * | |
1965 | * RETURNS: | |
1966 | * 0 on success, -errno otherwise. | |
6d97dbd7 | 1967 | */ |
9363c382 | 1968 | int ata_sff_softreset(struct ata_link *link, unsigned int *classes, |
624d5c51 | 1969 | unsigned long deadline) |
6d97dbd7 | 1970 | { |
624d5c51 TH |
1971 | struct ata_port *ap = link->ap; |
1972 | unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; | |
1973 | unsigned int devmask = 0; | |
1974 | int rc; | |
1975 | u8 err; | |
6d97dbd7 | 1976 | |
624d5c51 | 1977 | DPRINTK("ENTER\n"); |
6d97dbd7 | 1978 | |
624d5c51 TH |
1979 | /* determine if device 0/1 are present */ |
1980 | if (ata_devchk(ap, 0)) | |
1981 | devmask |= (1 << 0); | |
1982 | if (slave_possible && ata_devchk(ap, 1)) | |
1983 | devmask |= (1 << 1); | |
1984 | ||
1985 | /* select device 0 again */ | |
5682ed33 | 1986 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
1987 | |
1988 | /* issue bus reset */ | |
1989 | DPRINTK("about to softreset, devmask=%x\n", devmask); | |
1990 | rc = ata_bus_softreset(ap, devmask, deadline); | |
1991 | /* if link is occupied, -ENODEV too is an error */ | |
1992 | if (rc && (rc != -ENODEV || sata_scr_valid(link))) { | |
a9a79dfe | 1993 | ata_link_err(link, "SRST failed (errno=%d)\n", rc); |
624d5c51 TH |
1994 | return rc; |
1995 | } | |
0f0a3ad3 | 1996 | |
624d5c51 | 1997 | /* determine by signature whether we have ATA or ATAPI devices */ |
9363c382 | 1998 | classes[0] = ata_sff_dev_classify(&link->device[0], |
624d5c51 TH |
1999 | devmask & (1 << 0), &err); |
2000 | if (slave_possible && err != 0x81) | |
9363c382 | 2001 | classes[1] = ata_sff_dev_classify(&link->device[1], |
624d5c51 TH |
2002 | devmask & (1 << 1), &err); |
2003 | ||
624d5c51 TH |
2004 | DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]); |
2005 | return 0; | |
6d97dbd7 | 2006 | } |
0fe40ff8 | 2007 | EXPORT_SYMBOL_GPL(ata_sff_softreset); |
6d97dbd7 TH |
2008 | |
2009 | /** | |
9363c382 | 2010 | * sata_sff_hardreset - reset host port via SATA phy reset |
624d5c51 TH |
2011 | * @link: link to reset |
2012 | * @class: resulting class of attached device | |
2013 | * @deadline: deadline jiffies for the operation | |
6d97dbd7 | 2014 | * |
624d5c51 TH |
2015 | * SATA phy-reset host port using DET bits of SControl register, |
2016 | * wait for !BSY and classify the attached device. | |
6d97dbd7 TH |
2017 | * |
2018 | * LOCKING: | |
624d5c51 TH |
2019 | * Kernel thread context (may sleep) |
2020 | * | |
2021 | * RETURNS: | |
2022 | * 0 on success, -errno otherwise. | |
6d97dbd7 | 2023 | */ |
9363c382 | 2024 | int sata_sff_hardreset(struct ata_link *link, unsigned int *class, |
624d5c51 | 2025 | unsigned long deadline) |
6d97dbd7 | 2026 | { |
9dadd45b TH |
2027 | struct ata_eh_context *ehc = &link->eh_context; |
2028 | const unsigned long *timing = sata_ehc_deb_timing(ehc); | |
2029 | bool online; | |
624d5c51 TH |
2030 | int rc; |
2031 | ||
9dadd45b TH |
2032 | rc = sata_link_hardreset(link, timing, deadline, &online, |
2033 | ata_sff_check_ready); | |
9dadd45b TH |
2034 | if (online) |
2035 | *class = ata_sff_dev_classify(link->device, 1, NULL); | |
624d5c51 TH |
2036 | |
2037 | DPRINTK("EXIT, class=%u\n", *class); | |
9dadd45b | 2038 | return rc; |
6d97dbd7 | 2039 | } |
0fe40ff8 | 2040 | EXPORT_SYMBOL_GPL(sata_sff_hardreset); |
6d97dbd7 | 2041 | |
203c75b8 TH |
2042 | /** |
2043 | * ata_sff_postreset - SFF postreset callback | |
2044 | * @link: the target SFF ata_link | |
2045 | * @classes: classes of attached devices | |
2046 | * | |
2047 | * This function is invoked after a successful reset. It first | |
2048 | * calls ata_std_postreset() and performs SFF specific postreset | |
2049 | * processing. | |
2050 | * | |
2051 | * LOCKING: | |
2052 | * Kernel thread context (may sleep) | |
2053 | */ | |
2054 | void ata_sff_postreset(struct ata_link *link, unsigned int *classes) | |
2055 | { | |
2056 | struct ata_port *ap = link->ap; | |
2057 | ||
2058 | ata_std_postreset(link, classes); | |
2059 | ||
2060 | /* is double-select really necessary? */ | |
2061 | if (classes[0] != ATA_DEV_NONE) | |
2062 | ap->ops->sff_dev_select(ap, 1); | |
2063 | if (classes[1] != ATA_DEV_NONE) | |
2064 | ap->ops->sff_dev_select(ap, 0); | |
2065 | ||
2066 | /* bail out if no device is present */ | |
2067 | if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) { | |
2068 | DPRINTK("EXIT, no device\n"); | |
2069 | return; | |
2070 | } | |
2071 | ||
2072 | /* set up device control */ | |
41dec29b SS |
2073 | if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) { |
2074 | ata_sff_set_devctl(ap, ap->ctl); | |
e3e4385f SM |
2075 | ap->last_ctl = ap->ctl; |
2076 | } | |
203c75b8 | 2077 | } |
0fe40ff8 | 2078 | EXPORT_SYMBOL_GPL(ata_sff_postreset); |
203c75b8 | 2079 | |
3d47aa8e AC |
2080 | /** |
2081 | * ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers | |
2082 | * @qc: command | |
2083 | * | |
2084 | * Drain the FIFO and device of any stuck data following a command | |
3ad2f3fb | 2085 | * failing to complete. In some cases this is necessary before a |
3d47aa8e AC |
2086 | * reset will recover the device. |
2087 | * | |
2088 | */ | |
2089 | ||
2090 | void ata_sff_drain_fifo(struct ata_queued_cmd *qc) | |
2091 | { | |
2092 | int count; | |
2093 | struct ata_port *ap; | |
2094 | ||
2095 | /* We only need to flush incoming data when a command was running */ | |
2096 | if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE) | |
2097 | return; | |
2098 | ||
2099 | ap = qc->ap; | |
2100 | /* Drain up to 64K of data before we give up this recovery method */ | |
2101 | for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) | |
9a8fd68b | 2102 | && count < 65536; count += 2) |
3d47aa8e AC |
2103 | ioread16(ap->ioaddr.data_addr); |
2104 | ||
2105 | /* Can become DEBUG later */ | |
2106 | if (count) | |
a9a79dfe | 2107 | ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count); |
3d47aa8e AC |
2108 | |
2109 | } | |
2110 | EXPORT_SYMBOL_GPL(ata_sff_drain_fifo); | |
2111 | ||
6d97dbd7 | 2112 | /** |
fe06e5f9 | 2113 | * ata_sff_error_handler - Stock error handler for SFF controller |
6d97dbd7 | 2114 | * @ap: port to handle error for |
6d97dbd7 | 2115 | * |
9363c382 | 2116 | * Stock error handler for SFF controller. It can handle both |
6d97dbd7 TH |
2117 | * PATA and SATA controllers. Many controllers should be able to |
2118 | * use this EH as-is or with some added handling before and | |
2119 | * after. | |
2120 | * | |
6d97dbd7 TH |
2121 | * LOCKING: |
2122 | * Kernel thread context (may sleep) | |
2123 | */ | |
9363c382 | 2124 | void ata_sff_error_handler(struct ata_port *ap) |
6d97dbd7 | 2125 | { |
a1efdaba TH |
2126 | ata_reset_fn_t softreset = ap->ops->softreset; |
2127 | ata_reset_fn_t hardreset = ap->ops->hardreset; | |
6d97dbd7 TH |
2128 | struct ata_queued_cmd *qc; |
2129 | unsigned long flags; | |
6d97dbd7 | 2130 | |
9af5c9c9 | 2131 | qc = __ata_qc_from_tag(ap, ap->link.active_tag); |
6d97dbd7 TH |
2132 | if (qc && !(qc->flags & ATA_QCFLAG_FAILED)) |
2133 | qc = NULL; | |
2134 | ||
ba6a1308 | 2135 | spin_lock_irqsave(ap->lock, flags); |
6d97dbd7 | 2136 | |
fe06e5f9 TH |
2137 | /* |
2138 | * We *MUST* do FIFO draining before we issue a reset as | |
2139 | * several devices helpfully clear their internal state and | |
2140 | * will lock solid if we touch the data port post reset. Pass | |
2141 | * qc in case anyone wants to do different PIO/DMA recovery or | |
2142 | * has per command fixups | |
3d47aa8e | 2143 | */ |
8244cd05 TH |
2144 | if (ap->ops->sff_drain_fifo) |
2145 | ap->ops->sff_drain_fifo(qc); | |
6d97dbd7 | 2146 | |
ba6a1308 | 2147 | spin_unlock_irqrestore(ap->lock, flags); |
6d97dbd7 | 2148 | |
fe06e5f9 TH |
2149 | /* ignore built-in hardresets if SCR access is not available */ |
2150 | if ((hardreset == sata_std_hardreset || | |
2151 | hardreset == sata_sff_hardreset) && !sata_scr_valid(&ap->link)) | |
a1efdaba | 2152 | hardreset = NULL; |
6d97dbd7 | 2153 | |
a1efdaba TH |
2154 | ata_do_eh(ap, ap->ops->prereset, softreset, hardreset, |
2155 | ap->ops->postreset); | |
6d97dbd7 | 2156 | } |
0fe40ff8 | 2157 | EXPORT_SYMBOL_GPL(ata_sff_error_handler); |
6d97dbd7 | 2158 | |
624d5c51 | 2159 | /** |
9363c382 | 2160 | * ata_sff_std_ports - initialize ioaddr with standard port offsets. |
624d5c51 TH |
2161 | * @ioaddr: IO address structure to be initialized |
2162 | * | |
2163 | * Utility function which initializes data_addr, error_addr, | |
2164 | * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr, | |
2165 | * device_addr, status_addr, and command_addr to standard offsets | |
2166 | * relative to cmd_addr. | |
2167 | * | |
2168 | * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr. | |
2169 | */ | |
9363c382 | 2170 | void ata_sff_std_ports(struct ata_ioports *ioaddr) |
624d5c51 TH |
2171 | { |
2172 | ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA; | |
2173 | ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR; | |
2174 | ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE; | |
2175 | ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT; | |
2176 | ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL; | |
2177 | ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM; | |
2178 | ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH; | |
2179 | ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE; | |
2180 | ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS; | |
2181 | ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD; | |
2182 | } | |
0fe40ff8 | 2183 | EXPORT_SYMBOL_GPL(ata_sff_std_ports); |
624d5c51 | 2184 | |
1fdffbce | 2185 | #ifdef CONFIG_PCI |
4112e16a | 2186 | |
272f7884 TH |
2187 | static int ata_resources_present(struct pci_dev *pdev, int port) |
2188 | { | |
2189 | int i; | |
2190 | ||
2191 | /* Check the PCI resources for this channel are enabled */ | |
2192 | port = port * 2; | |
0fe40ff8 | 2193 | for (i = 0; i < 2; i++) { |
272f7884 TH |
2194 | if (pci_resource_start(pdev, port + i) == 0 || |
2195 | pci_resource_len(pdev, port + i) == 0) | |
2196 | return 0; | |
2197 | } | |
2198 | return 1; | |
2199 | } | |
2200 | ||
d491b27b | 2201 | /** |
9363c382 | 2202 | * ata_pci_sff_init_host - acquire native PCI ATA resources and init host |
d491b27b | 2203 | * @host: target ATA host |
d491b27b | 2204 | * |
1626aeb8 TH |
2205 | * Acquire native PCI ATA resources for @host and initialize the |
2206 | * first two ports of @host accordingly. Ports marked dummy are | |
2207 | * skipped and allocation failure makes the port dummy. | |
d491b27b | 2208 | * |
d583bc18 TH |
2209 | * Note that native PCI resources are valid even for legacy hosts |
2210 | * as we fix up pdev resources array early in boot, so this | |
2211 | * function can be used for both native and legacy SFF hosts. | |
2212 | * | |
d491b27b TH |
2213 | * LOCKING: |
2214 | * Inherited from calling layer (may sleep). | |
2215 | * | |
2216 | * RETURNS: | |
1626aeb8 TH |
2217 | * 0 if at least one port is initialized, -ENODEV if no port is |
2218 | * available. | |
d491b27b | 2219 | */ |
9363c382 | 2220 | int ata_pci_sff_init_host(struct ata_host *host) |
d491b27b TH |
2221 | { |
2222 | struct device *gdev = host->dev; | |
2223 | struct pci_dev *pdev = to_pci_dev(gdev); | |
1626aeb8 | 2224 | unsigned int mask = 0; |
d491b27b TH |
2225 | int i, rc; |
2226 | ||
d491b27b TH |
2227 | /* request, iomap BARs and init port addresses accordingly */ |
2228 | for (i = 0; i < 2; i++) { | |
2229 | struct ata_port *ap = host->ports[i]; | |
2230 | int base = i * 2; | |
2231 | void __iomem * const *iomap; | |
2232 | ||
1626aeb8 TH |
2233 | if (ata_port_is_dummy(ap)) |
2234 | continue; | |
2235 | ||
2236 | /* Discard disabled ports. Some controllers show | |
2237 | * their unused channels this way. Disabled ports are | |
2238 | * made dummy. | |
2239 | */ | |
2240 | if (!ata_resources_present(pdev, i)) { | |
2241 | ap->ops = &ata_dummy_port_ops; | |
d491b27b | 2242 | continue; |
1626aeb8 | 2243 | } |
d491b27b | 2244 | |
35a10a80 TH |
2245 | rc = pcim_iomap_regions(pdev, 0x3 << base, |
2246 | dev_driver_string(gdev)); | |
d491b27b | 2247 | if (rc) { |
a44fec1f JP |
2248 | dev_warn(gdev, |
2249 | "failed to request/iomap BARs for port %d (errno=%d)\n", | |
2250 | i, rc); | |
d491b27b TH |
2251 | if (rc == -EBUSY) |
2252 | pcim_pin_device(pdev); | |
1626aeb8 TH |
2253 | ap->ops = &ata_dummy_port_ops; |
2254 | continue; | |
d491b27b TH |
2255 | } |
2256 | host->iomap = iomap = pcim_iomap_table(pdev); | |
2257 | ||
2258 | ap->ioaddr.cmd_addr = iomap[base]; | |
2259 | ap->ioaddr.altstatus_addr = | |
2260 | ap->ioaddr.ctl_addr = (void __iomem *) | |
2261 | ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS); | |
9363c382 | 2262 | ata_sff_std_ports(&ap->ioaddr); |
1626aeb8 | 2263 | |
cbcdd875 TH |
2264 | ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx", |
2265 | (unsigned long long)pci_resource_start(pdev, base), | |
2266 | (unsigned long long)pci_resource_start(pdev, base + 1)); | |
2267 | ||
1626aeb8 TH |
2268 | mask |= 1 << i; |
2269 | } | |
2270 | ||
2271 | if (!mask) { | |
a44fec1f | 2272 | dev_err(gdev, "no available native port\n"); |
1626aeb8 | 2273 | return -ENODEV; |
d491b27b TH |
2274 | } |
2275 | ||
2276 | return 0; | |
2277 | } | |
0fe40ff8 | 2278 | EXPORT_SYMBOL_GPL(ata_pci_sff_init_host); |
d491b27b | 2279 | |
21b0ad4f | 2280 | /** |
1c5afdf7 | 2281 | * ata_pci_sff_prepare_host - helper to prepare PCI PIO-only SFF ATA host |
21b0ad4f | 2282 | * @pdev: target PCI device |
1626aeb8 | 2283 | * @ppi: array of port_info, must be enough for two ports |
21b0ad4f TH |
2284 | * @r_host: out argument for the initialized ATA host |
2285 | * | |
1c5afdf7 TH |
2286 | * Helper to allocate PIO-only SFF ATA host for @pdev, acquire |
2287 | * all PCI resources and initialize it accordingly in one go. | |
21b0ad4f TH |
2288 | * |
2289 | * LOCKING: | |
2290 | * Inherited from calling layer (may sleep). | |
2291 | * | |
2292 | * RETURNS: | |
2293 | * 0 on success, -errno otherwise. | |
2294 | */ | |
9363c382 | 2295 | int ata_pci_sff_prepare_host(struct pci_dev *pdev, |
0fe40ff8 | 2296 | const struct ata_port_info * const *ppi, |
d583bc18 | 2297 | struct ata_host **r_host) |
21b0ad4f TH |
2298 | { |
2299 | struct ata_host *host; | |
21b0ad4f TH |
2300 | int rc; |
2301 | ||
2302 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) | |
2303 | return -ENOMEM; | |
2304 | ||
2305 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); | |
2306 | if (!host) { | |
a44fec1f | 2307 | dev_err(&pdev->dev, "failed to allocate ATA host\n"); |
21b0ad4f TH |
2308 | rc = -ENOMEM; |
2309 | goto err_out; | |
2310 | } | |
2311 | ||
9363c382 | 2312 | rc = ata_pci_sff_init_host(host); |
21b0ad4f TH |
2313 | if (rc) |
2314 | goto err_out; | |
2315 | ||
21b0ad4f TH |
2316 | devres_remove_group(&pdev->dev, NULL); |
2317 | *r_host = host; | |
2318 | return 0; | |
2319 | ||
0fe40ff8 | 2320 | err_out: |
21b0ad4f TH |
2321 | devres_release_group(&pdev->dev, NULL); |
2322 | return rc; | |
2323 | } | |
0fe40ff8 | 2324 | EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host); |
21b0ad4f | 2325 | |
4e6b79fa | 2326 | /** |
9363c382 | 2327 | * ata_pci_sff_activate_host - start SFF host, request IRQ and register it |
4e6b79fa TH |
2328 | * @host: target SFF ATA host |
2329 | * @irq_handler: irq_handler used when requesting IRQ(s) | |
2330 | * @sht: scsi_host_template to use when registering the host | |
2331 | * | |
2332 | * This is the counterpart of ata_host_activate() for SFF ATA | |
2333 | * hosts. This separate helper is necessary because SFF hosts | |
2334 | * use two separate interrupts in legacy mode. | |
2335 | * | |
2336 | * LOCKING: | |
2337 | * Inherited from calling layer (may sleep). | |
2338 | * | |
2339 | * RETURNS: | |
2340 | * 0 on success, -errno otherwise. | |
2341 | */ | |
9363c382 | 2342 | int ata_pci_sff_activate_host(struct ata_host *host, |
4e6b79fa TH |
2343 | irq_handler_t irq_handler, |
2344 | struct scsi_host_template *sht) | |
2345 | { | |
2346 | struct device *dev = host->dev; | |
2347 | struct pci_dev *pdev = to_pci_dev(dev); | |
2348 | const char *drv_name = dev_driver_string(host->dev); | |
2349 | int legacy_mode = 0, rc; | |
2350 | ||
2351 | rc = ata_host_start(host); | |
2352 | if (rc) | |
2353 | return rc; | |
2354 | ||
2355 | if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) { | |
589d5726 | 2356 | u8 tmp8, mask = 0; |
4e6b79fa | 2357 | |
589d5726 DS |
2358 | /* |
2359 | * ATA spec says we should use legacy mode when one | |
2360 | * port is in legacy mode, but disabled ports on some | |
2361 | * PCI hosts appear as fixed legacy ports, e.g SB600/700 | |
2362 | * on which the secondary port is not wired, so | |
2363 | * ignore ports that are marked as 'dummy' during | |
2364 | * this check | |
2365 | */ | |
4e6b79fa | 2366 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8); |
589d5726 DS |
2367 | if (!ata_port_is_dummy(host->ports[0])) |
2368 | mask |= (1 << 0); | |
2369 | if (!ata_port_is_dummy(host->ports[1])) | |
2370 | mask |= (1 << 2); | |
4e6b79fa TH |
2371 | if ((tmp8 & mask) != mask) |
2372 | legacy_mode = 1; | |
4e6b79fa TH |
2373 | } |
2374 | ||
2375 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) | |
2376 | return -ENOMEM; | |
2377 | ||
2378 | if (!legacy_mode && pdev->irq) { | |
af649a1b JB |
2379 | int i; |
2380 | ||
4e6b79fa TH |
2381 | rc = devm_request_irq(dev, pdev->irq, irq_handler, |
2382 | IRQF_SHARED, drv_name, host); | |
2383 | if (rc) | |
2384 | goto out; | |
2385 | ||
af649a1b JB |
2386 | for (i = 0; i < 2; i++) { |
2387 | if (ata_port_is_dummy(host->ports[i])) | |
2388 | continue; | |
2389 | ata_port_desc(host->ports[i], "irq %d", pdev->irq); | |
2390 | } | |
4e6b79fa TH |
2391 | } else if (legacy_mode) { |
2392 | if (!ata_port_is_dummy(host->ports[0])) { | |
2393 | rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev), | |
2394 | irq_handler, IRQF_SHARED, | |
2395 | drv_name, host); | |
2396 | if (rc) | |
2397 | goto out; | |
2398 | ||
2399 | ata_port_desc(host->ports[0], "irq %d", | |
2400 | ATA_PRIMARY_IRQ(pdev)); | |
2401 | } | |
2402 | ||
2403 | if (!ata_port_is_dummy(host->ports[1])) { | |
2404 | rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev), | |
2405 | irq_handler, IRQF_SHARED, | |
2406 | drv_name, host); | |
2407 | if (rc) | |
2408 | goto out; | |
2409 | ||
2410 | ata_port_desc(host->ports[1], "irq %d", | |
2411 | ATA_SECONDARY_IRQ(pdev)); | |
2412 | } | |
2413 | } | |
2414 | ||
2415 | rc = ata_host_register(host, sht); | |
0fe40ff8 | 2416 | out: |
4e6b79fa TH |
2417 | if (rc == 0) |
2418 | devres_remove_group(dev, NULL); | |
2419 | else | |
2420 | devres_release_group(dev, NULL); | |
2421 | ||
2422 | return rc; | |
2423 | } | |
0fe40ff8 | 2424 | EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host); |
4e6b79fa | 2425 | |
1c5afdf7 TH |
2426 | static const struct ata_port_info *ata_sff_find_valid_pi( |
2427 | const struct ata_port_info * const *ppi) | |
2428 | { | |
2429 | int i; | |
2430 | ||
2431 | /* look up the first valid port_info */ | |
2432 | for (i = 0; i < 2 && ppi[i]; i++) | |
2433 | if (ppi[i]->port_ops != &ata_dummy_port_ops) | |
2434 | return ppi[i]; | |
2435 | ||
2436 | return NULL; | |
2437 | } | |
2438 | ||
c2036033 BZ |
2439 | static int ata_pci_init_one(struct pci_dev *pdev, |
2440 | const struct ata_port_info * const *ppi, | |
2441 | struct scsi_host_template *sht, void *host_priv, | |
2442 | int hflags, bool bmdma) | |
1fdffbce | 2443 | { |
f0d36efd | 2444 | struct device *dev = &pdev->dev; |
1c5afdf7 | 2445 | const struct ata_port_info *pi; |
0f834de3 | 2446 | struct ata_host *host = NULL; |
1c5afdf7 | 2447 | int rc; |
1fdffbce JG |
2448 | |
2449 | DPRINTK("ENTER\n"); | |
2450 | ||
1c5afdf7 | 2451 | pi = ata_sff_find_valid_pi(ppi); |
1626aeb8 | 2452 | if (!pi) { |
a44fec1f | 2453 | dev_err(&pdev->dev, "no valid port_info specified\n"); |
1626aeb8 TH |
2454 | return -EINVAL; |
2455 | } | |
c791c306 | 2456 | |
1626aeb8 TH |
2457 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) |
2458 | return -ENOMEM; | |
1fdffbce | 2459 | |
f0d36efd | 2460 | rc = pcim_enable_device(pdev); |
1fdffbce | 2461 | if (rc) |
4e6b79fa | 2462 | goto out; |
1fdffbce | 2463 | |
aab94404 | 2464 | #ifdef CONFIG_ATA_BMDMA |
c2036033 BZ |
2465 | if (bmdma) |
2466 | /* prepare and activate BMDMA host */ | |
2467 | rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host); | |
2468 | else | |
aab94404 | 2469 | #endif |
c2036033 BZ |
2470 | /* prepare and activate SFF host */ |
2471 | rc = ata_pci_sff_prepare_host(pdev, ppi, &host); | |
d583bc18 | 2472 | if (rc) |
4e6b79fa | 2473 | goto out; |
887125e3 | 2474 | host->private_data = host_priv; |
c2036033 | 2475 | host->flags |= hflags; |
d491b27b | 2476 | |
aab94404 | 2477 | #ifdef CONFIG_ATA_BMDMA |
c2036033 BZ |
2478 | if (bmdma) { |
2479 | pci_set_master(pdev); | |
2480 | rc = ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht); | |
2481 | } else | |
aab94404 | 2482 | #endif |
c2036033 | 2483 | rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht); |
0fe40ff8 | 2484 | out: |
4e6b79fa TH |
2485 | if (rc == 0) |
2486 | devres_remove_group(&pdev->dev, NULL); | |
2487 | else | |
2488 | devres_release_group(&pdev->dev, NULL); | |
d491b27b | 2489 | |
1fdffbce JG |
2490 | return rc; |
2491 | } | |
c2036033 BZ |
2492 | |
2493 | /** | |
2494 | * ata_pci_sff_init_one - Initialize/register PIO-only PCI IDE controller | |
2495 | * @pdev: Controller to be initialized | |
2496 | * @ppi: array of port_info, must be enough for two ports | |
2497 | * @sht: scsi_host_template to use when registering the host | |
2498 | * @host_priv: host private_data | |
2499 | * @hflag: host flags | |
2500 | * | |
2501 | * This is a helper function which can be called from a driver's | |
2502 | * xxx_init_one() probe function if the hardware uses traditional | |
2503 | * IDE taskfile registers and is PIO only. | |
2504 | * | |
2505 | * ASSUMPTION: | |
2506 | * Nobody makes a single channel controller that appears solely as | |
2507 | * the secondary legacy port on PCI. | |
2508 | * | |
2509 | * LOCKING: | |
2510 | * Inherited from PCI layer (may sleep). | |
2511 | * | |
2512 | * RETURNS: | |
2513 | * Zero on success, negative on errno-based value on error. | |
2514 | */ | |
2515 | int ata_pci_sff_init_one(struct pci_dev *pdev, | |
2516 | const struct ata_port_info * const *ppi, | |
2517 | struct scsi_host_template *sht, void *host_priv, int hflag) | |
2518 | { | |
2519 | return ata_pci_init_one(pdev, ppi, sht, host_priv, hflag, 0); | |
2520 | } | |
0fe40ff8 | 2521 | EXPORT_SYMBOL_GPL(ata_pci_sff_init_one); |
1fdffbce JG |
2522 | |
2523 | #endif /* CONFIG_PCI */ | |
9f2f7210 | 2524 | |
9a7780c9 TH |
2525 | /* |
2526 | * BMDMA support | |
2527 | */ | |
2528 | ||
2529 | #ifdef CONFIG_ATA_BMDMA | |
2530 | ||
9f2f7210 TH |
2531 | const struct ata_port_operations ata_bmdma_port_ops = { |
2532 | .inherits = &ata_sff_port_ops, | |
2533 | ||
fe06e5f9 TH |
2534 | .error_handler = ata_bmdma_error_handler, |
2535 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
2536 | ||
f47451c4 | 2537 | .qc_prep = ata_bmdma_qc_prep, |
360ff783 | 2538 | .qc_issue = ata_bmdma_qc_issue, |
f47451c4 | 2539 | |
37f65b8b | 2540 | .sff_irq_clear = ata_bmdma_irq_clear, |
9f2f7210 TH |
2541 | .bmdma_setup = ata_bmdma_setup, |
2542 | .bmdma_start = ata_bmdma_start, | |
2543 | .bmdma_stop = ata_bmdma_stop, | |
2544 | .bmdma_status = ata_bmdma_status, | |
c7087652 TH |
2545 | |
2546 | .port_start = ata_bmdma_port_start, | |
9f2f7210 TH |
2547 | }; |
2548 | EXPORT_SYMBOL_GPL(ata_bmdma_port_ops); | |
2549 | ||
2550 | const struct ata_port_operations ata_bmdma32_port_ops = { | |
2551 | .inherits = &ata_bmdma_port_ops, | |
2552 | ||
2553 | .sff_data_xfer = ata_sff_data_xfer32, | |
c7087652 | 2554 | .port_start = ata_bmdma_port_start32, |
9f2f7210 TH |
2555 | }; |
2556 | EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops); | |
2557 | ||
f47451c4 TH |
2558 | /** |
2559 | * ata_bmdma_fill_sg - Fill PCI IDE PRD table | |
2560 | * @qc: Metadata associated with taskfile to be transferred | |
2561 | * | |
2562 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
2563 | * associated with the current disk command. | |
2564 | * | |
2565 | * LOCKING: | |
2566 | * spin_lock_irqsave(host lock) | |
2567 | * | |
2568 | */ | |
2569 | static void ata_bmdma_fill_sg(struct ata_queued_cmd *qc) | |
2570 | { | |
2571 | struct ata_port *ap = qc->ap; | |
f60d7011 | 2572 | struct ata_bmdma_prd *prd = ap->bmdma_prd; |
f47451c4 TH |
2573 | struct scatterlist *sg; |
2574 | unsigned int si, pi; | |
2575 | ||
2576 | pi = 0; | |
2577 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
2578 | u32 addr, offset; | |
2579 | u32 sg_len, len; | |
2580 | ||
2581 | /* determine if physical DMA addr spans 64K boundary. | |
2582 | * Note h/w doesn't support 64-bit, so we unconditionally | |
2583 | * truncate dma_addr_t to u32. | |
2584 | */ | |
2585 | addr = (u32) sg_dma_address(sg); | |
2586 | sg_len = sg_dma_len(sg); | |
2587 | ||
2588 | while (sg_len) { | |
2589 | offset = addr & 0xffff; | |
2590 | len = sg_len; | |
2591 | if ((offset + sg_len) > 0x10000) | |
2592 | len = 0x10000 - offset; | |
2593 | ||
f60d7011 TH |
2594 | prd[pi].addr = cpu_to_le32(addr); |
2595 | prd[pi].flags_len = cpu_to_le32(len & 0xffff); | |
f47451c4 TH |
2596 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); |
2597 | ||
2598 | pi++; | |
2599 | sg_len -= len; | |
2600 | addr += len; | |
2601 | } | |
2602 | } | |
2603 | ||
f60d7011 | 2604 | prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); |
f47451c4 TH |
2605 | } |
2606 | ||
2607 | /** | |
2608 | * ata_bmdma_fill_sg_dumb - Fill PCI IDE PRD table | |
2609 | * @qc: Metadata associated with taskfile to be transferred | |
2610 | * | |
2611 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
2612 | * associated with the current disk command. Perform the fill | |
2613 | * so that we avoid writing any length 64K records for | |
2614 | * controllers that don't follow the spec. | |
2615 | * | |
2616 | * LOCKING: | |
2617 | * spin_lock_irqsave(host lock) | |
2618 | * | |
2619 | */ | |
2620 | static void ata_bmdma_fill_sg_dumb(struct ata_queued_cmd *qc) | |
2621 | { | |
2622 | struct ata_port *ap = qc->ap; | |
f60d7011 | 2623 | struct ata_bmdma_prd *prd = ap->bmdma_prd; |
f47451c4 TH |
2624 | struct scatterlist *sg; |
2625 | unsigned int si, pi; | |
2626 | ||
2627 | pi = 0; | |
2628 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
2629 | u32 addr, offset; | |
2630 | u32 sg_len, len, blen; | |
2631 | ||
2632 | /* determine if physical DMA addr spans 64K boundary. | |
2633 | * Note h/w doesn't support 64-bit, so we unconditionally | |
2634 | * truncate dma_addr_t to u32. | |
2635 | */ | |
2636 | addr = (u32) sg_dma_address(sg); | |
2637 | sg_len = sg_dma_len(sg); | |
2638 | ||
2639 | while (sg_len) { | |
2640 | offset = addr & 0xffff; | |
2641 | len = sg_len; | |
2642 | if ((offset + sg_len) > 0x10000) | |
2643 | len = 0x10000 - offset; | |
2644 | ||
2645 | blen = len & 0xffff; | |
f60d7011 | 2646 | prd[pi].addr = cpu_to_le32(addr); |
f47451c4 TH |
2647 | if (blen == 0) { |
2648 | /* Some PATA chipsets like the CS5530 can't | |
2649 | cope with 0x0000 meaning 64K as the spec | |
2650 | says */ | |
f60d7011 | 2651 | prd[pi].flags_len = cpu_to_le32(0x8000); |
f47451c4 | 2652 | blen = 0x8000; |
f60d7011 | 2653 | prd[++pi].addr = cpu_to_le32(addr + 0x8000); |
f47451c4 | 2654 | } |
f60d7011 | 2655 | prd[pi].flags_len = cpu_to_le32(blen); |
f47451c4 TH |
2656 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); |
2657 | ||
2658 | pi++; | |
2659 | sg_len -= len; | |
2660 | addr += len; | |
2661 | } | |
2662 | } | |
2663 | ||
f60d7011 | 2664 | prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); |
f47451c4 TH |
2665 | } |
2666 | ||
2667 | /** | |
2668 | * ata_bmdma_qc_prep - Prepare taskfile for submission | |
2669 | * @qc: Metadata associated with taskfile to be prepared | |
2670 | * | |
2671 | * Prepare ATA taskfile for submission. | |
2672 | * | |
2673 | * LOCKING: | |
2674 | * spin_lock_irqsave(host lock) | |
2675 | */ | |
2676 | void ata_bmdma_qc_prep(struct ata_queued_cmd *qc) | |
2677 | { | |
2678 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
2679 | return; | |
2680 | ||
2681 | ata_bmdma_fill_sg(qc); | |
2682 | } | |
2683 | EXPORT_SYMBOL_GPL(ata_bmdma_qc_prep); | |
2684 | ||
2685 | /** | |
2686 | * ata_bmdma_dumb_qc_prep - Prepare taskfile for submission | |
2687 | * @qc: Metadata associated with taskfile to be prepared | |
2688 | * | |
2689 | * Prepare ATA taskfile for submission. | |
2690 | * | |
2691 | * LOCKING: | |
2692 | * spin_lock_irqsave(host lock) | |
2693 | */ | |
2694 | void ata_bmdma_dumb_qc_prep(struct ata_queued_cmd *qc) | |
2695 | { | |
2696 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
2697 | return; | |
2698 | ||
2699 | ata_bmdma_fill_sg_dumb(qc); | |
2700 | } | |
2701 | EXPORT_SYMBOL_GPL(ata_bmdma_dumb_qc_prep); | |
2702 | ||
360ff783 TH |
2703 | /** |
2704 | * ata_bmdma_qc_issue - issue taskfile to a BMDMA controller | |
2705 | * @qc: command to issue to device | |
2706 | * | |
2707 | * This function issues a PIO, NODATA or DMA command to a | |
2708 | * SFF/BMDMA controller. PIO and NODATA are handled by | |
2709 | * ata_sff_qc_issue(). | |
2710 | * | |
2711 | * LOCKING: | |
2712 | * spin_lock_irqsave(host lock) | |
2713 | * | |
2714 | * RETURNS: | |
2715 | * Zero on success, AC_ERR_* mask on failure | |
2716 | */ | |
2717 | unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd *qc) | |
2718 | { | |
2719 | struct ata_port *ap = qc->ap; | |
ea3c6450 | 2720 | struct ata_link *link = qc->dev->link; |
360ff783 | 2721 | |
360ff783 TH |
2722 | /* defer PIO handling to sff_qc_issue */ |
2723 | if (!ata_is_dma(qc->tf.protocol)) | |
2724 | return ata_sff_qc_issue(qc); | |
2725 | ||
2726 | /* select the device */ | |
2727 | ata_dev_select(ap, qc->dev->devno, 1, 0); | |
2728 | ||
2729 | /* start the command */ | |
2730 | switch (qc->tf.protocol) { | |
2731 | case ATA_PROT_DMA: | |
2732 | WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING); | |
2733 | ||
2734 | ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ | |
2735 | ap->ops->bmdma_setup(qc); /* set up bmdma */ | |
2736 | ap->ops->bmdma_start(qc); /* initiate bmdma */ | |
2737 | ap->hsm_task_state = HSM_ST_LAST; | |
2738 | break; | |
2739 | ||
2740 | case ATAPI_PROT_DMA: | |
2741 | WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING); | |
2742 | ||
2743 | ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ | |
2744 | ap->ops->bmdma_setup(qc); /* set up bmdma */ | |
2745 | ap->hsm_task_state = HSM_ST_FIRST; | |
2746 | ||
2747 | /* send cdb by polling if no cdb interrupt */ | |
2748 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
ea3c6450 | 2749 | ata_sff_queue_pio_task(link, 0); |
360ff783 TH |
2750 | break; |
2751 | ||
2752 | default: | |
2753 | WARN_ON(1); | |
2754 | return AC_ERR_SYSTEM; | |
2755 | } | |
2756 | ||
2757 | return 0; | |
2758 | } | |
2759 | EXPORT_SYMBOL_GPL(ata_bmdma_qc_issue); | |
2760 | ||
c3b28894 TH |
2761 | /** |
2762 | * ata_bmdma_port_intr - Handle BMDMA port interrupt | |
2763 | * @ap: Port on which interrupt arrived (possibly...) | |
2764 | * @qc: Taskfile currently active in engine | |
2765 | * | |
2766 | * Handle port interrupt for given queued command. | |
2767 | * | |
2768 | * LOCKING: | |
2769 | * spin_lock_irqsave(host lock) | |
2770 | * | |
2771 | * RETURNS: | |
2772 | * One if interrupt was handled, zero if not (shared irq). | |
2773 | */ | |
2774 | unsigned int ata_bmdma_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc) | |
2775 | { | |
2776 | struct ata_eh_info *ehi = &ap->link.eh_info; | |
2777 | u8 host_stat = 0; | |
2778 | bool bmdma_stopped = false; | |
2779 | unsigned int handled; | |
2780 | ||
2781 | if (ap->hsm_task_state == HSM_ST_LAST && ata_is_dma(qc->tf.protocol)) { | |
2782 | /* check status of DMA engine */ | |
2783 | host_stat = ap->ops->bmdma_status(ap); | |
2784 | VPRINTK("ata%u: host_stat 0x%X\n", ap->print_id, host_stat); | |
2785 | ||
2786 | /* if it's not our irq... */ | |
2787 | if (!(host_stat & ATA_DMA_INTR)) | |
2788 | return ata_sff_idle_irq(ap); | |
2789 | ||
2790 | /* before we do anything else, clear DMA-Start bit */ | |
2791 | ap->ops->bmdma_stop(qc); | |
2792 | bmdma_stopped = true; | |
2793 | ||
2794 | if (unlikely(host_stat & ATA_DMA_ERR)) { | |
25985edc | 2795 | /* error when transferring data to/from memory */ |
c3b28894 TH |
2796 | qc->err_mask |= AC_ERR_HOST_BUS; |
2797 | ap->hsm_task_state = HSM_ST_ERR; | |
2798 | } | |
2799 | } | |
2800 | ||
2801 | handled = __ata_sff_port_intr(ap, qc, bmdma_stopped); | |
2802 | ||
2803 | if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol)) | |
2804 | ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat); | |
2805 | ||
2806 | return handled; | |
2807 | } | |
2808 | EXPORT_SYMBOL_GPL(ata_bmdma_port_intr); | |
2809 | ||
2810 | /** | |
2811 | * ata_bmdma_interrupt - Default BMDMA ATA host interrupt handler | |
2812 | * @irq: irq line (unused) | |
2813 | * @dev_instance: pointer to our ata_host information structure | |
2814 | * | |
2815 | * Default interrupt handler for PCI IDE devices. Calls | |
2816 | * ata_bmdma_port_intr() for each port that is not disabled. | |
2817 | * | |
2818 | * LOCKING: | |
2819 | * Obtains host lock during operation. | |
2820 | * | |
2821 | * RETURNS: | |
2822 | * IRQ_NONE or IRQ_HANDLED. | |
2823 | */ | |
2824 | irqreturn_t ata_bmdma_interrupt(int irq, void *dev_instance) | |
2825 | { | |
2826 | return __ata_sff_interrupt(irq, dev_instance, ata_bmdma_port_intr); | |
2827 | } | |
2828 | EXPORT_SYMBOL_GPL(ata_bmdma_interrupt); | |
2829 | ||
fe06e5f9 TH |
2830 | /** |
2831 | * ata_bmdma_error_handler - Stock error handler for BMDMA controller | |
2832 | * @ap: port to handle error for | |
2833 | * | |
2834 | * Stock error handler for BMDMA controller. It can handle both | |
2835 | * PATA and SATA controllers. Most BMDMA controllers should be | |
2836 | * able to use this EH as-is or with some added handling before | |
2837 | * and after. | |
2838 | * | |
2839 | * LOCKING: | |
2840 | * Kernel thread context (may sleep) | |
2841 | */ | |
2842 | void ata_bmdma_error_handler(struct ata_port *ap) | |
2843 | { | |
2844 | struct ata_queued_cmd *qc; | |
2845 | unsigned long flags; | |
2846 | bool thaw = false; | |
2847 | ||
2848 | qc = __ata_qc_from_tag(ap, ap->link.active_tag); | |
2849 | if (qc && !(qc->flags & ATA_QCFLAG_FAILED)) | |
2850 | qc = NULL; | |
2851 | ||
2852 | /* reset PIO HSM and stop DMA engine */ | |
2853 | spin_lock_irqsave(ap->lock, flags); | |
2854 | ||
2855 | if (qc && ata_is_dma(qc->tf.protocol)) { | |
2856 | u8 host_stat; | |
2857 | ||
2858 | host_stat = ap->ops->bmdma_status(ap); | |
2859 | ||
2860 | /* BMDMA controllers indicate host bus error by | |
2861 | * setting DMA_ERR bit and timing out. As it wasn't | |
2862 | * really a timeout event, adjust error mask and | |
2863 | * cancel frozen state. | |
2864 | */ | |
2865 | if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) { | |
2866 | qc->err_mask = AC_ERR_HOST_BUS; | |
2867 | thaw = true; | |
2868 | } | |
2869 | ||
2870 | ap->ops->bmdma_stop(qc); | |
2871 | ||
2872 | /* if we're gonna thaw, make sure IRQ is clear */ | |
2873 | if (thaw) { | |
2874 | ap->ops->sff_check_status(ap); | |
37f65b8b TH |
2875 | if (ap->ops->sff_irq_clear) |
2876 | ap->ops->sff_irq_clear(ap); | |
fe06e5f9 TH |
2877 | } |
2878 | } | |
2879 | ||
2880 | spin_unlock_irqrestore(ap->lock, flags); | |
2881 | ||
2882 | if (thaw) | |
2883 | ata_eh_thaw_port(ap); | |
2884 | ||
2885 | ata_sff_error_handler(ap); | |
2886 | } | |
2887 | EXPORT_SYMBOL_GPL(ata_bmdma_error_handler); | |
2888 | ||
2889 | /** | |
2890 | * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for BMDMA | |
2891 | * @qc: internal command to clean up | |
2892 | * | |
2893 | * LOCKING: | |
2894 | * Kernel thread context (may sleep) | |
2895 | */ | |
2896 | void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc) | |
2897 | { | |
2898 | struct ata_port *ap = qc->ap; | |
2899 | unsigned long flags; | |
2900 | ||
2901 | if (ata_is_dma(qc->tf.protocol)) { | |
2902 | spin_lock_irqsave(ap->lock, flags); | |
2903 | ap->ops->bmdma_stop(qc); | |
2904 | spin_unlock_irqrestore(ap->lock, flags); | |
2905 | } | |
2906 | } | |
2907 | EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd); | |
2908 | ||
37f65b8b TH |
2909 | /** |
2910 | * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt. | |
2911 | * @ap: Port associated with this ATA transaction. | |
2912 | * | |
2913 | * Clear interrupt and error flags in DMA status register. | |
2914 | * | |
2915 | * May be used as the irq_clear() entry in ata_port_operations. | |
2916 | * | |
2917 | * LOCKING: | |
2918 | * spin_lock_irqsave(host lock) | |
2919 | */ | |
2920 | void ata_bmdma_irq_clear(struct ata_port *ap) | |
2921 | { | |
2922 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
2923 | ||
2924 | if (!mmio) | |
2925 | return; | |
2926 | ||
2927 | iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS); | |
2928 | } | |
2929 | EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear); | |
2930 | ||
9f2f7210 TH |
2931 | /** |
2932 | * ata_bmdma_setup - Set up PCI IDE BMDMA transaction | |
2933 | * @qc: Info associated with this ATA transaction. | |
2934 | * | |
2935 | * LOCKING: | |
2936 | * spin_lock_irqsave(host lock) | |
2937 | */ | |
2938 | void ata_bmdma_setup(struct ata_queued_cmd *qc) | |
2939 | { | |
2940 | struct ata_port *ap = qc->ap; | |
2941 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
2942 | u8 dmactl; | |
2943 | ||
2944 | /* load PRD table addr. */ | |
2945 | mb(); /* make sure PRD table writes are visible to controller */ | |
f60d7011 | 2946 | iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); |
9f2f7210 TH |
2947 | |
2948 | /* specify data direction, triple-check start bit is clear */ | |
2949 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2950 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | |
2951 | if (!rw) | |
2952 | dmactl |= ATA_DMA_WR; | |
2953 | iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2954 | ||
2955 | /* issue r/w command */ | |
2956 | ap->ops->sff_exec_command(ap, &qc->tf); | |
2957 | } | |
2958 | EXPORT_SYMBOL_GPL(ata_bmdma_setup); | |
2959 | ||
2960 | /** | |
2961 | * ata_bmdma_start - Start a PCI IDE BMDMA transaction | |
2962 | * @qc: Info associated with this ATA transaction. | |
2963 | * | |
2964 | * LOCKING: | |
2965 | * spin_lock_irqsave(host lock) | |
2966 | */ | |
2967 | void ata_bmdma_start(struct ata_queued_cmd *qc) | |
2968 | { | |
2969 | struct ata_port *ap = qc->ap; | |
2970 | u8 dmactl; | |
2971 | ||
2972 | /* start host DMA transaction */ | |
2973 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2974 | iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2975 | ||
2976 | /* Strictly, one may wish to issue an ioread8() here, to | |
2977 | * flush the mmio write. However, control also passes | |
2978 | * to the hardware at this point, and it will interrupt | |
2979 | * us when we are to resume control. So, in effect, | |
2980 | * we don't care when the mmio write flushes. | |
2981 | * Further, a read of the DMA status register _immediately_ | |
2982 | * following the write may not be what certain flaky hardware | |
2983 | * is expected, so I think it is best to not add a readb() | |
2984 | * without first all the MMIO ATA cards/mobos. | |
2985 | * Or maybe I'm just being paranoid. | |
2986 | * | |
2987 | * FIXME: The posting of this write means I/O starts are | |
25985edc | 2988 | * unnecessarily delayed for MMIO |
9f2f7210 TH |
2989 | */ |
2990 | } | |
2991 | EXPORT_SYMBOL_GPL(ata_bmdma_start); | |
2992 | ||
2993 | /** | |
2994 | * ata_bmdma_stop - Stop PCI IDE BMDMA transfer | |
2995 | * @qc: Command we are ending DMA for | |
2996 | * | |
2997 | * Clears the ATA_DMA_START flag in the dma control register | |
2998 | * | |
2999 | * May be used as the bmdma_stop() entry in ata_port_operations. | |
3000 | * | |
3001 | * LOCKING: | |
3002 | * spin_lock_irqsave(host lock) | |
3003 | */ | |
3004 | void ata_bmdma_stop(struct ata_queued_cmd *qc) | |
3005 | { | |
3006 | struct ata_port *ap = qc->ap; | |
3007 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
3008 | ||
3009 | /* clear start/stop bit */ | |
3010 | iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, | |
3011 | mmio + ATA_DMA_CMD); | |
3012 | ||
3013 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | |
3014 | ata_sff_dma_pause(ap); | |
3015 | } | |
3016 | EXPORT_SYMBOL_GPL(ata_bmdma_stop); | |
3017 | ||
3018 | /** | |
3019 | * ata_bmdma_status - Read PCI IDE BMDMA status | |
3020 | * @ap: Port associated with this ATA transaction. | |
3021 | * | |
3022 | * Read and return BMDMA status register. | |
3023 | * | |
3024 | * May be used as the bmdma_status() entry in ata_port_operations. | |
3025 | * | |
3026 | * LOCKING: | |
3027 | * spin_lock_irqsave(host lock) | |
3028 | */ | |
3029 | u8 ata_bmdma_status(struct ata_port *ap) | |
3030 | { | |
3031 | return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); | |
3032 | } | |
3033 | EXPORT_SYMBOL_GPL(ata_bmdma_status); | |
3034 | ||
c7087652 TH |
3035 | |
3036 | /** | |
3037 | * ata_bmdma_port_start - Set port up for bmdma. | |
3038 | * @ap: Port to initialize | |
3039 | * | |
3040 | * Called just after data structures for each port are | |
3041 | * initialized. Allocates space for PRD table. | |
3042 | * | |
3043 | * May be used as the port_start() entry in ata_port_operations. | |
3044 | * | |
3045 | * LOCKING: | |
3046 | * Inherited from caller. | |
3047 | */ | |
3048 | int ata_bmdma_port_start(struct ata_port *ap) | |
3049 | { | |
3050 | if (ap->mwdma_mask || ap->udma_mask) { | |
f60d7011 TH |
3051 | ap->bmdma_prd = |
3052 | dmam_alloc_coherent(ap->host->dev, ATA_PRD_TBL_SZ, | |
3053 | &ap->bmdma_prd_dma, GFP_KERNEL); | |
3054 | if (!ap->bmdma_prd) | |
c7087652 TH |
3055 | return -ENOMEM; |
3056 | } | |
3057 | ||
3058 | return 0; | |
3059 | } | |
3060 | EXPORT_SYMBOL_GPL(ata_bmdma_port_start); | |
3061 | ||
3062 | /** | |
3063 | * ata_bmdma_port_start32 - Set port up for dma. | |
3064 | * @ap: Port to initialize | |
3065 | * | |
3066 | * Called just after data structures for each port are | |
3067 | * initialized. Enables 32bit PIO and allocates space for PRD | |
3068 | * table. | |
3069 | * | |
3070 | * May be used as the port_start() entry in ata_port_operations for | |
3071 | * devices that are capable of 32bit PIO. | |
3072 | * | |
3073 | * LOCKING: | |
3074 | * Inherited from caller. | |
3075 | */ | |
3076 | int ata_bmdma_port_start32(struct ata_port *ap) | |
3077 | { | |
3078 | ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE; | |
3079 | return ata_bmdma_port_start(ap); | |
3080 | } | |
3081 | EXPORT_SYMBOL_GPL(ata_bmdma_port_start32); | |
3082 | ||
9f2f7210 TH |
3083 | #ifdef CONFIG_PCI |
3084 | ||
3085 | /** | |
3086 | * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex | |
3087 | * @pdev: PCI device | |
3088 | * | |
3089 | * Some PCI ATA devices report simplex mode but in fact can be told to | |
3090 | * enter non simplex mode. This implements the necessary logic to | |
3091 | * perform the task on such devices. Calling it on other devices will | |
3092 | * have -undefined- behaviour. | |
3093 | */ | |
3094 | int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev) | |
3095 | { | |
3096 | unsigned long bmdma = pci_resource_start(pdev, 4); | |
3097 | u8 simplex; | |
3098 | ||
3099 | if (bmdma == 0) | |
3100 | return -ENOENT; | |
3101 | ||
3102 | simplex = inb(bmdma + 0x02); | |
3103 | outb(simplex & 0x60, bmdma + 0x02); | |
3104 | simplex = inb(bmdma + 0x02); | |
3105 | if (simplex & 0x80) | |
3106 | return -EOPNOTSUPP; | |
3107 | return 0; | |
3108 | } | |
3109 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex); | |
3110 | ||
c7087652 TH |
3111 | static void ata_bmdma_nodma(struct ata_host *host, const char *reason) |
3112 | { | |
3113 | int i; | |
3114 | ||
a44fec1f | 3115 | dev_err(host->dev, "BMDMA: %s, falling back to PIO\n", reason); |
c7087652 TH |
3116 | |
3117 | for (i = 0; i < 2; i++) { | |
3118 | host->ports[i]->mwdma_mask = 0; | |
3119 | host->ports[i]->udma_mask = 0; | |
3120 | } | |
3121 | } | |
3122 | ||
9f2f7210 TH |
3123 | /** |
3124 | * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host | |
3125 | * @host: target ATA host | |
3126 | * | |
3127 | * Acquire PCI BMDMA resources and initialize @host accordingly. | |
3128 | * | |
3129 | * LOCKING: | |
3130 | * Inherited from calling layer (may sleep). | |
9f2f7210 | 3131 | */ |
c7087652 | 3132 | void ata_pci_bmdma_init(struct ata_host *host) |
9f2f7210 TH |
3133 | { |
3134 | struct device *gdev = host->dev; | |
3135 | struct pci_dev *pdev = to_pci_dev(gdev); | |
3136 | int i, rc; | |
3137 | ||
3138 | /* No BAR4 allocation: No DMA */ | |
c7087652 TH |
3139 | if (pci_resource_start(pdev, 4) == 0) { |
3140 | ata_bmdma_nodma(host, "BAR4 is zero"); | |
3141 | return; | |
3142 | } | |
9f2f7210 | 3143 | |
c7087652 TH |
3144 | /* |
3145 | * Some controllers require BMDMA region to be initialized | |
3146 | * even if DMA is not in use to clear IRQ status via | |
3147 | * ->sff_irq_clear method. Try to initialize bmdma_addr | |
3148 | * regardless of dma masks. | |
3149 | */ | |
c54c719b | 3150 | rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK); |
9f2f7210 | 3151 | if (rc) |
c7087652 TH |
3152 | ata_bmdma_nodma(host, "failed to set dma mask"); |
3153 | if (!rc) { | |
c54c719b | 3154 | rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK); |
c7087652 TH |
3155 | if (rc) |
3156 | ata_bmdma_nodma(host, | |
3157 | "failed to set consistent dma mask"); | |
3158 | } | |
9f2f7210 TH |
3159 | |
3160 | /* request and iomap DMA region */ | |
3161 | rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev)); | |
3162 | if (rc) { | |
c7087652 TH |
3163 | ata_bmdma_nodma(host, "failed to request/iomap BAR4"); |
3164 | return; | |
9f2f7210 TH |
3165 | } |
3166 | host->iomap = pcim_iomap_table(pdev); | |
3167 | ||
3168 | for (i = 0; i < 2; i++) { | |
3169 | struct ata_port *ap = host->ports[i]; | |
3170 | void __iomem *bmdma = host->iomap[4] + 8 * i; | |
3171 | ||
3172 | if (ata_port_is_dummy(ap)) | |
3173 | continue; | |
3174 | ||
3175 | ap->ioaddr.bmdma_addr = bmdma; | |
3176 | if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) && | |
3177 | (ioread8(bmdma + 2) & 0x80)) | |
3178 | host->flags |= ATA_HOST_SIMPLEX; | |
3179 | ||
3180 | ata_port_desc(ap, "bmdma 0x%llx", | |
3181 | (unsigned long long)pci_resource_start(pdev, 4) + 8 * i); | |
3182 | } | |
9f2f7210 TH |
3183 | } |
3184 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_init); | |
3185 | ||
1c5afdf7 TH |
3186 | /** |
3187 | * ata_pci_bmdma_prepare_host - helper to prepare PCI BMDMA ATA host | |
3188 | * @pdev: target PCI device | |
3189 | * @ppi: array of port_info, must be enough for two ports | |
3190 | * @r_host: out argument for the initialized ATA host | |
3191 | * | |
3192 | * Helper to allocate BMDMA ATA host for @pdev, acquire all PCI | |
3193 | * resources and initialize it accordingly in one go. | |
3194 | * | |
3195 | * LOCKING: | |
3196 | * Inherited from calling layer (may sleep). | |
3197 | * | |
3198 | * RETURNS: | |
3199 | * 0 on success, -errno otherwise. | |
3200 | */ | |
3201 | int ata_pci_bmdma_prepare_host(struct pci_dev *pdev, | |
3202 | const struct ata_port_info * const * ppi, | |
3203 | struct ata_host **r_host) | |
3204 | { | |
3205 | int rc; | |
3206 | ||
3207 | rc = ata_pci_sff_prepare_host(pdev, ppi, r_host); | |
3208 | if (rc) | |
3209 | return rc; | |
3210 | ||
3211 | ata_pci_bmdma_init(*r_host); | |
3212 | return 0; | |
3213 | } | |
3214 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_prepare_host); | |
3215 | ||
3216 | /** | |
3217 | * ata_pci_bmdma_init_one - Initialize/register BMDMA PCI IDE controller | |
3218 | * @pdev: Controller to be initialized | |
3219 | * @ppi: array of port_info, must be enough for two ports | |
3220 | * @sht: scsi_host_template to use when registering the host | |
3221 | * @host_priv: host private_data | |
3222 | * @hflags: host flags | |
3223 | * | |
3224 | * This function is similar to ata_pci_sff_init_one() but also | |
3225 | * takes care of BMDMA initialization. | |
3226 | * | |
3227 | * LOCKING: | |
3228 | * Inherited from PCI layer (may sleep). | |
3229 | * | |
3230 | * RETURNS: | |
3231 | * Zero on success, negative on errno-based value on error. | |
3232 | */ | |
3233 | int ata_pci_bmdma_init_one(struct pci_dev *pdev, | |
3234 | const struct ata_port_info * const * ppi, | |
3235 | struct scsi_host_template *sht, void *host_priv, | |
3236 | int hflags) | |
3237 | { | |
c2036033 | 3238 | return ata_pci_init_one(pdev, ppi, sht, host_priv, hflags, 1); |
1c5afdf7 TH |
3239 | } |
3240 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_init_one); | |
3241 | ||
9f2f7210 | 3242 | #endif /* CONFIG_PCI */ |
9a7780c9 | 3243 | #endif /* CONFIG_ATA_BMDMA */ |
270390e1 TH |
3244 | |
3245 | /** | |
3246 | * ata_sff_port_init - Initialize SFF/BMDMA ATA port | |
3247 | * @ap: Port to initialize | |
3248 | * | |
3249 | * Called on port allocation to initialize SFF/BMDMA specific | |
3250 | * fields. | |
3251 | * | |
3252 | * LOCKING: | |
3253 | * None. | |
3254 | */ | |
3255 | void ata_sff_port_init(struct ata_port *ap) | |
3256 | { | |
c429137a | 3257 | INIT_DELAYED_WORK(&ap->sff_pio_task, ata_sff_pio_task); |
5fe7454a TH |
3258 | ap->ctl = ATA_DEVCTL_OBS; |
3259 | ap->last_ctl = 0xFF; | |
270390e1 TH |
3260 | } |
3261 | ||
3262 | int __init ata_sff_init(void) | |
3263 | { | |
6370a6ad | 3264 | ata_sff_wq = alloc_workqueue("ata_sff", WQ_MEM_RECLAIM, WQ_MAX_ACTIVE); |
c429137a TH |
3265 | if (!ata_sff_wq) |
3266 | return -ENOMEM; | |
3267 | ||
270390e1 TH |
3268 | return 0; |
3269 | } | |
3270 | ||
c43d559f | 3271 | void ata_sff_exit(void) |
270390e1 | 3272 | { |
c429137a | 3273 | destroy_workqueue(ata_sff_wq); |
270390e1 | 3274 | } |