projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ahci: Order SATA device IDs for codename Lewisburg
[linux-2.6-block.git] / drivers / ata / libahci.c
CommitLineData
365cfa1e
AV		 1/*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <tj@kernel.org>
365cfa1e
AV		 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
fbaf666b 36#include <linux/gfp.h>
365cfa1e 37#include <linux/module.h>
365cfa1e
AV		 38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
41#include <linux/dma-mapping.h>
42#include <linux/device.h>
43#include <scsi/scsi_host.h>
44#include <scsi/scsi_cmnd.h>
45#include <linux/libata.h>
46#include "ahci.h"
65fe1f0f 47#include "libata.h"
365cfa1e
AV		 48
49static int ahci_skip_host_reset;
50int ahci_ignore_sss;
51EXPORT_SYMBOL_GPL(ahci_ignore_sss);
52
53module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
56module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
57MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
58
6b7ae954
TH		 59static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
60 unsigned hints);
365cfa1e
AV		 61static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
62static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
63 size_t size);
64static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
65 ssize_t size);
66
67
68
69static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
70static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
365cfa1e
AV		 71static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
72static int ahci_port_start(struct ata_port *ap);
73static void ahci_port_stop(struct ata_port *ap);
74static void ahci_qc_prep(struct ata_queued_cmd *qc);
75static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
76static void ahci_freeze(struct ata_port *ap);
77static void ahci_thaw(struct ata_port *ap);
65fe1f0f 78static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
365cfa1e
AV		 79static void ahci_enable_fbs(struct ata_port *ap);
80static void ahci_disable_fbs(struct ata_port *ap);
81static void ahci_pmp_attach(struct ata_port *ap);
82static void ahci_pmp_detach(struct ata_port *ap);
83static int ahci_softreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
345347c5
YHC		 85static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
365cfa1e
AV		 87static int ahci_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89static void ahci_postreset(struct ata_link *link, unsigned int *class);
365cfa1e 90static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
365cfa1e 91static void ahci_dev_config(struct ata_device *dev);
365cfa1e
AV		 92#ifdef CONFIG_PM
93static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
94#endif
95static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
96static ssize_t ahci_activity_store(struct ata_device *dev,
97 enum sw_activity val);
98static void ahci_init_sw_activity(struct ata_link *link);
99
100static ssize_t ahci_show_host_caps(struct device *dev,
101 struct device_attribute *attr, char *buf);
102static ssize_t ahci_show_host_cap2(struct device *dev,
103 struct device_attribute *attr, char *buf);
104static ssize_t ahci_show_host_version(struct device *dev,
105 struct device_attribute *attr, char *buf);
106static ssize_t ahci_show_port_cmd(struct device *dev,
107 struct device_attribute *attr, char *buf);
c0623166
HZ		 108static ssize_t ahci_read_em_buffer(struct device *dev,
109 struct device_attribute *attr, char *buf);
110static ssize_t ahci_store_em_buffer(struct device *dev,
111 struct device_attribute *attr,
112 const char *buf, size_t size);
6e5fe5b1
HR		 113static ssize_t ahci_show_em_supported(struct device *dev,
114 struct device_attribute *attr, char *buf);
365cfa1e
AV		 115
116static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
117static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
118static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
119static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
c0623166
HZ		 120static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
121 ahci_read_em_buffer, ahci_store_em_buffer);
6e5fe5b1 122static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
365cfa1e 123
fad16e7a 124struct device_attribute *ahci_shost_attrs[] = {
365cfa1e
AV		 125 &dev_attr_link_power_management_policy,
126 &dev_attr_em_message_type,
127 &dev_attr_em_message,
128 &dev_attr_ahci_host_caps,
129 &dev_attr_ahci_host_cap2,
130 &dev_attr_ahci_host_version,
131 &dev_attr_ahci_port_cmd,
c0623166 132 &dev_attr_em_buffer,
6e5fe5b1 133 &dev_attr_em_message_supported,
365cfa1e
AV		 134 NULL
135};
fad16e7a 136EXPORT_SYMBOL_GPL(ahci_shost_attrs);
365cfa1e 137
fad16e7a 138struct device_attribute *ahci_sdev_attrs[] = {
365cfa1e
AV		 139 &dev_attr_sw_activity,
140 &dev_attr_unload_heads,
141 NULL
142};
fad16e7a 143EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
365cfa1e
AV		 144
145struct ata_port_operations ahci_ops = {
146 .inherits = &sata_pmp_port_ops,
147
148 .qc_defer = ahci_pmp_qc_defer,
149 .qc_prep = ahci_qc_prep,
150 .qc_issue = ahci_qc_issue,
151 .qc_fill_rtf = ahci_qc_fill_rtf,
152
153 .freeze = ahci_freeze,
154 .thaw = ahci_thaw,
155 .softreset = ahci_softreset,
156 .hardreset = ahci_hardreset,
157 .postreset = ahci_postreset,
158 .pmp_softreset = ahci_softreset,
159 .error_handler = ahci_error_handler,
160 .post_internal_cmd = ahci_post_internal_cmd,
161 .dev_config = ahci_dev_config,
162
163 .scr_read = ahci_scr_read,
164 .scr_write = ahci_scr_write,
165 .pmp_attach = ahci_pmp_attach,
166 .pmp_detach = ahci_pmp_detach,
167
6b7ae954 168 .set_lpm = ahci_set_lpm,
365cfa1e
AV		 169 .em_show = ahci_led_show,
170 .em_store = ahci_led_store,
171 .sw_activity_show = ahci_activity_show,
172 .sw_activity_store = ahci_activity_store,
439d7a35 173 .transmit_led_message = ahci_transmit_led_message,
365cfa1e
AV		 174#ifdef CONFIG_PM
175 .port_suspend = ahci_port_suspend,
176 .port_resume = ahci_port_resume,
177#endif
178 .port_start = ahci_port_start,
179 .port_stop = ahci_port_stop,
180};
181EXPORT_SYMBOL_GPL(ahci_ops);
182
345347c5
YHC		 183struct ata_port_operations ahci_pmp_retry_srst_ops = {
184 .inherits = &ahci_ops,
185 .softreset = ahci_pmp_retry_softreset,
186};
187EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
188
ed08d40c 189static bool ahci_em_messages __read_mostly = true;
365cfa1e 190EXPORT_SYMBOL_GPL(ahci_em_messages);
ed08d40c 191module_param(ahci_em_messages, bool, 0444);
365cfa1e
AV		 192/* add other LED protocol types when they become supported */
193MODULE_PARM_DESC(ahci_em_messages,
008dbd61 194 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
365cfa1e 195
ed08d40c
CL		 196/* device sleep idle timeout in ms */
197static int devslp_idle_timeout __read_mostly = 1000;
65fe1f0f
SH		 198module_param(devslp_idle_timeout, int, 0644);
199MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
200
365cfa1e
AV		 201static void ahci_enable_ahci(void __iomem *mmio)
202{
203 int i;
204 u32 tmp;
205
206 /* turn on AHCI_EN */
207 tmp = readl(mmio + HOST_CTL);
208 if (tmp & HOST_AHCI_EN)
209 return;
210
211 /* Some controllers need AHCI_EN to be written multiple times.
212 * Try a few times before giving up.
213 */
214 for (i = 0; i < 5; i++) {
215 tmp |= HOST_AHCI_EN;
216 writel(tmp, mmio + HOST_CTL);
217 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
218 if (tmp & HOST_AHCI_EN)
219 return;
220 msleep(10);
221 }
222
223 WARN_ON(1);
224}
225
226static ssize_t ahci_show_host_caps(struct device *dev,
227 struct device_attribute *attr, char *buf)
228{
229 struct Scsi_Host *shost = class_to_shost(dev);
230 struct ata_port *ap = ata_shost_to_port(shost);
231 struct ahci_host_priv *hpriv = ap->host->private_data;
232
233 return sprintf(buf, "%x\n", hpriv->cap);
234}
235
236static ssize_t ahci_show_host_cap2(struct device *dev,
237 struct device_attribute *attr, char *buf)
238{
239 struct Scsi_Host *shost = class_to_shost(dev);
240 struct ata_port *ap = ata_shost_to_port(shost);
241 struct ahci_host_priv *hpriv = ap->host->private_data;
242
243 return sprintf(buf, "%x\n", hpriv->cap2);
244}
245
246static ssize_t ahci_show_host_version(struct device *dev,
247 struct device_attribute *attr, char *buf)
248{
249 struct Scsi_Host *shost = class_to_shost(dev);
250 struct ata_port *ap = ata_shost_to_port(shost);
251 struct ahci_host_priv *hpriv = ap->host->private_data;
252 void __iomem *mmio = hpriv->mmio;
253
254 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
255}
256
257static ssize_t ahci_show_port_cmd(struct device *dev,
258 struct device_attribute *attr, char *buf)
259{
260 struct Scsi_Host *shost = class_to_shost(dev);
261 struct ata_port *ap = ata_shost_to_port(shost);
262 void __iomem *port_mmio = ahci_port_base(ap);
263
264 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
265}
266
c0623166
HZ		 267static ssize_t ahci_read_em_buffer(struct device *dev,
268 struct device_attribute *attr, char *buf)
269{
270 struct Scsi_Host *shost = class_to_shost(dev);
271 struct ata_port *ap = ata_shost_to_port(shost);
272 struct ahci_host_priv *hpriv = ap->host->private_data;
273 void __iomem *mmio = hpriv->mmio;
274 void __iomem *em_mmio = mmio + hpriv->em_loc;
275 u32 em_ctl, msg;
276 unsigned long flags;
277 size_t count;
278 int i;
279
280 spin_lock_irqsave(ap->lock, flags);
281
282 em_ctl = readl(mmio + HOST_EM_CTL);
283 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
284 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
285 spin_unlock_irqrestore(ap->lock, flags);
286 return -EINVAL;
287 }
288
289 if (!(em_ctl & EM_CTL_MR)) {
290 spin_unlock_irqrestore(ap->lock, flags);
291 return -EAGAIN;
292 }
293
294 if (!(em_ctl & EM_CTL_SMB))
295 em_mmio += hpriv->em_buf_sz;
296
297 count = hpriv->em_buf_sz;
298
299 /* the count should not be larger than PAGE_SIZE */
300 if (count > PAGE_SIZE) {
301 if (printk_ratelimit())
a9a79dfe
JP		 302 ata_port_warn(ap,
303 "EM read buffer size too large: "
304 "buffer size %u, page size %lu\n",
305 hpriv->em_buf_sz, PAGE_SIZE);
c0623166
HZ		 306 count = PAGE_SIZE;
307 }
308
309 for (i = 0; i < count; i += 4) {
310 msg = readl(em_mmio + i);
311 buf[i] = msg & 0xff;
312 buf[i + 1] = (msg >> 8) & 0xff;
313 buf[i + 2] = (msg >> 16) & 0xff;
314 buf[i + 3] = (msg >> 24) & 0xff;
315 }
316
317 spin_unlock_irqrestore(ap->lock, flags);
318
319 return i;
320}
321
322static ssize_t ahci_store_em_buffer(struct device *dev,
323 struct device_attribute *attr,
324 const char *buf, size_t size)
325{
326 struct Scsi_Host *shost = class_to_shost(dev);
327 struct ata_port *ap = ata_shost_to_port(shost);
328 struct ahci_host_priv *hpriv = ap->host->private_data;
329 void __iomem *mmio = hpriv->mmio;
330 void __iomem *em_mmio = mmio + hpriv->em_loc;
f9ce889b 331 const unsigned char *msg_buf = buf;
c0623166
HZ		 332 u32 em_ctl, msg;
333 unsigned long flags;
334 int i;
335
336 /* check size validity */
337 if (!(ap->flags & ATA_FLAG_EM) ||
338 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
339 size % 4 || size > hpriv->em_buf_sz)
340 return -EINVAL;
341
342 spin_lock_irqsave(ap->lock, flags);
343
344 em_ctl = readl(mmio + HOST_EM_CTL);
345 if (em_ctl & EM_CTL_TM) {
346 spin_unlock_irqrestore(ap->lock, flags);
347 return -EBUSY;
348 }
349
350 for (i = 0; i < size; i += 4) {
f9ce889b
HZ		 351 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
352 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
c0623166
HZ		 353 writel(msg, em_mmio + i);
354 }
355
356 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
357
358 spin_unlock_irqrestore(ap->lock, flags);
359
360 return size;
361}
362
6e5fe5b1
HR		 363static ssize_t ahci_show_em_supported(struct device *dev,
364 struct device_attribute *attr, char *buf)
365{
366 struct Scsi_Host *shost = class_to_shost(dev);
367 struct ata_port *ap = ata_shost_to_port(shost);
368 struct ahci_host_priv *hpriv = ap->host->private_data;
369 void __iomem *mmio = hpriv->mmio;
370 u32 em_ctl;
371
372 em_ctl = readl(mmio + HOST_EM_CTL);
373
374 return sprintf(buf, "%s%s%s%s\n",
375 em_ctl & EM_CTL_LED ? "led " : "",
376 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
377 em_ctl & EM_CTL_SES ? "ses-2 " : "",
378 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
379}
380
365cfa1e
AV		 381/**
382 * ahci_save_initial_config - Save and fixup initial config values
383 * @dev: target AHCI device
384 * @hpriv: host private area to store config values
365cfa1e
AV		 385 *
386 * Some registers containing configuration info might be setup by
387 * BIOS and might be cleared on reset. This function saves the
388 * initial values of those registers into @hpriv such that they
389 * can be restored after controller reset.
390 *
391 * If inconsistent, config values are fixed up by this function.
392 *
039ece38
HG		 393 * If it is not set already this function sets hpriv->start_engine to
394 * ahci_start_engine.
395 *
365cfa1e
AV		 396 * LOCKING:
397 * None.
398 */
725c7b57 399void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
365cfa1e
AV		 400{
401 void __iomem *mmio = hpriv->mmio;
402 u32 cap, cap2, vers, port_map;
403 int i;
404
405 /* make sure AHCI mode is enabled before accessing CAP */
406 ahci_enable_ahci(mmio);
407
408 /* Values prefixed with saved_ are written back to host after
409 * reset. Values without are used for driver operation.
410 */
411 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
412 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
413
414 /* CAP2 register is only defined for AHCI 1.2 and later */
415 vers = readl(mmio + HOST_VERSION);
416 if ((vers >> 16) > 1 ||
417 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
418 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
419 else
420 hpriv->saved_cap2 = cap2 = 0;
421
422 /* some chips have errata preventing 64bit use */
423 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
a44fec1f 424 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
365cfa1e
AV		 425 cap &= ~HOST_CAP_64;
426 }
427
428 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
a44fec1f 429 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
365cfa1e
AV		 430 cap &= ~HOST_CAP_NCQ;
431 }
432
433 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
a44fec1f 434 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
365cfa1e
AV		 435 cap |= HOST_CAP_NCQ;
436 }
437
438 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
a44fec1f 439 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
365cfa1e
AV		 440 cap &= ~HOST_CAP_PMP;
441 }
442
443 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
a44fec1f
JP		 444 dev_info(dev,
445 "controller can't do SNTF, turning off CAP_SNTF\n");
365cfa1e
AV		 446 cap &= ~HOST_CAP_SNTF;
447 }
448
0cf4a7d6
JP		 449 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
450 dev_info(dev,
451 "controller can't do DEVSLP, turning off\n");
452 cap2 &= ~HOST_CAP2_SDS;
453 cap2 &= ~HOST_CAP2_SADM;
454 }
455
5f173107 456 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
a44fec1f 457 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
5f173107
TH		 458 cap |= HOST_CAP_FBS;
459 }
460
888d91a0
KW		 461 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
462 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
463 cap &= ~HOST_CAP_FBS;
464 }
465
725c7b57 466 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
a44fec1f 467 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
725c7b57
AT		 468 port_map, hpriv->force_port_map);
469 port_map = hpriv->force_port_map;
365cfa1e
AV		 470 }
471
725c7b57 472 if (hpriv->mask_port_map) {
a44fec1f
JP		 473 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
474 port_map,
725c7b57
AT		 475 port_map & hpriv->mask_port_map);
476 port_map &= hpriv->mask_port_map;
365cfa1e
AV		 477 }
478
479 /* cross check port_map and cap.n_ports */
480 if (port_map) {
481 int map_ports = 0;
482
483 for (i = 0; i < AHCI_MAX_PORTS; i++)
484 if (port_map & (1 << i))
485 map_ports++;
486
487 /* If PI has more ports than n_ports, whine, clear
488 * port_map and let it be generated from n_ports.
489 */
490 if (map_ports > ahci_nr_ports(cap)) {
a44fec1f
JP		 491 dev_warn(dev,
492 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
493 port_map, ahci_nr_ports(cap));
365cfa1e
AV		 494 port_map = 0;
495 }
496 }
497
498 /* fabricate port_map from cap.nr_ports */
499 if (!port_map) {
500 port_map = (1 << ahci_nr_ports(cap)) - 1;
a44fec1f 501 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
365cfa1e
AV		 502
503 /* write the fixed up value to the PI register */
504 hpriv->saved_port_map = port_map;
505 }
506
507 /* record values to use during operation */
508 hpriv->cap = cap;
509 hpriv->cap2 = cap2;
510 hpriv->port_map = port_map;
039ece38
HG		 511
512 if (!hpriv->start_engine)
513 hpriv->start_engine = ahci_start_engine;
365cfa1e
AV		 514}
515EXPORT_SYMBOL_GPL(ahci_save_initial_config);
516
517/**
518 * ahci_restore_initial_config - Restore initial config
519 * @host: target ATA host
520 *
521 * Restore initial config stored by ahci_save_initial_config().
522 *
523 * LOCKING:
524 * None.
525 */
526static void ahci_restore_initial_config(struct ata_host *host)
527{
528 struct ahci_host_priv *hpriv = host->private_data;
529 void __iomem *mmio = hpriv->mmio;
530
531 writel(hpriv->saved_cap, mmio + HOST_CAP);
532 if (hpriv->saved_cap2)
533 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
534 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
535 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
536}
537
538static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
539{
540 static const int offset[] = {
541 [SCR_STATUS] = PORT_SCR_STAT,
542 [SCR_CONTROL] = PORT_SCR_CTL,
543 [SCR_ERROR] = PORT_SCR_ERR,
544 [SCR_ACTIVE] = PORT_SCR_ACT,
545 [SCR_NOTIFICATION] = PORT_SCR_NTF,
546 };
547 struct ahci_host_priv *hpriv = ap->host->private_data;
548
549 if (sc_reg < ARRAY_SIZE(offset) &&
550 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
551 return offset[sc_reg];
552 return 0;
553}
554
555static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
556{
557 void __iomem *port_mmio = ahci_port_base(link->ap);
558 int offset = ahci_scr_offset(link->ap, sc_reg);
559
560 if (offset) {
561 *val = readl(port_mmio + offset);
562 return 0;
563 }
564 return -EINVAL;
565}
566
567static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
568{
569 void __iomem *port_mmio = ahci_port_base(link->ap);
570 int offset = ahci_scr_offset(link->ap, sc_reg);
571
572 if (offset) {
573 writel(val, port_mmio + offset);
574 return 0;
575 }
576 return -EINVAL;
577}
578
579void ahci_start_engine(struct ata_port *ap)
580{
581 void __iomem *port_mmio = ahci_port_base(ap);
582 u32 tmp;
583
584 /* start DMA */
585 tmp = readl(port_mmio + PORT_CMD);
586 tmp |= PORT_CMD_START;
587 writel(tmp, port_mmio + PORT_CMD);
588 readl(port_mmio + PORT_CMD); /* flush */
589}
590EXPORT_SYMBOL_GPL(ahci_start_engine);
591
592int ahci_stop_engine(struct ata_port *ap)
593{
594 void __iomem *port_mmio = ahci_port_base(ap);
595 u32 tmp;
596
597 tmp = readl(port_mmio + PORT_CMD);
598
599 /* check if the HBA is idle */
600 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
601 return 0;
602
603 /* setting HBA to idle */
604 tmp &= ~PORT_CMD_START;
605 writel(tmp, port_mmio + PORT_CMD);
606
607 /* wait for engine to stop. This could be as long as 500 msec */
97750ceb 608 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 609 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
610 if (tmp & PORT_CMD_LIST_ON)
611 return -EIO;
612
613 return 0;
614}
615EXPORT_SYMBOL_GPL(ahci_stop_engine);
616
39e0ee99 617void ahci_start_fis_rx(struct ata_port *ap)
365cfa1e
AV		 618{
619 void __iomem *port_mmio = ahci_port_base(ap);
620 struct ahci_host_priv *hpriv = ap->host->private_data;
621 struct ahci_port_priv *pp = ap->private_data;
622 u32 tmp;
623
624 /* set FIS registers */
625 if (hpriv->cap & HOST_CAP_64)
626 writel((pp->cmd_slot_dma >> 16) >> 16,
627 port_mmio + PORT_LST_ADDR_HI);
628 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
629
630 if (hpriv->cap & HOST_CAP_64)
631 writel((pp->rx_fis_dma >> 16) >> 16,
632 port_mmio + PORT_FIS_ADDR_HI);
633 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
634
635 /* enable FIS reception */
636 tmp = readl(port_mmio + PORT_CMD);
637 tmp |= PORT_CMD_FIS_RX;
638 writel(tmp, port_mmio + PORT_CMD);
639
640 /* flush */
641 readl(port_mmio + PORT_CMD);
642}
39e0ee99 643EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
365cfa1e
AV		 644
645static int ahci_stop_fis_rx(struct ata_port *ap)
646{
647 void __iomem *port_mmio = ahci_port_base(ap);
648 u32 tmp;
649
650 /* disable FIS reception */
651 tmp = readl(port_mmio + PORT_CMD);
652 tmp &= ~PORT_CMD_FIS_RX;
653 writel(tmp, port_mmio + PORT_CMD);
654
655 /* wait for completion, spec says 500ms, give it 1000 */
97750ceb 656 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
365cfa1e
AV		 657 PORT_CMD_FIS_ON, 10, 1000);
658 if (tmp & PORT_CMD_FIS_ON)
659 return -EBUSY;
660
661 return 0;
662}
663
664static void ahci_power_up(struct ata_port *ap)
665{
666 struct ahci_host_priv *hpriv = ap->host->private_data;
667 void __iomem *port_mmio = ahci_port_base(ap);
668 u32 cmd;
669
670 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
671
672 /* spin up device */
673 if (hpriv->cap & HOST_CAP_SSS) {
674 cmd |= PORT_CMD_SPIN_UP;
675 writel(cmd, port_mmio + PORT_CMD);
676 }
677
678 /* wake up link */
679 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
680}
681
6b7ae954
TH		 682static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
683 unsigned int hints)
365cfa1e 684{
6b7ae954 685 struct ata_port *ap = link->ap;
365cfa1e 686 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 687 struct ahci_port_priv *pp = ap->private_data;
365cfa1e 688 void __iomem *port_mmio = ahci_port_base(ap);
365cfa1e 689
6b7ae954 690 if (policy != ATA_LPM_MAX_POWER) {
365cfa1e 691 /*
6b7ae954
TH		 692 * Disable interrupts on Phy Ready. This keeps us from
693 * getting woken up due to spurious phy ready
694 * interrupts.
365cfa1e 695 */
6b7ae954
TH		 696 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
697 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
698
699 sata_link_scr_lpm(link, policy, false);
365cfa1e
AV		 700 }
701
6b7ae954
TH		 702 if (hpriv->cap & HOST_CAP_ALPM) {
703 u32 cmd = readl(port_mmio + PORT_CMD);
365cfa1e 704
6b7ae954
TH		 705 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
706 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
707 cmd |= PORT_CMD_ICC_ACTIVE;
365cfa1e 708
6b7ae954
TH		 709 writel(cmd, port_mmio + PORT_CMD);
710 readl(port_mmio + PORT_CMD);
365cfa1e 711
6b7ae954 712 /* wait 10ms to be sure we've come out of LPM state */
97750ceb 713 ata_msleep(ap, 10);
6b7ae954
TH		 714 } else {
715 cmd |= PORT_CMD_ALPE;
716 if (policy == ATA_LPM_MIN_POWER)
717 cmd |= PORT_CMD_ASP;
365cfa1e 718
6b7ae954
TH		 719 /* write out new cmd value */
720 writel(cmd, port_mmio + PORT_CMD);
721 }
722 }
365cfa1e 723
65fe1f0f
SH		 724 /* set aggressive device sleep */
725 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
726 (hpriv->cap2 & HOST_CAP2_SADM) &&
727 (link->device->flags & ATA_DFLAG_DEVSLP)) {
728 if (policy == ATA_LPM_MIN_POWER)
729 ahci_set_aggressive_devslp(ap, true);
730 else
731 ahci_set_aggressive_devslp(ap, false);
732 }
733
6b7ae954
TH		 734 if (policy == ATA_LPM_MAX_POWER) {
735 sata_link_scr_lpm(link, policy, false);
736
737 /* turn PHYRDY IRQ back on */
738 pp->intr_mask |= PORT_IRQ_PHYRDY;
739 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
740 }
365cfa1e 741
365cfa1e
AV		 742 return 0;
743}
744
745#ifdef CONFIG_PM
746static void ahci_power_down(struct ata_port *ap)
747{
748 struct ahci_host_priv *hpriv = ap->host->private_data;
749 void __iomem *port_mmio = ahci_port_base(ap);
750 u32 cmd, scontrol;
751
752 if (!(hpriv->cap & HOST_CAP_SSS))
753 return;
754
755 /* put device into listen mode, first set PxSCTL.DET to 0 */
756 scontrol = readl(port_mmio + PORT_SCR_CTL);
757 scontrol &= ~0xf;
758 writel(scontrol, port_mmio + PORT_SCR_CTL);
759
760 /* then set PxCMD.SUD to 0 */
761 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
762 cmd &= ~PORT_CMD_SPIN_UP;
763 writel(cmd, port_mmio + PORT_CMD);
764}
765#endif
766
767static void ahci_start_port(struct ata_port *ap)
768{
66583c9f 769 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 770 struct ahci_port_priv *pp = ap->private_data;
771 struct ata_link *link;
772 struct ahci_em_priv *emp;
773 ssize_t rc;
774 int i;
775
776 /* enable FIS reception */
777 ahci_start_fis_rx(ap);
778
66583c9f
BN		 779 /* enable DMA */
780 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
039ece38 781 hpriv->start_engine(ap);
66583c9f 782
365cfa1e
AV		 783 /* turn on LEDs */
784 if (ap->flags & ATA_FLAG_EM) {
785 ata_for_each_link(link, ap, EDGE) {
786 emp = &pp->em_priv[link->pmp];
787
788 /* EM Transmit bit maybe busy during init */
789 for (i = 0; i < EM_MAX_RETRY; i++) {
439d7a35 790 rc = ap->ops->transmit_led_message(ap,
365cfa1e
AV		 791 emp->led_state,
792 4);
fa070ee6
LD		 793 /*
794 * If busy, give a breather but do not
795 * release EH ownership by using msleep()
796 * instead of ata_msleep(). EM Transmit
797 * bit is busy for the whole host and
798 * releasing ownership will cause other
799 * ports to fail the same way.
800 */
365cfa1e 801 if (rc == -EBUSY)
fa070ee6 802 msleep(1);
365cfa1e
AV		 803 else
804 break;
805 }
806 }
807 }
808
809 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
810 ata_for_each_link(link, ap, EDGE)
811 ahci_init_sw_activity(link);
812
813}
814
815static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
816{
817 int rc;
818
819 /* disable DMA */
820 rc = ahci_stop_engine(ap);
821 if (rc) {
822 *emsg = "failed to stop engine";
823 return rc;
824 }
825
826 /* disable FIS reception */
827 rc = ahci_stop_fis_rx(ap);
828 if (rc) {
829 *emsg = "failed stop FIS RX";
830 return rc;
831 }
832
833 return 0;
834}
835
836int ahci_reset_controller(struct ata_host *host)
837{
838 struct ahci_host_priv *hpriv = host->private_data;
839 void __iomem *mmio = hpriv->mmio;
840 u32 tmp;
841
842 /* we must be in AHCI mode, before using anything
843 * AHCI-specific, such as HOST_RESET.
844 */
845 ahci_enable_ahci(mmio);
846
847 /* global controller reset */
848 if (!ahci_skip_host_reset) {
849 tmp = readl(mmio + HOST_CTL);
850 if ((tmp & HOST_RESET) == 0) {
851 writel(tmp | HOST_RESET, mmio + HOST_CTL);
852 readl(mmio + HOST_CTL); /* flush */
853 }
854
855 /*
856 * to perform host reset, OS should set HOST_RESET
857 * and poll until this bit is read to be "0".
858 * reset must complete within 1 second, or
859 * the hardware should be considered fried.
860 */
97750ceb 861 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
365cfa1e
AV		 862 HOST_RESET, 10, 1000);
863
864 if (tmp & HOST_RESET) {
a44fec1f
JP		 865 dev_err(host->dev, "controller reset failed (0x%x)\n",
866 tmp);
365cfa1e
AV		 867 return -EIO;
868 }
869
870 /* turn on AHCI mode */
871 ahci_enable_ahci(mmio);
872
873 /* Some registers might be cleared on reset. Restore
874 * initial values.
875 */
876 ahci_restore_initial_config(host);
877 } else
a44fec1f 878 dev_info(host->dev, "skipping global host reset\n");
365cfa1e
AV		 879
880 return 0;
881}
882EXPORT_SYMBOL_GPL(ahci_reset_controller);
883
884static void ahci_sw_activity(struct ata_link *link)
885{
886 struct ata_port *ap = link->ap;
887 struct ahci_port_priv *pp = ap->private_data;
888 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
889
890 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
891 return;
892
893 emp->activity++;
894 if (!timer_pending(&emp->timer))
895 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
896}
897
898static void ahci_sw_activity_blink(unsigned long arg)
899{
900 struct ata_link *link = (struct ata_link *)arg;
901 struct ata_port *ap = link->ap;
902 struct ahci_port_priv *pp = ap->private_data;
903 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
904 unsigned long led_message = emp->led_state;
905 u32 activity_led_state;
906 unsigned long flags;
907
908 led_message &= EM_MSG_LED_VALUE;
909 led_message |= ap->port_no | (link->pmp << 8);
910
911 /* check to see if we've had activity. If so,
912 * toggle state of LED and reset timer. If not,
913 * turn LED to desired idle state.
914 */
915 spin_lock_irqsave(ap->lock, flags);
916 if (emp->saved_activity != emp->activity) {
917 emp->saved_activity = emp->activity;
918 /* get the current LED state */
919 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
920
921 if (activity_led_state)
922 activity_led_state = 0;
923 else
924 activity_led_state = 1;
925
926 /* clear old state */
927 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
928
929 /* toggle state */
930 led_message |= (activity_led_state << 16);
931 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
932 } else {
933 /* switch to idle */
934 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
935 if (emp->blink_policy == BLINK_OFF)
936 led_message |= (1 << 16);
937 }
938 spin_unlock_irqrestore(ap->lock, flags);
439d7a35 939 ap->ops->transmit_led_message(ap, led_message, 4);
365cfa1e
AV		 940}
941
942static void ahci_init_sw_activity(struct ata_link *link)
943{
944 struct ata_port *ap = link->ap;
945 struct ahci_port_priv *pp = ap->private_data;
946 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
947
948 /* init activity stats, setup timer */
949 emp->saved_activity = emp->activity = 0;
950 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
951
952 /* check our blink policy and set flag for link if it's enabled */
953 if (emp->blink_policy)
954 link->flags |= ATA_LFLAG_SW_ACTIVITY;
955}
956
957int ahci_reset_em(struct ata_host *host)
958{
959 struct ahci_host_priv *hpriv = host->private_data;
960 void __iomem *mmio = hpriv->mmio;
961 u32 em_ctl;
962
963 em_ctl = readl(mmio + HOST_EM_CTL);
964 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
965 return -EINVAL;
966
967 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
968 return 0;
969}
970EXPORT_SYMBOL_GPL(ahci_reset_em);
971
972static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
973 ssize_t size)
974{
975 struct ahci_host_priv *hpriv = ap->host->private_data;
976 struct ahci_port_priv *pp = ap->private_data;
977 void __iomem *mmio = hpriv->mmio;
978 u32 em_ctl;
979 u32 message[] = {0, 0};
980 unsigned long flags;
981 int pmp;
982 struct ahci_em_priv *emp;
983
984 /* get the slot number from the message */
985 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
986 if (pmp < EM_MAX_SLOTS)
987 emp = &pp->em_priv[pmp];
988 else
989 return -EINVAL;
990
991 spin_lock_irqsave(ap->lock, flags);
992
993 /*
994 * if we are still busy transmitting a previous message,
995 * do not allow
996 */
997 em_ctl = readl(mmio + HOST_EM_CTL);
998 if (em_ctl & EM_CTL_TM) {
999 spin_unlock_irqrestore(ap->lock, flags);
1000 return -EBUSY;
1001 }
1002
008dbd61
HZ		 1003 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1004 /*
1005 * create message header - this is all zero except for
1006 * the message size, which is 4 bytes.
1007 */
1008 message[0] |= (4 << 8);
365cfa1e 1009
008dbd61
HZ		 1010 /* ignore 0:4 of byte zero, fill in port info yourself */
1011 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
365cfa1e 1012
008dbd61
HZ		 1013 /* write message to EM_LOC */
1014 writel(message[0], mmio + hpriv->em_loc);
1015 writel(message[1], mmio + hpriv->em_loc+4);
1016
1017 /*
1018 * tell hardware to transmit the message
1019 */
1020 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1021 }
365cfa1e
AV		 1022
1023 /* save off new led state for port/slot */
1024 emp->led_state = state;
1025
365cfa1e
AV		 1026 spin_unlock_irqrestore(ap->lock, flags);
1027 return size;
1028}
1029
1030static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1031{
1032 struct ahci_port_priv *pp = ap->private_data;
1033 struct ata_link *link;
1034 struct ahci_em_priv *emp;
1035 int rc = 0;
1036
1037 ata_for_each_link(link, ap, EDGE) {
1038 emp = &pp->em_priv[link->pmp];
1039 rc += sprintf(buf, "%lx\n", emp->led_state);
1040 }
1041 return rc;
1042}
1043
1044static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1045 size_t size)
1046{
b2a52b6a 1047 unsigned int state;
365cfa1e
AV		 1048 int pmp;
1049 struct ahci_port_priv *pp = ap->private_data;
1050 struct ahci_em_priv *emp;
1051
b2a52b6a
DY		 1052 if (kstrtouint(buf, 0, &state) < 0)
1053 return -EINVAL;
365cfa1e
AV		 1054
1055 /* get the slot number from the message */
1056 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1057 if (pmp < EM_MAX_SLOTS)
1058 emp = &pp->em_priv[pmp];
1059 else
1060 return -EINVAL;
1061
1062 /* mask off the activity bits if we are in sw_activity
1063 * mode, user should turn off sw_activity before setting
1064 * activity led through em_message
1065 */
1066 if (emp->blink_policy)
1067 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1068
439d7a35 1069 return ap->ops->transmit_led_message(ap, state, size);
365cfa1e
AV		 1070}
1071
1072static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1073{
1074 struct ata_link *link = dev->link;
1075 struct ata_port *ap = link->ap;
1076 struct ahci_port_priv *pp = ap->private_data;
1077 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1078 u32 port_led_state = emp->led_state;
1079
1080 /* save the desired Activity LED behavior */
1081 if (val == OFF) {
1082 /* clear LFLAG */
1083 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1084
1085 /* set the LED to OFF */
1086 port_led_state &= EM_MSG_LED_VALUE_OFF;
1087 port_led_state |= (ap->port_no | (link->pmp << 8));
439d7a35 1088 ap->ops->transmit_led_message(ap, port_led_state, 4);
365cfa1e
AV		 1089 } else {
1090 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1091 if (val == BLINK_OFF) {
1092 /* set LED to ON for idle */
1093 port_led_state &= EM_MSG_LED_VALUE_OFF;
1094 port_led_state |= (ap->port_no | (link->pmp << 8));
1095 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
439d7a35 1096 ap->ops->transmit_led_message(ap, port_led_state, 4);
365cfa1e
AV		 1097 }
1098 }
1099 emp->blink_policy = val;
1100 return 0;
1101}
1102
1103static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1104{
1105 struct ata_link *link = dev->link;
1106 struct ata_port *ap = link->ap;
1107 struct ahci_port_priv *pp = ap->private_data;
1108 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1109
1110 /* display the saved value of activity behavior for this
1111 * disk.
1112 */
1113 return sprintf(buf, "%d\n", emp->blink_policy);
1114}
1115
1116static void ahci_port_init(struct device *dev, struct ata_port *ap,
1117 int port_no, void __iomem *mmio,
1118 void __iomem *port_mmio)
1119{
8a3e33cf 1120 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 1121 const char *emsg = NULL;
1122 int rc;
1123 u32 tmp;
1124
1125 /* make sure port is not active */
1126 rc = ahci_deinit_port(ap, &emsg);
1127 if (rc)
1128 dev_warn(dev, "%s (%d)\n", emsg, rc);
1129
1130 /* clear SError */
1131 tmp = readl(port_mmio + PORT_SCR_ERR);
1132 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1133 writel(tmp, port_mmio + PORT_SCR_ERR);
1134
1135 /* clear port IRQ */
1136 tmp = readl(port_mmio + PORT_IRQ_STAT);
1137 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1138 if (tmp)
1139 writel(tmp, port_mmio + PORT_IRQ_STAT);
1140
1141 writel(1 << port_no, mmio + HOST_IRQ_STAT);
8a3e33cf
ML		 1142
1143 /* mark esata ports */
1144 tmp = readl(port_mmio + PORT_CMD);
1145 if ((tmp & PORT_CMD_HPCP) ||
1146 ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)))
1147 ap->pflags |= ATA_PFLAG_EXTERNAL;
365cfa1e
AV		 1148}
1149
1150void ahci_init_controller(struct ata_host *host)
1151{
1152 struct ahci_host_priv *hpriv = host->private_data;
1153 void __iomem *mmio = hpriv->mmio;
1154 int i;
1155 void __iomem *port_mmio;
1156 u32 tmp;
1157
1158 for (i = 0; i < host->n_ports; i++) {
1159 struct ata_port *ap = host->ports[i];
1160
1161 port_mmio = ahci_port_base(ap);
1162 if (ata_port_is_dummy(ap))
1163 continue;
1164
1165 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1166 }
1167
1168 tmp = readl(mmio + HOST_CTL);
1169 VPRINTK("HOST_CTL 0x%x\n", tmp);
1170 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1171 tmp = readl(mmio + HOST_CTL);
1172 VPRINTK("HOST_CTL 0x%x\n", tmp);
1173}
1174EXPORT_SYMBOL_GPL(ahci_init_controller);
1175
1176static void ahci_dev_config(struct ata_device *dev)
1177{
1178 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1179
1180 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1181 dev->max_sectors = 255;
a9a79dfe
JP		 1182 ata_dev_info(dev,
1183 "SB600 AHCI: limiting to 255 sectors per cmd\n");
365cfa1e
AV		 1184 }
1185}
1186
bbb4ab43 1187unsigned int ahci_dev_classify(struct ata_port *ap)
365cfa1e
AV		 1188{
1189 void __iomem *port_mmio = ahci_port_base(ap);
1190 struct ata_taskfile tf;
1191 u32 tmp;
1192
1193 tmp = readl(port_mmio + PORT_SIG);
1194 tf.lbah = (tmp >> 24) & 0xff;
1195 tf.lbam = (tmp >> 16) & 0xff;
1196 tf.lbal = (tmp >> 8) & 0xff;
1197 tf.nsect = (tmp) & 0xff;
1198
1199 return ata_dev_classify(&tf);
1200}
bbb4ab43 1201EXPORT_SYMBOL_GPL(ahci_dev_classify);
365cfa1e 1202
02cdfcf0
DM		 1203void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1204 u32 opts)
365cfa1e
AV		 1205{
1206 dma_addr_t cmd_tbl_dma;
1207
1208 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1209
1210 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1211 pp->cmd_slot[tag].status = 0;
1212 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1213 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1214}
02cdfcf0 1215EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
365cfa1e
AV		 1216
1217int ahci_kick_engine(struct ata_port *ap)
1218{
1219 void __iomem *port_mmio = ahci_port_base(ap);
1220 struct ahci_host_priv *hpriv = ap->host->private_data;
1221 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1222 u32 tmp;
1223 int busy, rc;
1224
1225 /* stop engine */
1226 rc = ahci_stop_engine(ap);
1227 if (rc)
1228 goto out_restart;
1229
1230 /* need to do CLO?
1231 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1232 */
1233 busy = status & (ATA_BUSY | ATA_DRQ);
1234 if (!busy && !sata_pmp_attached(ap)) {
1235 rc = 0;
1236 goto out_restart;
1237 }
1238
1239 if (!(hpriv->cap & HOST_CAP_CLO)) {
1240 rc = -EOPNOTSUPP;
1241 goto out_restart;
1242 }
1243
1244 /* perform CLO */
1245 tmp = readl(port_mmio + PORT_CMD);
1246 tmp |= PORT_CMD_CLO;
1247 writel(tmp, port_mmio + PORT_CMD);
1248
1249 rc = 0;
97750ceb 1250 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 1251 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1252 if (tmp & PORT_CMD_CLO)
1253 rc = -EIO;
1254
1255 /* restart engine */
1256 out_restart:
039ece38 1257 hpriv->start_engine(ap);
365cfa1e
AV		 1258 return rc;
1259}
1260EXPORT_SYMBOL_GPL(ahci_kick_engine);
1261
1262static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1263 struct ata_taskfile *tf, int is_cmd, u16 flags,
1264 unsigned long timeout_msec)
1265{
1266 const u32 cmd_fis_len = 5; /* five dwords */
1267 struct ahci_port_priv *pp = ap->private_data;
1268 void __iomem *port_mmio = ahci_port_base(ap);
1269 u8 *fis = pp->cmd_tbl;
1270 u32 tmp;
1271
1272 /* prep the command */
1273 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1274 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1275
1276 /* issue & wait */
1277 writel(1, port_mmio + PORT_CMD_ISSUE);
1278
1279 if (timeout_msec) {
97750ceb
TH		 1280 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1281 0x1, 0x1, 1, timeout_msec);
365cfa1e
AV		 1282 if (tmp & 0x1) {
1283 ahci_kick_engine(ap);
1284 return -EBUSY;
1285 }
1286 } else
1287 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1288
1289 return 0;
1290}
1291
1292int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1293 int pmp, unsigned long deadline,
1294 int (*check_ready)(struct ata_link *link))
1295{
1296 struct ata_port *ap = link->ap;
1297 struct ahci_host_priv *hpriv = ap->host->private_data;
89dafa20 1298 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 1299 const char *reason = NULL;
1300 unsigned long now, msecs;
1301 struct ata_taskfile tf;
89dafa20 1302 bool fbs_disabled = false;
365cfa1e
AV		 1303 int rc;
1304
1305 DPRINTK("ENTER\n");
1306
1307 /* prepare for SRST (AHCI-1.1 10.4.1) */
1308 rc = ahci_kick_engine(ap);
1309 if (rc && rc != -EOPNOTSUPP)
a9a79dfe 1310 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
365cfa1e 1311
89dafa20 1312 /*
1313 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1314 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1315 * that is attached to port multiplier.
1316 */
1317 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1318 ahci_disable_fbs(ap);
1319 fbs_disabled = true;
1320 }
1321
365cfa1e
AV		 1322 ata_tf_init(link->device, &tf);
1323
1324 /* issue the first D2H Register FIS */
1325 msecs = 0;
1326 now = jiffies;
f1f5a807 1327 if (time_after(deadline, now))
365cfa1e
AV		 1328 msecs = jiffies_to_msecs(deadline - now);
1329
1330 tf.ctl |= ATA_SRST;
1331 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1332 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1333 rc = -EIO;
1334 reason = "1st FIS failed";
1335 goto fail;
1336 }
1337
1338 /* spec says at least 5us, but be generous and sleep for 1ms */
97750ceb 1339 ata_msleep(ap, 1);
365cfa1e
AV		 1340
1341 /* issue the second D2H Register FIS */
1342 tf.ctl &= ~ATA_SRST;
1343 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1344
1345 /* wait for link to become ready */
1346 rc = ata_wait_after_reset(link, deadline, check_ready);
1347 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1348 /*
1349 * Workaround for cases where link online status can't
1350 * be trusted. Treat device readiness timeout as link
1351 * offline.
1352 */
a9a79dfe 1353 ata_link_info(link, "device not ready, treating as offline\n");
365cfa1e
AV		 1354 *class = ATA_DEV_NONE;
1355 } else if (rc) {
1356 /* link occupied, -ENODEV too is an error */
1357 reason = "device not ready";
1358 goto fail;
1359 } else
1360 *class = ahci_dev_classify(ap);
1361
89dafa20 1362 /* re-enable FBS if disabled before */
1363 if (fbs_disabled)
1364 ahci_enable_fbs(ap);
1365
365cfa1e
AV		 1366 DPRINTK("EXIT, class=%u\n", *class);
1367 return 0;
1368
1369 fail:
a9a79dfe 1370 ata_link_err(link, "softreset failed (%s)\n", reason);
365cfa1e
AV		 1371 return rc;
1372}
1373
1374int ahci_check_ready(struct ata_link *link)
1375{
1376 void __iomem *port_mmio = ahci_port_base(link->ap);
1377 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1378
1379 return ata_check_ready(status);
1380}
1381EXPORT_SYMBOL_GPL(ahci_check_ready);
1382
1383static int ahci_softreset(struct ata_link *link, unsigned int *class,
1384 unsigned long deadline)
1385{
1386 int pmp = sata_srst_pmp(link);
1387
1388 DPRINTK("ENTER\n");
1389
1390 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1391}
1392EXPORT_SYMBOL_GPL(ahci_do_softreset);
1393
345347c5
YHC		 1394static int ahci_bad_pmp_check_ready(struct ata_link *link)
1395{
1396 void __iomem *port_mmio = ahci_port_base(link->ap);
1397 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1398 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1399
1400 /*
1401 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1402 * which can save timeout delay.
1403 */
1404 if (irq_status & PORT_IRQ_BAD_PMP)
1405 return -EIO;
1406
1407 return ata_check_ready(status);
1408}
1409
35186d05
DY		 1410static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1411 unsigned long deadline)
345347c5
YHC		 1412{
1413 struct ata_port *ap = link->ap;
1414 void __iomem *port_mmio = ahci_port_base(ap);
1415 int pmp = sata_srst_pmp(link);
1416 int rc;
1417 u32 irq_sts;
1418
1419 DPRINTK("ENTER\n");
1420
1421 rc = ahci_do_softreset(link, class, pmp, deadline,
1422 ahci_bad_pmp_check_ready);
1423
1424 /*
1425 * Soft reset fails with IPMS set when PMP is enabled but
1426 * SATA HDD/ODD is connected to SATA port, do soft reset
1427 * again to port 0.
1428 */
1429 if (rc == -EIO) {
1430 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1431 if (irq_sts & PORT_IRQ_BAD_PMP) {
39f80acb 1432 ata_link_warn(link,
345347c5
YHC		 1433 "applying PMP SRST workaround "
1434 "and retrying\n");
1435 rc = ahci_do_softreset(link, class, 0, deadline,
1436 ahci_check_ready);
1437 }
1438 }
1439
1440 return rc;
1441}
1442
365cfa1e
AV		 1443static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1444 unsigned long deadline)
1445{
1446 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1447 struct ata_port *ap = link->ap;
1448 struct ahci_port_priv *pp = ap->private_data;
039ece38 1449 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 1450 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1451 struct ata_taskfile tf;
1452 bool online;
1453 int rc;
1454
1455 DPRINTK("ENTER\n");
1456
1457 ahci_stop_engine(ap);
1458
1459 /* clear D2H reception area to properly wait for D2H FIS */
1460 ata_tf_init(link->device, &tf);
9bbb1b0e 1461 tf.command = ATA_BUSY;
365cfa1e
AV		 1462 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1463
1464 rc = sata_link_hardreset(link, timing, deadline, &online,
1465 ahci_check_ready);
1466
039ece38 1467 hpriv->start_engine(ap);
365cfa1e
AV		 1468
1469 if (online)
1470 *class = ahci_dev_classify(ap);
1471
1472 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1473 return rc;
1474}
1475
1476static void ahci_postreset(struct ata_link *link, unsigned int *class)
1477{
1478 struct ata_port *ap = link->ap;
1479 void __iomem *port_mmio = ahci_port_base(ap);
1480 u32 new_tmp, tmp;
1481
1482 ata_std_postreset(link, class);
1483
1484 /* Make sure port's ATAPI bit is set appropriately */
1485 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1486 if (*class == ATA_DEV_ATAPI)
1487 new_tmp |= PORT_CMD_ATAPI;
1488 else
1489 new_tmp &= ~PORT_CMD_ATAPI;
1490 if (new_tmp != tmp) {
1491 writel(new_tmp, port_mmio + PORT_CMD);
1492 readl(port_mmio + PORT_CMD); /* flush */
1493 }
1494}
1495
1496static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1497{
1498 struct scatterlist *sg;
1499 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1500 unsigned int si;
1501
1502 VPRINTK("ENTER\n");
1503
1504 /*
1505 * Next, the S/G list.
1506 */
1507 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1508 dma_addr_t addr = sg_dma_address(sg);
1509 u32 sg_len = sg_dma_len(sg);
1510
1511 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1512 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1513 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1514 }
1515
1516 return si;
1517}
1518
1519static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1520{
1521 struct ata_port *ap = qc->ap;
1522 struct ahci_port_priv *pp = ap->private_data;
1523
1524 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1525 return ata_std_qc_defer(qc);
1526 else
1527 return sata_pmp_qc_defer_cmd_switch(qc);
1528}
1529
1530static void ahci_qc_prep(struct ata_queued_cmd *qc)
1531{
1532 struct ata_port *ap = qc->ap;
1533 struct ahci_port_priv *pp = ap->private_data;
1534 int is_atapi = ata_is_atapi(qc->tf.protocol);
1535 void *cmd_tbl;
1536 u32 opts;
1537 const u32 cmd_fis_len = 5; /* five dwords */
1538 unsigned int n_elem;
1539
1540 /*
1541 * Fill in command table information. First, the header,
1542 * a SATA Register - Host to Device command FIS.
1543 */
1544 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1545
1546 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1547 if (is_atapi) {
1548 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1549 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1550 }
1551
1552 n_elem = 0;
1553 if (qc->flags & ATA_QCFLAG_DMAMAP)
1554 n_elem = ahci_fill_sg(qc, cmd_tbl);
1555
1556 /*
1557 * Fill in command slot information.
1558 */
1559 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1560 if (qc->tf.flags & ATA_TFLAG_WRITE)
1561 opts |= AHCI_CMD_WRITE;
1562 if (is_atapi)
1563 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1564
1565 ahci_fill_cmd_slot(pp, qc->tag, opts);
1566}
1567
1568static void ahci_fbs_dec_intr(struct ata_port *ap)
1569{
1570 struct ahci_port_priv *pp = ap->private_data;
1571 void __iomem *port_mmio = ahci_port_base(ap);
1572 u32 fbs = readl(port_mmio + PORT_FBS);
1573 int retries = 3;
1574
1575 DPRINTK("ENTER\n");
1576 BUG_ON(!pp->fbs_enabled);
1577
1578 /* time to wait for DEC is not specified by AHCI spec,
1579 * add a retry loop for safety.
1580 */
1581 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1582 fbs = readl(port_mmio + PORT_FBS);
1583 while ((fbs & PORT_FBS_DEC) && retries--) {
1584 udelay(1);
1585 fbs = readl(port_mmio + PORT_FBS);
1586 }
1587
1588 if (fbs & PORT_FBS_DEC)
a44fec1f 1589 dev_err(ap->host->dev, "failed to clear device error\n");
365cfa1e
AV		 1590}
1591
1592static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1593{
1594 struct ahci_host_priv *hpriv = ap->host->private_data;
1595 struct ahci_port_priv *pp = ap->private_data;
1596 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1597 struct ata_link *link = NULL;
1598 struct ata_queued_cmd *active_qc;
1599 struct ata_eh_info *active_ehi;
1600 bool fbs_need_dec = false;
1601 u32 serror;
1602
1603 /* determine active link with error */
1604 if (pp->fbs_enabled) {
1605 void __iomem *port_mmio = ahci_port_base(ap);
1606 u32 fbs = readl(port_mmio + PORT_FBS);
1607 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1608
912b9ac6 1609 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
365cfa1e
AV		 1610 link = &ap->pmp_link[pmp];
1611 fbs_need_dec = true;
1612 }
1613
1614 } else
1615 ata_for_each_link(link, ap, EDGE)
1616 if (ata_link_active(link))
1617 break;
1618
1619 if (!link)
1620 link = &ap->link;
1621
1622 active_qc = ata_qc_from_tag(ap, link->active_tag);
1623 active_ehi = &link->eh_info;
1624
1625 /* record irq stat */
1626 ata_ehi_clear_desc(host_ehi);
1627 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1628
1629 /* AHCI needs SError cleared; otherwise, it might lock up */
1630 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1631 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1632 host_ehi->serror |= serror;
1633
1634 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1635 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1636 irq_stat &= ~PORT_IRQ_IF_ERR;
1637
1638 if (irq_stat & PORT_IRQ_TF_ERR) {
1639 /* If qc is active, charge it; otherwise, the active
1640 * link. There's no active qc on NCQ errors. It will
1641 * be determined by EH by reading log page 10h.
1642 */
1643 if (active_qc)
1644 active_qc->err_mask |= AC_ERR_DEV;
1645 else
1646 active_ehi->err_mask |= AC_ERR_DEV;
1647
1648 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1649 host_ehi->serror &= ~SERR_INTERNAL;
1650 }
1651
1652 if (irq_stat & PORT_IRQ_UNK_FIS) {
d5185d65 1653 u32 *unk = pp->rx_fis + RX_FIS_UNK;
365cfa1e
AV		 1654
1655 active_ehi->err_mask |= AC_ERR_HSM;
1656 active_ehi->action |= ATA_EH_RESET;
1657 ata_ehi_push_desc(active_ehi,
1658 "unknown FIS %08x %08x %08x %08x" ,
1659 unk[0], unk[1], unk[2], unk[3]);
1660 }
1661
1662 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1663 active_ehi->err_mask |= AC_ERR_HSM;
1664 active_ehi->action |= ATA_EH_RESET;
1665 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1666 }
1667
1668 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1669 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1670 host_ehi->action |= ATA_EH_RESET;
1671 ata_ehi_push_desc(host_ehi, "host bus error");
1672 }
1673
1674 if (irq_stat & PORT_IRQ_IF_ERR) {
1675 if (fbs_need_dec)
1676 active_ehi->err_mask |= AC_ERR_DEV;
1677 else {
1678 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1679 host_ehi->action |= ATA_EH_RESET;
1680 }
1681
1682 ata_ehi_push_desc(host_ehi, "interface fatal error");
1683 }
1684
1685 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1686 ata_ehi_hotplugged(host_ehi);
1687 ata_ehi_push_desc(host_ehi, "%s",
1688 irq_stat & PORT_IRQ_CONNECT ?
1689 "connection status changed" : "PHY RDY changed");
1690 }
1691
1692 /* okay, let's hand over to EH */
1693
1694 if (irq_stat & PORT_IRQ_FREEZE)
1695 ata_port_freeze(ap);
1696 else if (fbs_need_dec) {
1697 ata_link_abort(link);
1698 ahci_fbs_dec_intr(ap);
1699 } else
1700 ata_port_abort(ap);
1701}
1702
5ca72c4f
AG		 1703static void ahci_handle_port_interrupt(struct ata_port *ap,
1704 void __iomem *port_mmio, u32 status)
365cfa1e 1705{
365cfa1e
AV		 1706 struct ata_eh_info *ehi = &ap->link.eh_info;
1707 struct ahci_port_priv *pp = ap->private_data;
1708 struct ahci_host_priv *hpriv = ap->host->private_data;
1709 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
5ca72c4f 1710 u32 qc_active = 0;
365cfa1e
AV		 1711 int rc;
1712
365cfa1e
AV		 1713 /* ignore BAD_PMP while resetting */
1714 if (unlikely(resetting))
1715 status &= ~PORT_IRQ_BAD_PMP;
1716
8393b811 1717 if (sata_lpm_ignore_phy_events(&ap->link)) {
365cfa1e 1718 status &= ~PORT_IRQ_PHYRDY;
6b7ae954 1719 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
365cfa1e
AV		 1720 }
1721
1722 if (unlikely(status & PORT_IRQ_ERROR)) {
1723 ahci_error_intr(ap, status);
1724 return;
1725 }
1726
1727 if (status & PORT_IRQ_SDB_FIS) {
1728 /* If SNotification is available, leave notification
1729 * handling to sata_async_notification(). If not,
1730 * emulate it by snooping SDB FIS RX area.
1731 *
1732 * Snooping FIS RX area is probably cheaper than
1733 * poking SNotification but some constrollers which
1734 * implement SNotification, ICH9 for example, don't
1735 * store AN SDB FIS into receive area.
1736 */
1737 if (hpriv->cap & HOST_CAP_SNTF)
1738 sata_async_notification(ap);
1739 else {
1740 /* If the 'N' bit in word 0 of the FIS is set,
1741 * we just received asynchronous notification.
1742 * Tell libata about it.
1743 *
1744 * Lack of SNotification should not appear in
1745 * ahci 1.2, so the workaround is unnecessary
1746 * when FBS is enabled.
1747 */
1748 if (pp->fbs_enabled)
1749 WARN_ON_ONCE(1);
1750 else {
1751 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1752 u32 f0 = le32_to_cpu(f[0]);
1753 if (f0 & (1 << 15))
1754 sata_async_notification(ap);
1755 }
1756 }
1757 }
1758
1759 /* pp->active_link is not reliable once FBS is enabled, both
1760 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1761 * NCQ and non-NCQ commands may be in flight at the same time.
1762 */
1763 if (pp->fbs_enabled) {
1764 if (ap->qc_active) {
1765 qc_active = readl(port_mmio + PORT_SCR_ACT);
1766 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1767 }
1768 } else {
1769 /* pp->active_link is valid iff any command is in flight */
1770 if (ap->qc_active && pp->active_link->sactive)
1771 qc_active = readl(port_mmio + PORT_SCR_ACT);
1772 else
1773 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1774 }
1775
1776
1777 rc = ata_qc_complete_multiple(ap, qc_active);
1778
1779 /* while resetting, invalid completions are expected */
1780 if (unlikely(rc < 0 && !resetting)) {
1781 ehi->err_mask |= AC_ERR_HSM;
1782 ehi->action |= ATA_EH_RESET;
1783 ata_port_freeze(ap);
1784 }
1785}
1786
7865f83f 1787static void ahci_port_intr(struct ata_port *ap)
5ca72c4f
AG		 1788{
1789 void __iomem *port_mmio = ahci_port_base(ap);
1790 u32 status;
1791
1792 status = readl(port_mmio + PORT_IRQ_STAT);
1793 writel(status, port_mmio + PORT_IRQ_STAT);
1794
7865f83f 1795 ahci_handle_port_interrupt(ap, port_mmio, status);
5ca72c4f
AG		 1796}
1797
5ee1cfd9 1798static irqreturn_t ahci_port_thread_fn(int irq, void *dev_instance)
5ca72c4f
AG		 1799{
1800 struct ata_port *ap = dev_instance;
1801 struct ahci_port_priv *pp = ap->private_data;
1802 void __iomem *port_mmio = ahci_port_base(ap);
5ca72c4f
AG		 1803 u32 status;
1804
227dfb4d
AG		 1805 status = atomic_xchg(&pp->intr_status, 0);
1806 if (!status)
1807 return IRQ_NONE;
5ca72c4f
AG		 1808
1809 spin_lock_bh(ap->lock);
1810 ahci_handle_port_interrupt(ap, port_mmio, status);
1811 spin_unlock_bh(ap->lock);
1812
1813 return IRQ_HANDLED;
1814}
5ca72c4f 1815
227dfb4d 1816static irqreturn_t ahci_multi_irqs_intr(int irq, void *dev_instance)
5ca72c4f 1817{
227dfb4d 1818 struct ata_port *ap = dev_instance;
5ca72c4f
AG		 1819 void __iomem *port_mmio = ahci_port_base(ap);
1820 struct ahci_port_priv *pp = ap->private_data;
1821 u32 status;
1822
5ca72c4f
AG		 1823 VPRINTK("ENTER\n");
1824
227dfb4d
AG		 1825 status = readl(port_mmio + PORT_IRQ_STAT);
1826 writel(status, port_mmio + PORT_IRQ_STAT);
5ca72c4f 1827
227dfb4d 1828 atomic_or(status, &pp->intr_status);
5ca72c4f
AG		 1829
1830 VPRINTK("EXIT\n");
1831
1832 return IRQ_WAKE_THREAD;
1833}
5ca72c4f 1834
a129db89 1835static u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
365cfa1e 1836{
365cfa1e 1837 unsigned int i, handled = 0;
03e83cbd 1838
365cfa1e
AV		 1839 for (i = 0; i < host->n_ports; i++) {
1840 struct ata_port *ap;
1841
1842 if (!(irq_masked & (1 << i)))
1843 continue;
1844
1845 ap = host->ports[i];
1846 if (ap) {
7865f83f 1847 ahci_port_intr(ap);
365cfa1e
AV		 1848 VPRINTK("port %u\n", i);
1849 } else {
1850 VPRINTK("port %u (no irq)\n", i);
1851 if (ata_ratelimit())
a44fec1f
JP		 1852 dev_warn(host->dev,
1853 "interrupt on disabled port %u\n", i);
365cfa1e
AV		 1854 }
1855
1856 handled = 1;
1857 }
1858
a129db89
ST		 1859 return handled;
1860}
1861
5903b164 1862static irqreturn_t ahci_single_edge_irq_intr(int irq, void *dev_instance)
365cfa1e
AV		 1863{
1864 struct ata_host *host = dev_instance;
1865 struct ahci_host_priv *hpriv;
5903b164 1866 unsigned int rc = 0;
365cfa1e
AV		 1867 void __iomem *mmio;
1868 u32 irq_stat, irq_masked;
1869
1870 VPRINTK("ENTER\n");
1871
1872 hpriv = host->private_data;
1873 mmio = hpriv->mmio;
1874
1875 /* sigh. 0xffffffff is a valid return from h/w */
1876 irq_stat = readl(mmio + HOST_IRQ_STAT);
1877 if (!irq_stat)
1878 return IRQ_NONE;
1879
1880 irq_masked = irq_stat & hpriv->port_map;
1881
03e83cbd
TH		 1882 spin_lock(&host->lock);
1883
5903b164
ST		 1884 /*
1885 * HOST_IRQ_STAT behaves as edge triggered latch meaning that
1886 * it should be cleared before all the port events are cleared.
1887 */
1888 writel(irq_stat, mmio + HOST_IRQ_STAT);
365cfa1e 1889
5903b164 1890 rc = ahci_handle_port_intr(host, irq_masked);
365cfa1e 1891
5903b164 1892 spin_unlock(&host->lock);
365cfa1e 1893
5903b164
ST		 1894 VPRINTK("EXIT\n");
1895
1896 return IRQ_RETVAL(rc);
1897}
1898
a129db89
ST		 1899static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1900{
1901 struct ata_host *host = dev_instance;
1902 struct ahci_host_priv *hpriv;
1903 unsigned int rc = 0;
1904 void __iomem *mmio;
1905 u32 irq_stat, irq_masked;
1906
1907 VPRINTK("ENTER\n");
1908
1909 hpriv = host->private_data;
1910 mmio = hpriv->mmio;
1911
1912 /* sigh. 0xffffffff is a valid return from h/w */
1913 irq_stat = readl(mmio + HOST_IRQ_STAT);
1914 if (!irq_stat)
1915 return IRQ_NONE;
1916
1917 irq_masked = irq_stat & hpriv->port_map;
1918
1919 spin_lock(&host->lock);
1920
1921 rc = ahci_handle_port_intr(host, irq_masked);
365cfa1e
AV		 1922
1923 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1924 * it should be cleared after all the port events are cleared;
1925 * otherwise, it will raise a spurious interrupt after each
1926 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1927 * information.
1928 *
1929 * Also, use the unmasked value to clear interrupt as spurious
1930 * pending event on a dummy port might cause screaming IRQ.
1931 */
1932 writel(irq_stat, mmio + HOST_IRQ_STAT);
1933
03e83cbd
TH		 1934 spin_unlock(&host->lock);
1935
365cfa1e
AV		 1936 VPRINTK("EXIT\n");
1937
a129db89 1938 return IRQ_RETVAL(rc);
365cfa1e 1939}
365cfa1e 1940
39e0ee99 1941unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
365cfa1e
AV		 1942{
1943 struct ata_port *ap = qc->ap;
1944 void __iomem *port_mmio = ahci_port_base(ap);
1945 struct ahci_port_priv *pp = ap->private_data;
1946
1947 /* Keep track of the currently active link. It will be used
1948 * in completion path to determine whether NCQ phase is in
1949 * progress.
1950 */
1951 pp->active_link = qc->dev->link;
1952
1953 if (qc->tf.protocol == ATA_PROT_NCQ)
1954 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1955
1956 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1957 u32 fbs = readl(port_mmio + PORT_FBS);
1958 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1959 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1960 writel(fbs, port_mmio + PORT_FBS);
1961 pp->fbs_last_dev = qc->dev->link->pmp;
1962 }
1963
1964 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1965
1966 ahci_sw_activity(qc->dev->link);
1967
1968 return 0;
1969}
39e0ee99 1970EXPORT_SYMBOL_GPL(ahci_qc_issue);
365cfa1e
AV		 1971
1972static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1973{
1974 struct ahci_port_priv *pp = qc->ap->private_data;
6ad60195 1975 u8 *rx_fis = pp->rx_fis;
365cfa1e
AV		 1976
1977 if (pp->fbs_enabled)
6ad60195
TH		 1978 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1979
1980 /*
1981 * After a successful execution of an ATA PIO data-in command,
1982 * the device doesn't send D2H Reg FIS to update the TF and
1983 * the host should take TF and E_Status from the preceding PIO
1984 * Setup FIS.
1985 */
1986 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
1987 !(qc->flags & ATA_QCFLAG_FAILED)) {
1988 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
1989 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
1990 } else
1991 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
365cfa1e 1992
365cfa1e
AV		 1993 return true;
1994}
1995
1996static void ahci_freeze(struct ata_port *ap)
1997{
1998 void __iomem *port_mmio = ahci_port_base(ap);
1999
2000 /* turn IRQ off */
2001 writel(0, port_mmio + PORT_IRQ_MASK);
2002}
2003
2004static void ahci_thaw(struct ata_port *ap)
2005{
2006 struct ahci_host_priv *hpriv = ap->host->private_data;
2007 void __iomem *mmio = hpriv->mmio;
2008 void __iomem *port_mmio = ahci_port_base(ap);
2009 u32 tmp;
2010 struct ahci_port_priv *pp = ap->private_data;
2011
2012 /* clear IRQ */
2013 tmp = readl(port_mmio + PORT_IRQ_STAT);
2014 writel(tmp, port_mmio + PORT_IRQ_STAT);
2015 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2016
2017 /* turn IRQ back on */
2018 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2019}
2020
8b789d89 2021void ahci_error_handler(struct ata_port *ap)
365cfa1e 2022{
039ece38
HG		 2023 struct ahci_host_priv *hpriv = ap->host->private_data;
2024
365cfa1e
AV		 2025 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2026 /* restart engine */
2027 ahci_stop_engine(ap);
039ece38 2028 hpriv->start_engine(ap);
365cfa1e
AV		 2029 }
2030
2031 sata_pmp_error_handler(ap);
0ee71952
TH		 2032
2033 if (!ata_dev_enabled(ap->link.device))
2034 ahci_stop_engine(ap);
365cfa1e 2035}
8b789d89 2036EXPORT_SYMBOL_GPL(ahci_error_handler);
365cfa1e
AV		 2037
2038static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2039{
2040 struct ata_port *ap = qc->ap;
2041
2042 /* make DMA engine forget about the failed command */
2043 if (qc->flags & ATA_QCFLAG_FAILED)
2044 ahci_kick_engine(ap);
2045}
2046
65fe1f0f
SH		 2047static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2048{
039ece38 2049 struct ahci_host_priv *hpriv = ap->host->private_data;
65fe1f0f
SH		 2050 void __iomem *port_mmio = ahci_port_base(ap);
2051 struct ata_device *dev = ap->link.device;
2052 u32 devslp, dm, dito, mdat, deto;
2053 int rc;
2054 unsigned int err_mask;
2055
2056 devslp = readl(port_mmio + PORT_DEVSLP);
2057 if (!(devslp & PORT_DEVSLP_DSP)) {
95bbbe9a 2058 dev_info(ap->host->dev, "port does not support device sleep\n");
65fe1f0f
SH		 2059 return;
2060 }
2061
2062 /* disable device sleep */
2063 if (!sleep) {
2064 if (devslp & PORT_DEVSLP_ADSE) {
2065 writel(devslp & ~PORT_DEVSLP_ADSE,
2066 port_mmio + PORT_DEVSLP);
2067 err_mask = ata_dev_set_feature(dev,
2068 SETFEATURES_SATA_DISABLE,
2069 SATA_DEVSLP);
2070 if (err_mask && err_mask != AC_ERR_DEV)
2071 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2072 }
2073 return;
2074 }
2075
2076 /* device sleep was already enabled */
2077 if (devslp & PORT_DEVSLP_ADSE)
2078 return;
2079
2080 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2081 rc = ahci_stop_engine(ap);
2082 if (rc)
2083 return;
2084
2085 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2086 dito = devslp_idle_timeout / (dm + 1);
2087 if (dito > 0x3ff)
2088 dito = 0x3ff;
2089
2090 /* Use the nominal value 10 ms if the read MDAT is zero,
2091 * the nominal value of DETO is 20 ms.
2092 */
803739d2 2093 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
65fe1f0f 2094 ATA_LOG_DEVSLP_VALID_MASK) {
803739d2 2095 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
65fe1f0f
SH		 2096 ATA_LOG_DEVSLP_MDAT_MASK;
2097 if (!mdat)
2098 mdat = 10;
803739d2 2099 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
65fe1f0f
SH		 2100 if (!deto)
2101 deto = 20;
2102 } else {
2103 mdat = 10;
2104 deto = 20;
2105 }
2106
2107 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2108 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2109 (deto << PORT_DEVSLP_DETO_OFFSET) |
2110 PORT_DEVSLP_ADSE);
2111 writel(devslp, port_mmio + PORT_DEVSLP);
2112
039ece38 2113 hpriv->start_engine(ap);
65fe1f0f
SH		 2114
2115 /* enable device sleep feature for the drive */
2116 err_mask = ata_dev_set_feature(dev,
2117 SETFEATURES_SATA_ENABLE,
2118 SATA_DEVSLP);
2119 if (err_mask && err_mask != AC_ERR_DEV)
2120 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2121}
2122
365cfa1e
AV		 2123static void ahci_enable_fbs(struct ata_port *ap)
2124{
039ece38 2125 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 2126 struct ahci_port_priv *pp = ap->private_data;
2127 void __iomem *port_mmio = ahci_port_base(ap);
2128 u32 fbs;
2129 int rc;
2130
2131 if (!pp->fbs_supported)
2132 return;
2133
2134 fbs = readl(port_mmio + PORT_FBS);
2135 if (fbs & PORT_FBS_EN) {
2136 pp->fbs_enabled = true;
2137 pp->fbs_last_dev = -1; /* initialization */
2138 return;
2139 }
2140
2141 rc = ahci_stop_engine(ap);
2142 if (rc)
2143 return;
2144
2145 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2146 fbs = readl(port_mmio + PORT_FBS);
2147 if (fbs & PORT_FBS_EN) {
a44fec1f 2148 dev_info(ap->host->dev, "FBS is enabled\n");
365cfa1e
AV		 2149 pp->fbs_enabled = true;
2150 pp->fbs_last_dev = -1; /* initialization */
2151 } else
a44fec1f 2152 dev_err(ap->host->dev, "Failed to enable FBS\n");
365cfa1e 2153
039ece38 2154 hpriv->start_engine(ap);
365cfa1e
AV		 2155}
2156
2157static void ahci_disable_fbs(struct ata_port *ap)
2158{
039ece38 2159 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 2160 struct ahci_port_priv *pp = ap->private_data;
2161 void __iomem *port_mmio = ahci_port_base(ap);
2162 u32 fbs;
2163 int rc;
2164
2165 if (!pp->fbs_supported)
2166 return;
2167
2168 fbs = readl(port_mmio + PORT_FBS);
2169 if ((fbs & PORT_FBS_EN) == 0) {
2170 pp->fbs_enabled = false;
2171 return;
2172 }
2173
2174 rc = ahci_stop_engine(ap);
2175 if (rc)
2176 return;
2177
2178 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2179 fbs = readl(port_mmio + PORT_FBS);
2180 if (fbs & PORT_FBS_EN)
a44fec1f 2181 dev_err(ap->host->dev, "Failed to disable FBS\n");
365cfa1e 2182 else {
a44fec1f 2183 dev_info(ap->host->dev, "FBS is disabled\n");
365cfa1e
AV		 2184 pp->fbs_enabled = false;
2185 }
2186
039ece38 2187 hpriv->start_engine(ap);
365cfa1e
AV		 2188}
2189
2190static void ahci_pmp_attach(struct ata_port *ap)
2191{
2192 void __iomem *port_mmio = ahci_port_base(ap);
2193 struct ahci_port_priv *pp = ap->private_data;
2194 u32 cmd;
2195
2196 cmd = readl(port_mmio + PORT_CMD);
2197 cmd |= PORT_CMD_PMP;
2198 writel(cmd, port_mmio + PORT_CMD);
2199
2200 ahci_enable_fbs(ap);
2201
2202 pp->intr_mask |= PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 2203
2204 /*
2205 * We must not change the port interrupt mask register if the
2206 * port is marked frozen, the value in pp->intr_mask will be
2207 * restored later when the port is thawed.
2208 *
2209 * Note that during initialization, the port is marked as
2210 * frozen since the irq handler is not yet registered.
2211 */
2212 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2213 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 2214}
2215
2216static void ahci_pmp_detach(struct ata_port *ap)
2217{
2218 void __iomem *port_mmio = ahci_port_base(ap);
2219 struct ahci_port_priv *pp = ap->private_data;
2220 u32 cmd;
2221
2222 ahci_disable_fbs(ap);
2223
2224 cmd = readl(port_mmio + PORT_CMD);
2225 cmd &= ~PORT_CMD_PMP;
2226 writel(cmd, port_mmio + PORT_CMD);
2227
2228 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 2229
2230 /* see comment above in ahci_pmp_attach() */
2231 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2232 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 2233}
2234
02cdfcf0 2235int ahci_port_resume(struct ata_port *ap)
365cfa1e
AV		 2236{
2237 ahci_power_up(ap);
2238 ahci_start_port(ap);
2239
2240 if (sata_pmp_attached(ap))
2241 ahci_pmp_attach(ap);
2242 else
2243 ahci_pmp_detach(ap);
2244
2245 return 0;
2246}
02cdfcf0 2247EXPORT_SYMBOL_GPL(ahci_port_resume);
365cfa1e
AV		 2248
2249#ifdef CONFIG_PM
2250static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2251{
2252 const char *emsg = NULL;
2253 int rc;
2254
2255 rc = ahci_deinit_port(ap, &emsg);
2256 if (rc == 0)
2257 ahci_power_down(ap);
2258 else {
a9a79dfe 2259 ata_port_err(ap, "%s (%d)\n", emsg, rc);
7faa33da 2260 ata_port_freeze(ap);
365cfa1e
AV		 2261 }
2262
2263 return rc;
2264}
2265#endif
2266
2267static int ahci_port_start(struct ata_port *ap)
2268{
2269 struct ahci_host_priv *hpriv = ap->host->private_data;
2270 struct device *dev = ap->host->dev;
2271 struct ahci_port_priv *pp;
2272 void *mem;
2273 dma_addr_t mem_dma;
2274 size_t dma_sz, rx_fis_sz;
2275
2276 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2277 if (!pp)
2278 return -ENOMEM;
2279
b29900e6
AG		 2280 if (ap->host->n_ports > 1) {
2281 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2282 if (!pp->irq_desc) {
2283 devm_kfree(dev, pp);
2284 return -ENOMEM;
2285 }
2286 snprintf(pp->irq_desc, 8,
2287 "%s%d", dev_driver_string(dev), ap->port_no);
2288 }
2289
365cfa1e
AV		 2290 /* check FBS capability */
2291 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2292 void __iomem *port_mmio = ahci_port_base(ap);
2293 u32 cmd = readl(port_mmio + PORT_CMD);
2294 if (cmd & PORT_CMD_FBSCP)
2295 pp->fbs_supported = true;
5f173107 2296 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
a44fec1f
JP		 2297 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2298 ap->port_no);
5f173107
TH		 2299 pp->fbs_supported = true;
2300 } else
a44fec1f
JP		 2301 dev_warn(dev, "port %d is not capable of FBS\n",
2302 ap->port_no);
365cfa1e
AV		 2303 }
2304
2305 if (pp->fbs_supported) {
2306 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2307 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2308 } else {
2309 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2310 rx_fis_sz = AHCI_RX_FIS_SZ;
2311 }
2312
2313 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2314 if (!mem)
2315 return -ENOMEM;
2316 memset(mem, 0, dma_sz);
2317
2318 /*
2319 * First item in chunk of DMA memory: 32-slot command table,
2320 * 32 bytes each in size
2321 */
2322 pp->cmd_slot = mem;
2323 pp->cmd_slot_dma = mem_dma;
2324
2325 mem += AHCI_CMD_SLOT_SZ;
2326 mem_dma += AHCI_CMD_SLOT_SZ;
2327
2328 /*
2329 * Second item: Received-FIS area
2330 */
2331 pp->rx_fis = mem;
2332 pp->rx_fis_dma = mem_dma;
2333
2334 mem += rx_fis_sz;
2335 mem_dma += rx_fis_sz;
2336
2337 /*
2338 * Third item: data area for storing a single command
2339 * and its scatter-gather table
2340 */
2341 pp->cmd_tbl = mem;
2342 pp->cmd_tbl_dma = mem_dma;
2343
2344 /*
2345 * Save off initial list of interrupts to be enabled.
2346 * This could be changed later
2347 */
2348 pp->intr_mask = DEF_PORT_IRQ;
2349
7865f83f
TH		 2350 /*
2351 * Switch to per-port locking in case each port has its own MSI vector.
2352 */
21bfd1aa 2353 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
7865f83f
TH		 2354 spin_lock_init(&pp->lock);
2355 ap->lock = &pp->lock;
2356 }
5ca72c4f 2357
365cfa1e
AV		 2358 ap->private_data = pp;
2359
2360 /* engage engines, captain */
2361 return ahci_port_resume(ap);
2362}
2363
2364static void ahci_port_stop(struct ata_port *ap)
2365{
2366 const char *emsg = NULL;
2367 int rc;
2368
2369 /* de-initialize port */
2370 rc = ahci_deinit_port(ap, &emsg);
2371 if (rc)
a9a79dfe 2372 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
365cfa1e
AV		 2373}
2374
2375void ahci_print_info(struct ata_host *host, const char *scc_s)
2376{
2377 struct ahci_host_priv *hpriv = host->private_data;
2378 void __iomem *mmio = hpriv->mmio;
2379 u32 vers, cap, cap2, impl, speed;
2380 const char *speed_s;
2381
2382 vers = readl(mmio + HOST_VERSION);
2383 cap = hpriv->cap;
2384 cap2 = hpriv->cap2;
2385 impl = hpriv->port_map;
2386
2387 speed = (cap >> 20) & 0xf;
2388 if (speed == 1)
2389 speed_s = "1.5";
2390 else if (speed == 2)
2391 speed_s = "3";
2392 else if (speed == 3)
2393 speed_s = "6";
2394 else
2395 speed_s = "?";
2396
2397 dev_info(host->dev,
2398 "AHCI %02x%02x.%02x%02x "
2399 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2400 ,
2401
2402 (vers >> 24) & 0xff,
2403 (vers >> 16) & 0xff,
2404 (vers >> 8) & 0xff,
2405 vers & 0xff,
2406
2407 ((cap >> 8) & 0x1f) + 1,
2408 (cap & 0x1f) + 1,
2409 speed_s,
2410 impl,
2411 scc_s);
2412
2413 dev_info(host->dev,
2414 "flags: "
2415 "%s%s%s%s%s%s%s"
2416 "%s%s%s%s%s%s%s"
65fe1f0f
SH		 2417 "%s%s%s%s%s%s%s"
2418 "%s%s\n"
365cfa1e
AV		 2419 ,
2420
2421 cap & HOST_CAP_64 ? "64bit " : "",
2422 cap & HOST_CAP_NCQ ? "ncq " : "",
2423 cap & HOST_CAP_SNTF ? "sntf " : "",
2424 cap & HOST_CAP_MPS ? "ilck " : "",
2425 cap & HOST_CAP_SSS ? "stag " : "",
2426 cap & HOST_CAP_ALPM ? "pm " : "",
2427 cap & HOST_CAP_LED ? "led " : "",
2428 cap & HOST_CAP_CLO ? "clo " : "",
2429 cap & HOST_CAP_ONLY ? "only " : "",
2430 cap & HOST_CAP_PMP ? "pmp " : "",
2431 cap & HOST_CAP_FBS ? "fbs " : "",
2432 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2433 cap & HOST_CAP_SSC ? "slum " : "",
2434 cap & HOST_CAP_PART ? "part " : "",
2435 cap & HOST_CAP_CCC ? "ccc " : "",
2436 cap & HOST_CAP_EMS ? "ems " : "",
2437 cap & HOST_CAP_SXS ? "sxs " : "",
65fe1f0f
SH		 2438 cap2 & HOST_CAP2_DESO ? "deso " : "",
2439 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2440 cap2 & HOST_CAP2_SDS ? "sds " : "",
365cfa1e
AV		 2441 cap2 & HOST_CAP2_APST ? "apst " : "",
2442 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2443 cap2 & HOST_CAP2_BOH ? "boh " : ""
2444 );
2445}
2446EXPORT_SYMBOL_GPL(ahci_print_info);
2447
2448void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2449 struct ata_port_info *pi)
2450{
2451 u8 messages;
2452 void __iomem *mmio = hpriv->mmio;
2453 u32 em_loc = readl(mmio + HOST_EM_LOC);
2454 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2455
2456 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2457 return;
2458
2459 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2460
008dbd61 2461 if (messages) {
365cfa1e
AV		 2462 /* store em_loc */
2463 hpriv->em_loc = ((em_loc >> 16) * 4);
c0623166 2464 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
008dbd61 2465 hpriv->em_msg_type = messages;
365cfa1e
AV		 2466 pi->flags |= ATA_FLAG_EM;
2467 if (!(em_ctl & EM_CTL_ALHD))
2468 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2469 }
2470}
2471EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2472
d1028e2f
AG		 2473static int ahci_host_activate_multi_irqs(struct ata_host *host, int irq,
2474 struct scsi_host_template *sht)
1c62854f
AG		 2475{
2476 int i, rc;
2477
2478 rc = ata_host_start(host);
2479 if (rc)
2480 return rc;
21bfd1aa
RR		 2481 /*
2482 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2483 * allocated. That is one MSI per port, starting from @irq.
2484 */
1c62854f
AG		 2485 for (i = 0; i < host->n_ports; i++) {
2486 struct ahci_port_priv *pp = host->ports[i]->private_data;
2487
2488 /* Do not receive interrupts sent by dummy ports */
2489 if (!pp) {
2490 disable_irq(irq + i);
2491 continue;
2492 }
2493
2494 rc = devm_request_threaded_irq(host->dev, irq + i,
5ee1cfd9 2495 ahci_multi_irqs_intr,
899a63c3 2496 ahci_port_thread_fn, 0,
1c62854f
AG		 2497 pp->irq_desc, host->ports[i]);
2498 if (rc)
0a142b26 2499 return rc;
1c62854f 2500 ata_port_desc(host->ports[i], "irq %d", irq + i);
0a142b26
DW		 2501 }
2502 return ata_host_register(host, sht);
1c62854f 2503}
d1028e2f
AG		 2504
2505/**
2506 * ahci_host_activate - start AHCI host, request IRQs and register it
2507 * @host: target ATA host
d1028e2f
AG		 2508 * @sht: scsi_host_template to use when registering the host
2509 *
d1028e2f
AG		 2510 * LOCKING:
2511 * Inherited from calling layer (may sleep).
2512 *
2513 * RETURNS:
2514 * 0 on success, -errno otherwise.
2515 */
21bfd1aa 2516int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
d1028e2f
AG		 2517{
2518 struct ahci_host_priv *hpriv = host->private_data;
21bfd1aa 2519 int irq = hpriv->irq;
d1028e2f
AG		 2520 int rc;
2521
2522 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
2523 rc = ahci_host_activate_multi_irqs(host, irq, sht);
5903b164
ST		 2524 else if (hpriv->flags & AHCI_HFLAG_EDGE_IRQ)
2525 rc = ata_host_activate(host, irq, ahci_single_edge_irq_intr,
2526 IRQF_SHARED, sht);
d1028e2f 2527 else
a129db89 2528 rc = ata_host_activate(host, irq, ahci_single_level_irq_intr,
7865f83f 2529 IRQF_SHARED, sht);
d1028e2f
AG		 2530 return rc;
2531}
1c62854f
AG		 2532EXPORT_SYMBOL_GPL(ahci_host_activate);
2533
365cfa1e
AV		 2534MODULE_AUTHOR("Jeff Garzik");
2535MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2536MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)