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libnvdimm/altmap: Track namespace boundaries in altmap
[linux-2.6-block.git] / drivers / ata / libahci.c
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c82ee6d3 1// SPDX-License-Identifier: GPL-2.0-or-later
365cfa1e
AV		 2/*
3 * libahci.c - Common AHCI SATA low-level routines
4 *
8c3d3d4b 5 * Maintained by: Tejun Heo <tj@kernel.org>
365cfa1e
AV		 6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
365cfa1e 11 * libata documentation is available via 'make {ps|pdf}docs',
9bb9a39c 12 * as Documentation/driver-api/libata.rst
365cfa1e
AV		 13 *
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
365cfa1e
AV		 17 */
18
19#include <linux/kernel.h>
fbaf666b 20#include <linux/gfp.h>
365cfa1e 21#include <linux/module.h>
fae2a637 22#include <linux/nospec.h>
365cfa1e
AV		 23#include <linux/blkdev.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/dma-mapping.h>
27#include <linux/device.h>
28#include <scsi/scsi_host.h>
29#include <scsi/scsi_cmnd.h>
30#include <linux/libata.h>
d684a90d 31#include <linux/pci.h>
365cfa1e 32#include "ahci.h"
65fe1f0f 33#include "libata.h"
365cfa1e
AV		 34
35static int ahci_skip_host_reset;
36int ahci_ignore_sss;
37EXPORT_SYMBOL_GPL(ahci_ignore_sss);
38
39module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
40MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
41
42module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
43MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
44
6b7ae954
TH		 45static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
46 unsigned hints);
365cfa1e
AV		 47static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
48static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
49 size_t size);
50static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
51 ssize_t size);
52
53
54
55static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
56static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
365cfa1e
AV		 57static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
58static int ahci_port_start(struct ata_port *ap);
59static void ahci_port_stop(struct ata_port *ap);
60static void ahci_qc_prep(struct ata_queued_cmd *qc);
61static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
62static void ahci_freeze(struct ata_port *ap);
63static void ahci_thaw(struct ata_port *ap);
65fe1f0f 64static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
365cfa1e
AV		 65static void ahci_enable_fbs(struct ata_port *ap);
66static void ahci_disable_fbs(struct ata_port *ap);
67static void ahci_pmp_attach(struct ata_port *ap);
68static void ahci_pmp_detach(struct ata_port *ap);
69static int ahci_softreset(struct ata_link *link, unsigned int *class,
70 unsigned long deadline);
345347c5
YHC		 71static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
72 unsigned long deadline);
365cfa1e
AV		 73static int ahci_hardreset(struct ata_link *link, unsigned int *class,
74 unsigned long deadline);
75static void ahci_postreset(struct ata_link *link, unsigned int *class);
365cfa1e 76static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
365cfa1e 77static void ahci_dev_config(struct ata_device *dev);
365cfa1e
AV		 78#ifdef CONFIG_PM
79static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
80#endif
81static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
82static ssize_t ahci_activity_store(struct ata_device *dev,
83 enum sw_activity val);
84static void ahci_init_sw_activity(struct ata_link *link);
85
86static ssize_t ahci_show_host_caps(struct device *dev,
87 struct device_attribute *attr, char *buf);
88static ssize_t ahci_show_host_cap2(struct device *dev,
89 struct device_attribute *attr, char *buf);
90static ssize_t ahci_show_host_version(struct device *dev,
91 struct device_attribute *attr, char *buf);
92static ssize_t ahci_show_port_cmd(struct device *dev,
93 struct device_attribute *attr, char *buf);
c0623166
HZ		 94static ssize_t ahci_read_em_buffer(struct device *dev,
95 struct device_attribute *attr, char *buf);
96static ssize_t ahci_store_em_buffer(struct device *dev,
97 struct device_attribute *attr,
98 const char *buf, size_t size);
6e5fe5b1
HR		 99static ssize_t ahci_show_em_supported(struct device *dev,
100 struct device_attribute *attr, char *buf);
f070d671 101static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
365cfa1e
AV		 102
103static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
104static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
105static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
106static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
c0623166
HZ		 107static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
108 ahci_read_em_buffer, ahci_store_em_buffer);
6e5fe5b1 109static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
365cfa1e 110
fad16e7a 111struct device_attribute *ahci_shost_attrs[] = {
365cfa1e
AV		 112 &dev_attr_link_power_management_policy,
113 &dev_attr_em_message_type,
114 &dev_attr_em_message,
115 &dev_attr_ahci_host_caps,
116 &dev_attr_ahci_host_cap2,
117 &dev_attr_ahci_host_version,
118 &dev_attr_ahci_port_cmd,
c0623166 119 &dev_attr_em_buffer,
6e5fe5b1 120 &dev_attr_em_message_supported,
365cfa1e
AV		 121 NULL
122};
fad16e7a 123EXPORT_SYMBOL_GPL(ahci_shost_attrs);
365cfa1e 124
fad16e7a 125struct device_attribute *ahci_sdev_attrs[] = {
365cfa1e
AV		 126 &dev_attr_sw_activity,
127 &dev_attr_unload_heads,
84f95243 128 &dev_attr_ncq_prio_enable,
365cfa1e
AV		 129 NULL
130};
fad16e7a 131EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
365cfa1e
AV		 132
133struct ata_port_operations ahci_ops = {
134 .inherits = &sata_pmp_port_ops,
135
136 .qc_defer = ahci_pmp_qc_defer,
137 .qc_prep = ahci_qc_prep,
138 .qc_issue = ahci_qc_issue,
139 .qc_fill_rtf = ahci_qc_fill_rtf,
140
141 .freeze = ahci_freeze,
142 .thaw = ahci_thaw,
143 .softreset = ahci_softreset,
144 .hardreset = ahci_hardreset,
145 .postreset = ahci_postreset,
146 .pmp_softreset = ahci_softreset,
147 .error_handler = ahci_error_handler,
148 .post_internal_cmd = ahci_post_internal_cmd,
149 .dev_config = ahci_dev_config,
150
151 .scr_read = ahci_scr_read,
152 .scr_write = ahci_scr_write,
153 .pmp_attach = ahci_pmp_attach,
154 .pmp_detach = ahci_pmp_detach,
155
6b7ae954 156 .set_lpm = ahci_set_lpm,
365cfa1e
AV		 157 .em_show = ahci_led_show,
158 .em_store = ahci_led_store,
159 .sw_activity_show = ahci_activity_show,
160 .sw_activity_store = ahci_activity_store,
439d7a35 161 .transmit_led_message = ahci_transmit_led_message,
365cfa1e
AV		 162#ifdef CONFIG_PM
163 .port_suspend = ahci_port_suspend,
164 .port_resume = ahci_port_resume,
165#endif
166 .port_start = ahci_port_start,
167 .port_stop = ahci_port_stop,
168};
169EXPORT_SYMBOL_GPL(ahci_ops);
170
345347c5
YHC		 171struct ata_port_operations ahci_pmp_retry_srst_ops = {
172 .inherits = &ahci_ops,
173 .softreset = ahci_pmp_retry_softreset,
174};
175EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
176
ed08d40c 177static bool ahci_em_messages __read_mostly = true;
365cfa1e 178EXPORT_SYMBOL_GPL(ahci_em_messages);
ed08d40c 179module_param(ahci_em_messages, bool, 0444);
365cfa1e
AV		 180/* add other LED protocol types when they become supported */
181MODULE_PARM_DESC(ahci_em_messages,
008dbd61 182 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
365cfa1e 183
ed08d40c
CL		 184/* device sleep idle timeout in ms */
185static int devslp_idle_timeout __read_mostly = 1000;
65fe1f0f
SH		 186module_param(devslp_idle_timeout, int, 0644);
187MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
188
365cfa1e
AV		 189static void ahci_enable_ahci(void __iomem *mmio)
190{
191 int i;
192 u32 tmp;
193
194 /* turn on AHCI_EN */
195 tmp = readl(mmio + HOST_CTL);
196 if (tmp & HOST_AHCI_EN)
197 return;
198
199 /* Some controllers need AHCI_EN to be written multiple times.
200 * Try a few times before giving up.
201 */
202 for (i = 0; i < 5; i++) {
203 tmp |= HOST_AHCI_EN;
204 writel(tmp, mmio + HOST_CTL);
205 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
206 if (tmp & HOST_AHCI_EN)
207 return;
208 msleep(10);
209 }
210
211 WARN_ON(1);
212}
213
bb03c640
MW		 214/**
215 * ahci_rpm_get_port - Make sure the port is powered on
216 * @ap: Port to power on
217 *
218 * Whenever there is need to access the AHCI host registers outside of
219 * normal execution paths, call this function to make sure the host is
220 * actually powered on.
221 */
222static int ahci_rpm_get_port(struct ata_port *ap)
223{
224 return pm_runtime_get_sync(ap->dev);
225}
226
227/**
228 * ahci_rpm_put_port - Undoes ahci_rpm_get_port()
229 * @ap: Port to power down
230 *
231 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host
232 * if it has no more active users.
233 */
234static void ahci_rpm_put_port(struct ata_port *ap)
235{
236 pm_runtime_put(ap->dev);
237}
238
365cfa1e
AV		 239static ssize_t ahci_show_host_caps(struct device *dev,
240 struct device_attribute *attr, char *buf)
241{
242 struct Scsi_Host *shost = class_to_shost(dev);
243 struct ata_port *ap = ata_shost_to_port(shost);
244 struct ahci_host_priv *hpriv = ap->host->private_data;
245
246 return sprintf(buf, "%x\n", hpriv->cap);
247}
248
249static ssize_t ahci_show_host_cap2(struct device *dev,
250 struct device_attribute *attr, char *buf)
251{
252 struct Scsi_Host *shost = class_to_shost(dev);
253 struct ata_port *ap = ata_shost_to_port(shost);
254 struct ahci_host_priv *hpriv = ap->host->private_data;
255
256 return sprintf(buf, "%x\n", hpriv->cap2);
257}
258
259static ssize_t ahci_show_host_version(struct device *dev,
260 struct device_attribute *attr, char *buf)
261{
262 struct Scsi_Host *shost = class_to_shost(dev);
263 struct ata_port *ap = ata_shost_to_port(shost);
264 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 265
8ea909cb 266 return sprintf(buf, "%x\n", hpriv->version);
365cfa1e
AV		 267}
268
269static ssize_t ahci_show_port_cmd(struct device *dev,
270 struct device_attribute *attr, char *buf)
271{
272 struct Scsi_Host *shost = class_to_shost(dev);
273 struct ata_port *ap = ata_shost_to_port(shost);
274 void __iomem *port_mmio = ahci_port_base(ap);
bb03c640 275 ssize_t ret;
365cfa1e 276
bb03c640
MW		 277 ahci_rpm_get_port(ap);
278 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
279 ahci_rpm_put_port(ap);
280
281 return ret;
365cfa1e
AV		 282}
283
c0623166
HZ		 284static ssize_t ahci_read_em_buffer(struct device *dev,
285 struct device_attribute *attr, char *buf)
286{
287 struct Scsi_Host *shost = class_to_shost(dev);
288 struct ata_port *ap = ata_shost_to_port(shost);
289 struct ahci_host_priv *hpriv = ap->host->private_data;
290 void __iomem *mmio = hpriv->mmio;
291 void __iomem *em_mmio = mmio + hpriv->em_loc;
292 u32 em_ctl, msg;
293 unsigned long flags;
294 size_t count;
295 int i;
296
bb03c640 297 ahci_rpm_get_port(ap);
c0623166
HZ		 298 spin_lock_irqsave(ap->lock, flags);
299
300 em_ctl = readl(mmio + HOST_EM_CTL);
301 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
302 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
303 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 304 ahci_rpm_put_port(ap);
c0623166
HZ		 305 return -EINVAL;
306 }
307
308 if (!(em_ctl & EM_CTL_MR)) {
309 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 310 ahci_rpm_put_port(ap);
c0623166
HZ		 311 return -EAGAIN;
312 }
313
314 if (!(em_ctl & EM_CTL_SMB))
315 em_mmio += hpriv->em_buf_sz;
316
317 count = hpriv->em_buf_sz;
318
319 /* the count should not be larger than PAGE_SIZE */
320 if (count > PAGE_SIZE) {
321 if (printk_ratelimit())
a9a79dfe
JP		 322 ata_port_warn(ap,
323 "EM read buffer size too large: "
324 "buffer size %u, page size %lu\n",
325 hpriv->em_buf_sz, PAGE_SIZE);
c0623166
HZ		 326 count = PAGE_SIZE;
327 }
328
329 for (i = 0; i < count; i += 4) {
330 msg = readl(em_mmio + i);
331 buf[i] = msg & 0xff;
332 buf[i + 1] = (msg >> 8) & 0xff;
333 buf[i + 2] = (msg >> 16) & 0xff;
334 buf[i + 3] = (msg >> 24) & 0xff;
335 }
336
337 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 338 ahci_rpm_put_port(ap);
c0623166
HZ		 339
340 return i;
341}
342
343static ssize_t ahci_store_em_buffer(struct device *dev,
344 struct device_attribute *attr,
345 const char *buf, size_t size)
346{
347 struct Scsi_Host *shost = class_to_shost(dev);
348 struct ata_port *ap = ata_shost_to_port(shost);
349 struct ahci_host_priv *hpriv = ap->host->private_data;
350 void __iomem *mmio = hpriv->mmio;
351 void __iomem *em_mmio = mmio + hpriv->em_loc;
f9ce889b 352 const unsigned char *msg_buf = buf;
c0623166
HZ		 353 u32 em_ctl, msg;
354 unsigned long flags;
355 int i;
356
357 /* check size validity */
358 if (!(ap->flags & ATA_FLAG_EM) ||
359 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
360 size % 4 || size > hpriv->em_buf_sz)
361 return -EINVAL;
362
bb03c640 363 ahci_rpm_get_port(ap);
c0623166
HZ		 364 spin_lock_irqsave(ap->lock, flags);
365
366 em_ctl = readl(mmio + HOST_EM_CTL);
367 if (em_ctl & EM_CTL_TM) {
368 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 369 ahci_rpm_put_port(ap);
c0623166
HZ		 370 return -EBUSY;
371 }
372
373 for (i = 0; i < size; i += 4) {
f9ce889b
HZ		 374 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
375 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
c0623166
HZ		 376 writel(msg, em_mmio + i);
377 }
378
379 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
380
381 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 382 ahci_rpm_put_port(ap);
c0623166
HZ		 383
384 return size;
385}
386
6e5fe5b1
HR		 387static ssize_t ahci_show_em_supported(struct device *dev,
388 struct device_attribute *attr, char *buf)
389{
390 struct Scsi_Host *shost = class_to_shost(dev);
391 struct ata_port *ap = ata_shost_to_port(shost);
392 struct ahci_host_priv *hpriv = ap->host->private_data;
393 void __iomem *mmio = hpriv->mmio;
394 u32 em_ctl;
395
bb03c640 396 ahci_rpm_get_port(ap);
6e5fe5b1 397 em_ctl = readl(mmio + HOST_EM_CTL);
bb03c640 398 ahci_rpm_put_port(ap);
6e5fe5b1
HR		 399
400 return sprintf(buf, "%s%s%s%s\n",
401 em_ctl & EM_CTL_LED ? "led " : "",
402 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
403 em_ctl & EM_CTL_SES ? "ses-2 " : "",
404 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
405}
406
365cfa1e
AV		 407/**
408 * ahci_save_initial_config - Save and fixup initial config values
409 * @dev: target AHCI device
410 * @hpriv: host private area to store config values
365cfa1e
AV		 411 *
412 * Some registers containing configuration info might be setup by
413 * BIOS and might be cleared on reset. This function saves the
414 * initial values of those registers into @hpriv such that they
415 * can be restored after controller reset.
416 *
417 * If inconsistent, config values are fixed up by this function.
418 *
039ece38
HG		 419 * If it is not set already this function sets hpriv->start_engine to
420 * ahci_start_engine.
421 *
365cfa1e
AV		 422 * LOCKING:
423 * None.
424 */
725c7b57 425void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
365cfa1e
AV		 426{
427 void __iomem *mmio = hpriv->mmio;
428 u32 cap, cap2, vers, port_map;
429 int i;
430
431 /* make sure AHCI mode is enabled before accessing CAP */
432 ahci_enable_ahci(mmio);
433
434 /* Values prefixed with saved_ are written back to host after
435 * reset. Values without are used for driver operation.
436 */
437 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
438 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
439
440 /* CAP2 register is only defined for AHCI 1.2 and later */
441 vers = readl(mmio + HOST_VERSION);
442 if ((vers >> 16) > 1 ||
443 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
444 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
445 else
446 hpriv->saved_cap2 = cap2 = 0;
447
448 /* some chips have errata preventing 64bit use */
449 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
a44fec1f 450 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
365cfa1e
AV		 451 cap &= ~HOST_CAP_64;
452 }
453
454 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
a44fec1f 455 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
365cfa1e
AV		 456 cap &= ~HOST_CAP_NCQ;
457 }
458
459 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
a44fec1f 460 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
365cfa1e
AV		 461 cap |= HOST_CAP_NCQ;
462 }
463
464 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
a44fec1f 465 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
365cfa1e
AV		 466 cap &= ~HOST_CAP_PMP;
467 }
468
469 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
a44fec1f
JP		 470 dev_info(dev,
471 "controller can't do SNTF, turning off CAP_SNTF\n");
365cfa1e
AV		 472 cap &= ~HOST_CAP_SNTF;
473 }
474
0cf4a7d6
JP		 475 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
476 dev_info(dev,
477 "controller can't do DEVSLP, turning off\n");
478 cap2 &= ~HOST_CAP2_SDS;
479 cap2 &= ~HOST_CAP2_SADM;
480 }
481
5f173107 482 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
a44fec1f 483 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
5f173107
TH		 484 cap |= HOST_CAP_FBS;
485 }
486
888d91a0
KW		 487 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
488 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
489 cap &= ~HOST_CAP_FBS;
490 }
491
ef0da1bf
DB		 492 if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) {
493 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n");
494 cap |= HOST_CAP_ALPM;
495 }
496
725c7b57 497 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
a44fec1f 498 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
725c7b57
AT		 499 port_map, hpriv->force_port_map);
500 port_map = hpriv->force_port_map;
2fd0f46c 501 hpriv->saved_port_map = port_map;
365cfa1e
AV		 502 }
503
725c7b57 504 if (hpriv->mask_port_map) {
a44fec1f
JP		 505 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
506 port_map,
725c7b57
AT		 507 port_map & hpriv->mask_port_map);
508 port_map &= hpriv->mask_port_map;
365cfa1e
AV		 509 }
510
511 /* cross check port_map and cap.n_ports */
512 if (port_map) {
513 int map_ports = 0;
514
515 for (i = 0; i < AHCI_MAX_PORTS; i++)
516 if (port_map & (1 << i))
517 map_ports++;
518
519 /* If PI has more ports than n_ports, whine, clear
520 * port_map and let it be generated from n_ports.
521 */
522 if (map_ports > ahci_nr_ports(cap)) {
a44fec1f
JP		 523 dev_warn(dev,
524 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
525 port_map, ahci_nr_ports(cap));
365cfa1e
AV		 526 port_map = 0;
527 }
528 }
529
566d1827
TH		 530 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
531 if (!port_map && vers < 0x10300) {
365cfa1e 532 port_map = (1 << ahci_nr_ports(cap)) - 1;
a44fec1f 533 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
365cfa1e
AV		 534
535 /* write the fixed up value to the PI register */
536 hpriv->saved_port_map = port_map;
537 }
538
539 /* record values to use during operation */
540 hpriv->cap = cap;
541 hpriv->cap2 = cap2;
8ea909cb 542 hpriv->version = readl(mmio + HOST_VERSION);
365cfa1e 543 hpriv->port_map = port_map;
039ece38
HG		 544
545 if (!hpriv->start_engine)
546 hpriv->start_engine = ahci_start_engine;
f070d671 547
fa89f53b
EW		 548 if (!hpriv->stop_engine)
549 hpriv->stop_engine = ahci_stop_engine;
550
f070d671 551 if (!hpriv->irq_handler)
d867b95f 552 hpriv->irq_handler = ahci_single_level_irq_intr;
365cfa1e
AV		 553}
554EXPORT_SYMBOL_GPL(ahci_save_initial_config);
555
556/**
557 * ahci_restore_initial_config - Restore initial config
558 * @host: target ATA host
559 *
560 * Restore initial config stored by ahci_save_initial_config().
561 *
562 * LOCKING:
563 * None.
564 */
565static void ahci_restore_initial_config(struct ata_host *host)
566{
567 struct ahci_host_priv *hpriv = host->private_data;
568 void __iomem *mmio = hpriv->mmio;
569
570 writel(hpriv->saved_cap, mmio + HOST_CAP);
571 if (hpriv->saved_cap2)
572 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
573 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
574 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
575}
576
577static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
578{
579 static const int offset[] = {
580 [SCR_STATUS] = PORT_SCR_STAT,
581 [SCR_CONTROL] = PORT_SCR_CTL,
582 [SCR_ERROR] = PORT_SCR_ERR,
583 [SCR_ACTIVE] = PORT_SCR_ACT,
584 [SCR_NOTIFICATION] = PORT_SCR_NTF,
585 };
586 struct ahci_host_priv *hpriv = ap->host->private_data;
587
588 if (sc_reg < ARRAY_SIZE(offset) &&
589 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
590 return offset[sc_reg];
591 return 0;
592}
593
594static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
595{
596 void __iomem *port_mmio = ahci_port_base(link->ap);
597 int offset = ahci_scr_offset(link->ap, sc_reg);
598
599 if (offset) {
600 *val = readl(port_mmio + offset);
601 return 0;
602 }
603 return -EINVAL;
604}
605
606static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
607{
608 void __iomem *port_mmio = ahci_port_base(link->ap);
609 int offset = ahci_scr_offset(link->ap, sc_reg);
610
611 if (offset) {
612 writel(val, port_mmio + offset);
613 return 0;
614 }
615 return -EINVAL;
616}
617
618void ahci_start_engine(struct ata_port *ap)
619{
620 void __iomem *port_mmio = ahci_port_base(ap);
621 u32 tmp;
622
623 /* start DMA */
624 tmp = readl(port_mmio + PORT_CMD);
625 tmp |= PORT_CMD_START;
626 writel(tmp, port_mmio + PORT_CMD);
627 readl(port_mmio + PORT_CMD); /* flush */
628}
629EXPORT_SYMBOL_GPL(ahci_start_engine);
630
631int ahci_stop_engine(struct ata_port *ap)
632{
633 void __iomem *port_mmio = ahci_port_base(ap);
fb329633 634 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 635 u32 tmp;
636
fb329633
DP		 637 /*
638 * On some controllers, stopping a port's DMA engine while the port
639 * is in ALPM state (partial or slumber) results in failures on
640 * subsequent DMA engine starts. For those controllers, put the
641 * port back in active state before stopping its DMA engine.
642 */
643 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
644 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
645 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
646 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
647 return -EIO;
648 }
649
365cfa1e
AV		 650 tmp = readl(port_mmio + PORT_CMD);
651
652 /* check if the HBA is idle */
653 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
654 return 0;
655
3b61e512
SR		 656 /*
657 * Don't try to issue commands but return with ENODEV if the
658 * AHCI controller not available anymore (e.g. due to PCIe hot
659 * unplugging). Otherwise a 500ms delay for each port is added.
660 */
661 if (tmp == 0xffffffff) {
662 dev_err(ap->host->dev, "AHCI controller unavailable!\n");
663 return -ENODEV;
664 }
665
365cfa1e
AV		 666 /* setting HBA to idle */
667 tmp &= ~PORT_CMD_START;
668 writel(tmp, port_mmio + PORT_CMD);
669
670 /* wait for engine to stop. This could be as long as 500 msec */
97750ceb 671 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 672 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
673 if (tmp & PORT_CMD_LIST_ON)
674 return -EIO;
675
676 return 0;
677}
678EXPORT_SYMBOL_GPL(ahci_stop_engine);
679
39e0ee99 680void ahci_start_fis_rx(struct ata_port *ap)
365cfa1e
AV		 681{
682 void __iomem *port_mmio = ahci_port_base(ap);
683 struct ahci_host_priv *hpriv = ap->host->private_data;
684 struct ahci_port_priv *pp = ap->private_data;
685 u32 tmp;
686
687 /* set FIS registers */
688 if (hpriv->cap & HOST_CAP_64)
689 writel((pp->cmd_slot_dma >> 16) >> 16,
690 port_mmio + PORT_LST_ADDR_HI);
691 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
692
693 if (hpriv->cap & HOST_CAP_64)
694 writel((pp->rx_fis_dma >> 16) >> 16,
695 port_mmio + PORT_FIS_ADDR_HI);
696 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
697
698 /* enable FIS reception */
699 tmp = readl(port_mmio + PORT_CMD);
700 tmp |= PORT_CMD_FIS_RX;
701 writel(tmp, port_mmio + PORT_CMD);
702
703 /* flush */
704 readl(port_mmio + PORT_CMD);
705}
39e0ee99 706EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
365cfa1e
AV		 707
708static int ahci_stop_fis_rx(struct ata_port *ap)
709{
710 void __iomem *port_mmio = ahci_port_base(ap);
711 u32 tmp;
712
713 /* disable FIS reception */
714 tmp = readl(port_mmio + PORT_CMD);
715 tmp &= ~PORT_CMD_FIS_RX;
716 writel(tmp, port_mmio + PORT_CMD);
717
718 /* wait for completion, spec says 500ms, give it 1000 */
97750ceb 719 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
365cfa1e
AV		 720 PORT_CMD_FIS_ON, 10, 1000);
721 if (tmp & PORT_CMD_FIS_ON)
722 return -EBUSY;
723
724 return 0;
725}
726
727static void ahci_power_up(struct ata_port *ap)
728{
729 struct ahci_host_priv *hpriv = ap->host->private_data;
730 void __iomem *port_mmio = ahci_port_base(ap);
731 u32 cmd;
732
733 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
734
735 /* spin up device */
736 if (hpriv->cap & HOST_CAP_SSS) {
737 cmd |= PORT_CMD_SPIN_UP;
738 writel(cmd, port_mmio + PORT_CMD);
739 }
740
741 /* wake up link */
742 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
743}
744
6b7ae954
TH		 745static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
746 unsigned int hints)
365cfa1e 747{
6b7ae954 748 struct ata_port *ap = link->ap;
365cfa1e 749 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 750 struct ahci_port_priv *pp = ap->private_data;
365cfa1e 751 void __iomem *port_mmio = ahci_port_base(ap);
365cfa1e 752
6b7ae954 753 if (policy != ATA_LPM_MAX_POWER) {
fb329633
DP		 754 /* wakeup flag only applies to the max power policy */
755 hints &= ~ATA_LPM_WAKE_ONLY;
756
365cfa1e 757 /*
6b7ae954
TH		 758 * Disable interrupts on Phy Ready. This keeps us from
759 * getting woken up due to spurious phy ready
760 * interrupts.
365cfa1e 761 */
6b7ae954
TH		 762 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
763 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
764
765 sata_link_scr_lpm(link, policy, false);
365cfa1e
AV		 766 }
767
6b7ae954
TH		 768 if (hpriv->cap & HOST_CAP_ALPM) {
769 u32 cmd = readl(port_mmio + PORT_CMD);
365cfa1e 770
6b7ae954 771 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
fb329633
DP		 772 if (!(hints & ATA_LPM_WAKE_ONLY))
773 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
6b7ae954 774 cmd |= PORT_CMD_ICC_ACTIVE;
365cfa1e 775
6b7ae954
TH		 776 writel(cmd, port_mmio + PORT_CMD);
777 readl(port_mmio + PORT_CMD);
365cfa1e 778
6b7ae954 779 /* wait 10ms to be sure we've come out of LPM state */
97750ceb 780 ata_msleep(ap, 10);
fb329633
DP		 781
782 if (hints & ATA_LPM_WAKE_ONLY)
783 return 0;
6b7ae954
TH		 784 } else {
785 cmd |= PORT_CMD_ALPE;
786 if (policy == ATA_LPM_MIN_POWER)
787 cmd |= PORT_CMD_ASP;
a5ec5a7b
SP		 788 else if (policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
789 cmd &= ~PORT_CMD_ASP;
365cfa1e 790
6b7ae954
TH		 791 /* write out new cmd value */
792 writel(cmd, port_mmio + PORT_CMD);
793 }
794 }
365cfa1e 795
65fe1f0f
SH		 796 /* set aggressive device sleep */
797 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
798 (hpriv->cap2 & HOST_CAP2_SADM) &&
799 (link->device->flags & ATA_DFLAG_DEVSLP)) {
a5ec5a7b
SP		 800 if (policy == ATA_LPM_MIN_POWER ||
801 policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
65fe1f0f
SH		 802 ahci_set_aggressive_devslp(ap, true);
803 else
804 ahci_set_aggressive_devslp(ap, false);
805 }
806
6b7ae954
TH		 807 if (policy == ATA_LPM_MAX_POWER) {
808 sata_link_scr_lpm(link, policy, false);
809
810 /* turn PHYRDY IRQ back on */
811 pp->intr_mask |= PORT_IRQ_PHYRDY;
812 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
813 }
365cfa1e 814
365cfa1e
AV		 815 return 0;
816}
817
818#ifdef CONFIG_PM
819static void ahci_power_down(struct ata_port *ap)
820{
821 struct ahci_host_priv *hpriv = ap->host->private_data;
822 void __iomem *port_mmio = ahci_port_base(ap);
823 u32 cmd, scontrol;
824
825 if (!(hpriv->cap & HOST_CAP_SSS))
826 return;
827
828 /* put device into listen mode, first set PxSCTL.DET to 0 */
829 scontrol = readl(port_mmio + PORT_SCR_CTL);
830 scontrol &= ~0xf;
831 writel(scontrol, port_mmio + PORT_SCR_CTL);
832
833 /* then set PxCMD.SUD to 0 */
834 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
835 cmd &= ~PORT_CMD_SPIN_UP;
836 writel(cmd, port_mmio + PORT_CMD);
837}
838#endif
839
840static void ahci_start_port(struct ata_port *ap)
841{
66583c9f 842 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 843 struct ahci_port_priv *pp = ap->private_data;
844 struct ata_link *link;
845 struct ahci_em_priv *emp;
846 ssize_t rc;
847 int i;
848
849 /* enable FIS reception */
850 ahci_start_fis_rx(ap);
851
66583c9f
BN		 852 /* enable DMA */
853 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
039ece38 854 hpriv->start_engine(ap);
66583c9f 855
365cfa1e
AV		 856 /* turn on LEDs */
857 if (ap->flags & ATA_FLAG_EM) {
858 ata_for_each_link(link, ap, EDGE) {
859 emp = &pp->em_priv[link->pmp];
860
861 /* EM Transmit bit maybe busy during init */
862 for (i = 0; i < EM_MAX_RETRY; i++) {
439d7a35 863 rc = ap->ops->transmit_led_message(ap,
365cfa1e
AV		 864 emp->led_state,
865 4);
fa070ee6
LD		 866 /*
867 * If busy, give a breather but do not
868 * release EH ownership by using msleep()
869 * instead of ata_msleep(). EM Transmit
870 * bit is busy for the whole host and
871 * releasing ownership will cause other
872 * ports to fail the same way.
873 */
365cfa1e 874 if (rc == -EBUSY)
fa070ee6 875 msleep(1);
365cfa1e
AV		 876 else
877 break;
878 }
879 }
880 }
881
882 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
883 ata_for_each_link(link, ap, EDGE)
884 ahci_init_sw_activity(link);
885
886}
887
888static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
889{
890 int rc;
fa89f53b 891 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 892
893 /* disable DMA */
fa89f53b 894 rc = hpriv->stop_engine(ap);
365cfa1e
AV		 895 if (rc) {
896 *emsg = "failed to stop engine";
897 return rc;
898 }
899
900 /* disable FIS reception */
901 rc = ahci_stop_fis_rx(ap);
902 if (rc) {
903 *emsg = "failed stop FIS RX";
904 return rc;
905 }
906
907 return 0;
908}
909
910int ahci_reset_controller(struct ata_host *host)
911{
912 struct ahci_host_priv *hpriv = host->private_data;
913 void __iomem *mmio = hpriv->mmio;
914 u32 tmp;
915
916 /* we must be in AHCI mode, before using anything
917 * AHCI-specific, such as HOST_RESET.
918 */
919 ahci_enable_ahci(mmio);
920
921 /* global controller reset */
922 if (!ahci_skip_host_reset) {
923 tmp = readl(mmio + HOST_CTL);
924 if ((tmp & HOST_RESET) == 0) {
925 writel(tmp | HOST_RESET, mmio + HOST_CTL);
926 readl(mmio + HOST_CTL); /* flush */
927 }
928
929 /*
930 * to perform host reset, OS should set HOST_RESET
931 * and poll until this bit is read to be "0".
932 * reset must complete within 1 second, or
933 * the hardware should be considered fried.
934 */
97750ceb 935 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
365cfa1e
AV		 936 HOST_RESET, 10, 1000);
937
938 if (tmp & HOST_RESET) {
a44fec1f
JP		 939 dev_err(host->dev, "controller reset failed (0x%x)\n",
940 tmp);
365cfa1e
AV		 941 return -EIO;
942 }
943
944 /* turn on AHCI mode */
945 ahci_enable_ahci(mmio);
946
947 /* Some registers might be cleared on reset. Restore
948 * initial values.
949 */
7fab72f8
DB		 950 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO))
951 ahci_restore_initial_config(host);
365cfa1e 952 } else
a44fec1f 953 dev_info(host->dev, "skipping global host reset\n");
365cfa1e
AV		 954
955 return 0;
956}
957EXPORT_SYMBOL_GPL(ahci_reset_controller);
958
959static void ahci_sw_activity(struct ata_link *link)
960{
961 struct ata_port *ap = link->ap;
962 struct ahci_port_priv *pp = ap->private_data;
963 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
964
965 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
966 return;
967
968 emp->activity++;
969 if (!timer_pending(&emp->timer))
970 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
971}
972
1843594c 973static void ahci_sw_activity_blink(struct timer_list *t)
365cfa1e 974{
1843594c
KC		 975 struct ahci_em_priv *emp = from_timer(emp, t, timer);
976 struct ata_link *link = emp->link;
365cfa1e 977 struct ata_port *ap = link->ap;
1843594c 978
365cfa1e
AV		 979 unsigned long led_message = emp->led_state;
980 u32 activity_led_state;
981 unsigned long flags;
982
983 led_message &= EM_MSG_LED_VALUE;
984 led_message |= ap->port_no | (link->pmp << 8);
985
986 /* check to see if we've had activity. If so,
987 * toggle state of LED and reset timer. If not,
988 * turn LED to desired idle state.
989 */
990 spin_lock_irqsave(ap->lock, flags);
991 if (emp->saved_activity != emp->activity) {
992 emp->saved_activity = emp->activity;
993 /* get the current LED state */
994 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
995
996 if (activity_led_state)
997 activity_led_state = 0;
998 else
999 activity_led_state = 1;
1000
1001 /* clear old state */
1002 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1003
1004 /* toggle state */
1005 led_message |= (activity_led_state << 16);
1006 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1007 } else {
1008 /* switch to idle */
1009 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1010 if (emp->blink_policy == BLINK_OFF)
1011 led_message |= (1 << 16);
1012 }
1013 spin_unlock_irqrestore(ap->lock, flags);
439d7a35 1014 ap->ops->transmit_led_message(ap, led_message, 4);
365cfa1e
AV		 1015}
1016
1017static void ahci_init_sw_activity(struct ata_link *link)
1018{
1019 struct ata_port *ap = link->ap;
1020 struct ahci_port_priv *pp = ap->private_data;
1021 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1022
1023 /* init activity stats, setup timer */
1024 emp->saved_activity = emp->activity = 0;
1843594c
KC		 1025 emp->link = link;
1026 timer_setup(&emp->timer, ahci_sw_activity_blink, 0);
365cfa1e
AV		 1027
1028 /* check our blink policy and set flag for link if it's enabled */
1029 if (emp->blink_policy)
1030 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1031}
1032
1033int ahci_reset_em(struct ata_host *host)
1034{
1035 struct ahci_host_priv *hpriv = host->private_data;
1036 void __iomem *mmio = hpriv->mmio;
1037 u32 em_ctl;
1038
1039 em_ctl = readl(mmio + HOST_EM_CTL);
1040 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1041 return -EINVAL;
1042
1043 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1044 return 0;
1045}
1046EXPORT_SYMBOL_GPL(ahci_reset_em);
1047
1048static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1049 ssize_t size)
1050{
1051 struct ahci_host_priv *hpriv = ap->host->private_data;
1052 struct ahci_port_priv *pp = ap->private_data;
1053 void __iomem *mmio = hpriv->mmio;
1054 u32 em_ctl;
1055 u32 message[] = {0, 0};
1056 unsigned long flags;
1057 int pmp;
1058 struct ahci_em_priv *emp;
1059
1060 /* get the slot number from the message */
1061 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1062 if (pmp < EM_MAX_SLOTS)
1063 emp = &pp->em_priv[pmp];
1064 else
1065 return -EINVAL;
1066
bb03c640 1067 ahci_rpm_get_port(ap);
365cfa1e
AV		 1068 spin_lock_irqsave(ap->lock, flags);
1069
1070 /*
1071 * if we are still busy transmitting a previous message,
1072 * do not allow
1073 */
1074 em_ctl = readl(mmio + HOST_EM_CTL);
1075 if (em_ctl & EM_CTL_TM) {
1076 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 1077 ahci_rpm_put_port(ap);
365cfa1e
AV		 1078 return -EBUSY;
1079 }
1080
008dbd61
HZ		 1081 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1082 /*
1083 * create message header - this is all zero except for
1084 * the message size, which is 4 bytes.
1085 */
1086 message[0] |= (4 << 8);
365cfa1e 1087
008dbd61
HZ		 1088 /* ignore 0:4 of byte zero, fill in port info yourself */
1089 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
365cfa1e 1090
008dbd61
HZ		 1091 /* write message to EM_LOC */
1092 writel(message[0], mmio + hpriv->em_loc);
1093 writel(message[1], mmio + hpriv->em_loc+4);
1094
1095 /*
1096 * tell hardware to transmit the message
1097 */
1098 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1099 }
365cfa1e
AV		 1100
1101 /* save off new led state for port/slot */
1102 emp->led_state = state;
1103
365cfa1e 1104 spin_unlock_irqrestore(ap->lock, flags);
bb03c640
MW		 1105 ahci_rpm_put_port(ap);
1106
365cfa1e
AV		 1107 return size;
1108}
1109
1110static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1111{
1112 struct ahci_port_priv *pp = ap->private_data;
1113 struct ata_link *link;
1114 struct ahci_em_priv *emp;
1115 int rc = 0;
1116
1117 ata_for_each_link(link, ap, EDGE) {
1118 emp = &pp->em_priv[link->pmp];
1119 rc += sprintf(buf, "%lx\n", emp->led_state);
1120 }
1121 return rc;
1122}
1123
1124static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1125 size_t size)
1126{
b2a52b6a 1127 unsigned int state;
365cfa1e
AV		 1128 int pmp;
1129 struct ahci_port_priv *pp = ap->private_data;
1130 struct ahci_em_priv *emp;
1131
b2a52b6a
DY		 1132 if (kstrtouint(buf, 0, &state) < 0)
1133 return -EINVAL;
365cfa1e
AV		 1134
1135 /* get the slot number from the message */
1136 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
fae2a637
JG		 1137 if (pmp < EM_MAX_SLOTS) {
1138 pmp = array_index_nospec(pmp, EM_MAX_SLOTS);
365cfa1e 1139 emp = &pp->em_priv[pmp];
fae2a637 1140 } else {
365cfa1e 1141 return -EINVAL;
fae2a637 1142 }
365cfa1e
AV		 1143
1144 /* mask off the activity bits if we are in sw_activity
1145 * mode, user should turn off sw_activity before setting
1146 * activity led through em_message
1147 */
1148 if (emp->blink_policy)
1149 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1150
439d7a35 1151 return ap->ops->transmit_led_message(ap, state, size);
365cfa1e
AV		 1152}
1153
1154static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1155{
1156 struct ata_link *link = dev->link;
1157 struct ata_port *ap = link->ap;
1158 struct ahci_port_priv *pp = ap->private_data;
1159 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1160 u32 port_led_state = emp->led_state;
1161
1162 /* save the desired Activity LED behavior */
1163 if (val == OFF) {
1164 /* clear LFLAG */
1165 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1166
1167 /* set the LED to OFF */
1168 port_led_state &= EM_MSG_LED_VALUE_OFF;
1169 port_led_state |= (ap->port_no | (link->pmp << 8));
439d7a35 1170 ap->ops->transmit_led_message(ap, port_led_state, 4);
365cfa1e
AV		 1171 } else {
1172 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1173 if (val == BLINK_OFF) {
1174 /* set LED to ON for idle */
1175 port_led_state &= EM_MSG_LED_VALUE_OFF;
1176 port_led_state |= (ap->port_no | (link->pmp << 8));
1177 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
439d7a35 1178 ap->ops->transmit_led_message(ap, port_led_state, 4);
365cfa1e
AV		 1179 }
1180 }
1181 emp->blink_policy = val;
1182 return 0;
1183}
1184
1185static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1186{
1187 struct ata_link *link = dev->link;
1188 struct ata_port *ap = link->ap;
1189 struct ahci_port_priv *pp = ap->private_data;
1190 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1191
1192 /* display the saved value of activity behavior for this
1193 * disk.
1194 */
1195 return sprintf(buf, "%d\n", emp->blink_policy);
1196}
1197
1198static void ahci_port_init(struct device *dev, struct ata_port *ap,
1199 int port_no, void __iomem *mmio,
1200 void __iomem *port_mmio)
1201{
8a3e33cf 1202 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 1203 const char *emsg = NULL;
1204 int rc;
1205 u32 tmp;
1206
1207 /* make sure port is not active */
1208 rc = ahci_deinit_port(ap, &emsg);
1209 if (rc)
1210 dev_warn(dev, "%s (%d)\n", emsg, rc);
1211
1212 /* clear SError */
1213 tmp = readl(port_mmio + PORT_SCR_ERR);
1214 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1215 writel(tmp, port_mmio + PORT_SCR_ERR);
1216
1217 /* clear port IRQ */
1218 tmp = readl(port_mmio + PORT_IRQ_STAT);
1219 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1220 if (tmp)
1221 writel(tmp, port_mmio + PORT_IRQ_STAT);
1222
1223 writel(1 << port_no, mmio + HOST_IRQ_STAT);
8a3e33cf
ML		 1224
1225 /* mark esata ports */
1226 tmp = readl(port_mmio + PORT_CMD);
dc8b4afc 1227 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
8a3e33cf 1228 ap->pflags |= ATA_PFLAG_EXTERNAL;
365cfa1e
AV		 1229}
1230
1231void ahci_init_controller(struct ata_host *host)
1232{
1233 struct ahci_host_priv *hpriv = host->private_data;
1234 void __iomem *mmio = hpriv->mmio;
1235 int i;
1236 void __iomem *port_mmio;
1237 u32 tmp;
1238
1239 for (i = 0; i < host->n_ports; i++) {
1240 struct ata_port *ap = host->ports[i];
1241
1242 port_mmio = ahci_port_base(ap);
1243 if (ata_port_is_dummy(ap))
1244 continue;
1245
1246 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1247 }
1248
1249 tmp = readl(mmio + HOST_CTL);
1250 VPRINTK("HOST_CTL 0x%x\n", tmp);
1251 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1252 tmp = readl(mmio + HOST_CTL);
1253 VPRINTK("HOST_CTL 0x%x\n", tmp);
1254}
1255EXPORT_SYMBOL_GPL(ahci_init_controller);
1256
1257static void ahci_dev_config(struct ata_device *dev)
1258{
1259 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1260
1261 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1262 dev->max_sectors = 255;
a9a79dfe
JP		 1263 ata_dev_info(dev,
1264 "SB600 AHCI: limiting to 255 sectors per cmd\n");
365cfa1e
AV		 1265 }
1266}
1267
bbb4ab43 1268unsigned int ahci_dev_classify(struct ata_port *ap)
365cfa1e
AV		 1269{
1270 void __iomem *port_mmio = ahci_port_base(ap);
1271 struct ata_taskfile tf;
1272 u32 tmp;
1273
1274 tmp = readl(port_mmio + PORT_SIG);
1275 tf.lbah = (tmp >> 24) & 0xff;
1276 tf.lbam = (tmp >> 16) & 0xff;
1277 tf.lbal = (tmp >> 8) & 0xff;
1278 tf.nsect = (tmp) & 0xff;
1279
1280 return ata_dev_classify(&tf);
1281}
bbb4ab43 1282EXPORT_SYMBOL_GPL(ahci_dev_classify);
365cfa1e 1283
02cdfcf0
DM		 1284void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1285 u32 opts)
365cfa1e
AV		 1286{
1287 dma_addr_t cmd_tbl_dma;
1288
1289 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1290
1291 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1292 pp->cmd_slot[tag].status = 0;
1293 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1294 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1295}
02cdfcf0 1296EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
365cfa1e
AV		 1297
1298int ahci_kick_engine(struct ata_port *ap)
1299{
1300 void __iomem *port_mmio = ahci_port_base(ap);
1301 struct ahci_host_priv *hpriv = ap->host->private_data;
1302 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1303 u32 tmp;
1304 int busy, rc;
1305
1306 /* stop engine */
fa89f53b 1307 rc = hpriv->stop_engine(ap);
365cfa1e
AV		 1308 if (rc)
1309 goto out_restart;
1310
1311 /* need to do CLO?
1312 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1313 */
1314 busy = status & (ATA_BUSY | ATA_DRQ);
1315 if (!busy && !sata_pmp_attached(ap)) {
1316 rc = 0;
1317 goto out_restart;
1318 }
1319
1320 if (!(hpriv->cap & HOST_CAP_CLO)) {
1321 rc = -EOPNOTSUPP;
1322 goto out_restart;
1323 }
1324
1325 /* perform CLO */
1326 tmp = readl(port_mmio + PORT_CMD);
1327 tmp |= PORT_CMD_CLO;
1328 writel(tmp, port_mmio + PORT_CMD);
1329
1330 rc = 0;
97750ceb 1331 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 1332 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1333 if (tmp & PORT_CMD_CLO)
1334 rc = -EIO;
1335
1336 /* restart engine */
1337 out_restart:
039ece38 1338 hpriv->start_engine(ap);
365cfa1e
AV		 1339 return rc;
1340}
1341EXPORT_SYMBOL_GPL(ahci_kick_engine);
1342
1343static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1344 struct ata_taskfile *tf, int is_cmd, u16 flags,
1345 unsigned long timeout_msec)
1346{
1347 const u32 cmd_fis_len = 5; /* five dwords */
1348 struct ahci_port_priv *pp = ap->private_data;
1349 void __iomem *port_mmio = ahci_port_base(ap);
1350 u8 *fis = pp->cmd_tbl;
1351 u32 tmp;
1352
1353 /* prep the command */
1354 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1355 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1356
023113d2
XY		 1357 /* set port value for softreset of Port Multiplier */
1358 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1359 tmp = readl(port_mmio + PORT_FBS);
1360 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1361 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1362 writel(tmp, port_mmio + PORT_FBS);
1363 pp->fbs_last_dev = pmp;
1364 }
1365
365cfa1e
AV		 1366 /* issue & wait */
1367 writel(1, port_mmio + PORT_CMD_ISSUE);
1368
1369 if (timeout_msec) {
97750ceb
TH		 1370 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1371 0x1, 0x1, 1, timeout_msec);
365cfa1e
AV		 1372 if (tmp & 0x1) {
1373 ahci_kick_engine(ap);
1374 return -EBUSY;
1375 }
1376 } else
1377 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1378
1379 return 0;
1380}
1381
1382int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1383 int pmp, unsigned long deadline,
1384 int (*check_ready)(struct ata_link *link))
1385{
1386 struct ata_port *ap = link->ap;
1387 struct ahci_host_priv *hpriv = ap->host->private_data;
89dafa20 1388 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 1389 const char *reason = NULL;
1390 unsigned long now, msecs;
1391 struct ata_taskfile tf;
89dafa20 1392 bool fbs_disabled = false;
365cfa1e
AV		 1393 int rc;
1394
1395 DPRINTK("ENTER\n");
1396
1397 /* prepare for SRST (AHCI-1.1 10.4.1) */
1398 rc = ahci_kick_engine(ap);
1399 if (rc && rc != -EOPNOTSUPP)
a9a79dfe 1400 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
365cfa1e 1401
89dafa20 1402 /*
1403 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1404 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1405 * that is attached to port multiplier.
1406 */
1407 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1408 ahci_disable_fbs(ap);
1409 fbs_disabled = true;
1410 }
1411
365cfa1e
AV		 1412 ata_tf_init(link->device, &tf);
1413
08fc4756 1414 /* issue the first H2D Register FIS */
365cfa1e
AV		 1415 msecs = 0;
1416 now = jiffies;
f1f5a807 1417 if (time_after(deadline, now))
365cfa1e
AV		 1418 msecs = jiffies_to_msecs(deadline - now);
1419
1420 tf.ctl |= ATA_SRST;
1421 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1422 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1423 rc = -EIO;
1424 reason = "1st FIS failed";
1425 goto fail;
1426 }
1427
1428 /* spec says at least 5us, but be generous and sleep for 1ms */
97750ceb 1429 ata_msleep(ap, 1);
365cfa1e 1430
08fc4756 1431 /* issue the second H2D Register FIS */
365cfa1e
AV		 1432 tf.ctl &= ~ATA_SRST;
1433 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1434
1435 /* wait for link to become ready */
1436 rc = ata_wait_after_reset(link, deadline, check_ready);
1437 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1438 /*
1439 * Workaround for cases where link online status can't
1440 * be trusted. Treat device readiness timeout as link
1441 * offline.
1442 */
a9a79dfe 1443 ata_link_info(link, "device not ready, treating as offline\n");
365cfa1e
AV		 1444 *class = ATA_DEV_NONE;
1445 } else if (rc) {
1446 /* link occupied, -ENODEV too is an error */
1447 reason = "device not ready";
1448 goto fail;
1449 } else
1450 *class = ahci_dev_classify(ap);
1451
89dafa20 1452 /* re-enable FBS if disabled before */
1453 if (fbs_disabled)
1454 ahci_enable_fbs(ap);
1455
365cfa1e
AV		 1456 DPRINTK("EXIT, class=%u\n", *class);
1457 return 0;
1458
1459 fail:
a9a79dfe 1460 ata_link_err(link, "softreset failed (%s)\n", reason);
365cfa1e
AV		 1461 return rc;
1462}
1463
1464int ahci_check_ready(struct ata_link *link)
1465{
1466 void __iomem *port_mmio = ahci_port_base(link->ap);
1467 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1468
1469 return ata_check_ready(status);
1470}
1471EXPORT_SYMBOL_GPL(ahci_check_ready);
1472
1473static int ahci_softreset(struct ata_link *link, unsigned int *class,
1474 unsigned long deadline)
1475{
1476 int pmp = sata_srst_pmp(link);
1477
1478 DPRINTK("ENTER\n");
1479
1480 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1481}
1482EXPORT_SYMBOL_GPL(ahci_do_softreset);
1483
345347c5
YHC		 1484static int ahci_bad_pmp_check_ready(struct ata_link *link)
1485{
1486 void __iomem *port_mmio = ahci_port_base(link->ap);
1487 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1488 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1489
1490 /*
1491 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1492 * which can save timeout delay.
1493 */
1494 if (irq_status & PORT_IRQ_BAD_PMP)
1495 return -EIO;
1496
1497 return ata_check_ready(status);
1498}
1499
35186d05
DY		 1500static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1501 unsigned long deadline)
345347c5
YHC		 1502{
1503 struct ata_port *ap = link->ap;
1504 void __iomem *port_mmio = ahci_port_base(ap);
1505 int pmp = sata_srst_pmp(link);
1506 int rc;
1507 u32 irq_sts;
1508
1509 DPRINTK("ENTER\n");
1510
1511 rc = ahci_do_softreset(link, class, pmp, deadline,
1512 ahci_bad_pmp_check_ready);
1513
1514 /*
1515 * Soft reset fails with IPMS set when PMP is enabled but
1516 * SATA HDD/ODD is connected to SATA port, do soft reset
1517 * again to port 0.
1518 */
1519 if (rc == -EIO) {
1520 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1521 if (irq_sts & PORT_IRQ_BAD_PMP) {
39f80acb 1522 ata_link_warn(link,
345347c5
YHC		 1523 "applying PMP SRST workaround "
1524 "and retrying\n");
1525 rc = ahci_do_softreset(link, class, 0, deadline,
1526 ahci_check_ready);
1527 }
1528 }
1529
1530 return rc;
1531}
1532
d436501e
BG		 1533int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
1534 unsigned long deadline, bool *online)
365cfa1e
AV		 1535{
1536 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1537 struct ata_port *ap = link->ap;
1538 struct ahci_port_priv *pp = ap->private_data;
039ece38 1539 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 1540 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1541 struct ata_taskfile tf;
365cfa1e
AV		 1542 int rc;
1543
1544 DPRINTK("ENTER\n");
1545
fa89f53b 1546 hpriv->stop_engine(ap);
365cfa1e
AV		 1547
1548 /* clear D2H reception area to properly wait for D2H FIS */
1549 ata_tf_init(link->device, &tf);
9bbb1b0e 1550 tf.command = ATA_BUSY;
365cfa1e
AV		 1551 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1552
d436501e 1553 rc = sata_link_hardreset(link, timing, deadline, online,
365cfa1e
AV		 1554 ahci_check_ready);
1555
039ece38 1556 hpriv->start_engine(ap);
365cfa1e 1557
d436501e 1558 if (*online)
365cfa1e
AV		 1559 *class = ahci_dev_classify(ap);
1560
1561 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1562 return rc;
1563}
d436501e
BG		 1564EXPORT_SYMBOL_GPL(ahci_do_hardreset);
1565
1566static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1567 unsigned long deadline)
1568{
1569 bool online;
1570
1571 return ahci_do_hardreset(link, class, deadline, &online);
1572}
365cfa1e
AV		 1573
1574static void ahci_postreset(struct ata_link *link, unsigned int *class)
1575{
1576 struct ata_port *ap = link->ap;
1577 void __iomem *port_mmio = ahci_port_base(ap);
1578 u32 new_tmp, tmp;
1579
1580 ata_std_postreset(link, class);
1581
1582 /* Make sure port's ATAPI bit is set appropriately */
1583 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1584 if (*class == ATA_DEV_ATAPI)
1585 new_tmp |= PORT_CMD_ATAPI;
1586 else
1587 new_tmp &= ~PORT_CMD_ATAPI;
1588 if (new_tmp != tmp) {
1589 writel(new_tmp, port_mmio + PORT_CMD);
1590 readl(port_mmio + PORT_CMD); /* flush */
1591 }
1592}
1593
1594static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1595{
1596 struct scatterlist *sg;
1597 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1598 unsigned int si;
1599
1600 VPRINTK("ENTER\n");
1601
1602 /*
1603 * Next, the S/G list.
1604 */
1605 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1606 dma_addr_t addr = sg_dma_address(sg);
1607 u32 sg_len = sg_dma_len(sg);
1608
1609 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1610 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1611 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1612 }
1613
1614 return si;
1615}
1616
1617static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1618{
1619 struct ata_port *ap = qc->ap;
1620 struct ahci_port_priv *pp = ap->private_data;
1621
1622 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1623 return ata_std_qc_defer(qc);
1624 else
1625 return sata_pmp_qc_defer_cmd_switch(qc);
1626}
1627
1628static void ahci_qc_prep(struct ata_queued_cmd *qc)
1629{
1630 struct ata_port *ap = qc->ap;
1631 struct ahci_port_priv *pp = ap->private_data;
1632 int is_atapi = ata_is_atapi(qc->tf.protocol);
1633 void *cmd_tbl;
1634 u32 opts;
1635 const u32 cmd_fis_len = 5; /* five dwords */
1636 unsigned int n_elem;
1637
1638 /*
1639 * Fill in command table information. First, the header,
1640 * a SATA Register - Host to Device command FIS.
1641 */
4e5b6260 1642 cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ;
365cfa1e
AV		 1643
1644 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1645 if (is_atapi) {
1646 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1647 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1648 }
1649
1650 n_elem = 0;
1651 if (qc->flags & ATA_QCFLAG_DMAMAP)
1652 n_elem = ahci_fill_sg(qc, cmd_tbl);
1653
1654 /*
1655 * Fill in command slot information.
1656 */
1657 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1658 if (qc->tf.flags & ATA_TFLAG_WRITE)
1659 opts |= AHCI_CMD_WRITE;
1660 if (is_atapi)
1661 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1662
4e5b6260 1663 ahci_fill_cmd_slot(pp, qc->hw_tag, opts);
365cfa1e
AV		 1664}
1665
1666static void ahci_fbs_dec_intr(struct ata_port *ap)
1667{
1668 struct ahci_port_priv *pp = ap->private_data;
1669 void __iomem *port_mmio = ahci_port_base(ap);
1670 u32 fbs = readl(port_mmio + PORT_FBS);
1671 int retries = 3;
1672
1673 DPRINTK("ENTER\n");
1674 BUG_ON(!pp->fbs_enabled);
1675
1676 /* time to wait for DEC is not specified by AHCI spec,
1677 * add a retry loop for safety.
1678 */
1679 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1680 fbs = readl(port_mmio + PORT_FBS);
1681 while ((fbs & PORT_FBS_DEC) && retries--) {
1682 udelay(1);
1683 fbs = readl(port_mmio + PORT_FBS);
1684 }
1685
1686 if (fbs & PORT_FBS_DEC)
a44fec1f 1687 dev_err(ap->host->dev, "failed to clear device error\n");
365cfa1e
AV		 1688}
1689
1690static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1691{
1692 struct ahci_host_priv *hpriv = ap->host->private_data;
1693 struct ahci_port_priv *pp = ap->private_data;
1694 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1695 struct ata_link *link = NULL;
1696 struct ata_queued_cmd *active_qc;
1697 struct ata_eh_info *active_ehi;
1698 bool fbs_need_dec = false;
1699 u32 serror;
1700
1701 /* determine active link with error */
1702 if (pp->fbs_enabled) {
1703 void __iomem *port_mmio = ahci_port_base(ap);
1704 u32 fbs = readl(port_mmio + PORT_FBS);
1705 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1706
912b9ac6 1707 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
365cfa1e
AV		 1708 link = &ap->pmp_link[pmp];
1709 fbs_need_dec = true;
1710 }
1711
1712 } else
1713 ata_for_each_link(link, ap, EDGE)
1714 if (ata_link_active(link))
1715 break;
1716
1717 if (!link)
1718 link = &ap->link;
1719
1720 active_qc = ata_qc_from_tag(ap, link->active_tag);
1721 active_ehi = &link->eh_info;
1722
1723 /* record irq stat */
1724 ata_ehi_clear_desc(host_ehi);
1725 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1726
1727 /* AHCI needs SError cleared; otherwise, it might lock up */
1728 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1729 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1730 host_ehi->serror |= serror;
1731
1732 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1733 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1734 irq_stat &= ~PORT_IRQ_IF_ERR;
1735
1736 if (irq_stat & PORT_IRQ_TF_ERR) {
1737 /* If qc is active, charge it; otherwise, the active
1738 * link. There's no active qc on NCQ errors. It will
1739 * be determined by EH by reading log page 10h.
1740 */
1741 if (active_qc)
1742 active_qc->err_mask |= AC_ERR_DEV;
1743 else
1744 active_ehi->err_mask |= AC_ERR_DEV;
1745
1746 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1747 host_ehi->serror &= ~SERR_INTERNAL;
1748 }
1749
1750 if (irq_stat & PORT_IRQ_UNK_FIS) {
d5185d65 1751 u32 *unk = pp->rx_fis + RX_FIS_UNK;
365cfa1e
AV		 1752
1753 active_ehi->err_mask |= AC_ERR_HSM;
1754 active_ehi->action |= ATA_EH_RESET;
1755 ata_ehi_push_desc(active_ehi,
1756 "unknown FIS %08x %08x %08x %08x" ,
1757 unk[0], unk[1], unk[2], unk[3]);
1758 }
1759
1760 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1761 active_ehi->err_mask |= AC_ERR_HSM;
1762 active_ehi->action |= ATA_EH_RESET;
1763 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1764 }
1765
1766 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1767 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1768 host_ehi->action |= ATA_EH_RESET;
1769 ata_ehi_push_desc(host_ehi, "host bus error");
1770 }
1771
1772 if (irq_stat & PORT_IRQ_IF_ERR) {
1773 if (fbs_need_dec)
1774 active_ehi->err_mask |= AC_ERR_DEV;
1775 else {
1776 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1777 host_ehi->action |= ATA_EH_RESET;
1778 }
1779
1780 ata_ehi_push_desc(host_ehi, "interface fatal error");
1781 }
1782
1783 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1784 ata_ehi_hotplugged(host_ehi);
1785 ata_ehi_push_desc(host_ehi, "%s",
1786 irq_stat & PORT_IRQ_CONNECT ?
1787 "connection status changed" : "PHY RDY changed");
1788 }
1789
1790 /* okay, let's hand over to EH */
1791
1792 if (irq_stat & PORT_IRQ_FREEZE)
1793 ata_port_freeze(ap);
1794 else if (fbs_need_dec) {
1795 ata_link_abort(link);
1796 ahci_fbs_dec_intr(ap);
1797 } else
1798 ata_port_abort(ap);
1799}
1800
5ca72c4f
AG		 1801static void ahci_handle_port_interrupt(struct ata_port *ap,
1802 void __iomem *port_mmio, u32 status)
365cfa1e 1803{
365cfa1e
AV		 1804 struct ata_eh_info *ehi = &ap->link.eh_info;
1805 struct ahci_port_priv *pp = ap->private_data;
1806 struct ahci_host_priv *hpriv = ap->host->private_data;
1807 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
5ca72c4f 1808 u32 qc_active = 0;
365cfa1e
AV		 1809 int rc;
1810
365cfa1e
AV		 1811 /* ignore BAD_PMP while resetting */
1812 if (unlikely(resetting))
1813 status &= ~PORT_IRQ_BAD_PMP;
1814
8393b811 1815 if (sata_lpm_ignore_phy_events(&ap->link)) {
365cfa1e 1816 status &= ~PORT_IRQ_PHYRDY;
6b7ae954 1817 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
365cfa1e
AV		 1818 }
1819
1820 if (unlikely(status & PORT_IRQ_ERROR)) {
1821 ahci_error_intr(ap, status);
1822 return;
1823 }
1824
1825 if (status & PORT_IRQ_SDB_FIS) {
1826 /* If SNotification is available, leave notification
1827 * handling to sata_async_notification(). If not,
1828 * emulate it by snooping SDB FIS RX area.
1829 *
1830 * Snooping FIS RX area is probably cheaper than
1831 * poking SNotification but some constrollers which
1832 * implement SNotification, ICH9 for example, don't
1833 * store AN SDB FIS into receive area.
1834 */
1835 if (hpriv->cap & HOST_CAP_SNTF)
1836 sata_async_notification(ap);
1837 else {
1838 /* If the 'N' bit in word 0 of the FIS is set,
1839 * we just received asynchronous notification.
1840 * Tell libata about it.
1841 *
1842 * Lack of SNotification should not appear in
1843 * ahci 1.2, so the workaround is unnecessary
1844 * when FBS is enabled.
1845 */
1846 if (pp->fbs_enabled)
1847 WARN_ON_ONCE(1);
1848 else {
1849 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1850 u32 f0 = le32_to_cpu(f[0]);
1851 if (f0 & (1 << 15))
1852 sata_async_notification(ap);
1853 }
1854 }
1855 }
1856
1857 /* pp->active_link is not reliable once FBS is enabled, both
1858 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1859 * NCQ and non-NCQ commands may be in flight at the same time.
1860 */
1861 if (pp->fbs_enabled) {
1862 if (ap->qc_active) {
1863 qc_active = readl(port_mmio + PORT_SCR_ACT);
1864 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1865 }
1866 } else {
1867 /* pp->active_link is valid iff any command is in flight */
1868 if (ap->qc_active && pp->active_link->sactive)
1869 qc_active = readl(port_mmio + PORT_SCR_ACT);
1870 else
1871 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1872 }
1873
1874
1875 rc = ata_qc_complete_multiple(ap, qc_active);
1876
1877 /* while resetting, invalid completions are expected */
1878 if (unlikely(rc < 0 && !resetting)) {
1879 ehi->err_mask |= AC_ERR_HSM;
1880 ehi->action |= ATA_EH_RESET;
1881 ata_port_freeze(ap);
1882 }
1883}
1884
7865f83f 1885static void ahci_port_intr(struct ata_port *ap)
5ca72c4f
AG		 1886{
1887 void __iomem *port_mmio = ahci_port_base(ap);
1888 u32 status;
1889
1890 status = readl(port_mmio + PORT_IRQ_STAT);
1891 writel(status, port_mmio + PORT_IRQ_STAT);
1892
7865f83f 1893 ahci_handle_port_interrupt(ap, port_mmio, status);
5ca72c4f
AG		 1894}
1895
a6b7fb76 1896static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
5ca72c4f
AG		 1897{
1898 struct ata_port *ap = dev_instance;
5ca72c4f 1899 void __iomem *port_mmio = ahci_port_base(ap);
5ca72c4f
AG		 1900 u32 status;
1901
5ca72c4f
AG		 1902 VPRINTK("ENTER\n");
1903
227dfb4d
AG		 1904 status = readl(port_mmio + PORT_IRQ_STAT);
1905 writel(status, port_mmio + PORT_IRQ_STAT);
5ca72c4f 1906
a6b7fb76
DW		 1907 spin_lock(ap->lock);
1908 ahci_handle_port_interrupt(ap, port_mmio, status);
1909 spin_unlock(ap->lock);
5ca72c4f
AG		 1910
1911 VPRINTK("EXIT\n");
1912
a6b7fb76 1913 return IRQ_HANDLED;
5ca72c4f 1914}
5ca72c4f 1915
f070d671 1916u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
365cfa1e 1917{
365cfa1e 1918 unsigned int i, handled = 0;
03e83cbd 1919
365cfa1e
AV		 1920 for (i = 0; i < host->n_ports; i++) {
1921 struct ata_port *ap;
1922
1923 if (!(irq_masked & (1 << i)))
1924 continue;
1925
1926 ap = host->ports[i];
1927 if (ap) {
7865f83f 1928 ahci_port_intr(ap);
365cfa1e
AV		 1929 VPRINTK("port %u\n", i);
1930 } else {
1931 VPRINTK("port %u (no irq)\n", i);
1932 if (ata_ratelimit())
a44fec1f
JP		 1933 dev_warn(host->dev,
1934 "interrupt on disabled port %u\n", i);
365cfa1e
AV		 1935 }
1936
1937 handled = 1;
1938 }
1939
a129db89
ST		 1940 return handled;
1941}
f070d671 1942EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
a129db89
ST		 1943
1944static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1945{
1946 struct ata_host *host = dev_instance;
1947 struct ahci_host_priv *hpriv;
1948 unsigned int rc = 0;
1949 void __iomem *mmio;
1950 u32 irq_stat, irq_masked;
1951
1952 VPRINTK("ENTER\n");
1953
1954 hpriv = host->private_data;
1955 mmio = hpriv->mmio;
1956
1957 /* sigh. 0xffffffff is a valid return from h/w */
1958 irq_stat = readl(mmio + HOST_IRQ_STAT);
1959 if (!irq_stat)
1960 return IRQ_NONE;
1961
1962 irq_masked = irq_stat & hpriv->port_map;
1963
1964 spin_lock(&host->lock);
1965
1966 rc = ahci_handle_port_intr(host, irq_masked);
365cfa1e
AV		 1967
1968 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1969 * it should be cleared after all the port events are cleared;
1970 * otherwise, it will raise a spurious interrupt after each
1971 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1972 * information.
1973 *
1974 * Also, use the unmasked value to clear interrupt as spurious
1975 * pending event on a dummy port might cause screaming IRQ.
1976 */
1977 writel(irq_stat, mmio + HOST_IRQ_STAT);
1978
03e83cbd
TH		 1979 spin_unlock(&host->lock);
1980
365cfa1e
AV		 1981 VPRINTK("EXIT\n");
1982
a129db89 1983 return IRQ_RETVAL(rc);
365cfa1e 1984}
365cfa1e 1985
39e0ee99 1986unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
365cfa1e
AV		 1987{
1988 struct ata_port *ap = qc->ap;
1989 void __iomem *port_mmio = ahci_port_base(ap);
1990 struct ahci_port_priv *pp = ap->private_data;
1991
1992 /* Keep track of the currently active link. It will be used
1993 * in completion path to determine whether NCQ phase is in
1994 * progress.
1995 */
1996 pp->active_link = qc->dev->link;
1997
179b310a 1998 if (ata_is_ncq(qc->tf.protocol))
4e5b6260 1999 writel(1 << qc->hw_tag, port_mmio + PORT_SCR_ACT);
365cfa1e
AV		 2000
2001 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
2002 u32 fbs = readl(port_mmio + PORT_FBS);
2003 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
2004 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
2005 writel(fbs, port_mmio + PORT_FBS);
2006 pp->fbs_last_dev = qc->dev->link->pmp;
2007 }
2008
4e5b6260 2009 writel(1 << qc->hw_tag, port_mmio + PORT_CMD_ISSUE);
365cfa1e
AV		 2010
2011 ahci_sw_activity(qc->dev->link);
2012
2013 return 0;
2014}
39e0ee99 2015EXPORT_SYMBOL_GPL(ahci_qc_issue);
365cfa1e
AV		 2016
2017static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2018{
2019 struct ahci_port_priv *pp = qc->ap->private_data;
6ad60195 2020 u8 *rx_fis = pp->rx_fis;
365cfa1e
AV		 2021
2022 if (pp->fbs_enabled)
6ad60195
TH		 2023 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2024
2025 /*
2026 * After a successful execution of an ATA PIO data-in command,
2027 * the device doesn't send D2H Reg FIS to update the TF and
2028 * the host should take TF and E_Status from the preceding PIO
2029 * Setup FIS.
2030 */
2031 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2032 !(qc->flags & ATA_QCFLAG_FAILED)) {
2033 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2034 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
2035 } else
2036 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
365cfa1e 2037
365cfa1e
AV		 2038 return true;
2039}
2040
2041static void ahci_freeze(struct ata_port *ap)
2042{
2043 void __iomem *port_mmio = ahci_port_base(ap);
2044
2045 /* turn IRQ off */
2046 writel(0, port_mmio + PORT_IRQ_MASK);
2047}
2048
2049static void ahci_thaw(struct ata_port *ap)
2050{
2051 struct ahci_host_priv *hpriv = ap->host->private_data;
2052 void __iomem *mmio = hpriv->mmio;
2053 void __iomem *port_mmio = ahci_port_base(ap);
2054 u32 tmp;
2055 struct ahci_port_priv *pp = ap->private_data;
2056
2057 /* clear IRQ */
2058 tmp = readl(port_mmio + PORT_IRQ_STAT);
2059 writel(tmp, port_mmio + PORT_IRQ_STAT);
2060 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2061
2062 /* turn IRQ back on */
2063 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2064}
2065
8b789d89 2066void ahci_error_handler(struct ata_port *ap)
365cfa1e 2067{
039ece38
HG		 2068 struct ahci_host_priv *hpriv = ap->host->private_data;
2069
365cfa1e
AV		 2070 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2071 /* restart engine */
fa89f53b 2072 hpriv->stop_engine(ap);
039ece38 2073 hpriv->start_engine(ap);
365cfa1e
AV		 2074 }
2075
2076 sata_pmp_error_handler(ap);
0ee71952
TH		 2077
2078 if (!ata_dev_enabled(ap->link.device))
fa89f53b 2079 hpriv->stop_engine(ap);
365cfa1e 2080}
8b789d89 2081EXPORT_SYMBOL_GPL(ahci_error_handler);
365cfa1e
AV		 2082
2083static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2084{
2085 struct ata_port *ap = qc->ap;
2086
2087 /* make DMA engine forget about the failed command */
2088 if (qc->flags & ATA_QCFLAG_FAILED)
2089 ahci_kick_engine(ap);
2090}
2091
65fe1f0f
SH		 2092static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2093{
039ece38 2094 struct ahci_host_priv *hpriv = ap->host->private_data;
65fe1f0f
SH		 2095 void __iomem *port_mmio = ahci_port_base(ap);
2096 struct ata_device *dev = ap->link.device;
11c29146 2097 u32 devslp, dm, dito, mdat, deto, dito_conf;
65fe1f0f
SH		 2098 int rc;
2099 unsigned int err_mask;
2100
2101 devslp = readl(port_mmio + PORT_DEVSLP);
2102 if (!(devslp & PORT_DEVSLP_DSP)) {
95bbbe9a 2103 dev_info(ap->host->dev, "port does not support device sleep\n");
65fe1f0f
SH		 2104 return;
2105 }
2106
2107 /* disable device sleep */
2108 if (!sleep) {
2109 if (devslp & PORT_DEVSLP_ADSE) {
2110 writel(devslp & ~PORT_DEVSLP_ADSE,
2111 port_mmio + PORT_DEVSLP);
2112 err_mask = ata_dev_set_feature(dev,
2113 SETFEATURES_SATA_DISABLE,
2114 SATA_DEVSLP);
2115 if (err_mask && err_mask != AC_ERR_DEV)
2116 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2117 }
2118 return;
2119 }
2120
11c29146
SP		 2121 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2122 dito = devslp_idle_timeout / (dm + 1);
2123 if (dito > 0x3ff)
2124 dito = 0x3ff;
2125
2126 dito_conf = (devslp >> PORT_DEVSLP_DITO_OFFSET) & 0x3FF;
2127
2128 /* device sleep was already enabled and same dito */
2129 if ((devslp & PORT_DEVSLP_ADSE) && (dito_conf == dito))
65fe1f0f
SH		 2130 return;
2131
2132 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
fa89f53b 2133 rc = hpriv->stop_engine(ap);
65fe1f0f
SH		 2134 if (rc)
2135 return;
2136
65fe1f0f
SH		 2137 /* Use the nominal value 10 ms if the read MDAT is zero,
2138 * the nominal value of DETO is 20 ms.
2139 */
803739d2 2140 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
65fe1f0f 2141 ATA_LOG_DEVSLP_VALID_MASK) {
803739d2 2142 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
65fe1f0f
SH		 2143 ATA_LOG_DEVSLP_MDAT_MASK;
2144 if (!mdat)
2145 mdat = 10;
803739d2 2146 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
65fe1f0f
SH		 2147 if (!deto)
2148 deto = 20;
2149 } else {
2150 mdat = 10;
2151 deto = 20;
2152 }
2153
2dbb3ec2
SP		 2154 /* Make dito, mdat, deto bits to 0s */
2155 devslp &= ~GENMASK_ULL(24, 2);
65fe1f0f
SH		 2156 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2157 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2158 (deto << PORT_DEVSLP_DETO_OFFSET) |
2159 PORT_DEVSLP_ADSE);
2160 writel(devslp, port_mmio + PORT_DEVSLP);
2161
039ece38 2162 hpriv->start_engine(ap);
65fe1f0f
SH		 2163
2164 /* enable device sleep feature for the drive */
2165 err_mask = ata_dev_set_feature(dev,
2166 SETFEATURES_SATA_ENABLE,
2167 SATA_DEVSLP);
2168 if (err_mask && err_mask != AC_ERR_DEV)
2169 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2170}
2171
365cfa1e
AV		 2172static void ahci_enable_fbs(struct ata_port *ap)
2173{
039ece38 2174 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 2175 struct ahci_port_priv *pp = ap->private_data;
2176 void __iomem *port_mmio = ahci_port_base(ap);
2177 u32 fbs;
2178 int rc;
2179
2180 if (!pp->fbs_supported)
2181 return;
2182
2183 fbs = readl(port_mmio + PORT_FBS);
2184 if (fbs & PORT_FBS_EN) {
2185 pp->fbs_enabled = true;
2186 pp->fbs_last_dev = -1; /* initialization */
2187 return;
2188 }
2189
fa89f53b 2190 rc = hpriv->stop_engine(ap);
365cfa1e
AV		 2191 if (rc)
2192 return;
2193
2194 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2195 fbs = readl(port_mmio + PORT_FBS);
2196 if (fbs & PORT_FBS_EN) {
a44fec1f 2197 dev_info(ap->host->dev, "FBS is enabled\n");
365cfa1e
AV		 2198 pp->fbs_enabled = true;
2199 pp->fbs_last_dev = -1; /* initialization */
2200 } else
a44fec1f 2201 dev_err(ap->host->dev, "Failed to enable FBS\n");
365cfa1e 2202
039ece38 2203 hpriv->start_engine(ap);
365cfa1e
AV		 2204}
2205
2206static void ahci_disable_fbs(struct ata_port *ap)
2207{
039ece38 2208 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 2209 struct ahci_port_priv *pp = ap->private_data;
2210 void __iomem *port_mmio = ahci_port_base(ap);
2211 u32 fbs;
2212 int rc;
2213
2214 if (!pp->fbs_supported)
2215 return;
2216
2217 fbs = readl(port_mmio + PORT_FBS);
2218 if ((fbs & PORT_FBS_EN) == 0) {
2219 pp->fbs_enabled = false;
2220 return;
2221 }
2222
fa89f53b 2223 rc = hpriv->stop_engine(ap);
365cfa1e
AV		 2224 if (rc)
2225 return;
2226
2227 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2228 fbs = readl(port_mmio + PORT_FBS);
2229 if (fbs & PORT_FBS_EN)
a44fec1f 2230 dev_err(ap->host->dev, "Failed to disable FBS\n");
365cfa1e 2231 else {
a44fec1f 2232 dev_info(ap->host->dev, "FBS is disabled\n");
365cfa1e
AV		 2233 pp->fbs_enabled = false;
2234 }
2235
039ece38 2236 hpriv->start_engine(ap);
365cfa1e
AV		 2237}
2238
2239static void ahci_pmp_attach(struct ata_port *ap)
2240{
2241 void __iomem *port_mmio = ahci_port_base(ap);
2242 struct ahci_port_priv *pp = ap->private_data;
2243 u32 cmd;
2244
2245 cmd = readl(port_mmio + PORT_CMD);
2246 cmd |= PORT_CMD_PMP;
2247 writel(cmd, port_mmio + PORT_CMD);
2248
2249 ahci_enable_fbs(ap);
2250
2251 pp->intr_mask |= PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 2252
2253 /*
2254 * We must not change the port interrupt mask register if the
2255 * port is marked frozen, the value in pp->intr_mask will be
2256 * restored later when the port is thawed.
2257 *
2258 * Note that during initialization, the port is marked as
2259 * frozen since the irq handler is not yet registered.
2260 */
2261 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2262 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 2263}
2264
2265static void ahci_pmp_detach(struct ata_port *ap)
2266{
2267 void __iomem *port_mmio = ahci_port_base(ap);
2268 struct ahci_port_priv *pp = ap->private_data;
2269 u32 cmd;
2270
2271 ahci_disable_fbs(ap);
2272
2273 cmd = readl(port_mmio + PORT_CMD);
2274 cmd &= ~PORT_CMD_PMP;
2275 writel(cmd, port_mmio + PORT_CMD);
2276
2277 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 2278
2279 /* see comment above in ahci_pmp_attach() */
2280 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2281 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 2282}
2283
02cdfcf0 2284int ahci_port_resume(struct ata_port *ap)
365cfa1e 2285{
bb03c640
MW		 2286 ahci_rpm_get_port(ap);
2287
365cfa1e
AV		 2288 ahci_power_up(ap);
2289 ahci_start_port(ap);
2290
2291 if (sata_pmp_attached(ap))
2292 ahci_pmp_attach(ap);
2293 else
2294 ahci_pmp_detach(ap);
2295
2296 return 0;
2297}
02cdfcf0 2298EXPORT_SYMBOL_GPL(ahci_port_resume);
365cfa1e
AV		 2299
2300#ifdef CONFIG_PM
2301static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2302{
2303 const char *emsg = NULL;
2304 int rc;
2305
2306 rc = ahci_deinit_port(ap, &emsg);
2307 if (rc == 0)
2308 ahci_power_down(ap);
2309 else {
a9a79dfe 2310 ata_port_err(ap, "%s (%d)\n", emsg, rc);
7faa33da 2311 ata_port_freeze(ap);
365cfa1e
AV		 2312 }
2313
bb03c640 2314 ahci_rpm_put_port(ap);
365cfa1e
AV		 2315 return rc;
2316}
2317#endif
2318
2319static int ahci_port_start(struct ata_port *ap)
2320{
2321 struct ahci_host_priv *hpriv = ap->host->private_data;
2322 struct device *dev = ap->host->dev;
2323 struct ahci_port_priv *pp;
2324 void *mem;
2325 dma_addr_t mem_dma;
2326 size_t dma_sz, rx_fis_sz;
2327
2328 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2329 if (!pp)
2330 return -ENOMEM;
2331
b29900e6
AG		 2332 if (ap->host->n_ports > 1) {
2333 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2334 if (!pp->irq_desc) {
2335 devm_kfree(dev, pp);
2336 return -ENOMEM;
2337 }
2338 snprintf(pp->irq_desc, 8,
2339 "%s%d", dev_driver_string(dev), ap->port_no);
2340 }
2341
365cfa1e
AV		 2342 /* check FBS capability */
2343 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2344 void __iomem *port_mmio = ahci_port_base(ap);
2345 u32 cmd = readl(port_mmio + PORT_CMD);
2346 if (cmd & PORT_CMD_FBSCP)
2347 pp->fbs_supported = true;
5f173107 2348 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
a44fec1f
JP		 2349 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2350 ap->port_no);
5f173107
TH		 2351 pp->fbs_supported = true;
2352 } else
a44fec1f
JP		 2353 dev_warn(dev, "port %d is not capable of FBS\n",
2354 ap->port_no);
365cfa1e
AV		 2355 }
2356
2357 if (pp->fbs_supported) {
2358 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2359 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2360 } else {
2361 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2362 rx_fis_sz = AHCI_RX_FIS_SZ;
2363 }
2364
2365 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2366 if (!mem)
2367 return -ENOMEM;
365cfa1e
AV		 2368
2369 /*
2370 * First item in chunk of DMA memory: 32-slot command table,
2371 * 32 bytes each in size
2372 */
2373 pp->cmd_slot = mem;
2374 pp->cmd_slot_dma = mem_dma;
2375
2376 mem += AHCI_CMD_SLOT_SZ;
2377 mem_dma += AHCI_CMD_SLOT_SZ;
2378
2379 /*
2380 * Second item: Received-FIS area
2381 */
2382 pp->rx_fis = mem;
2383 pp->rx_fis_dma = mem_dma;
2384
2385 mem += rx_fis_sz;
2386 mem_dma += rx_fis_sz;
2387
2388 /*
2389 * Third item: data area for storing a single command
2390 * and its scatter-gather table
2391 */
2392 pp->cmd_tbl = mem;
2393 pp->cmd_tbl_dma = mem_dma;
2394
2395 /*
2396 * Save off initial list of interrupts to be enabled.
2397 * This could be changed later
2398 */
2399 pp->intr_mask = DEF_PORT_IRQ;
2400
7865f83f
TH		 2401 /*
2402 * Switch to per-port locking in case each port has its own MSI vector.
2403 */
0b9e2988 2404 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
7865f83f
TH		 2405 spin_lock_init(&pp->lock);
2406 ap->lock = &pp->lock;
2407 }
5ca72c4f 2408
365cfa1e
AV		 2409 ap->private_data = pp;
2410
2411 /* engage engines, captain */
2412 return ahci_port_resume(ap);
2413}
2414
2415static void ahci_port_stop(struct ata_port *ap)
2416{
2417 const char *emsg = NULL;
0516900a
PR		 2418 struct ahci_host_priv *hpriv = ap->host->private_data;
2419 void __iomem *host_mmio = hpriv->mmio;
365cfa1e
AV		 2420 int rc;
2421
2422 /* de-initialize port */
2423 rc = ahci_deinit_port(ap, &emsg);
2424 if (rc)
a9a79dfe 2425 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
0516900a
PR		 2426
2427 /*
2428 * Clear GHC.IS to prevent stuck INTx after disabling MSI and
2429 * re-enabling INTx.
2430 */
2431 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT);
332c42a9
SM		 2432
2433 ahci_rpm_put_port(ap);
365cfa1e
AV		 2434}
2435
2436void ahci_print_info(struct ata_host *host, const char *scc_s)
2437{
2438 struct ahci_host_priv *hpriv = host->private_data;
365cfa1e
AV		 2439 u32 vers, cap, cap2, impl, speed;
2440 const char *speed_s;
2441
8ea909cb 2442 vers = hpriv->version;
365cfa1e
AV		 2443 cap = hpriv->cap;
2444 cap2 = hpriv->cap2;
2445 impl = hpriv->port_map;
2446
2447 speed = (cap >> 20) & 0xf;
2448 if (speed == 1)
2449 speed_s = "1.5";
2450 else if (speed == 2)
2451 speed_s = "3";
2452 else if (speed == 3)
2453 speed_s = "6";
2454 else
2455 speed_s = "?";
2456
2457 dev_info(host->dev,
2458 "AHCI %02x%02x.%02x%02x "
2459 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2460 ,
2461
2462 (vers >> 24) & 0xff,
2463 (vers >> 16) & 0xff,
2464 (vers >> 8) & 0xff,
2465 vers & 0xff,
2466
2467 ((cap >> 8) & 0x1f) + 1,
2468 (cap & 0x1f) + 1,
2469 speed_s,
2470 impl,
2471 scc_s);
2472
2473 dev_info(host->dev,
2474 "flags: "
2475 "%s%s%s%s%s%s%s"
2476 "%s%s%s%s%s%s%s"
65fe1f0f
SH		 2477 "%s%s%s%s%s%s%s"
2478 "%s%s\n"
365cfa1e
AV		 2479 ,
2480
2481 cap & HOST_CAP_64 ? "64bit " : "",
2482 cap & HOST_CAP_NCQ ? "ncq " : "",
2483 cap & HOST_CAP_SNTF ? "sntf " : "",
2484 cap & HOST_CAP_MPS ? "ilck " : "",
2485 cap & HOST_CAP_SSS ? "stag " : "",
2486 cap & HOST_CAP_ALPM ? "pm " : "",
2487 cap & HOST_CAP_LED ? "led " : "",
2488 cap & HOST_CAP_CLO ? "clo " : "",
2489 cap & HOST_CAP_ONLY ? "only " : "",
2490 cap & HOST_CAP_PMP ? "pmp " : "",
2491 cap & HOST_CAP_FBS ? "fbs " : "",
2492 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2493 cap & HOST_CAP_SSC ? "slum " : "",
2494 cap & HOST_CAP_PART ? "part " : "",
2495 cap & HOST_CAP_CCC ? "ccc " : "",
2496 cap & HOST_CAP_EMS ? "ems " : "",
2497 cap & HOST_CAP_SXS ? "sxs " : "",
65fe1f0f
SH		 2498 cap2 & HOST_CAP2_DESO ? "deso " : "",
2499 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2500 cap2 & HOST_CAP2_SDS ? "sds " : "",
365cfa1e
AV		 2501 cap2 & HOST_CAP2_APST ? "apst " : "",
2502 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2503 cap2 & HOST_CAP2_BOH ? "boh " : ""
2504 );
2505}
2506EXPORT_SYMBOL_GPL(ahci_print_info);
2507
2508void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2509 struct ata_port_info *pi)
2510{
2511 u8 messages;
2512 void __iomem *mmio = hpriv->mmio;
2513 u32 em_loc = readl(mmio + HOST_EM_LOC);
2514 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2515
2516 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2517 return;
2518
2519 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2520
008dbd61 2521 if (messages) {
365cfa1e
AV		 2522 /* store em_loc */
2523 hpriv->em_loc = ((em_loc >> 16) * 4);
c0623166 2524 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
008dbd61 2525 hpriv->em_msg_type = messages;
365cfa1e
AV		 2526 pi->flags |= ATA_FLAG_EM;
2527 if (!(em_ctl & EM_CTL_ALHD))
2528 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2529 }
2530}
2531EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2532
d684a90d 2533static int ahci_host_activate_multi_irqs(struct ata_host *host,
d1028e2f 2534 struct scsi_host_template *sht)
1c62854f 2535{
d684a90d 2536 struct ahci_host_priv *hpriv = host->private_data;
1c62854f
AG		 2537 int i, rc;
2538
2539 rc = ata_host_start(host);
2540 if (rc)
2541 return rc;
21bfd1aa
RR		 2542 /*
2543 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2544 * allocated. That is one MSI per port, starting from @irq.
2545 */
1c62854f
AG		 2546 for (i = 0; i < host->n_ports; i++) {
2547 struct ahci_port_priv *pp = host->ports[i]->private_data;
0b9e2988 2548 int irq = hpriv->get_irq_vector(host, i);
1c62854f
AG		 2549
2550 /* Do not receive interrupts sent by dummy ports */
2551 if (!pp) {
9b4b3f6a 2552 disable_irq(irq);
1c62854f
AG		 2553 continue;
2554 }
2555
a6b7fb76
DW		 2556 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2557 0, pp->irq_desc, host->ports[i]);
2558
1c62854f 2559 if (rc)
0a142b26 2560 return rc;
d684a90d 2561 ata_port_desc(host->ports[i], "irq %d", irq);
0a142b26 2562 }
d684a90d 2563
0a142b26 2564 return ata_host_register(host, sht);
1c62854f 2565}
d1028e2f
AG		 2566
2567/**
2568 * ahci_host_activate - start AHCI host, request IRQs and register it
2569 * @host: target ATA host
d1028e2f
AG		 2570 * @sht: scsi_host_template to use when registering the host
2571 *
d1028e2f
AG		 2572 * LOCKING:
2573 * Inherited from calling layer (may sleep).
2574 *
2575 * RETURNS:
2576 * 0 on success, -errno otherwise.
2577 */
21bfd1aa 2578int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
d1028e2f
AG		 2579{
2580 struct ahci_host_priv *hpriv = host->private_data;
21bfd1aa 2581 int irq = hpriv->irq;
d1028e2f
AG		 2582 int rc;
2583
0b9e2988 2584 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
3bac408a
JG		 2585 if (hpriv->irq_handler &&
2586 hpriv->irq_handler != ahci_single_level_irq_intr)
d991c872
SE		 2587 dev_warn(host->dev,
2588 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n");
0b9e2988
CH		 2589 if (!hpriv->get_irq_vector) {
2590 dev_err(host->dev,
2591 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n");
2592 return -EIO;
2593 }
f070d671 2594
d684a90d 2595 rc = ahci_host_activate_multi_irqs(host, sht);
f070d671
ST		 2596 } else {
2597 rc = ata_host_activate(host, irq, hpriv->irq_handler,
7865f83f 2598 IRQF_SHARED, sht);
f070d671
ST		 2599 }
2600
2601
d1028e2f
AG		 2602 return rc;
2603}
1c62854f
AG		 2604EXPORT_SYMBOL_GPL(ahci_host_activate);
2605
365cfa1e
AV		 2606MODULE_AUTHOR("Jeff Garzik");
2607MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2608MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)