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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mszeredi...
[linux-block.git] / drivers / ata / libahci.c
CommitLineData
365cfa1e
AV		 1/*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <tj@kernel.org>
365cfa1e
AV		 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
fbaf666b 36#include <linux/gfp.h>
365cfa1e 37#include <linux/module.h>
365cfa1e
AV		 38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
41#include <linux/dma-mapping.h>
42#include <linux/device.h>
43#include <scsi/scsi_host.h>
44#include <scsi/scsi_cmnd.h>
45#include <linux/libata.h>
46#include "ahci.h"
65fe1f0f 47#include "libata.h"
365cfa1e
AV		 48
49static int ahci_skip_host_reset;
50int ahci_ignore_sss;
51EXPORT_SYMBOL_GPL(ahci_ignore_sss);
52
53module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
56module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
57MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
58
6b7ae954
TH		 59static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
60 unsigned hints);
365cfa1e
AV		 61static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
62static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
63 size_t size);
64static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
65 ssize_t size);
66
67
68
69static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
70static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
365cfa1e
AV		 71static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
72static int ahci_port_start(struct ata_port *ap);
73static void ahci_port_stop(struct ata_port *ap);
74static void ahci_qc_prep(struct ata_queued_cmd *qc);
75static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
76static void ahci_freeze(struct ata_port *ap);
77static void ahci_thaw(struct ata_port *ap);
65fe1f0f 78static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
365cfa1e
AV		 79static void ahci_enable_fbs(struct ata_port *ap);
80static void ahci_disable_fbs(struct ata_port *ap);
81static void ahci_pmp_attach(struct ata_port *ap);
82static void ahci_pmp_detach(struct ata_port *ap);
83static int ahci_softreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
345347c5
YHC		 85static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
365cfa1e
AV		 87static int ahci_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89static void ahci_postreset(struct ata_link *link, unsigned int *class);
365cfa1e 90static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
365cfa1e 91static void ahci_dev_config(struct ata_device *dev);
365cfa1e
AV		 92#ifdef CONFIG_PM
93static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
94#endif
95static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
96static ssize_t ahci_activity_store(struct ata_device *dev,
97 enum sw_activity val);
98static void ahci_init_sw_activity(struct ata_link *link);
99
100static ssize_t ahci_show_host_caps(struct device *dev,
101 struct device_attribute *attr, char *buf);
102static ssize_t ahci_show_host_cap2(struct device *dev,
103 struct device_attribute *attr, char *buf);
104static ssize_t ahci_show_host_version(struct device *dev,
105 struct device_attribute *attr, char *buf);
106static ssize_t ahci_show_port_cmd(struct device *dev,
107 struct device_attribute *attr, char *buf);
c0623166
HZ		 108static ssize_t ahci_read_em_buffer(struct device *dev,
109 struct device_attribute *attr, char *buf);
110static ssize_t ahci_store_em_buffer(struct device *dev,
111 struct device_attribute *attr,
112 const char *buf, size_t size);
6e5fe5b1
HR		 113static ssize_t ahci_show_em_supported(struct device *dev,
114 struct device_attribute *attr, char *buf);
365cfa1e
AV		 115
116static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
117static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
118static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
119static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
c0623166
HZ		 120static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
121 ahci_read_em_buffer, ahci_store_em_buffer);
6e5fe5b1 122static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
365cfa1e 123
fad16e7a 124struct device_attribute *ahci_shost_attrs[] = {
365cfa1e
AV		 125 &dev_attr_link_power_management_policy,
126 &dev_attr_em_message_type,
127 &dev_attr_em_message,
128 &dev_attr_ahci_host_caps,
129 &dev_attr_ahci_host_cap2,
130 &dev_attr_ahci_host_version,
131 &dev_attr_ahci_port_cmd,
c0623166 132 &dev_attr_em_buffer,
6e5fe5b1 133 &dev_attr_em_message_supported,
365cfa1e
AV		 134 NULL
135};
fad16e7a 136EXPORT_SYMBOL_GPL(ahci_shost_attrs);
365cfa1e 137
fad16e7a 138struct device_attribute *ahci_sdev_attrs[] = {
365cfa1e
AV		 139 &dev_attr_sw_activity,
140 &dev_attr_unload_heads,
141 NULL
142};
fad16e7a 143EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
365cfa1e
AV		 144
145struct ata_port_operations ahci_ops = {
146 .inherits = &sata_pmp_port_ops,
147
148 .qc_defer = ahci_pmp_qc_defer,
149 .qc_prep = ahci_qc_prep,
150 .qc_issue = ahci_qc_issue,
151 .qc_fill_rtf = ahci_qc_fill_rtf,
152
153 .freeze = ahci_freeze,
154 .thaw = ahci_thaw,
155 .softreset = ahci_softreset,
156 .hardreset = ahci_hardreset,
157 .postreset = ahci_postreset,
158 .pmp_softreset = ahci_softreset,
159 .error_handler = ahci_error_handler,
160 .post_internal_cmd = ahci_post_internal_cmd,
161 .dev_config = ahci_dev_config,
162
163 .scr_read = ahci_scr_read,
164 .scr_write = ahci_scr_write,
165 .pmp_attach = ahci_pmp_attach,
166 .pmp_detach = ahci_pmp_detach,
167
6b7ae954 168 .set_lpm = ahci_set_lpm,
365cfa1e
AV		 169 .em_show = ahci_led_show,
170 .em_store = ahci_led_store,
171 .sw_activity_show = ahci_activity_show,
172 .sw_activity_store = ahci_activity_store,
439d7a35 173 .transmit_led_message = ahci_transmit_led_message,
365cfa1e
AV		 174#ifdef CONFIG_PM
175 .port_suspend = ahci_port_suspend,
176 .port_resume = ahci_port_resume,
177#endif
178 .port_start = ahci_port_start,
179 .port_stop = ahci_port_stop,
180};
181EXPORT_SYMBOL_GPL(ahci_ops);
182
345347c5
YHC		 183struct ata_port_operations ahci_pmp_retry_srst_ops = {
184 .inherits = &ahci_ops,
185 .softreset = ahci_pmp_retry_softreset,
186};
187EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
188
ed08d40c 189static bool ahci_em_messages __read_mostly = true;
365cfa1e 190EXPORT_SYMBOL_GPL(ahci_em_messages);
ed08d40c 191module_param(ahci_em_messages, bool, 0444);
365cfa1e
AV		 192/* add other LED protocol types when they become supported */
193MODULE_PARM_DESC(ahci_em_messages,
008dbd61 194 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
365cfa1e 195
ed08d40c
CL		 196/* device sleep idle timeout in ms */
197static int devslp_idle_timeout __read_mostly = 1000;
65fe1f0f
SH		 198module_param(devslp_idle_timeout, int, 0644);
199MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
200
365cfa1e
AV		 201static void ahci_enable_ahci(void __iomem *mmio)
202{
203 int i;
204 u32 tmp;
205
206 /* turn on AHCI_EN */
207 tmp = readl(mmio + HOST_CTL);
208 if (tmp & HOST_AHCI_EN)
209 return;
210
211 /* Some controllers need AHCI_EN to be written multiple times.
212 * Try a few times before giving up.
213 */
214 for (i = 0; i < 5; i++) {
215 tmp |= HOST_AHCI_EN;
216 writel(tmp, mmio + HOST_CTL);
217 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
218 if (tmp & HOST_AHCI_EN)
219 return;
220 msleep(10);
221 }
222
223 WARN_ON(1);
224}
225
226static ssize_t ahci_show_host_caps(struct device *dev,
227 struct device_attribute *attr, char *buf)
228{
229 struct Scsi_Host *shost = class_to_shost(dev);
230 struct ata_port *ap = ata_shost_to_port(shost);
231 struct ahci_host_priv *hpriv = ap->host->private_data;
232
233 return sprintf(buf, "%x\n", hpriv->cap);
234}
235
236static ssize_t ahci_show_host_cap2(struct device *dev,
237 struct device_attribute *attr, char *buf)
238{
239 struct Scsi_Host *shost = class_to_shost(dev);
240 struct ata_port *ap = ata_shost_to_port(shost);
241 struct ahci_host_priv *hpriv = ap->host->private_data;
242
243 return sprintf(buf, "%x\n", hpriv->cap2);
244}
245
246static ssize_t ahci_show_host_version(struct device *dev,
247 struct device_attribute *attr, char *buf)
248{
249 struct Scsi_Host *shost = class_to_shost(dev);
250 struct ata_port *ap = ata_shost_to_port(shost);
251 struct ahci_host_priv *hpriv = ap->host->private_data;
252 void __iomem *mmio = hpriv->mmio;
253
254 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
255}
256
257static ssize_t ahci_show_port_cmd(struct device *dev,
258 struct device_attribute *attr, char *buf)
259{
260 struct Scsi_Host *shost = class_to_shost(dev);
261 struct ata_port *ap = ata_shost_to_port(shost);
262 void __iomem *port_mmio = ahci_port_base(ap);
263
264 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
265}
266
c0623166
HZ		 267static ssize_t ahci_read_em_buffer(struct device *dev,
268 struct device_attribute *attr, char *buf)
269{
270 struct Scsi_Host *shost = class_to_shost(dev);
271 struct ata_port *ap = ata_shost_to_port(shost);
272 struct ahci_host_priv *hpriv = ap->host->private_data;
273 void __iomem *mmio = hpriv->mmio;
274 void __iomem *em_mmio = mmio + hpriv->em_loc;
275 u32 em_ctl, msg;
276 unsigned long flags;
277 size_t count;
278 int i;
279
280 spin_lock_irqsave(ap->lock, flags);
281
282 em_ctl = readl(mmio + HOST_EM_CTL);
283 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
284 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
285 spin_unlock_irqrestore(ap->lock, flags);
286 return -EINVAL;
287 }
288
289 if (!(em_ctl & EM_CTL_MR)) {
290 spin_unlock_irqrestore(ap->lock, flags);
291 return -EAGAIN;
292 }
293
294 if (!(em_ctl & EM_CTL_SMB))
295 em_mmio += hpriv->em_buf_sz;
296
297 count = hpriv->em_buf_sz;
298
299 /* the count should not be larger than PAGE_SIZE */
300 if (count > PAGE_SIZE) {
301 if (printk_ratelimit())
a9a79dfe
JP		 302 ata_port_warn(ap,
303 "EM read buffer size too large: "
304 "buffer size %u, page size %lu\n",
305 hpriv->em_buf_sz, PAGE_SIZE);
c0623166
HZ		 306 count = PAGE_SIZE;
307 }
308
309 for (i = 0; i < count; i += 4) {
310 msg = readl(em_mmio + i);
311 buf[i] = msg & 0xff;
312 buf[i + 1] = (msg >> 8) & 0xff;
313 buf[i + 2] = (msg >> 16) & 0xff;
314 buf[i + 3] = (msg >> 24) & 0xff;
315 }
316
317 spin_unlock_irqrestore(ap->lock, flags);
318
319 return i;
320}
321
322static ssize_t ahci_store_em_buffer(struct device *dev,
323 struct device_attribute *attr,
324 const char *buf, size_t size)
325{
326 struct Scsi_Host *shost = class_to_shost(dev);
327 struct ata_port *ap = ata_shost_to_port(shost);
328 struct ahci_host_priv *hpriv = ap->host->private_data;
329 void __iomem *mmio = hpriv->mmio;
330 void __iomem *em_mmio = mmio + hpriv->em_loc;
f9ce889b 331 const unsigned char *msg_buf = buf;
c0623166
HZ		 332 u32 em_ctl, msg;
333 unsigned long flags;
334 int i;
335
336 /* check size validity */
337 if (!(ap->flags & ATA_FLAG_EM) ||
338 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
339 size % 4 || size > hpriv->em_buf_sz)
340 return -EINVAL;
341
342 spin_lock_irqsave(ap->lock, flags);
343
344 em_ctl = readl(mmio + HOST_EM_CTL);
345 if (em_ctl & EM_CTL_TM) {
346 spin_unlock_irqrestore(ap->lock, flags);
347 return -EBUSY;
348 }
349
350 for (i = 0; i < size; i += 4) {
f9ce889b
HZ		 351 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
352 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
c0623166
HZ		 353 writel(msg, em_mmio + i);
354 }
355
356 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
357
358 spin_unlock_irqrestore(ap->lock, flags);
359
360 return size;
361}
362
6e5fe5b1
HR		 363static ssize_t ahci_show_em_supported(struct device *dev,
364 struct device_attribute *attr, char *buf)
365{
366 struct Scsi_Host *shost = class_to_shost(dev);
367 struct ata_port *ap = ata_shost_to_port(shost);
368 struct ahci_host_priv *hpriv = ap->host->private_data;
369 void __iomem *mmio = hpriv->mmio;
370 u32 em_ctl;
371
372 em_ctl = readl(mmio + HOST_EM_CTL);
373
374 return sprintf(buf, "%s%s%s%s\n",
375 em_ctl & EM_CTL_LED ? "led " : "",
376 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
377 em_ctl & EM_CTL_SES ? "ses-2 " : "",
378 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
379}
380
365cfa1e
AV		 381/**
382 * ahci_save_initial_config - Save and fixup initial config values
383 * @dev: target AHCI device
384 * @hpriv: host private area to store config values
385 * @force_port_map: force port map to a specified value
386 * @mask_port_map: mask out particular bits from port map
387 *
388 * Some registers containing configuration info might be setup by
389 * BIOS and might be cleared on reset. This function saves the
390 * initial values of those registers into @hpriv such that they
391 * can be restored after controller reset.
392 *
393 * If inconsistent, config values are fixed up by this function.
394 *
039ece38
HG		 395 * If it is not set already this function sets hpriv->start_engine to
396 * ahci_start_engine.
397 *
365cfa1e
AV		 398 * LOCKING:
399 * None.
400 */
401void ahci_save_initial_config(struct device *dev,
402 struct ahci_host_priv *hpriv,
403 unsigned int force_port_map,
404 unsigned int mask_port_map)
405{
406 void __iomem *mmio = hpriv->mmio;
407 u32 cap, cap2, vers, port_map;
408 int i;
409
410 /* make sure AHCI mode is enabled before accessing CAP */
411 ahci_enable_ahci(mmio);
412
413 /* Values prefixed with saved_ are written back to host after
414 * reset. Values without are used for driver operation.
415 */
416 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
417 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
418
419 /* CAP2 register is only defined for AHCI 1.2 and later */
420 vers = readl(mmio + HOST_VERSION);
421 if ((vers >> 16) > 1 ||
422 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
423 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
424 else
425 hpriv->saved_cap2 = cap2 = 0;
426
427 /* some chips have errata preventing 64bit use */
428 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
a44fec1f 429 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
365cfa1e
AV		 430 cap &= ~HOST_CAP_64;
431 }
432
433 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
a44fec1f 434 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
365cfa1e
AV		 435 cap &= ~HOST_CAP_NCQ;
436 }
437
438 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
a44fec1f 439 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
365cfa1e
AV		 440 cap |= HOST_CAP_NCQ;
441 }
442
443 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
a44fec1f 444 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
365cfa1e
AV		 445 cap &= ~HOST_CAP_PMP;
446 }
447
448 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
a44fec1f
JP		 449 dev_info(dev,
450 "controller can't do SNTF, turning off CAP_SNTF\n");
365cfa1e
AV		 451 cap &= ~HOST_CAP_SNTF;
452 }
453
0cf4a7d6
JP		 454 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
455 dev_info(dev,
456 "controller can't do DEVSLP, turning off\n");
457 cap2 &= ~HOST_CAP2_SDS;
458 cap2 &= ~HOST_CAP2_SADM;
459 }
460
5f173107 461 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
a44fec1f 462 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
5f173107
TH		 463 cap |= HOST_CAP_FBS;
464 }
465
888d91a0
KW		 466 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
467 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
468 cap &= ~HOST_CAP_FBS;
469 }
470
365cfa1e 471 if (force_port_map && port_map != force_port_map) {
a44fec1f
JP		 472 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
473 port_map, force_port_map);
365cfa1e
AV		 474 port_map = force_port_map;
475 }
476
477 if (mask_port_map) {
a44fec1f
JP		 478 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
479 port_map,
480 port_map & mask_port_map);
365cfa1e
AV		 481 port_map &= mask_port_map;
482 }
483
484 /* cross check port_map and cap.n_ports */
485 if (port_map) {
486 int map_ports = 0;
487
488 for (i = 0; i < AHCI_MAX_PORTS; i++)
489 if (port_map & (1 << i))
490 map_ports++;
491
492 /* If PI has more ports than n_ports, whine, clear
493 * port_map and let it be generated from n_ports.
494 */
495 if (map_ports > ahci_nr_ports(cap)) {
a44fec1f
JP		 496 dev_warn(dev,
497 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
498 port_map, ahci_nr_ports(cap));
365cfa1e
AV		 499 port_map = 0;
500 }
501 }
502
503 /* fabricate port_map from cap.nr_ports */
504 if (!port_map) {
505 port_map = (1 << ahci_nr_ports(cap)) - 1;
a44fec1f 506 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
365cfa1e
AV		 507
508 /* write the fixed up value to the PI register */
509 hpriv->saved_port_map = port_map;
510 }
511
512 /* record values to use during operation */
513 hpriv->cap = cap;
514 hpriv->cap2 = cap2;
515 hpriv->port_map = port_map;
039ece38
HG		 516
517 if (!hpriv->start_engine)
518 hpriv->start_engine = ahci_start_engine;
365cfa1e
AV		 519}
520EXPORT_SYMBOL_GPL(ahci_save_initial_config);
521
522/**
523 * ahci_restore_initial_config - Restore initial config
524 * @host: target ATA host
525 *
526 * Restore initial config stored by ahci_save_initial_config().
527 *
528 * LOCKING:
529 * None.
530 */
531static void ahci_restore_initial_config(struct ata_host *host)
532{
533 struct ahci_host_priv *hpriv = host->private_data;
534 void __iomem *mmio = hpriv->mmio;
535
536 writel(hpriv->saved_cap, mmio + HOST_CAP);
537 if (hpriv->saved_cap2)
538 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
539 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
540 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
541}
542
543static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
544{
545 static const int offset[] = {
546 [SCR_STATUS] = PORT_SCR_STAT,
547 [SCR_CONTROL] = PORT_SCR_CTL,
548 [SCR_ERROR] = PORT_SCR_ERR,
549 [SCR_ACTIVE] = PORT_SCR_ACT,
550 [SCR_NOTIFICATION] = PORT_SCR_NTF,
551 };
552 struct ahci_host_priv *hpriv = ap->host->private_data;
553
554 if (sc_reg < ARRAY_SIZE(offset) &&
555 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
556 return offset[sc_reg];
557 return 0;
558}
559
560static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
561{
562 void __iomem *port_mmio = ahci_port_base(link->ap);
563 int offset = ahci_scr_offset(link->ap, sc_reg);
564
565 if (offset) {
566 *val = readl(port_mmio + offset);
567 return 0;
568 }
569 return -EINVAL;
570}
571
572static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
573{
574 void __iomem *port_mmio = ahci_port_base(link->ap);
575 int offset = ahci_scr_offset(link->ap, sc_reg);
576
577 if (offset) {
578 writel(val, port_mmio + offset);
579 return 0;
580 }
581 return -EINVAL;
582}
583
584void ahci_start_engine(struct ata_port *ap)
585{
586 void __iomem *port_mmio = ahci_port_base(ap);
587 u32 tmp;
588
589 /* start DMA */
590 tmp = readl(port_mmio + PORT_CMD);
591 tmp |= PORT_CMD_START;
592 writel(tmp, port_mmio + PORT_CMD);
593 readl(port_mmio + PORT_CMD); /* flush */
594}
595EXPORT_SYMBOL_GPL(ahci_start_engine);
596
597int ahci_stop_engine(struct ata_port *ap)
598{
599 void __iomem *port_mmio = ahci_port_base(ap);
600 u32 tmp;
601
602 tmp = readl(port_mmio + PORT_CMD);
603
604 /* check if the HBA is idle */
605 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
606 return 0;
607
608 /* setting HBA to idle */
609 tmp &= ~PORT_CMD_START;
610 writel(tmp, port_mmio + PORT_CMD);
611
612 /* wait for engine to stop. This could be as long as 500 msec */
97750ceb 613 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 614 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
615 if (tmp & PORT_CMD_LIST_ON)
616 return -EIO;
617
618 return 0;
619}
620EXPORT_SYMBOL_GPL(ahci_stop_engine);
621
39e0ee99 622void ahci_start_fis_rx(struct ata_port *ap)
365cfa1e
AV		 623{
624 void __iomem *port_mmio = ahci_port_base(ap);
625 struct ahci_host_priv *hpriv = ap->host->private_data;
626 struct ahci_port_priv *pp = ap->private_data;
627 u32 tmp;
628
629 /* set FIS registers */
630 if (hpriv->cap & HOST_CAP_64)
631 writel((pp->cmd_slot_dma >> 16) >> 16,
632 port_mmio + PORT_LST_ADDR_HI);
633 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
634
635 if (hpriv->cap & HOST_CAP_64)
636 writel((pp->rx_fis_dma >> 16) >> 16,
637 port_mmio + PORT_FIS_ADDR_HI);
638 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
639
640 /* enable FIS reception */
641 tmp = readl(port_mmio + PORT_CMD);
642 tmp |= PORT_CMD_FIS_RX;
643 writel(tmp, port_mmio + PORT_CMD);
644
645 /* flush */
646 readl(port_mmio + PORT_CMD);
647}
39e0ee99 648EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
365cfa1e
AV		 649
650static int ahci_stop_fis_rx(struct ata_port *ap)
651{
652 void __iomem *port_mmio = ahci_port_base(ap);
653 u32 tmp;
654
655 /* disable FIS reception */
656 tmp = readl(port_mmio + PORT_CMD);
657 tmp &= ~PORT_CMD_FIS_RX;
658 writel(tmp, port_mmio + PORT_CMD);
659
660 /* wait for completion, spec says 500ms, give it 1000 */
97750ceb 661 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
365cfa1e
AV		 662 PORT_CMD_FIS_ON, 10, 1000);
663 if (tmp & PORT_CMD_FIS_ON)
664 return -EBUSY;
665
666 return 0;
667}
668
669static void ahci_power_up(struct ata_port *ap)
670{
671 struct ahci_host_priv *hpriv = ap->host->private_data;
672 void __iomem *port_mmio = ahci_port_base(ap);
673 u32 cmd;
674
675 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
676
677 /* spin up device */
678 if (hpriv->cap & HOST_CAP_SSS) {
679 cmd |= PORT_CMD_SPIN_UP;
680 writel(cmd, port_mmio + PORT_CMD);
681 }
682
683 /* wake up link */
684 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
685}
686
6b7ae954
TH		 687static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
688 unsigned int hints)
365cfa1e 689{
6b7ae954 690 struct ata_port *ap = link->ap;
365cfa1e 691 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 692 struct ahci_port_priv *pp = ap->private_data;
365cfa1e 693 void __iomem *port_mmio = ahci_port_base(ap);
365cfa1e 694
6b7ae954 695 if (policy != ATA_LPM_MAX_POWER) {
365cfa1e 696 /*
6b7ae954
TH		 697 * Disable interrupts on Phy Ready. This keeps us from
698 * getting woken up due to spurious phy ready
699 * interrupts.
365cfa1e 700 */
6b7ae954
TH		 701 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
702 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
703
704 sata_link_scr_lpm(link, policy, false);
365cfa1e
AV		 705 }
706
6b7ae954
TH		 707 if (hpriv->cap & HOST_CAP_ALPM) {
708 u32 cmd = readl(port_mmio + PORT_CMD);
365cfa1e 709
6b7ae954
TH		 710 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
711 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
712 cmd |= PORT_CMD_ICC_ACTIVE;
365cfa1e 713
6b7ae954
TH		 714 writel(cmd, port_mmio + PORT_CMD);
715 readl(port_mmio + PORT_CMD);
365cfa1e 716
6b7ae954 717 /* wait 10ms to be sure we've come out of LPM state */
97750ceb 718 ata_msleep(ap, 10);
6b7ae954
TH		 719 } else {
720 cmd |= PORT_CMD_ALPE;
721 if (policy == ATA_LPM_MIN_POWER)
722 cmd |= PORT_CMD_ASP;
365cfa1e 723
6b7ae954
TH		 724 /* write out new cmd value */
725 writel(cmd, port_mmio + PORT_CMD);
726 }
727 }
365cfa1e 728
65fe1f0f
SH		 729 /* set aggressive device sleep */
730 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
731 (hpriv->cap2 & HOST_CAP2_SADM) &&
732 (link->device->flags & ATA_DFLAG_DEVSLP)) {
733 if (policy == ATA_LPM_MIN_POWER)
734 ahci_set_aggressive_devslp(ap, true);
735 else
736 ahci_set_aggressive_devslp(ap, false);
737 }
738
6b7ae954
TH		 739 if (policy == ATA_LPM_MAX_POWER) {
740 sata_link_scr_lpm(link, policy, false);
741
742 /* turn PHYRDY IRQ back on */
743 pp->intr_mask |= PORT_IRQ_PHYRDY;
744 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
745 }
365cfa1e 746
365cfa1e
AV		 747 return 0;
748}
749
750#ifdef CONFIG_PM
751static void ahci_power_down(struct ata_port *ap)
752{
753 struct ahci_host_priv *hpriv = ap->host->private_data;
754 void __iomem *port_mmio = ahci_port_base(ap);
755 u32 cmd, scontrol;
756
757 if (!(hpriv->cap & HOST_CAP_SSS))
758 return;
759
760 /* put device into listen mode, first set PxSCTL.DET to 0 */
761 scontrol = readl(port_mmio + PORT_SCR_CTL);
762 scontrol &= ~0xf;
763 writel(scontrol, port_mmio + PORT_SCR_CTL);
764
765 /* then set PxCMD.SUD to 0 */
766 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
767 cmd &= ~PORT_CMD_SPIN_UP;
768 writel(cmd, port_mmio + PORT_CMD);
769}
770#endif
771
772static void ahci_start_port(struct ata_port *ap)
773{
66583c9f 774 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 775 struct ahci_port_priv *pp = ap->private_data;
776 struct ata_link *link;
777 struct ahci_em_priv *emp;
778 ssize_t rc;
779 int i;
780
781 /* enable FIS reception */
782 ahci_start_fis_rx(ap);
783
66583c9f
BN		 784 /* enable DMA */
785 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
039ece38 786 hpriv->start_engine(ap);
66583c9f 787
365cfa1e
AV		 788 /* turn on LEDs */
789 if (ap->flags & ATA_FLAG_EM) {
790 ata_for_each_link(link, ap, EDGE) {
791 emp = &pp->em_priv[link->pmp];
792
793 /* EM Transmit bit maybe busy during init */
794 for (i = 0; i < EM_MAX_RETRY; i++) {
439d7a35 795 rc = ap->ops->transmit_led_message(ap,
365cfa1e
AV		 796 emp->led_state,
797 4);
fa070ee6
LD		 798 /*
799 * If busy, give a breather but do not
800 * release EH ownership by using msleep()
801 * instead of ata_msleep(). EM Transmit
802 * bit is busy for the whole host and
803 * releasing ownership will cause other
804 * ports to fail the same way.
805 */
365cfa1e 806 if (rc == -EBUSY)
fa070ee6 807 msleep(1);
365cfa1e
AV		 808 else
809 break;
810 }
811 }
812 }
813
814 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
815 ata_for_each_link(link, ap, EDGE)
816 ahci_init_sw_activity(link);
817
818}
819
820static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
821{
822 int rc;
823
824 /* disable DMA */
825 rc = ahci_stop_engine(ap);
826 if (rc) {
827 *emsg = "failed to stop engine";
828 return rc;
829 }
830
831 /* disable FIS reception */
832 rc = ahci_stop_fis_rx(ap);
833 if (rc) {
834 *emsg = "failed stop FIS RX";
835 return rc;
836 }
837
838 return 0;
839}
840
841int ahci_reset_controller(struct ata_host *host)
842{
843 struct ahci_host_priv *hpriv = host->private_data;
844 void __iomem *mmio = hpriv->mmio;
845 u32 tmp;
846
847 /* we must be in AHCI mode, before using anything
848 * AHCI-specific, such as HOST_RESET.
849 */
850 ahci_enable_ahci(mmio);
851
852 /* global controller reset */
853 if (!ahci_skip_host_reset) {
854 tmp = readl(mmio + HOST_CTL);
855 if ((tmp & HOST_RESET) == 0) {
856 writel(tmp | HOST_RESET, mmio + HOST_CTL);
857 readl(mmio + HOST_CTL); /* flush */
858 }
859
860 /*
861 * to perform host reset, OS should set HOST_RESET
862 * and poll until this bit is read to be "0".
863 * reset must complete within 1 second, or
864 * the hardware should be considered fried.
865 */
97750ceb 866 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
365cfa1e
AV		 867 HOST_RESET, 10, 1000);
868
869 if (tmp & HOST_RESET) {
a44fec1f
JP		 870 dev_err(host->dev, "controller reset failed (0x%x)\n",
871 tmp);
365cfa1e
AV		 872 return -EIO;
873 }
874
875 /* turn on AHCI mode */
876 ahci_enable_ahci(mmio);
877
878 /* Some registers might be cleared on reset. Restore
879 * initial values.
880 */
881 ahci_restore_initial_config(host);
882 } else
a44fec1f 883 dev_info(host->dev, "skipping global host reset\n");
365cfa1e
AV		 884
885 return 0;
886}
887EXPORT_SYMBOL_GPL(ahci_reset_controller);
888
889static void ahci_sw_activity(struct ata_link *link)
890{
891 struct ata_port *ap = link->ap;
892 struct ahci_port_priv *pp = ap->private_data;
893 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
894
895 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
896 return;
897
898 emp->activity++;
899 if (!timer_pending(&emp->timer))
900 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
901}
902
903static void ahci_sw_activity_blink(unsigned long arg)
904{
905 struct ata_link *link = (struct ata_link *)arg;
906 struct ata_port *ap = link->ap;
907 struct ahci_port_priv *pp = ap->private_data;
908 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
909 unsigned long led_message = emp->led_state;
910 u32 activity_led_state;
911 unsigned long flags;
912
913 led_message &= EM_MSG_LED_VALUE;
914 led_message |= ap->port_no | (link->pmp << 8);
915
916 /* check to see if we've had activity. If so,
917 * toggle state of LED and reset timer. If not,
918 * turn LED to desired idle state.
919 */
920 spin_lock_irqsave(ap->lock, flags);
921 if (emp->saved_activity != emp->activity) {
922 emp->saved_activity = emp->activity;
923 /* get the current LED state */
924 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
925
926 if (activity_led_state)
927 activity_led_state = 0;
928 else
929 activity_led_state = 1;
930
931 /* clear old state */
932 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
933
934 /* toggle state */
935 led_message |= (activity_led_state << 16);
936 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
937 } else {
938 /* switch to idle */
939 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
940 if (emp->blink_policy == BLINK_OFF)
941 led_message |= (1 << 16);
942 }
943 spin_unlock_irqrestore(ap->lock, flags);
439d7a35 944 ap->ops->transmit_led_message(ap, led_message, 4);
365cfa1e
AV		 945}
946
947static void ahci_init_sw_activity(struct ata_link *link)
948{
949 struct ata_port *ap = link->ap;
950 struct ahci_port_priv *pp = ap->private_data;
951 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
952
953 /* init activity stats, setup timer */
954 emp->saved_activity = emp->activity = 0;
955 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
956
957 /* check our blink policy and set flag for link if it's enabled */
958 if (emp->blink_policy)
959 link->flags |= ATA_LFLAG_SW_ACTIVITY;
960}
961
962int ahci_reset_em(struct ata_host *host)
963{
964 struct ahci_host_priv *hpriv = host->private_data;
965 void __iomem *mmio = hpriv->mmio;
966 u32 em_ctl;
967
968 em_ctl = readl(mmio + HOST_EM_CTL);
969 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
970 return -EINVAL;
971
972 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
973 return 0;
974}
975EXPORT_SYMBOL_GPL(ahci_reset_em);
976
977static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
978 ssize_t size)
979{
980 struct ahci_host_priv *hpriv = ap->host->private_data;
981 struct ahci_port_priv *pp = ap->private_data;
982 void __iomem *mmio = hpriv->mmio;
983 u32 em_ctl;
984 u32 message[] = {0, 0};
985 unsigned long flags;
986 int pmp;
987 struct ahci_em_priv *emp;
988
989 /* get the slot number from the message */
990 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
991 if (pmp < EM_MAX_SLOTS)
992 emp = &pp->em_priv[pmp];
993 else
994 return -EINVAL;
995
996 spin_lock_irqsave(ap->lock, flags);
997
998 /*
999 * if we are still busy transmitting a previous message,
1000 * do not allow
1001 */
1002 em_ctl = readl(mmio + HOST_EM_CTL);
1003 if (em_ctl & EM_CTL_TM) {
1004 spin_unlock_irqrestore(ap->lock, flags);
1005 return -EBUSY;
1006 }
1007
008dbd61
HZ		 1008 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1009 /*
1010 * create message header - this is all zero except for
1011 * the message size, which is 4 bytes.
1012 */
1013 message[0] |= (4 << 8);
365cfa1e 1014
008dbd61
HZ		 1015 /* ignore 0:4 of byte zero, fill in port info yourself */
1016 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
365cfa1e 1017
008dbd61
HZ		 1018 /* write message to EM_LOC */
1019 writel(message[0], mmio + hpriv->em_loc);
1020 writel(message[1], mmio + hpriv->em_loc+4);
1021
1022 /*
1023 * tell hardware to transmit the message
1024 */
1025 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1026 }
365cfa1e
AV		 1027
1028 /* save off new led state for port/slot */
1029 emp->led_state = state;
1030
365cfa1e
AV		 1031 spin_unlock_irqrestore(ap->lock, flags);
1032 return size;
1033}
1034
1035static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1036{
1037 struct ahci_port_priv *pp = ap->private_data;
1038 struct ata_link *link;
1039 struct ahci_em_priv *emp;
1040 int rc = 0;
1041
1042 ata_for_each_link(link, ap, EDGE) {
1043 emp = &pp->em_priv[link->pmp];
1044 rc += sprintf(buf, "%lx\n", emp->led_state);
1045 }
1046 return rc;
1047}
1048
1049static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1050 size_t size)
1051{
b2a52b6a 1052 unsigned int state;
365cfa1e
AV		 1053 int pmp;
1054 struct ahci_port_priv *pp = ap->private_data;
1055 struct ahci_em_priv *emp;
1056
b2a52b6a
DY		 1057 if (kstrtouint(buf, 0, &state) < 0)
1058 return -EINVAL;
365cfa1e
AV		 1059
1060 /* get the slot number from the message */
1061 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1062 if (pmp < EM_MAX_SLOTS)
1063 emp = &pp->em_priv[pmp];
1064 else
1065 return -EINVAL;
1066
1067 /* mask off the activity bits if we are in sw_activity
1068 * mode, user should turn off sw_activity before setting
1069 * activity led through em_message
1070 */
1071 if (emp->blink_policy)
1072 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1073
439d7a35 1074 return ap->ops->transmit_led_message(ap, state, size);
365cfa1e
AV		 1075}
1076
1077static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1078{
1079 struct ata_link *link = dev->link;
1080 struct ata_port *ap = link->ap;
1081 struct ahci_port_priv *pp = ap->private_data;
1082 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1083 u32 port_led_state = emp->led_state;
1084
1085 /* save the desired Activity LED behavior */
1086 if (val == OFF) {
1087 /* clear LFLAG */
1088 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1089
1090 /* set the LED to OFF */
1091 port_led_state &= EM_MSG_LED_VALUE_OFF;
1092 port_led_state |= (ap->port_no | (link->pmp << 8));
439d7a35 1093 ap->ops->transmit_led_message(ap, port_led_state, 4);
365cfa1e
AV		 1094 } else {
1095 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1096 if (val == BLINK_OFF) {
1097 /* set LED to ON for idle */
1098 port_led_state &= EM_MSG_LED_VALUE_OFF;
1099 port_led_state |= (ap->port_no | (link->pmp << 8));
1100 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
439d7a35 1101 ap->ops->transmit_led_message(ap, port_led_state, 4);
365cfa1e
AV		 1102 }
1103 }
1104 emp->blink_policy = val;
1105 return 0;
1106}
1107
1108static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1109{
1110 struct ata_link *link = dev->link;
1111 struct ata_port *ap = link->ap;
1112 struct ahci_port_priv *pp = ap->private_data;
1113 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1114
1115 /* display the saved value of activity behavior for this
1116 * disk.
1117 */
1118 return sprintf(buf, "%d\n", emp->blink_policy);
1119}
1120
1121static void ahci_port_init(struct device *dev, struct ata_port *ap,
1122 int port_no, void __iomem *mmio,
1123 void __iomem *port_mmio)
1124{
1125 const char *emsg = NULL;
1126 int rc;
1127 u32 tmp;
1128
1129 /* make sure port is not active */
1130 rc = ahci_deinit_port(ap, &emsg);
1131 if (rc)
1132 dev_warn(dev, "%s (%d)\n", emsg, rc);
1133
1134 /* clear SError */
1135 tmp = readl(port_mmio + PORT_SCR_ERR);
1136 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1137 writel(tmp, port_mmio + PORT_SCR_ERR);
1138
1139 /* clear port IRQ */
1140 tmp = readl(port_mmio + PORT_IRQ_STAT);
1141 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1142 if (tmp)
1143 writel(tmp, port_mmio + PORT_IRQ_STAT);
1144
1145 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1146}
1147
1148void ahci_init_controller(struct ata_host *host)
1149{
1150 struct ahci_host_priv *hpriv = host->private_data;
1151 void __iomem *mmio = hpriv->mmio;
1152 int i;
1153 void __iomem *port_mmio;
1154 u32 tmp;
1155
1156 for (i = 0; i < host->n_ports; i++) {
1157 struct ata_port *ap = host->ports[i];
1158
1159 port_mmio = ahci_port_base(ap);
1160 if (ata_port_is_dummy(ap))
1161 continue;
1162
1163 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1164 }
1165
1166 tmp = readl(mmio + HOST_CTL);
1167 VPRINTK("HOST_CTL 0x%x\n", tmp);
1168 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1169 tmp = readl(mmio + HOST_CTL);
1170 VPRINTK("HOST_CTL 0x%x\n", tmp);
1171}
1172EXPORT_SYMBOL_GPL(ahci_init_controller);
1173
1174static void ahci_dev_config(struct ata_device *dev)
1175{
1176 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1177
1178 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1179 dev->max_sectors = 255;
a9a79dfe
JP		 1180 ata_dev_info(dev,
1181 "SB600 AHCI: limiting to 255 sectors per cmd\n");
365cfa1e
AV		 1182 }
1183}
1184
bbb4ab43 1185unsigned int ahci_dev_classify(struct ata_port *ap)
365cfa1e
AV		 1186{
1187 void __iomem *port_mmio = ahci_port_base(ap);
1188 struct ata_taskfile tf;
1189 u32 tmp;
1190
1191 tmp = readl(port_mmio + PORT_SIG);
1192 tf.lbah = (tmp >> 24) & 0xff;
1193 tf.lbam = (tmp >> 16) & 0xff;
1194 tf.lbal = (tmp >> 8) & 0xff;
1195 tf.nsect = (tmp) & 0xff;
1196
1197 return ata_dev_classify(&tf);
1198}
bbb4ab43 1199EXPORT_SYMBOL_GPL(ahci_dev_classify);
365cfa1e 1200
02cdfcf0
DM		 1201void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1202 u32 opts)
365cfa1e
AV		 1203{
1204 dma_addr_t cmd_tbl_dma;
1205
1206 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1207
1208 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1209 pp->cmd_slot[tag].status = 0;
1210 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1211 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1212}
02cdfcf0 1213EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
365cfa1e
AV		 1214
1215int ahci_kick_engine(struct ata_port *ap)
1216{
1217 void __iomem *port_mmio = ahci_port_base(ap);
1218 struct ahci_host_priv *hpriv = ap->host->private_data;
1219 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1220 u32 tmp;
1221 int busy, rc;
1222
1223 /* stop engine */
1224 rc = ahci_stop_engine(ap);
1225 if (rc)
1226 goto out_restart;
1227
1228 /* need to do CLO?
1229 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1230 */
1231 busy = status & (ATA_BUSY | ATA_DRQ);
1232 if (!busy && !sata_pmp_attached(ap)) {
1233 rc = 0;
1234 goto out_restart;
1235 }
1236
1237 if (!(hpriv->cap & HOST_CAP_CLO)) {
1238 rc = -EOPNOTSUPP;
1239 goto out_restart;
1240 }
1241
1242 /* perform CLO */
1243 tmp = readl(port_mmio + PORT_CMD);
1244 tmp |= PORT_CMD_CLO;
1245 writel(tmp, port_mmio + PORT_CMD);
1246
1247 rc = 0;
97750ceb 1248 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 1249 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1250 if (tmp & PORT_CMD_CLO)
1251 rc = -EIO;
1252
1253 /* restart engine */
1254 out_restart:
039ece38 1255 hpriv->start_engine(ap);
365cfa1e
AV		 1256 return rc;
1257}
1258EXPORT_SYMBOL_GPL(ahci_kick_engine);
1259
1260static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1261 struct ata_taskfile *tf, int is_cmd, u16 flags,
1262 unsigned long timeout_msec)
1263{
1264 const u32 cmd_fis_len = 5; /* five dwords */
1265 struct ahci_port_priv *pp = ap->private_data;
1266 void __iomem *port_mmio = ahci_port_base(ap);
1267 u8 *fis = pp->cmd_tbl;
1268 u32 tmp;
1269
1270 /* prep the command */
1271 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1272 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1273
1274 /* issue & wait */
1275 writel(1, port_mmio + PORT_CMD_ISSUE);
1276
1277 if (timeout_msec) {
97750ceb
TH		 1278 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1279 0x1, 0x1, 1, timeout_msec);
365cfa1e
AV		 1280 if (tmp & 0x1) {
1281 ahci_kick_engine(ap);
1282 return -EBUSY;
1283 }
1284 } else
1285 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1286
1287 return 0;
1288}
1289
1290int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1291 int pmp, unsigned long deadline,
1292 int (*check_ready)(struct ata_link *link))
1293{
1294 struct ata_port *ap = link->ap;
1295 struct ahci_host_priv *hpriv = ap->host->private_data;
89dafa20 1296 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 1297 const char *reason = NULL;
1298 unsigned long now, msecs;
1299 struct ata_taskfile tf;
89dafa20 1300 bool fbs_disabled = false;
365cfa1e
AV		 1301 int rc;
1302
1303 DPRINTK("ENTER\n");
1304
1305 /* prepare for SRST (AHCI-1.1 10.4.1) */
1306 rc = ahci_kick_engine(ap);
1307 if (rc && rc != -EOPNOTSUPP)
a9a79dfe 1308 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
365cfa1e 1309
89dafa20 1310 /*
1311 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1312 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1313 * that is attached to port multiplier.
1314 */
1315 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1316 ahci_disable_fbs(ap);
1317 fbs_disabled = true;
1318 }
1319
365cfa1e
AV		 1320 ata_tf_init(link->device, &tf);
1321
1322 /* issue the first D2H Register FIS */
1323 msecs = 0;
1324 now = jiffies;
f1f5a807 1325 if (time_after(deadline, now))
365cfa1e
AV		 1326 msecs = jiffies_to_msecs(deadline - now);
1327
1328 tf.ctl |= ATA_SRST;
1329 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1330 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1331 rc = -EIO;
1332 reason = "1st FIS failed";
1333 goto fail;
1334 }
1335
1336 /* spec says at least 5us, but be generous and sleep for 1ms */
97750ceb 1337 ata_msleep(ap, 1);
365cfa1e
AV		 1338
1339 /* issue the second D2H Register FIS */
1340 tf.ctl &= ~ATA_SRST;
1341 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1342
1343 /* wait for link to become ready */
1344 rc = ata_wait_after_reset(link, deadline, check_ready);
1345 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1346 /*
1347 * Workaround for cases where link online status can't
1348 * be trusted. Treat device readiness timeout as link
1349 * offline.
1350 */
a9a79dfe 1351 ata_link_info(link, "device not ready, treating as offline\n");
365cfa1e
AV		 1352 *class = ATA_DEV_NONE;
1353 } else if (rc) {
1354 /* link occupied, -ENODEV too is an error */
1355 reason = "device not ready";
1356 goto fail;
1357 } else
1358 *class = ahci_dev_classify(ap);
1359
89dafa20 1360 /* re-enable FBS if disabled before */
1361 if (fbs_disabled)
1362 ahci_enable_fbs(ap);
1363
365cfa1e
AV		 1364 DPRINTK("EXIT, class=%u\n", *class);
1365 return 0;
1366
1367 fail:
a9a79dfe 1368 ata_link_err(link, "softreset failed (%s)\n", reason);
365cfa1e
AV		 1369 return rc;
1370}
1371
1372int ahci_check_ready(struct ata_link *link)
1373{
1374 void __iomem *port_mmio = ahci_port_base(link->ap);
1375 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1376
1377 return ata_check_ready(status);
1378}
1379EXPORT_SYMBOL_GPL(ahci_check_ready);
1380
1381static int ahci_softreset(struct ata_link *link, unsigned int *class,
1382 unsigned long deadline)
1383{
1384 int pmp = sata_srst_pmp(link);
1385
1386 DPRINTK("ENTER\n");
1387
1388 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1389}
1390EXPORT_SYMBOL_GPL(ahci_do_softreset);
1391
345347c5
YHC		 1392static int ahci_bad_pmp_check_ready(struct ata_link *link)
1393{
1394 void __iomem *port_mmio = ahci_port_base(link->ap);
1395 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1396 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1397
1398 /*
1399 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1400 * which can save timeout delay.
1401 */
1402 if (irq_status & PORT_IRQ_BAD_PMP)
1403 return -EIO;
1404
1405 return ata_check_ready(status);
1406}
1407
35186d05
DY		 1408static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1409 unsigned long deadline)
345347c5
YHC		 1410{
1411 struct ata_port *ap = link->ap;
1412 void __iomem *port_mmio = ahci_port_base(ap);
1413 int pmp = sata_srst_pmp(link);
1414 int rc;
1415 u32 irq_sts;
1416
1417 DPRINTK("ENTER\n");
1418
1419 rc = ahci_do_softreset(link, class, pmp, deadline,
1420 ahci_bad_pmp_check_ready);
1421
1422 /*
1423 * Soft reset fails with IPMS set when PMP is enabled but
1424 * SATA HDD/ODD is connected to SATA port, do soft reset
1425 * again to port 0.
1426 */
1427 if (rc == -EIO) {
1428 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1429 if (irq_sts & PORT_IRQ_BAD_PMP) {
39f80acb 1430 ata_link_warn(link,
345347c5
YHC		 1431 "applying PMP SRST workaround "
1432 "and retrying\n");
1433 rc = ahci_do_softreset(link, class, 0, deadline,
1434 ahci_check_ready);
1435 }
1436 }
1437
1438 return rc;
1439}
1440
365cfa1e
AV		 1441static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1442 unsigned long deadline)
1443{
1444 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1445 struct ata_port *ap = link->ap;
1446 struct ahci_port_priv *pp = ap->private_data;
039ece38 1447 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 1448 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1449 struct ata_taskfile tf;
1450 bool online;
1451 int rc;
1452
1453 DPRINTK("ENTER\n");
1454
1455 ahci_stop_engine(ap);
1456
1457 /* clear D2H reception area to properly wait for D2H FIS */
1458 ata_tf_init(link->device, &tf);
9bbb1b0e 1459 tf.command = ATA_BUSY;
365cfa1e
AV		 1460 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1461
1462 rc = sata_link_hardreset(link, timing, deadline, &online,
1463 ahci_check_ready);
1464
039ece38 1465 hpriv->start_engine(ap);
365cfa1e
AV		 1466
1467 if (online)
1468 *class = ahci_dev_classify(ap);
1469
1470 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1471 return rc;
1472}
1473
1474static void ahci_postreset(struct ata_link *link, unsigned int *class)
1475{
1476 struct ata_port *ap = link->ap;
1477 void __iomem *port_mmio = ahci_port_base(ap);
1478 u32 new_tmp, tmp;
1479
1480 ata_std_postreset(link, class);
1481
1482 /* Make sure port's ATAPI bit is set appropriately */
1483 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1484 if (*class == ATA_DEV_ATAPI)
1485 new_tmp |= PORT_CMD_ATAPI;
1486 else
1487 new_tmp &= ~PORT_CMD_ATAPI;
1488 if (new_tmp != tmp) {
1489 writel(new_tmp, port_mmio + PORT_CMD);
1490 readl(port_mmio + PORT_CMD); /* flush */
1491 }
1492}
1493
1494static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1495{
1496 struct scatterlist *sg;
1497 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1498 unsigned int si;
1499
1500 VPRINTK("ENTER\n");
1501
1502 /*
1503 * Next, the S/G list.
1504 */
1505 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1506 dma_addr_t addr = sg_dma_address(sg);
1507 u32 sg_len = sg_dma_len(sg);
1508
1509 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1510 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1511 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1512 }
1513
1514 return si;
1515}
1516
1517static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1518{
1519 struct ata_port *ap = qc->ap;
1520 struct ahci_port_priv *pp = ap->private_data;
1521
1522 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1523 return ata_std_qc_defer(qc);
1524 else
1525 return sata_pmp_qc_defer_cmd_switch(qc);
1526}
1527
1528static void ahci_qc_prep(struct ata_queued_cmd *qc)
1529{
1530 struct ata_port *ap = qc->ap;
1531 struct ahci_port_priv *pp = ap->private_data;
1532 int is_atapi = ata_is_atapi(qc->tf.protocol);
1533 void *cmd_tbl;
1534 u32 opts;
1535 const u32 cmd_fis_len = 5; /* five dwords */
1536 unsigned int n_elem;
1537
1538 /*
1539 * Fill in command table information. First, the header,
1540 * a SATA Register - Host to Device command FIS.
1541 */
1542 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1543
1544 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1545 if (is_atapi) {
1546 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1547 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1548 }
1549
1550 n_elem = 0;
1551 if (qc->flags & ATA_QCFLAG_DMAMAP)
1552 n_elem = ahci_fill_sg(qc, cmd_tbl);
1553
1554 /*
1555 * Fill in command slot information.
1556 */
1557 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1558 if (qc->tf.flags & ATA_TFLAG_WRITE)
1559 opts |= AHCI_CMD_WRITE;
1560 if (is_atapi)
1561 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1562
1563 ahci_fill_cmd_slot(pp, qc->tag, opts);
1564}
1565
1566static void ahci_fbs_dec_intr(struct ata_port *ap)
1567{
1568 struct ahci_port_priv *pp = ap->private_data;
1569 void __iomem *port_mmio = ahci_port_base(ap);
1570 u32 fbs = readl(port_mmio + PORT_FBS);
1571 int retries = 3;
1572
1573 DPRINTK("ENTER\n");
1574 BUG_ON(!pp->fbs_enabled);
1575
1576 /* time to wait for DEC is not specified by AHCI spec,
1577 * add a retry loop for safety.
1578 */
1579 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1580 fbs = readl(port_mmio + PORT_FBS);
1581 while ((fbs & PORT_FBS_DEC) && retries--) {
1582 udelay(1);
1583 fbs = readl(port_mmio + PORT_FBS);
1584 }
1585
1586 if (fbs & PORT_FBS_DEC)
a44fec1f 1587 dev_err(ap->host->dev, "failed to clear device error\n");
365cfa1e
AV		 1588}
1589
1590static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1591{
1592 struct ahci_host_priv *hpriv = ap->host->private_data;
1593 struct ahci_port_priv *pp = ap->private_data;
1594 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1595 struct ata_link *link = NULL;
1596 struct ata_queued_cmd *active_qc;
1597 struct ata_eh_info *active_ehi;
1598 bool fbs_need_dec = false;
1599 u32 serror;
1600
1601 /* determine active link with error */
1602 if (pp->fbs_enabled) {
1603 void __iomem *port_mmio = ahci_port_base(ap);
1604 u32 fbs = readl(port_mmio + PORT_FBS);
1605 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1606
912b9ac6 1607 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
365cfa1e
AV		 1608 link = &ap->pmp_link[pmp];
1609 fbs_need_dec = true;
1610 }
1611
1612 } else
1613 ata_for_each_link(link, ap, EDGE)
1614 if (ata_link_active(link))
1615 break;
1616
1617 if (!link)
1618 link = &ap->link;
1619
1620 active_qc = ata_qc_from_tag(ap, link->active_tag);
1621 active_ehi = &link->eh_info;
1622
1623 /* record irq stat */
1624 ata_ehi_clear_desc(host_ehi);
1625 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1626
1627 /* AHCI needs SError cleared; otherwise, it might lock up */
1628 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1629 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1630 host_ehi->serror |= serror;
1631
1632 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1633 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1634 irq_stat &= ~PORT_IRQ_IF_ERR;
1635
1636 if (irq_stat & PORT_IRQ_TF_ERR) {
1637 /* If qc is active, charge it; otherwise, the active
1638 * link. There's no active qc on NCQ errors. It will
1639 * be determined by EH by reading log page 10h.
1640 */
1641 if (active_qc)
1642 active_qc->err_mask |= AC_ERR_DEV;
1643 else
1644 active_ehi->err_mask |= AC_ERR_DEV;
1645
1646 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1647 host_ehi->serror &= ~SERR_INTERNAL;
1648 }
1649
1650 if (irq_stat & PORT_IRQ_UNK_FIS) {
d5185d65 1651 u32 *unk = pp->rx_fis + RX_FIS_UNK;
365cfa1e
AV		 1652
1653 active_ehi->err_mask |= AC_ERR_HSM;
1654 active_ehi->action |= ATA_EH_RESET;
1655 ata_ehi_push_desc(active_ehi,
1656 "unknown FIS %08x %08x %08x %08x" ,
1657 unk[0], unk[1], unk[2], unk[3]);
1658 }
1659
1660 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1661 active_ehi->err_mask |= AC_ERR_HSM;
1662 active_ehi->action |= ATA_EH_RESET;
1663 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1664 }
1665
1666 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1667 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1668 host_ehi->action |= ATA_EH_RESET;
1669 ata_ehi_push_desc(host_ehi, "host bus error");
1670 }
1671
1672 if (irq_stat & PORT_IRQ_IF_ERR) {
1673 if (fbs_need_dec)
1674 active_ehi->err_mask |= AC_ERR_DEV;
1675 else {
1676 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1677 host_ehi->action |= ATA_EH_RESET;
1678 }
1679
1680 ata_ehi_push_desc(host_ehi, "interface fatal error");
1681 }
1682
1683 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1684 ata_ehi_hotplugged(host_ehi);
1685 ata_ehi_push_desc(host_ehi, "%s",
1686 irq_stat & PORT_IRQ_CONNECT ?
1687 "connection status changed" : "PHY RDY changed");
1688 }
1689
1690 /* okay, let's hand over to EH */
1691
1692 if (irq_stat & PORT_IRQ_FREEZE)
1693 ata_port_freeze(ap);
1694 else if (fbs_need_dec) {
1695 ata_link_abort(link);
1696 ahci_fbs_dec_intr(ap);
1697 } else
1698 ata_port_abort(ap);
1699}
1700
5ca72c4f
AG		 1701static void ahci_handle_port_interrupt(struct ata_port *ap,
1702 void __iomem *port_mmio, u32 status)
365cfa1e 1703{
365cfa1e
AV		 1704 struct ata_eh_info *ehi = &ap->link.eh_info;
1705 struct ahci_port_priv *pp = ap->private_data;
1706 struct ahci_host_priv *hpriv = ap->host->private_data;
1707 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
5ca72c4f 1708 u32 qc_active = 0;
365cfa1e
AV		 1709 int rc;
1710
365cfa1e
AV		 1711 /* ignore BAD_PMP while resetting */
1712 if (unlikely(resetting))
1713 status &= ~PORT_IRQ_BAD_PMP;
1714
6b7ae954
TH		 1715 /* if LPM is enabled, PHYRDY doesn't mean anything */
1716 if (ap->link.lpm_policy > ATA_LPM_MAX_POWER) {
365cfa1e 1717 status &= ~PORT_IRQ_PHYRDY;
6b7ae954 1718 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
365cfa1e
AV		 1719 }
1720
1721 if (unlikely(status & PORT_IRQ_ERROR)) {
1722 ahci_error_intr(ap, status);
1723 return;
1724 }
1725
1726 if (status & PORT_IRQ_SDB_FIS) {
1727 /* If SNotification is available, leave notification
1728 * handling to sata_async_notification(). If not,
1729 * emulate it by snooping SDB FIS RX area.
1730 *
1731 * Snooping FIS RX area is probably cheaper than
1732 * poking SNotification but some constrollers which
1733 * implement SNotification, ICH9 for example, don't
1734 * store AN SDB FIS into receive area.
1735 */
1736 if (hpriv->cap & HOST_CAP_SNTF)
1737 sata_async_notification(ap);
1738 else {
1739 /* If the 'N' bit in word 0 of the FIS is set,
1740 * we just received asynchronous notification.
1741 * Tell libata about it.
1742 *
1743 * Lack of SNotification should not appear in
1744 * ahci 1.2, so the workaround is unnecessary
1745 * when FBS is enabled.
1746 */
1747 if (pp->fbs_enabled)
1748 WARN_ON_ONCE(1);
1749 else {
1750 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1751 u32 f0 = le32_to_cpu(f[0]);
1752 if (f0 & (1 << 15))
1753 sata_async_notification(ap);
1754 }
1755 }
1756 }
1757
1758 /* pp->active_link is not reliable once FBS is enabled, both
1759 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1760 * NCQ and non-NCQ commands may be in flight at the same time.
1761 */
1762 if (pp->fbs_enabled) {
1763 if (ap->qc_active) {
1764 qc_active = readl(port_mmio + PORT_SCR_ACT);
1765 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1766 }
1767 } else {
1768 /* pp->active_link is valid iff any command is in flight */
1769 if (ap->qc_active && pp->active_link->sactive)
1770 qc_active = readl(port_mmio + PORT_SCR_ACT);
1771 else
1772 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1773 }
1774
1775
1776 rc = ata_qc_complete_multiple(ap, qc_active);
1777
1778 /* while resetting, invalid completions are expected */
1779 if (unlikely(rc < 0 && !resetting)) {
1780 ehi->err_mask |= AC_ERR_HSM;
1781 ehi->action |= ATA_EH_RESET;
1782 ata_port_freeze(ap);
1783 }
1784}
1785
73993396 1786static void ahci_port_intr(struct ata_port *ap)
5ca72c4f
AG		 1787{
1788 void __iomem *port_mmio = ahci_port_base(ap);
1789 u32 status;
1790
1791 status = readl(port_mmio + PORT_IRQ_STAT);
1792 writel(status, port_mmio + PORT_IRQ_STAT);
1793
1794 ahci_handle_port_interrupt(ap, port_mmio, status);
1795}
1796
1797irqreturn_t ahci_thread_fn(int irq, void *dev_instance)
1798{
1799 struct ata_port *ap = dev_instance;
1800 struct ahci_port_priv *pp = ap->private_data;
1801 void __iomem *port_mmio = ahci_port_base(ap);
1802 unsigned long flags;
1803 u32 status;
1804
1805 spin_lock_irqsave(&ap->host->lock, flags);
1806 status = pp->intr_status;
1807 if (status)
1808 pp->intr_status = 0;
1809 spin_unlock_irqrestore(&ap->host->lock, flags);
1810
1811 spin_lock_bh(ap->lock);
1812 ahci_handle_port_interrupt(ap, port_mmio, status);
1813 spin_unlock_bh(ap->lock);
1814
1815 return IRQ_HANDLED;
1816}
1817EXPORT_SYMBOL_GPL(ahci_thread_fn);
1818
73993396 1819static void ahci_hw_port_interrupt(struct ata_port *ap)
5ca72c4f
AG		 1820{
1821 void __iomem *port_mmio = ahci_port_base(ap);
1822 struct ahci_port_priv *pp = ap->private_data;
1823 u32 status;
1824
1825 status = readl(port_mmio + PORT_IRQ_STAT);
1826 writel(status, port_mmio + PORT_IRQ_STAT);
1827
1828 pp->intr_status |= status;
1829}
1830
1831irqreturn_t ahci_hw_interrupt(int irq, void *dev_instance)
1832{
1833 struct ata_port *ap_this = dev_instance;
1834 struct ahci_port_priv *pp = ap_this->private_data;
1835 struct ata_host *host = ap_this->host;
1836 struct ahci_host_priv *hpriv = host->private_data;
1837 void __iomem *mmio = hpriv->mmio;
1838 unsigned int i;
1839 u32 irq_stat, irq_masked;
1840
1841 VPRINTK("ENTER\n");
1842
1843 spin_lock(&host->lock);
1844
1845 irq_stat = readl(mmio + HOST_IRQ_STAT);
1846
1847 if (!irq_stat) {
1848 u32 status = pp->intr_status;
1849
1850 spin_unlock(&host->lock);
1851
1852 VPRINTK("EXIT\n");
1853
1854 return status ? IRQ_WAKE_THREAD : IRQ_NONE;
1855 }
1856
1857 irq_masked = irq_stat & hpriv->port_map;
1858
1859 for (i = 0; i < host->n_ports; i++) {
1860 struct ata_port *ap;
1861
1862 if (!(irq_masked & (1 << i)))
1863 continue;
1864
1865 ap = host->ports[i];
1866 if (ap) {
1867 ahci_hw_port_interrupt(ap);
1868 VPRINTK("port %u\n", i);
1869 } else {
1870 VPRINTK("port %u (no irq)\n", i);
1871 if (ata_ratelimit())
1872 dev_warn(host->dev,
1873 "interrupt on disabled port %u\n", i);
1874 }
1875 }
1876
1877 writel(irq_stat, mmio + HOST_IRQ_STAT);
1878
1879 spin_unlock(&host->lock);
1880
1881 VPRINTK("EXIT\n");
1882
1883 return IRQ_WAKE_THREAD;
1884}
1885EXPORT_SYMBOL_GPL(ahci_hw_interrupt);
1886
365cfa1e
AV		 1887irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1888{
1889 struct ata_host *host = dev_instance;
1890 struct ahci_host_priv *hpriv;
1891 unsigned int i, handled = 0;
1892 void __iomem *mmio;
1893 u32 irq_stat, irq_masked;
1894
1895 VPRINTK("ENTER\n");
1896
1897 hpriv = host->private_data;
1898 mmio = hpriv->mmio;
1899
1900 /* sigh. 0xffffffff is a valid return from h/w */
1901 irq_stat = readl(mmio + HOST_IRQ_STAT);
1902 if (!irq_stat)
1903 return IRQ_NONE;
1904
1905 irq_masked = irq_stat & hpriv->port_map;
1906
1907 spin_lock(&host->lock);
1908
1909 for (i = 0; i < host->n_ports; i++) {
1910 struct ata_port *ap;
1911
1912 if (!(irq_masked & (1 << i)))
1913 continue;
1914
1915 ap = host->ports[i];
1916 if (ap) {
1917 ahci_port_intr(ap);
1918 VPRINTK("port %u\n", i);
1919 } else {
1920 VPRINTK("port %u (no irq)\n", i);
1921 if (ata_ratelimit())
a44fec1f
JP		 1922 dev_warn(host->dev,
1923 "interrupt on disabled port %u\n", i);
365cfa1e
AV		 1924 }
1925
1926 handled = 1;
1927 }
1928
1929 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1930 * it should be cleared after all the port events are cleared;
1931 * otherwise, it will raise a spurious interrupt after each
1932 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1933 * information.
1934 *
1935 * Also, use the unmasked value to clear interrupt as spurious
1936 * pending event on a dummy port might cause screaming IRQ.
1937 */
1938 writel(irq_stat, mmio + HOST_IRQ_STAT);
1939
1940 spin_unlock(&host->lock);
1941
1942 VPRINTK("EXIT\n");
1943
1944 return IRQ_RETVAL(handled);
1945}
1946EXPORT_SYMBOL_GPL(ahci_interrupt);
1947
39e0ee99 1948unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
365cfa1e
AV		 1949{
1950 struct ata_port *ap = qc->ap;
1951 void __iomem *port_mmio = ahci_port_base(ap);
1952 struct ahci_port_priv *pp = ap->private_data;
1953
1954 /* Keep track of the currently active link. It will be used
1955 * in completion path to determine whether NCQ phase is in
1956 * progress.
1957 */
1958 pp->active_link = qc->dev->link;
1959
1960 if (qc->tf.protocol == ATA_PROT_NCQ)
1961 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1962
1963 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1964 u32 fbs = readl(port_mmio + PORT_FBS);
1965 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1966 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1967 writel(fbs, port_mmio + PORT_FBS);
1968 pp->fbs_last_dev = qc->dev->link->pmp;
1969 }
1970
1971 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1972
1973 ahci_sw_activity(qc->dev->link);
1974
1975 return 0;
1976}
39e0ee99 1977EXPORT_SYMBOL_GPL(ahci_qc_issue);
365cfa1e
AV		 1978
1979static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1980{
1981 struct ahci_port_priv *pp = qc->ap->private_data;
6ad60195 1982 u8 *rx_fis = pp->rx_fis;
365cfa1e
AV		 1983
1984 if (pp->fbs_enabled)
6ad60195
TH		 1985 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1986
1987 /*
1988 * After a successful execution of an ATA PIO data-in command,
1989 * the device doesn't send D2H Reg FIS to update the TF and
1990 * the host should take TF and E_Status from the preceding PIO
1991 * Setup FIS.
1992 */
1993 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
1994 !(qc->flags & ATA_QCFLAG_FAILED)) {
1995 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
1996 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
1997 } else
1998 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
365cfa1e 1999
365cfa1e
AV		 2000 return true;
2001}
2002
2003static void ahci_freeze(struct ata_port *ap)
2004{
2005 void __iomem *port_mmio = ahci_port_base(ap);
2006
2007 /* turn IRQ off */
2008 writel(0, port_mmio + PORT_IRQ_MASK);
2009}
2010
2011static void ahci_thaw(struct ata_port *ap)
2012{
2013 struct ahci_host_priv *hpriv = ap->host->private_data;
2014 void __iomem *mmio = hpriv->mmio;
2015 void __iomem *port_mmio = ahci_port_base(ap);
2016 u32 tmp;
2017 struct ahci_port_priv *pp = ap->private_data;
2018
2019 /* clear IRQ */
2020 tmp = readl(port_mmio + PORT_IRQ_STAT);
2021 writel(tmp, port_mmio + PORT_IRQ_STAT);
2022 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2023
2024 /* turn IRQ back on */
2025 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2026}
2027
8b789d89 2028void ahci_error_handler(struct ata_port *ap)
365cfa1e 2029{
039ece38
HG		 2030 struct ahci_host_priv *hpriv = ap->host->private_data;
2031
365cfa1e
AV		 2032 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2033 /* restart engine */
2034 ahci_stop_engine(ap);
039ece38 2035 hpriv->start_engine(ap);
365cfa1e
AV		 2036 }
2037
2038 sata_pmp_error_handler(ap);
0ee71952
TH		 2039
2040 if (!ata_dev_enabled(ap->link.device))
2041 ahci_stop_engine(ap);
365cfa1e 2042}
8b789d89 2043EXPORT_SYMBOL_GPL(ahci_error_handler);
365cfa1e
AV		 2044
2045static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2046{
2047 struct ata_port *ap = qc->ap;
2048
2049 /* make DMA engine forget about the failed command */
2050 if (qc->flags & ATA_QCFLAG_FAILED)
2051 ahci_kick_engine(ap);
2052}
2053
65fe1f0f
SH		 2054static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2055{
039ece38 2056 struct ahci_host_priv *hpriv = ap->host->private_data;
65fe1f0f
SH		 2057 void __iomem *port_mmio = ahci_port_base(ap);
2058 struct ata_device *dev = ap->link.device;
2059 u32 devslp, dm, dito, mdat, deto;
2060 int rc;
2061 unsigned int err_mask;
2062
2063 devslp = readl(port_mmio + PORT_DEVSLP);
2064 if (!(devslp & PORT_DEVSLP_DSP)) {
2065 dev_err(ap->host->dev, "port does not support device sleep\n");
2066 return;
2067 }
2068
2069 /* disable device sleep */
2070 if (!sleep) {
2071 if (devslp & PORT_DEVSLP_ADSE) {
2072 writel(devslp & ~PORT_DEVSLP_ADSE,
2073 port_mmio + PORT_DEVSLP);
2074 err_mask = ata_dev_set_feature(dev,
2075 SETFEATURES_SATA_DISABLE,
2076 SATA_DEVSLP);
2077 if (err_mask && err_mask != AC_ERR_DEV)
2078 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2079 }
2080 return;
2081 }
2082
2083 /* device sleep was already enabled */
2084 if (devslp & PORT_DEVSLP_ADSE)
2085 return;
2086
2087 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2088 rc = ahci_stop_engine(ap);
2089 if (rc)
2090 return;
2091
2092 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2093 dito = devslp_idle_timeout / (dm + 1);
2094 if (dito > 0x3ff)
2095 dito = 0x3ff;
2096
2097 /* Use the nominal value 10 ms if the read MDAT is zero,
2098 * the nominal value of DETO is 20 ms.
2099 */
803739d2 2100 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
65fe1f0f 2101 ATA_LOG_DEVSLP_VALID_MASK) {
803739d2 2102 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
65fe1f0f
SH		 2103 ATA_LOG_DEVSLP_MDAT_MASK;
2104 if (!mdat)
2105 mdat = 10;
803739d2 2106 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
65fe1f0f
SH		 2107 if (!deto)
2108 deto = 20;
2109 } else {
2110 mdat = 10;
2111 deto = 20;
2112 }
2113
2114 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2115 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2116 (deto << PORT_DEVSLP_DETO_OFFSET) |
2117 PORT_DEVSLP_ADSE);
2118 writel(devslp, port_mmio + PORT_DEVSLP);
2119
039ece38 2120 hpriv->start_engine(ap);
65fe1f0f
SH		 2121
2122 /* enable device sleep feature for the drive */
2123 err_mask = ata_dev_set_feature(dev,
2124 SETFEATURES_SATA_ENABLE,
2125 SATA_DEVSLP);
2126 if (err_mask && err_mask != AC_ERR_DEV)
2127 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2128}
2129
365cfa1e
AV		 2130static void ahci_enable_fbs(struct ata_port *ap)
2131{
039ece38 2132 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 2133 struct ahci_port_priv *pp = ap->private_data;
2134 void __iomem *port_mmio = ahci_port_base(ap);
2135 u32 fbs;
2136 int rc;
2137
2138 if (!pp->fbs_supported)
2139 return;
2140
2141 fbs = readl(port_mmio + PORT_FBS);
2142 if (fbs & PORT_FBS_EN) {
2143 pp->fbs_enabled = true;
2144 pp->fbs_last_dev = -1; /* initialization */
2145 return;
2146 }
2147
2148 rc = ahci_stop_engine(ap);
2149 if (rc)
2150 return;
2151
2152 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2153 fbs = readl(port_mmio + PORT_FBS);
2154 if (fbs & PORT_FBS_EN) {
a44fec1f 2155 dev_info(ap->host->dev, "FBS is enabled\n");
365cfa1e
AV		 2156 pp->fbs_enabled = true;
2157 pp->fbs_last_dev = -1; /* initialization */
2158 } else
a44fec1f 2159 dev_err(ap->host->dev, "Failed to enable FBS\n");
365cfa1e 2160
039ece38 2161 hpriv->start_engine(ap);
365cfa1e
AV		 2162}
2163
2164static void ahci_disable_fbs(struct ata_port *ap)
2165{
039ece38 2166 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 2167 struct ahci_port_priv *pp = ap->private_data;
2168 void __iomem *port_mmio = ahci_port_base(ap);
2169 u32 fbs;
2170 int rc;
2171
2172 if (!pp->fbs_supported)
2173 return;
2174
2175 fbs = readl(port_mmio + PORT_FBS);
2176 if ((fbs & PORT_FBS_EN) == 0) {
2177 pp->fbs_enabled = false;
2178 return;
2179 }
2180
2181 rc = ahci_stop_engine(ap);
2182 if (rc)
2183 return;
2184
2185 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2186 fbs = readl(port_mmio + PORT_FBS);
2187 if (fbs & PORT_FBS_EN)
a44fec1f 2188 dev_err(ap->host->dev, "Failed to disable FBS\n");
365cfa1e 2189 else {
a44fec1f 2190 dev_info(ap->host->dev, "FBS is disabled\n");
365cfa1e
AV		 2191 pp->fbs_enabled = false;
2192 }
2193
039ece38 2194 hpriv->start_engine(ap);
365cfa1e
AV		 2195}
2196
2197static void ahci_pmp_attach(struct ata_port *ap)
2198{
2199 void __iomem *port_mmio = ahci_port_base(ap);
2200 struct ahci_port_priv *pp = ap->private_data;
2201 u32 cmd;
2202
2203 cmd = readl(port_mmio + PORT_CMD);
2204 cmd |= PORT_CMD_PMP;
2205 writel(cmd, port_mmio + PORT_CMD);
2206
2207 ahci_enable_fbs(ap);
2208
2209 pp->intr_mask |= PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 2210
2211 /*
2212 * We must not change the port interrupt mask register if the
2213 * port is marked frozen, the value in pp->intr_mask will be
2214 * restored later when the port is thawed.
2215 *
2216 * Note that during initialization, the port is marked as
2217 * frozen since the irq handler is not yet registered.
2218 */
2219 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2220 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 2221}
2222
2223static void ahci_pmp_detach(struct ata_port *ap)
2224{
2225 void __iomem *port_mmio = ahci_port_base(ap);
2226 struct ahci_port_priv *pp = ap->private_data;
2227 u32 cmd;
2228
2229 ahci_disable_fbs(ap);
2230
2231 cmd = readl(port_mmio + PORT_CMD);
2232 cmd &= ~PORT_CMD_PMP;
2233 writel(cmd, port_mmio + PORT_CMD);
2234
2235 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 2236
2237 /* see comment above in ahci_pmp_attach() */
2238 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2239 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 2240}
2241
02cdfcf0 2242int ahci_port_resume(struct ata_port *ap)
365cfa1e
AV		 2243{
2244 ahci_power_up(ap);
2245 ahci_start_port(ap);
2246
2247 if (sata_pmp_attached(ap))
2248 ahci_pmp_attach(ap);
2249 else
2250 ahci_pmp_detach(ap);
2251
2252 return 0;
2253}
02cdfcf0 2254EXPORT_SYMBOL_GPL(ahci_port_resume);
365cfa1e
AV		 2255
2256#ifdef CONFIG_PM
2257static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2258{
2259 const char *emsg = NULL;
2260 int rc;
2261
2262 rc = ahci_deinit_port(ap, &emsg);
2263 if (rc == 0)
2264 ahci_power_down(ap);
2265 else {
a9a79dfe 2266 ata_port_err(ap, "%s (%d)\n", emsg, rc);
7faa33da 2267 ata_port_freeze(ap);
365cfa1e
AV		 2268 }
2269
2270 return rc;
2271}
2272#endif
2273
2274static int ahci_port_start(struct ata_port *ap)
2275{
2276 struct ahci_host_priv *hpriv = ap->host->private_data;
2277 struct device *dev = ap->host->dev;
2278 struct ahci_port_priv *pp;
2279 void *mem;
2280 dma_addr_t mem_dma;
2281 size_t dma_sz, rx_fis_sz;
2282
2283 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2284 if (!pp)
2285 return -ENOMEM;
2286
b29900e6
AG		 2287 if (ap->host->n_ports > 1) {
2288 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2289 if (!pp->irq_desc) {
2290 devm_kfree(dev, pp);
2291 return -ENOMEM;
2292 }
2293 snprintf(pp->irq_desc, 8,
2294 "%s%d", dev_driver_string(dev), ap->port_no);
2295 }
2296
365cfa1e
AV		 2297 /* check FBS capability */
2298 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2299 void __iomem *port_mmio = ahci_port_base(ap);
2300 u32 cmd = readl(port_mmio + PORT_CMD);
2301 if (cmd & PORT_CMD_FBSCP)
2302 pp->fbs_supported = true;
5f173107 2303 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
a44fec1f
JP		 2304 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2305 ap->port_no);
5f173107
TH		 2306 pp->fbs_supported = true;
2307 } else
a44fec1f
JP		 2308 dev_warn(dev, "port %d is not capable of FBS\n",
2309 ap->port_no);
365cfa1e
AV		 2310 }
2311
2312 if (pp->fbs_supported) {
2313 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2314 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2315 } else {
2316 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2317 rx_fis_sz = AHCI_RX_FIS_SZ;
2318 }
2319
2320 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2321 if (!mem)
2322 return -ENOMEM;
2323 memset(mem, 0, dma_sz);
2324
2325 /*
2326 * First item in chunk of DMA memory: 32-slot command table,
2327 * 32 bytes each in size
2328 */
2329 pp->cmd_slot = mem;
2330 pp->cmd_slot_dma = mem_dma;
2331
2332 mem += AHCI_CMD_SLOT_SZ;
2333 mem_dma += AHCI_CMD_SLOT_SZ;
2334
2335 /*
2336 * Second item: Received-FIS area
2337 */
2338 pp->rx_fis = mem;
2339 pp->rx_fis_dma = mem_dma;
2340
2341 mem += rx_fis_sz;
2342 mem_dma += rx_fis_sz;
2343
2344 /*
2345 * Third item: data area for storing a single command
2346 * and its scatter-gather table
2347 */
2348 pp->cmd_tbl = mem;
2349 pp->cmd_tbl_dma = mem_dma;
2350
2351 /*
2352 * Save off initial list of interrupts to be enabled.
2353 * This could be changed later
2354 */
2355 pp->intr_mask = DEF_PORT_IRQ;
2356
5ca72c4f
AG		 2357 /*
2358 * Switch to per-port locking in case each port has its own MSI vector.
2359 */
2360 if ((hpriv->flags & AHCI_HFLAG_MULTI_MSI)) {
2361 spin_lock_init(&pp->lock);
2362 ap->lock = &pp->lock;
2363 }
2364
365cfa1e
AV		 2365 ap->private_data = pp;
2366
2367 /* engage engines, captain */
2368 return ahci_port_resume(ap);
2369}
2370
2371static void ahci_port_stop(struct ata_port *ap)
2372{
2373 const char *emsg = NULL;
2374 int rc;
2375
2376 /* de-initialize port */
2377 rc = ahci_deinit_port(ap, &emsg);
2378 if (rc)
a9a79dfe 2379 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
365cfa1e
AV		 2380}
2381
2382void ahci_print_info(struct ata_host *host, const char *scc_s)
2383{
2384 struct ahci_host_priv *hpriv = host->private_data;
2385 void __iomem *mmio = hpriv->mmio;
2386 u32 vers, cap, cap2, impl, speed;
2387 const char *speed_s;
2388
2389 vers = readl(mmio + HOST_VERSION);
2390 cap = hpriv->cap;
2391 cap2 = hpriv->cap2;
2392 impl = hpriv->port_map;
2393
2394 speed = (cap >> 20) & 0xf;
2395 if (speed == 1)
2396 speed_s = "1.5";
2397 else if (speed == 2)
2398 speed_s = "3";
2399 else if (speed == 3)
2400 speed_s = "6";
2401 else
2402 speed_s = "?";
2403
2404 dev_info(host->dev,
2405 "AHCI %02x%02x.%02x%02x "
2406 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2407 ,
2408
2409 (vers >> 24) & 0xff,
2410 (vers >> 16) & 0xff,
2411 (vers >> 8) & 0xff,
2412 vers & 0xff,
2413
2414 ((cap >> 8) & 0x1f) + 1,
2415 (cap & 0x1f) + 1,
2416 speed_s,
2417 impl,
2418 scc_s);
2419
2420 dev_info(host->dev,
2421 "flags: "
2422 "%s%s%s%s%s%s%s"
2423 "%s%s%s%s%s%s%s"
65fe1f0f
SH		 2424 "%s%s%s%s%s%s%s"
2425 "%s%s\n"
365cfa1e
AV		 2426 ,
2427
2428 cap & HOST_CAP_64 ? "64bit " : "",
2429 cap & HOST_CAP_NCQ ? "ncq " : "",
2430 cap & HOST_CAP_SNTF ? "sntf " : "",
2431 cap & HOST_CAP_MPS ? "ilck " : "",
2432 cap & HOST_CAP_SSS ? "stag " : "",
2433 cap & HOST_CAP_ALPM ? "pm " : "",
2434 cap & HOST_CAP_LED ? "led " : "",
2435 cap & HOST_CAP_CLO ? "clo " : "",
2436 cap & HOST_CAP_ONLY ? "only " : "",
2437 cap & HOST_CAP_PMP ? "pmp " : "",
2438 cap & HOST_CAP_FBS ? "fbs " : "",
2439 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2440 cap & HOST_CAP_SSC ? "slum " : "",
2441 cap & HOST_CAP_PART ? "part " : "",
2442 cap & HOST_CAP_CCC ? "ccc " : "",
2443 cap & HOST_CAP_EMS ? "ems " : "",
2444 cap & HOST_CAP_SXS ? "sxs " : "",
65fe1f0f
SH		 2445 cap2 & HOST_CAP2_DESO ? "deso " : "",
2446 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2447 cap2 & HOST_CAP2_SDS ? "sds " : "",
365cfa1e
AV		 2448 cap2 & HOST_CAP2_APST ? "apst " : "",
2449 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2450 cap2 & HOST_CAP2_BOH ? "boh " : ""
2451 );
2452}
2453EXPORT_SYMBOL_GPL(ahci_print_info);
2454
2455void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2456 struct ata_port_info *pi)
2457{
2458 u8 messages;
2459 void __iomem *mmio = hpriv->mmio;
2460 u32 em_loc = readl(mmio + HOST_EM_LOC);
2461 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2462
2463 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2464 return;
2465
2466 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2467
008dbd61 2468 if (messages) {
365cfa1e
AV		 2469 /* store em_loc */
2470 hpriv->em_loc = ((em_loc >> 16) * 4);
c0623166 2471 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
008dbd61 2472 hpriv->em_msg_type = messages;
365cfa1e
AV		 2473 pi->flags |= ATA_FLAG_EM;
2474 if (!(em_ctl & EM_CTL_ALHD))
2475 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2476 }
2477}
2478EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2479
2480MODULE_AUTHOR("Jeff Garzik");
2481MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2482MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)