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Merge branch 'mailbox-for-next' of git://git.linaro.org/landing-teams/working/fujitsu...
[linux-2.6-block.git] / drivers / ata / libahci.c
CommitLineData
365cfa1e
AV		 1/*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <tj@kernel.org>
365cfa1e
AV		 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
fbaf666b 36#include <linux/gfp.h>
365cfa1e 37#include <linux/module.h>
365cfa1e
AV		 38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
41#include <linux/dma-mapping.h>
42#include <linux/device.h>
43#include <scsi/scsi_host.h>
44#include <scsi/scsi_cmnd.h>
45#include <linux/libata.h>
d684a90d 46#include <linux/pci.h>
365cfa1e 47#include "ahci.h"
65fe1f0f 48#include "libata.h"
365cfa1e
AV		 49
50static int ahci_skip_host_reset;
51int ahci_ignore_sss;
52EXPORT_SYMBOL_GPL(ahci_ignore_sss);
53
54module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
55MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
56
57module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
58MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
59
6b7ae954
TH		 60static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
61 unsigned hints);
365cfa1e
AV		 62static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
63static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
64 size_t size);
65static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
66 ssize_t size);
67
68
69
70static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
71static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
365cfa1e
AV		 72static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
73static int ahci_port_start(struct ata_port *ap);
74static void ahci_port_stop(struct ata_port *ap);
75static void ahci_qc_prep(struct ata_queued_cmd *qc);
76static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
77static void ahci_freeze(struct ata_port *ap);
78static void ahci_thaw(struct ata_port *ap);
65fe1f0f 79static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
365cfa1e
AV		 80static void ahci_enable_fbs(struct ata_port *ap);
81static void ahci_disable_fbs(struct ata_port *ap);
82static void ahci_pmp_attach(struct ata_port *ap);
83static void ahci_pmp_detach(struct ata_port *ap);
84static int ahci_softreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
345347c5
YHC		 86static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
365cfa1e
AV		 88static int ahci_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90static void ahci_postreset(struct ata_link *link, unsigned int *class);
365cfa1e 91static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
365cfa1e 92static void ahci_dev_config(struct ata_device *dev);
365cfa1e
AV		 93#ifdef CONFIG_PM
94static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
95#endif
96static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
97static ssize_t ahci_activity_store(struct ata_device *dev,
98 enum sw_activity val);
99static void ahci_init_sw_activity(struct ata_link *link);
100
101static ssize_t ahci_show_host_caps(struct device *dev,
102 struct device_attribute *attr, char *buf);
103static ssize_t ahci_show_host_cap2(struct device *dev,
104 struct device_attribute *attr, char *buf);
105static ssize_t ahci_show_host_version(struct device *dev,
106 struct device_attribute *attr, char *buf);
107static ssize_t ahci_show_port_cmd(struct device *dev,
108 struct device_attribute *attr, char *buf);
c0623166
HZ		 109static ssize_t ahci_read_em_buffer(struct device *dev,
110 struct device_attribute *attr, char *buf);
111static ssize_t ahci_store_em_buffer(struct device *dev,
112 struct device_attribute *attr,
113 const char *buf, size_t size);
6e5fe5b1
HR		 114static ssize_t ahci_show_em_supported(struct device *dev,
115 struct device_attribute *attr, char *buf);
f070d671 116static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
365cfa1e
AV		 117
118static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
119static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
120static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
121static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
c0623166
HZ		 122static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
123 ahci_read_em_buffer, ahci_store_em_buffer);
6e5fe5b1 124static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
365cfa1e 125
fad16e7a 126struct device_attribute *ahci_shost_attrs[] = {
365cfa1e
AV		 127 &dev_attr_link_power_management_policy,
128 &dev_attr_em_message_type,
129 &dev_attr_em_message,
130 &dev_attr_ahci_host_caps,
131 &dev_attr_ahci_host_cap2,
132 &dev_attr_ahci_host_version,
133 &dev_attr_ahci_port_cmd,
c0623166 134 &dev_attr_em_buffer,
6e5fe5b1 135 &dev_attr_em_message_supported,
365cfa1e
AV		 136 NULL
137};
fad16e7a 138EXPORT_SYMBOL_GPL(ahci_shost_attrs);
365cfa1e 139
fad16e7a 140struct device_attribute *ahci_sdev_attrs[] = {
365cfa1e
AV		 141 &dev_attr_sw_activity,
142 &dev_attr_unload_heads,
143 NULL
144};
fad16e7a 145EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
365cfa1e
AV		 146
147struct ata_port_operations ahci_ops = {
148 .inherits = &sata_pmp_port_ops,
149
150 .qc_defer = ahci_pmp_qc_defer,
151 .qc_prep = ahci_qc_prep,
152 .qc_issue = ahci_qc_issue,
153 .qc_fill_rtf = ahci_qc_fill_rtf,
154
155 .freeze = ahci_freeze,
156 .thaw = ahci_thaw,
157 .softreset = ahci_softreset,
158 .hardreset = ahci_hardreset,
159 .postreset = ahci_postreset,
160 .pmp_softreset = ahci_softreset,
161 .error_handler = ahci_error_handler,
162 .post_internal_cmd = ahci_post_internal_cmd,
163 .dev_config = ahci_dev_config,
164
165 .scr_read = ahci_scr_read,
166 .scr_write = ahci_scr_write,
167 .pmp_attach = ahci_pmp_attach,
168 .pmp_detach = ahci_pmp_detach,
169
6b7ae954 170 .set_lpm = ahci_set_lpm,
365cfa1e
AV		 171 .em_show = ahci_led_show,
172 .em_store = ahci_led_store,
173 .sw_activity_show = ahci_activity_show,
174 .sw_activity_store = ahci_activity_store,
439d7a35 175 .transmit_led_message = ahci_transmit_led_message,
365cfa1e
AV		 176#ifdef CONFIG_PM
177 .port_suspend = ahci_port_suspend,
178 .port_resume = ahci_port_resume,
179#endif
180 .port_start = ahci_port_start,
181 .port_stop = ahci_port_stop,
182};
183EXPORT_SYMBOL_GPL(ahci_ops);
184
345347c5
YHC		 185struct ata_port_operations ahci_pmp_retry_srst_ops = {
186 .inherits = &ahci_ops,
187 .softreset = ahci_pmp_retry_softreset,
188};
189EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
190
ed08d40c 191static bool ahci_em_messages __read_mostly = true;
365cfa1e 192EXPORT_SYMBOL_GPL(ahci_em_messages);
ed08d40c 193module_param(ahci_em_messages, bool, 0444);
365cfa1e
AV		 194/* add other LED protocol types when they become supported */
195MODULE_PARM_DESC(ahci_em_messages,
008dbd61 196 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
365cfa1e 197
ed08d40c
CL		 198/* device sleep idle timeout in ms */
199static int devslp_idle_timeout __read_mostly = 1000;
65fe1f0f
SH		 200module_param(devslp_idle_timeout, int, 0644);
201MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
202
365cfa1e
AV		 203static void ahci_enable_ahci(void __iomem *mmio)
204{
205 int i;
206 u32 tmp;
207
208 /* turn on AHCI_EN */
209 tmp = readl(mmio + HOST_CTL);
210 if (tmp & HOST_AHCI_EN)
211 return;
212
213 /* Some controllers need AHCI_EN to be written multiple times.
214 * Try a few times before giving up.
215 */
216 for (i = 0; i < 5; i++) {
217 tmp |= HOST_AHCI_EN;
218 writel(tmp, mmio + HOST_CTL);
219 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
220 if (tmp & HOST_AHCI_EN)
221 return;
222 msleep(10);
223 }
224
225 WARN_ON(1);
226}
227
bb03c640
MW		 228/**
229 * ahci_rpm_get_port - Make sure the port is powered on
230 * @ap: Port to power on
231 *
232 * Whenever there is need to access the AHCI host registers outside of
233 * normal execution paths, call this function to make sure the host is
234 * actually powered on.
235 */
236static int ahci_rpm_get_port(struct ata_port *ap)
237{
238 return pm_runtime_get_sync(ap->dev);
239}
240
241/**
242 * ahci_rpm_put_port - Undoes ahci_rpm_get_port()
243 * @ap: Port to power down
244 *
245 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host
246 * if it has no more active users.
247 */
248static void ahci_rpm_put_port(struct ata_port *ap)
249{
250 pm_runtime_put(ap->dev);
251}
252
365cfa1e
AV		 253static ssize_t ahci_show_host_caps(struct device *dev,
254 struct device_attribute *attr, char *buf)
255{
256 struct Scsi_Host *shost = class_to_shost(dev);
257 struct ata_port *ap = ata_shost_to_port(shost);
258 struct ahci_host_priv *hpriv = ap->host->private_data;
259
260 return sprintf(buf, "%x\n", hpriv->cap);
261}
262
263static ssize_t ahci_show_host_cap2(struct device *dev,
264 struct device_attribute *attr, char *buf)
265{
266 struct Scsi_Host *shost = class_to_shost(dev);
267 struct ata_port *ap = ata_shost_to_port(shost);
268 struct ahci_host_priv *hpriv = ap->host->private_data;
269
270 return sprintf(buf, "%x\n", hpriv->cap2);
271}
272
273static ssize_t ahci_show_host_version(struct device *dev,
274 struct device_attribute *attr, char *buf)
275{
276 struct Scsi_Host *shost = class_to_shost(dev);
277 struct ata_port *ap = ata_shost_to_port(shost);
278 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 279
8ea909cb 280 return sprintf(buf, "%x\n", hpriv->version);
365cfa1e
AV		 281}
282
283static ssize_t ahci_show_port_cmd(struct device *dev,
284 struct device_attribute *attr, char *buf)
285{
286 struct Scsi_Host *shost = class_to_shost(dev);
287 struct ata_port *ap = ata_shost_to_port(shost);
288 void __iomem *port_mmio = ahci_port_base(ap);
bb03c640 289 ssize_t ret;
365cfa1e 290
bb03c640
MW		 291 ahci_rpm_get_port(ap);
292 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
293 ahci_rpm_put_port(ap);
294
295 return ret;
365cfa1e
AV		 296}
297
c0623166
HZ		 298static ssize_t ahci_read_em_buffer(struct device *dev,
299 struct device_attribute *attr, char *buf)
300{
301 struct Scsi_Host *shost = class_to_shost(dev);
302 struct ata_port *ap = ata_shost_to_port(shost);
303 struct ahci_host_priv *hpriv = ap->host->private_data;
304 void __iomem *mmio = hpriv->mmio;
305 void __iomem *em_mmio = mmio + hpriv->em_loc;
306 u32 em_ctl, msg;
307 unsigned long flags;
308 size_t count;
309 int i;
310
bb03c640 311 ahci_rpm_get_port(ap);
c0623166
HZ		 312 spin_lock_irqsave(ap->lock, flags);
313
314 em_ctl = readl(mmio + HOST_EM_CTL);
315 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
316 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
317 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 318 ahci_rpm_put_port(ap);
c0623166
HZ		 319 return -EINVAL;
320 }
321
322 if (!(em_ctl & EM_CTL_MR)) {
323 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 324 ahci_rpm_put_port(ap);
c0623166
HZ		 325 return -EAGAIN;
326 }
327
328 if (!(em_ctl & EM_CTL_SMB))
329 em_mmio += hpriv->em_buf_sz;
330
331 count = hpriv->em_buf_sz;
332
333 /* the count should not be larger than PAGE_SIZE */
334 if (count > PAGE_SIZE) {
335 if (printk_ratelimit())
a9a79dfe
JP		 336 ata_port_warn(ap,
337 "EM read buffer size too large: "
338 "buffer size %u, page size %lu\n",
339 hpriv->em_buf_sz, PAGE_SIZE);
c0623166
HZ		 340 count = PAGE_SIZE;
341 }
342
343 for (i = 0; i < count; i += 4) {
344 msg = readl(em_mmio + i);
345 buf[i] = msg & 0xff;
346 buf[i + 1] = (msg >> 8) & 0xff;
347 buf[i + 2] = (msg >> 16) & 0xff;
348 buf[i + 3] = (msg >> 24) & 0xff;
349 }
350
351 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 352 ahci_rpm_put_port(ap);
c0623166
HZ		 353
354 return i;
355}
356
357static ssize_t ahci_store_em_buffer(struct device *dev,
358 struct device_attribute *attr,
359 const char *buf, size_t size)
360{
361 struct Scsi_Host *shost = class_to_shost(dev);
362 struct ata_port *ap = ata_shost_to_port(shost);
363 struct ahci_host_priv *hpriv = ap->host->private_data;
364 void __iomem *mmio = hpriv->mmio;
365 void __iomem *em_mmio = mmio + hpriv->em_loc;
f9ce889b 366 const unsigned char *msg_buf = buf;
c0623166
HZ		 367 u32 em_ctl, msg;
368 unsigned long flags;
369 int i;
370
371 /* check size validity */
372 if (!(ap->flags & ATA_FLAG_EM) ||
373 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
374 size % 4 || size > hpriv->em_buf_sz)
375 return -EINVAL;
376
bb03c640 377 ahci_rpm_get_port(ap);
c0623166
HZ		 378 spin_lock_irqsave(ap->lock, flags);
379
380 em_ctl = readl(mmio + HOST_EM_CTL);
381 if (em_ctl & EM_CTL_TM) {
382 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 383 ahci_rpm_put_port(ap);
c0623166
HZ		 384 return -EBUSY;
385 }
386
387 for (i = 0; i < size; i += 4) {
f9ce889b
HZ		 388 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
389 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
c0623166
HZ		 390 writel(msg, em_mmio + i);
391 }
392
393 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
394
395 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 396 ahci_rpm_put_port(ap);
c0623166
HZ		 397
398 return size;
399}
400
6e5fe5b1
HR		 401static ssize_t ahci_show_em_supported(struct device *dev,
402 struct device_attribute *attr, char *buf)
403{
404 struct Scsi_Host *shost = class_to_shost(dev);
405 struct ata_port *ap = ata_shost_to_port(shost);
406 struct ahci_host_priv *hpriv = ap->host->private_data;
407 void __iomem *mmio = hpriv->mmio;
408 u32 em_ctl;
409
bb03c640 410 ahci_rpm_get_port(ap);
6e5fe5b1 411 em_ctl = readl(mmio + HOST_EM_CTL);
bb03c640 412 ahci_rpm_put_port(ap);
6e5fe5b1
HR		 413
414 return sprintf(buf, "%s%s%s%s\n",
415 em_ctl & EM_CTL_LED ? "led " : "",
416 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
417 em_ctl & EM_CTL_SES ? "ses-2 " : "",
418 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
419}
420
365cfa1e
AV		 421/**
422 * ahci_save_initial_config - Save and fixup initial config values
423 * @dev: target AHCI device
424 * @hpriv: host private area to store config values
365cfa1e
AV		 425 *
426 * Some registers containing configuration info might be setup by
427 * BIOS and might be cleared on reset. This function saves the
428 * initial values of those registers into @hpriv such that they
429 * can be restored after controller reset.
430 *
431 * If inconsistent, config values are fixed up by this function.
432 *
039ece38
HG		 433 * If it is not set already this function sets hpriv->start_engine to
434 * ahci_start_engine.
435 *
365cfa1e
AV		 436 * LOCKING:
437 * None.
438 */
725c7b57 439void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
365cfa1e
AV		 440{
441 void __iomem *mmio = hpriv->mmio;
442 u32 cap, cap2, vers, port_map;
443 int i;
444
445 /* make sure AHCI mode is enabled before accessing CAP */
446 ahci_enable_ahci(mmio);
447
448 /* Values prefixed with saved_ are written back to host after
449 * reset. Values without are used for driver operation.
450 */
451 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
452 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
453
454 /* CAP2 register is only defined for AHCI 1.2 and later */
455 vers = readl(mmio + HOST_VERSION);
456 if ((vers >> 16) > 1 ||
457 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
458 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
459 else
460 hpriv->saved_cap2 = cap2 = 0;
461
462 /* some chips have errata preventing 64bit use */
463 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
a44fec1f 464 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
365cfa1e
AV		 465 cap &= ~HOST_CAP_64;
466 }
467
468 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
a44fec1f 469 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
365cfa1e
AV		 470 cap &= ~HOST_CAP_NCQ;
471 }
472
473 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
a44fec1f 474 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
365cfa1e
AV		 475 cap |= HOST_CAP_NCQ;
476 }
477
478 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
a44fec1f 479 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
365cfa1e
AV		 480 cap &= ~HOST_CAP_PMP;
481 }
482
483 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
a44fec1f
JP		 484 dev_info(dev,
485 "controller can't do SNTF, turning off CAP_SNTF\n");
365cfa1e
AV		 486 cap &= ~HOST_CAP_SNTF;
487 }
488
0cf4a7d6
JP		 489 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
490 dev_info(dev,
491 "controller can't do DEVSLP, turning off\n");
492 cap2 &= ~HOST_CAP2_SDS;
493 cap2 &= ~HOST_CAP2_SADM;
494 }
495
5f173107 496 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
a44fec1f 497 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
5f173107
TH		 498 cap |= HOST_CAP_FBS;
499 }
500
888d91a0
KW		 501 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
502 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
503 cap &= ~HOST_CAP_FBS;
504 }
505
725c7b57 506 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
a44fec1f 507 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
725c7b57
AT		 508 port_map, hpriv->force_port_map);
509 port_map = hpriv->force_port_map;
365cfa1e
AV		 510 }
511
725c7b57 512 if (hpriv->mask_port_map) {
a44fec1f
JP		 513 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
514 port_map,
725c7b57
AT		 515 port_map & hpriv->mask_port_map);
516 port_map &= hpriv->mask_port_map;
365cfa1e
AV		 517 }
518
519 /* cross check port_map and cap.n_ports */
520 if (port_map) {
521 int map_ports = 0;
522
523 for (i = 0; i < AHCI_MAX_PORTS; i++)
524 if (port_map & (1 << i))
525 map_ports++;
526
527 /* If PI has more ports than n_ports, whine, clear
528 * port_map and let it be generated from n_ports.
529 */
530 if (map_ports > ahci_nr_ports(cap)) {
a44fec1f
JP		 531 dev_warn(dev,
532 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
533 port_map, ahci_nr_ports(cap));
365cfa1e
AV		 534 port_map = 0;
535 }
536 }
537
566d1827
TH		 538 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
539 if (!port_map && vers < 0x10300) {
365cfa1e 540 port_map = (1 << ahci_nr_ports(cap)) - 1;
a44fec1f 541 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
365cfa1e
AV		 542
543 /* write the fixed up value to the PI register */
544 hpriv->saved_port_map = port_map;
545 }
546
547 /* record values to use during operation */
548 hpriv->cap = cap;
549 hpriv->cap2 = cap2;
8ea909cb 550 hpriv->version = readl(mmio + HOST_VERSION);
365cfa1e 551 hpriv->port_map = port_map;
039ece38
HG		 552
553 if (!hpriv->start_engine)
554 hpriv->start_engine = ahci_start_engine;
f070d671
ST		 555
556 if (!hpriv->irq_handler)
d867b95f 557 hpriv->irq_handler = ahci_single_level_irq_intr;
365cfa1e
AV		 558}
559EXPORT_SYMBOL_GPL(ahci_save_initial_config);
560
561/**
562 * ahci_restore_initial_config - Restore initial config
563 * @host: target ATA host
564 *
565 * Restore initial config stored by ahci_save_initial_config().
566 *
567 * LOCKING:
568 * None.
569 */
570static void ahci_restore_initial_config(struct ata_host *host)
571{
572 struct ahci_host_priv *hpriv = host->private_data;
573 void __iomem *mmio = hpriv->mmio;
574
575 writel(hpriv->saved_cap, mmio + HOST_CAP);
576 if (hpriv->saved_cap2)
577 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
578 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
579 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
580}
581
582static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
583{
584 static const int offset[] = {
585 [SCR_STATUS] = PORT_SCR_STAT,
586 [SCR_CONTROL] = PORT_SCR_CTL,
587 [SCR_ERROR] = PORT_SCR_ERR,
588 [SCR_ACTIVE] = PORT_SCR_ACT,
589 [SCR_NOTIFICATION] = PORT_SCR_NTF,
590 };
591 struct ahci_host_priv *hpriv = ap->host->private_data;
592
593 if (sc_reg < ARRAY_SIZE(offset) &&
594 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
595 return offset[sc_reg];
596 return 0;
597}
598
599static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
600{
601 void __iomem *port_mmio = ahci_port_base(link->ap);
602 int offset = ahci_scr_offset(link->ap, sc_reg);
603
604 if (offset) {
605 *val = readl(port_mmio + offset);
606 return 0;
607 }
608 return -EINVAL;
609}
610
611static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
612{
613 void __iomem *port_mmio = ahci_port_base(link->ap);
614 int offset = ahci_scr_offset(link->ap, sc_reg);
615
616 if (offset) {
617 writel(val, port_mmio + offset);
618 return 0;
619 }
620 return -EINVAL;
621}
622
623void ahci_start_engine(struct ata_port *ap)
624{
625 void __iomem *port_mmio = ahci_port_base(ap);
626 u32 tmp;
627
628 /* start DMA */
629 tmp = readl(port_mmio + PORT_CMD);
630 tmp |= PORT_CMD_START;
631 writel(tmp, port_mmio + PORT_CMD);
632 readl(port_mmio + PORT_CMD); /* flush */
633}
634EXPORT_SYMBOL_GPL(ahci_start_engine);
635
636int ahci_stop_engine(struct ata_port *ap)
637{
638 void __iomem *port_mmio = ahci_port_base(ap);
fb329633 639 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 640 u32 tmp;
641
fb329633
DP		 642 /*
643 * On some controllers, stopping a port's DMA engine while the port
644 * is in ALPM state (partial or slumber) results in failures on
645 * subsequent DMA engine starts. For those controllers, put the
646 * port back in active state before stopping its DMA engine.
647 */
648 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
649 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
650 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
651 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
652 return -EIO;
653 }
654
365cfa1e
AV		 655 tmp = readl(port_mmio + PORT_CMD);
656
657 /* check if the HBA is idle */
658 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
659 return 0;
660
661 /* setting HBA to idle */
662 tmp &= ~PORT_CMD_START;
663 writel(tmp, port_mmio + PORT_CMD);
664
665 /* wait for engine to stop. This could be as long as 500 msec */
97750ceb 666 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 667 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
668 if (tmp & PORT_CMD_LIST_ON)
669 return -EIO;
670
671 return 0;
672}
673EXPORT_SYMBOL_GPL(ahci_stop_engine);
674
39e0ee99 675void ahci_start_fis_rx(struct ata_port *ap)
365cfa1e
AV		 676{
677 void __iomem *port_mmio = ahci_port_base(ap);
678 struct ahci_host_priv *hpriv = ap->host->private_data;
679 struct ahci_port_priv *pp = ap->private_data;
680 u32 tmp;
681
682 /* set FIS registers */
683 if (hpriv->cap & HOST_CAP_64)
684 writel((pp->cmd_slot_dma >> 16) >> 16,
685 port_mmio + PORT_LST_ADDR_HI);
686 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
687
688 if (hpriv->cap & HOST_CAP_64)
689 writel((pp->rx_fis_dma >> 16) >> 16,
690 port_mmio + PORT_FIS_ADDR_HI);
691 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
692
693 /* enable FIS reception */
694 tmp = readl(port_mmio + PORT_CMD);
695 tmp |= PORT_CMD_FIS_RX;
696 writel(tmp, port_mmio + PORT_CMD);
697
698 /* flush */
699 readl(port_mmio + PORT_CMD);
700}
39e0ee99 701EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
365cfa1e
AV		 702
703static int ahci_stop_fis_rx(struct ata_port *ap)
704{
705 void __iomem *port_mmio = ahci_port_base(ap);
706 u32 tmp;
707
708 /* disable FIS reception */
709 tmp = readl(port_mmio + PORT_CMD);
710 tmp &= ~PORT_CMD_FIS_RX;
711 writel(tmp, port_mmio + PORT_CMD);
712
713 /* wait for completion, spec says 500ms, give it 1000 */
97750ceb 714 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
365cfa1e
AV		 715 PORT_CMD_FIS_ON, 10, 1000);
716 if (tmp & PORT_CMD_FIS_ON)
717 return -EBUSY;
718
719 return 0;
720}
721
722static void ahci_power_up(struct ata_port *ap)
723{
724 struct ahci_host_priv *hpriv = ap->host->private_data;
725 void __iomem *port_mmio = ahci_port_base(ap);
726 u32 cmd;
727
728 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
729
730 /* spin up device */
731 if (hpriv->cap & HOST_CAP_SSS) {
732 cmd |= PORT_CMD_SPIN_UP;
733 writel(cmd, port_mmio + PORT_CMD);
734 }
735
736 /* wake up link */
737 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
738}
739
6b7ae954
TH		 740static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
741 unsigned int hints)
365cfa1e 742{
6b7ae954 743 struct ata_port *ap = link->ap;
365cfa1e 744 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 745 struct ahci_port_priv *pp = ap->private_data;
365cfa1e 746 void __iomem *port_mmio = ahci_port_base(ap);
365cfa1e 747
6b7ae954 748 if (policy != ATA_LPM_MAX_POWER) {
fb329633
DP		 749 /* wakeup flag only applies to the max power policy */
750 hints &= ~ATA_LPM_WAKE_ONLY;
751
365cfa1e 752 /*
6b7ae954
TH		 753 * Disable interrupts on Phy Ready. This keeps us from
754 * getting woken up due to spurious phy ready
755 * interrupts.
365cfa1e 756 */
6b7ae954
TH		 757 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
758 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
759
760 sata_link_scr_lpm(link, policy, false);
365cfa1e
AV		 761 }
762
6b7ae954
TH		 763 if (hpriv->cap & HOST_CAP_ALPM) {
764 u32 cmd = readl(port_mmio + PORT_CMD);
365cfa1e 765
6b7ae954 766 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
fb329633
DP		 767 if (!(hints & ATA_LPM_WAKE_ONLY))
768 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
6b7ae954 769 cmd |= PORT_CMD_ICC_ACTIVE;
365cfa1e 770
6b7ae954
TH		 771 writel(cmd, port_mmio + PORT_CMD);
772 readl(port_mmio + PORT_CMD);
365cfa1e 773
6b7ae954 774 /* wait 10ms to be sure we've come out of LPM state */
97750ceb 775 ata_msleep(ap, 10);
fb329633
DP		 776
777 if (hints & ATA_LPM_WAKE_ONLY)
778 return 0;
6b7ae954
TH		 779 } else {
780 cmd |= PORT_CMD_ALPE;
781 if (policy == ATA_LPM_MIN_POWER)
782 cmd |= PORT_CMD_ASP;
365cfa1e 783
6b7ae954
TH		 784 /* write out new cmd value */
785 writel(cmd, port_mmio + PORT_CMD);
786 }
787 }
365cfa1e 788
65fe1f0f
SH		 789 /* set aggressive device sleep */
790 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
791 (hpriv->cap2 & HOST_CAP2_SADM) &&
792 (link->device->flags & ATA_DFLAG_DEVSLP)) {
793 if (policy == ATA_LPM_MIN_POWER)
794 ahci_set_aggressive_devslp(ap, true);
795 else
796 ahci_set_aggressive_devslp(ap, false);
797 }
798
6b7ae954
TH		 799 if (policy == ATA_LPM_MAX_POWER) {
800 sata_link_scr_lpm(link, policy, false);
801
802 /* turn PHYRDY IRQ back on */
803 pp->intr_mask |= PORT_IRQ_PHYRDY;
804 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
805 }
365cfa1e 806
365cfa1e
AV		 807 return 0;
808}
809
810#ifdef CONFIG_PM
811static void ahci_power_down(struct ata_port *ap)
812{
813 struct ahci_host_priv *hpriv = ap->host->private_data;
814 void __iomem *port_mmio = ahci_port_base(ap);
815 u32 cmd, scontrol;
816
817 if (!(hpriv->cap & HOST_CAP_SSS))
818 return;
819
820 /* put device into listen mode, first set PxSCTL.DET to 0 */
821 scontrol = readl(port_mmio + PORT_SCR_CTL);
822 scontrol &= ~0xf;
823 writel(scontrol, port_mmio + PORT_SCR_CTL);
824
825 /* then set PxCMD.SUD to 0 */
826 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
827 cmd &= ~PORT_CMD_SPIN_UP;
828 writel(cmd, port_mmio + PORT_CMD);
829}
830#endif
831
832static void ahci_start_port(struct ata_port *ap)
833{
66583c9f 834 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 835 struct ahci_port_priv *pp = ap->private_data;
836 struct ata_link *link;
837 struct ahci_em_priv *emp;
838 ssize_t rc;
839 int i;
840
841 /* enable FIS reception */
842 ahci_start_fis_rx(ap);
843
66583c9f
BN		 844 /* enable DMA */
845 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
039ece38 846 hpriv->start_engine(ap);
66583c9f 847
365cfa1e
AV		 848 /* turn on LEDs */
849 if (ap->flags & ATA_FLAG_EM) {
850 ata_for_each_link(link, ap, EDGE) {
851 emp = &pp->em_priv[link->pmp];
852
853 /* EM Transmit bit maybe busy during init */
854 for (i = 0; i < EM_MAX_RETRY; i++) {
439d7a35 855 rc = ap->ops->transmit_led_message(ap,
365cfa1e
AV		 856 emp->led_state,
857 4);
fa070ee6
LD		 858 /*
859 * If busy, give a breather but do not
860 * release EH ownership by using msleep()
861 * instead of ata_msleep(). EM Transmit
862 * bit is busy for the whole host and
863 * releasing ownership will cause other
864 * ports to fail the same way.
865 */
365cfa1e 866 if (rc == -EBUSY)
fa070ee6 867 msleep(1);
365cfa1e
AV		 868 else
869 break;
870 }
871 }
872 }
873
874 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
875 ata_for_each_link(link, ap, EDGE)
876 ahci_init_sw_activity(link);
877
878}
879
880static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
881{
882 int rc;
883
884 /* disable DMA */
885 rc = ahci_stop_engine(ap);
886 if (rc) {
887 *emsg = "failed to stop engine";
888 return rc;
889 }
890
891 /* disable FIS reception */
892 rc = ahci_stop_fis_rx(ap);
893 if (rc) {
894 *emsg = "failed stop FIS RX";
895 return rc;
896 }
897
898 return 0;
899}
900
901int ahci_reset_controller(struct ata_host *host)
902{
903 struct ahci_host_priv *hpriv = host->private_data;
904 void __iomem *mmio = hpriv->mmio;
905 u32 tmp;
906
907 /* we must be in AHCI mode, before using anything
908 * AHCI-specific, such as HOST_RESET.
909 */
910 ahci_enable_ahci(mmio);
911
912 /* global controller reset */
913 if (!ahci_skip_host_reset) {
914 tmp = readl(mmio + HOST_CTL);
915 if ((tmp & HOST_RESET) == 0) {
916 writel(tmp | HOST_RESET, mmio + HOST_CTL);
917 readl(mmio + HOST_CTL); /* flush */
918 }
919
920 /*
921 * to perform host reset, OS should set HOST_RESET
922 * and poll until this bit is read to be "0".
923 * reset must complete within 1 second, or
924 * the hardware should be considered fried.
925 */
97750ceb 926 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
365cfa1e
AV		 927 HOST_RESET, 10, 1000);
928
929 if (tmp & HOST_RESET) {
a44fec1f
JP		 930 dev_err(host->dev, "controller reset failed (0x%x)\n",
931 tmp);
365cfa1e
AV		 932 return -EIO;
933 }
934
935 /* turn on AHCI mode */
936 ahci_enable_ahci(mmio);
937
938 /* Some registers might be cleared on reset. Restore
939 * initial values.
940 */
941 ahci_restore_initial_config(host);
942 } else
a44fec1f 943 dev_info(host->dev, "skipping global host reset\n");
365cfa1e
AV		 944
945 return 0;
946}
947EXPORT_SYMBOL_GPL(ahci_reset_controller);
948
949static void ahci_sw_activity(struct ata_link *link)
950{
951 struct ata_port *ap = link->ap;
952 struct ahci_port_priv *pp = ap->private_data;
953 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
954
955 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
956 return;
957
958 emp->activity++;
959 if (!timer_pending(&emp->timer))
960 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
961}
962
963static void ahci_sw_activity_blink(unsigned long arg)
964{
965 struct ata_link *link = (struct ata_link *)arg;
966 struct ata_port *ap = link->ap;
967 struct ahci_port_priv *pp = ap->private_data;
968 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
969 unsigned long led_message = emp->led_state;
970 u32 activity_led_state;
971 unsigned long flags;
972
973 led_message &= EM_MSG_LED_VALUE;
974 led_message |= ap->port_no | (link->pmp << 8);
975
976 /* check to see if we've had activity. If so,
977 * toggle state of LED and reset timer. If not,
978 * turn LED to desired idle state.
979 */
980 spin_lock_irqsave(ap->lock, flags);
981 if (emp->saved_activity != emp->activity) {
982 emp->saved_activity = emp->activity;
983 /* get the current LED state */
984 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
985
986 if (activity_led_state)
987 activity_led_state = 0;
988 else
989 activity_led_state = 1;
990
991 /* clear old state */
992 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
993
994 /* toggle state */
995 led_message |= (activity_led_state << 16);
996 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
997 } else {
998 /* switch to idle */
999 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1000 if (emp->blink_policy == BLINK_OFF)
1001 led_message |= (1 << 16);
1002 }
1003 spin_unlock_irqrestore(ap->lock, flags);
439d7a35 1004 ap->ops->transmit_led_message(ap, led_message, 4);
365cfa1e
AV		 1005}
1006
1007static void ahci_init_sw_activity(struct ata_link *link)
1008{
1009 struct ata_port *ap = link->ap;
1010 struct ahci_port_priv *pp = ap->private_data;
1011 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1012
1013 /* init activity stats, setup timer */
1014 emp->saved_activity = emp->activity = 0;
1015 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1016
1017 /* check our blink policy and set flag for link if it's enabled */
1018 if (emp->blink_policy)
1019 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1020}
1021
1022int ahci_reset_em(struct ata_host *host)
1023{
1024 struct ahci_host_priv *hpriv = host->private_data;
1025 void __iomem *mmio = hpriv->mmio;
1026 u32 em_ctl;
1027
1028 em_ctl = readl(mmio + HOST_EM_CTL);
1029 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1030 return -EINVAL;
1031
1032 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1033 return 0;
1034}
1035EXPORT_SYMBOL_GPL(ahci_reset_em);
1036
1037static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1038 ssize_t size)
1039{
1040 struct ahci_host_priv *hpriv = ap->host->private_data;
1041 struct ahci_port_priv *pp = ap->private_data;
1042 void __iomem *mmio = hpriv->mmio;
1043 u32 em_ctl;
1044 u32 message[] = {0, 0};
1045 unsigned long flags;
1046 int pmp;
1047 struct ahci_em_priv *emp;
1048
1049 /* get the slot number from the message */
1050 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1051 if (pmp < EM_MAX_SLOTS)
1052 emp = &pp->em_priv[pmp];
1053 else
1054 return -EINVAL;
1055
bb03c640 1056 ahci_rpm_get_port(ap);
365cfa1e
AV		 1057 spin_lock_irqsave(ap->lock, flags);
1058
1059 /*
1060 * if we are still busy transmitting a previous message,
1061 * do not allow
1062 */
1063 em_ctl = readl(mmio + HOST_EM_CTL);
1064 if (em_ctl & EM_CTL_TM) {
1065 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 1066 ahci_rpm_put_port(ap);
365cfa1e
AV		 1067 return -EBUSY;
1068 }
1069
008dbd61
HZ		 1070 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1071 /*
1072 * create message header - this is all zero except for
1073 * the message size, which is 4 bytes.
1074 */
1075 message[0] |= (4 << 8);
365cfa1e 1076
008dbd61
HZ		 1077 /* ignore 0:4 of byte zero, fill in port info yourself */
1078 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
365cfa1e 1079
008dbd61
HZ		 1080 /* write message to EM_LOC */
1081 writel(message[0], mmio + hpriv->em_loc);
1082 writel(message[1], mmio + hpriv->em_loc+4);
1083
1084 /*
1085 * tell hardware to transmit the message
1086 */
1087 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1088 }
365cfa1e
AV		 1089
1090 /* save off new led state for port/slot */
1091 emp->led_state = state;
1092
365cfa1e 1093 spin_unlock_irqrestore(ap->lock, flags);
bb03c640
MW		 1094 ahci_rpm_put_port(ap);
1095
365cfa1e
AV		 1096 return size;
1097}
1098
1099static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1100{
1101 struct ahci_port_priv *pp = ap->private_data;
1102 struct ata_link *link;
1103 struct ahci_em_priv *emp;
1104 int rc = 0;
1105
1106 ata_for_each_link(link, ap, EDGE) {
1107 emp = &pp->em_priv[link->pmp];
1108 rc += sprintf(buf, "%lx\n", emp->led_state);
1109 }
1110 return rc;
1111}
1112
1113static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1114 size_t size)
1115{
b2a52b6a 1116 unsigned int state;
365cfa1e
AV		 1117 int pmp;
1118 struct ahci_port_priv *pp = ap->private_data;
1119 struct ahci_em_priv *emp;
1120
b2a52b6a
DY		 1121 if (kstrtouint(buf, 0, &state) < 0)
1122 return -EINVAL;
365cfa1e
AV		 1123
1124 /* get the slot number from the message */
1125 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1126 if (pmp < EM_MAX_SLOTS)
1127 emp = &pp->em_priv[pmp];
1128 else
1129 return -EINVAL;
1130
1131 /* mask off the activity bits if we are in sw_activity
1132 * mode, user should turn off sw_activity before setting
1133 * activity led through em_message
1134 */
1135 if (emp->blink_policy)
1136 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1137
439d7a35 1138 return ap->ops->transmit_led_message(ap, state, size);
365cfa1e
AV		 1139}
1140
1141static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1142{
1143 struct ata_link *link = dev->link;
1144 struct ata_port *ap = link->ap;
1145 struct ahci_port_priv *pp = ap->private_data;
1146 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1147 u32 port_led_state = emp->led_state;
1148
1149 /* save the desired Activity LED behavior */
1150 if (val == OFF) {
1151 /* clear LFLAG */
1152 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1153
1154 /* set the LED to OFF */
1155 port_led_state &= EM_MSG_LED_VALUE_OFF;
1156 port_led_state |= (ap->port_no | (link->pmp << 8));
439d7a35 1157 ap->ops->transmit_led_message(ap, port_led_state, 4);
365cfa1e
AV		 1158 } else {
1159 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1160 if (val == BLINK_OFF) {
1161 /* set LED to ON for idle */
1162 port_led_state &= EM_MSG_LED_VALUE_OFF;
1163 port_led_state |= (ap->port_no | (link->pmp << 8));
1164 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
439d7a35 1165 ap->ops->transmit_led_message(ap, port_led_state, 4);
365cfa1e
AV		 1166 }
1167 }
1168 emp->blink_policy = val;
1169 return 0;
1170}
1171
1172static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1173{
1174 struct ata_link *link = dev->link;
1175 struct ata_port *ap = link->ap;
1176 struct ahci_port_priv *pp = ap->private_data;
1177 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1178
1179 /* display the saved value of activity behavior for this
1180 * disk.
1181 */
1182 return sprintf(buf, "%d\n", emp->blink_policy);
1183}
1184
1185static void ahci_port_init(struct device *dev, struct ata_port *ap,
1186 int port_no, void __iomem *mmio,
1187 void __iomem *port_mmio)
1188{
8a3e33cf 1189 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 1190 const char *emsg = NULL;
1191 int rc;
1192 u32 tmp;
1193
1194 /* make sure port is not active */
1195 rc = ahci_deinit_port(ap, &emsg);
1196 if (rc)
1197 dev_warn(dev, "%s (%d)\n", emsg, rc);
1198
1199 /* clear SError */
1200 tmp = readl(port_mmio + PORT_SCR_ERR);
1201 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1202 writel(tmp, port_mmio + PORT_SCR_ERR);
1203
1204 /* clear port IRQ */
1205 tmp = readl(port_mmio + PORT_IRQ_STAT);
1206 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1207 if (tmp)
1208 writel(tmp, port_mmio + PORT_IRQ_STAT);
1209
1210 writel(1 << port_no, mmio + HOST_IRQ_STAT);
8a3e33cf
ML		 1211
1212 /* mark esata ports */
1213 tmp = readl(port_mmio + PORT_CMD);
dc8b4afc 1214 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
8a3e33cf 1215 ap->pflags |= ATA_PFLAG_EXTERNAL;
365cfa1e
AV		 1216}
1217
1218void ahci_init_controller(struct ata_host *host)
1219{
1220 struct ahci_host_priv *hpriv = host->private_data;
1221 void __iomem *mmio = hpriv->mmio;
1222 int i;
1223 void __iomem *port_mmio;
1224 u32 tmp;
1225
1226 for (i = 0; i < host->n_ports; i++) {
1227 struct ata_port *ap = host->ports[i];
1228
1229 port_mmio = ahci_port_base(ap);
1230 if (ata_port_is_dummy(ap))
1231 continue;
1232
1233 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1234 }
1235
1236 tmp = readl(mmio + HOST_CTL);
1237 VPRINTK("HOST_CTL 0x%x\n", tmp);
1238 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1239 tmp = readl(mmio + HOST_CTL);
1240 VPRINTK("HOST_CTL 0x%x\n", tmp);
1241}
1242EXPORT_SYMBOL_GPL(ahci_init_controller);
1243
1244static void ahci_dev_config(struct ata_device *dev)
1245{
1246 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1247
1248 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1249 dev->max_sectors = 255;
a9a79dfe
JP		 1250 ata_dev_info(dev,
1251 "SB600 AHCI: limiting to 255 sectors per cmd\n");
365cfa1e
AV		 1252 }
1253}
1254
bbb4ab43 1255unsigned int ahci_dev_classify(struct ata_port *ap)
365cfa1e
AV		 1256{
1257 void __iomem *port_mmio = ahci_port_base(ap);
1258 struct ata_taskfile tf;
1259 u32 tmp;
1260
1261 tmp = readl(port_mmio + PORT_SIG);
1262 tf.lbah = (tmp >> 24) & 0xff;
1263 tf.lbam = (tmp >> 16) & 0xff;
1264 tf.lbal = (tmp >> 8) & 0xff;
1265 tf.nsect = (tmp) & 0xff;
1266
1267 return ata_dev_classify(&tf);
1268}
bbb4ab43 1269EXPORT_SYMBOL_GPL(ahci_dev_classify);
365cfa1e 1270
02cdfcf0
DM		 1271void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1272 u32 opts)
365cfa1e
AV		 1273{
1274 dma_addr_t cmd_tbl_dma;
1275
1276 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1277
1278 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1279 pp->cmd_slot[tag].status = 0;
1280 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1281 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1282}
02cdfcf0 1283EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
365cfa1e
AV		 1284
1285int ahci_kick_engine(struct ata_port *ap)
1286{
1287 void __iomem *port_mmio = ahci_port_base(ap);
1288 struct ahci_host_priv *hpriv = ap->host->private_data;
1289 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1290 u32 tmp;
1291 int busy, rc;
1292
1293 /* stop engine */
1294 rc = ahci_stop_engine(ap);
1295 if (rc)
1296 goto out_restart;
1297
1298 /* need to do CLO?
1299 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1300 */
1301 busy = status & (ATA_BUSY | ATA_DRQ);
1302 if (!busy && !sata_pmp_attached(ap)) {
1303 rc = 0;
1304 goto out_restart;
1305 }
1306
1307 if (!(hpriv->cap & HOST_CAP_CLO)) {
1308 rc = -EOPNOTSUPP;
1309 goto out_restart;
1310 }
1311
1312 /* perform CLO */
1313 tmp = readl(port_mmio + PORT_CMD);
1314 tmp |= PORT_CMD_CLO;
1315 writel(tmp, port_mmio + PORT_CMD);
1316
1317 rc = 0;
97750ceb 1318 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 1319 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1320 if (tmp & PORT_CMD_CLO)
1321 rc = -EIO;
1322
1323 /* restart engine */
1324 out_restart:
039ece38 1325 hpriv->start_engine(ap);
365cfa1e
AV		 1326 return rc;
1327}
1328EXPORT_SYMBOL_GPL(ahci_kick_engine);
1329
1330static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1331 struct ata_taskfile *tf, int is_cmd, u16 flags,
1332 unsigned long timeout_msec)
1333{
1334 const u32 cmd_fis_len = 5; /* five dwords */
1335 struct ahci_port_priv *pp = ap->private_data;
1336 void __iomem *port_mmio = ahci_port_base(ap);
1337 u8 *fis = pp->cmd_tbl;
1338 u32 tmp;
1339
1340 /* prep the command */
1341 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1342 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1343
023113d2
XY		 1344 /* set port value for softreset of Port Multiplier */
1345 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1346 tmp = readl(port_mmio + PORT_FBS);
1347 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1348 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1349 writel(tmp, port_mmio + PORT_FBS);
1350 pp->fbs_last_dev = pmp;
1351 }
1352
365cfa1e
AV		 1353 /* issue & wait */
1354 writel(1, port_mmio + PORT_CMD_ISSUE);
1355
1356 if (timeout_msec) {
97750ceb
TH		 1357 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1358 0x1, 0x1, 1, timeout_msec);
365cfa1e
AV		 1359 if (tmp & 0x1) {
1360 ahci_kick_engine(ap);
1361 return -EBUSY;
1362 }
1363 } else
1364 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1365
1366 return 0;
1367}
1368
1369int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1370 int pmp, unsigned long deadline,
1371 int (*check_ready)(struct ata_link *link))
1372{
1373 struct ata_port *ap = link->ap;
1374 struct ahci_host_priv *hpriv = ap->host->private_data;
89dafa20 1375 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 1376 const char *reason = NULL;
1377 unsigned long now, msecs;
1378 struct ata_taskfile tf;
89dafa20 1379 bool fbs_disabled = false;
365cfa1e
AV		 1380 int rc;
1381
1382 DPRINTK("ENTER\n");
1383
1384 /* prepare for SRST (AHCI-1.1 10.4.1) */
1385 rc = ahci_kick_engine(ap);
1386 if (rc && rc != -EOPNOTSUPP)
a9a79dfe 1387 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
365cfa1e 1388
89dafa20 1389 /*
1390 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1391 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1392 * that is attached to port multiplier.
1393 */
1394 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1395 ahci_disable_fbs(ap);
1396 fbs_disabled = true;
1397 }
1398
365cfa1e
AV		 1399 ata_tf_init(link->device, &tf);
1400
1401 /* issue the first D2H Register FIS */
1402 msecs = 0;
1403 now = jiffies;
f1f5a807 1404 if (time_after(deadline, now))
365cfa1e
AV		 1405 msecs = jiffies_to_msecs(deadline - now);
1406
1407 tf.ctl |= ATA_SRST;
1408 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1409 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1410 rc = -EIO;
1411 reason = "1st FIS failed";
1412 goto fail;
1413 }
1414
1415 /* spec says at least 5us, but be generous and sleep for 1ms */
97750ceb 1416 ata_msleep(ap, 1);
365cfa1e
AV		 1417
1418 /* issue the second D2H Register FIS */
1419 tf.ctl &= ~ATA_SRST;
1420 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1421
1422 /* wait for link to become ready */
1423 rc = ata_wait_after_reset(link, deadline, check_ready);
1424 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1425 /*
1426 * Workaround for cases where link online status can't
1427 * be trusted. Treat device readiness timeout as link
1428 * offline.
1429 */
a9a79dfe 1430 ata_link_info(link, "device not ready, treating as offline\n");
365cfa1e
AV		 1431 *class = ATA_DEV_NONE;
1432 } else if (rc) {
1433 /* link occupied, -ENODEV too is an error */
1434 reason = "device not ready";
1435 goto fail;
1436 } else
1437 *class = ahci_dev_classify(ap);
1438
89dafa20 1439 /* re-enable FBS if disabled before */
1440 if (fbs_disabled)
1441 ahci_enable_fbs(ap);
1442
365cfa1e
AV		 1443 DPRINTK("EXIT, class=%u\n", *class);
1444 return 0;
1445
1446 fail:
a9a79dfe 1447 ata_link_err(link, "softreset failed (%s)\n", reason);
365cfa1e
AV		 1448 return rc;
1449}
1450
1451int ahci_check_ready(struct ata_link *link)
1452{
1453 void __iomem *port_mmio = ahci_port_base(link->ap);
1454 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1455
1456 return ata_check_ready(status);
1457}
1458EXPORT_SYMBOL_GPL(ahci_check_ready);
1459
1460static int ahci_softreset(struct ata_link *link, unsigned int *class,
1461 unsigned long deadline)
1462{
1463 int pmp = sata_srst_pmp(link);
1464
1465 DPRINTK("ENTER\n");
1466
1467 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1468}
1469EXPORT_SYMBOL_GPL(ahci_do_softreset);
1470
345347c5
YHC		 1471static int ahci_bad_pmp_check_ready(struct ata_link *link)
1472{
1473 void __iomem *port_mmio = ahci_port_base(link->ap);
1474 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1475 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1476
1477 /*
1478 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1479 * which can save timeout delay.
1480 */
1481 if (irq_status & PORT_IRQ_BAD_PMP)
1482 return -EIO;
1483
1484 return ata_check_ready(status);
1485}
1486
35186d05
DY		 1487static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1488 unsigned long deadline)
345347c5
YHC		 1489{
1490 struct ata_port *ap = link->ap;
1491 void __iomem *port_mmio = ahci_port_base(ap);
1492 int pmp = sata_srst_pmp(link);
1493 int rc;
1494 u32 irq_sts;
1495
1496 DPRINTK("ENTER\n");
1497
1498 rc = ahci_do_softreset(link, class, pmp, deadline,
1499 ahci_bad_pmp_check_ready);
1500
1501 /*
1502 * Soft reset fails with IPMS set when PMP is enabled but
1503 * SATA HDD/ODD is connected to SATA port, do soft reset
1504 * again to port 0.
1505 */
1506 if (rc == -EIO) {
1507 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1508 if (irq_sts & PORT_IRQ_BAD_PMP) {
39f80acb 1509 ata_link_warn(link,
345347c5
YHC		 1510 "applying PMP SRST workaround "
1511 "and retrying\n");
1512 rc = ahci_do_softreset(link, class, 0, deadline,
1513 ahci_check_ready);
1514 }
1515 }
1516
1517 return rc;
1518}
1519
365cfa1e
AV		 1520static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1521 unsigned long deadline)
1522{
1523 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1524 struct ata_port *ap = link->ap;
1525 struct ahci_port_priv *pp = ap->private_data;
039ece38 1526 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 1527 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1528 struct ata_taskfile tf;
1529 bool online;
1530 int rc;
1531
1532 DPRINTK("ENTER\n");
1533
1534 ahci_stop_engine(ap);
1535
1536 /* clear D2H reception area to properly wait for D2H FIS */
1537 ata_tf_init(link->device, &tf);
9bbb1b0e 1538 tf.command = ATA_BUSY;
365cfa1e
AV		 1539 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1540
1541 rc = sata_link_hardreset(link, timing, deadline, &online,
1542 ahci_check_ready);
1543
039ece38 1544 hpriv->start_engine(ap);
365cfa1e
AV		 1545
1546 if (online)
1547 *class = ahci_dev_classify(ap);
1548
1549 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1550 return rc;
1551}
1552
1553static void ahci_postreset(struct ata_link *link, unsigned int *class)
1554{
1555 struct ata_port *ap = link->ap;
1556 void __iomem *port_mmio = ahci_port_base(ap);
1557 u32 new_tmp, tmp;
1558
1559 ata_std_postreset(link, class);
1560
1561 /* Make sure port's ATAPI bit is set appropriately */
1562 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1563 if (*class == ATA_DEV_ATAPI)
1564 new_tmp |= PORT_CMD_ATAPI;
1565 else
1566 new_tmp &= ~PORT_CMD_ATAPI;
1567 if (new_tmp != tmp) {
1568 writel(new_tmp, port_mmio + PORT_CMD);
1569 readl(port_mmio + PORT_CMD); /* flush */
1570 }
1571}
1572
1573static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1574{
1575 struct scatterlist *sg;
1576 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1577 unsigned int si;
1578
1579 VPRINTK("ENTER\n");
1580
1581 /*
1582 * Next, the S/G list.
1583 */
1584 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1585 dma_addr_t addr = sg_dma_address(sg);
1586 u32 sg_len = sg_dma_len(sg);
1587
1588 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1589 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1590 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1591 }
1592
1593 return si;
1594}
1595
1596static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1597{
1598 struct ata_port *ap = qc->ap;
1599 struct ahci_port_priv *pp = ap->private_data;
1600
1601 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1602 return ata_std_qc_defer(qc);
1603 else
1604 return sata_pmp_qc_defer_cmd_switch(qc);
1605}
1606
1607static void ahci_qc_prep(struct ata_queued_cmd *qc)
1608{
1609 struct ata_port *ap = qc->ap;
1610 struct ahci_port_priv *pp = ap->private_data;
1611 int is_atapi = ata_is_atapi(qc->tf.protocol);
1612 void *cmd_tbl;
1613 u32 opts;
1614 const u32 cmd_fis_len = 5; /* five dwords */
1615 unsigned int n_elem;
1616
1617 /*
1618 * Fill in command table information. First, the header,
1619 * a SATA Register - Host to Device command FIS.
1620 */
1621 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1622
1623 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1624 if (is_atapi) {
1625 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1626 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1627 }
1628
1629 n_elem = 0;
1630 if (qc->flags & ATA_QCFLAG_DMAMAP)
1631 n_elem = ahci_fill_sg(qc, cmd_tbl);
1632
1633 /*
1634 * Fill in command slot information.
1635 */
1636 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1637 if (qc->tf.flags & ATA_TFLAG_WRITE)
1638 opts |= AHCI_CMD_WRITE;
1639 if (is_atapi)
1640 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1641
1642 ahci_fill_cmd_slot(pp, qc->tag, opts);
1643}
1644
1645static void ahci_fbs_dec_intr(struct ata_port *ap)
1646{
1647 struct ahci_port_priv *pp = ap->private_data;
1648 void __iomem *port_mmio = ahci_port_base(ap);
1649 u32 fbs = readl(port_mmio + PORT_FBS);
1650 int retries = 3;
1651
1652 DPRINTK("ENTER\n");
1653 BUG_ON(!pp->fbs_enabled);
1654
1655 /* time to wait for DEC is not specified by AHCI spec,
1656 * add a retry loop for safety.
1657 */
1658 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1659 fbs = readl(port_mmio + PORT_FBS);
1660 while ((fbs & PORT_FBS_DEC) && retries--) {
1661 udelay(1);
1662 fbs = readl(port_mmio + PORT_FBS);
1663 }
1664
1665 if (fbs & PORT_FBS_DEC)
a44fec1f 1666 dev_err(ap->host->dev, "failed to clear device error\n");
365cfa1e
AV		 1667}
1668
1669static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1670{
1671 struct ahci_host_priv *hpriv = ap->host->private_data;
1672 struct ahci_port_priv *pp = ap->private_data;
1673 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1674 struct ata_link *link = NULL;
1675 struct ata_queued_cmd *active_qc;
1676 struct ata_eh_info *active_ehi;
1677 bool fbs_need_dec = false;
1678 u32 serror;
1679
1680 /* determine active link with error */
1681 if (pp->fbs_enabled) {
1682 void __iomem *port_mmio = ahci_port_base(ap);
1683 u32 fbs = readl(port_mmio + PORT_FBS);
1684 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1685
912b9ac6 1686 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
365cfa1e
AV		 1687 link = &ap->pmp_link[pmp];
1688 fbs_need_dec = true;
1689 }
1690
1691 } else
1692 ata_for_each_link(link, ap, EDGE)
1693 if (ata_link_active(link))
1694 break;
1695
1696 if (!link)
1697 link = &ap->link;
1698
1699 active_qc = ata_qc_from_tag(ap, link->active_tag);
1700 active_ehi = &link->eh_info;
1701
1702 /* record irq stat */
1703 ata_ehi_clear_desc(host_ehi);
1704 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1705
1706 /* AHCI needs SError cleared; otherwise, it might lock up */
1707 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1708 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1709 host_ehi->serror |= serror;
1710
1711 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1712 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1713 irq_stat &= ~PORT_IRQ_IF_ERR;
1714
1715 if (irq_stat & PORT_IRQ_TF_ERR) {
1716 /* If qc is active, charge it; otherwise, the active
1717 * link. There's no active qc on NCQ errors. It will
1718 * be determined by EH by reading log page 10h.
1719 */
1720 if (active_qc)
1721 active_qc->err_mask |= AC_ERR_DEV;
1722 else
1723 active_ehi->err_mask |= AC_ERR_DEV;
1724
1725 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1726 host_ehi->serror &= ~SERR_INTERNAL;
1727 }
1728
1729 if (irq_stat & PORT_IRQ_UNK_FIS) {
d5185d65 1730 u32 *unk = pp->rx_fis + RX_FIS_UNK;
365cfa1e
AV		 1731
1732 active_ehi->err_mask |= AC_ERR_HSM;
1733 active_ehi->action |= ATA_EH_RESET;
1734 ata_ehi_push_desc(active_ehi,
1735 "unknown FIS %08x %08x %08x %08x" ,
1736 unk[0], unk[1], unk[2], unk[3]);
1737 }
1738
1739 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1740 active_ehi->err_mask |= AC_ERR_HSM;
1741 active_ehi->action |= ATA_EH_RESET;
1742 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1743 }
1744
1745 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1746 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1747 host_ehi->action |= ATA_EH_RESET;
1748 ata_ehi_push_desc(host_ehi, "host bus error");
1749 }
1750
1751 if (irq_stat & PORT_IRQ_IF_ERR) {
1752 if (fbs_need_dec)
1753 active_ehi->err_mask |= AC_ERR_DEV;
1754 else {
1755 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1756 host_ehi->action |= ATA_EH_RESET;
1757 }
1758
1759 ata_ehi_push_desc(host_ehi, "interface fatal error");
1760 }
1761
1762 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1763 ata_ehi_hotplugged(host_ehi);
1764 ata_ehi_push_desc(host_ehi, "%s",
1765 irq_stat & PORT_IRQ_CONNECT ?
1766 "connection status changed" : "PHY RDY changed");
1767 }
1768
1769 /* okay, let's hand over to EH */
1770
1771 if (irq_stat & PORT_IRQ_FREEZE)
1772 ata_port_freeze(ap);
1773 else if (fbs_need_dec) {
1774 ata_link_abort(link);
1775 ahci_fbs_dec_intr(ap);
1776 } else
1777 ata_port_abort(ap);
1778}
1779
5ca72c4f
AG		 1780static void ahci_handle_port_interrupt(struct ata_port *ap,
1781 void __iomem *port_mmio, u32 status)
365cfa1e 1782{
365cfa1e
AV		 1783 struct ata_eh_info *ehi = &ap->link.eh_info;
1784 struct ahci_port_priv *pp = ap->private_data;
1785 struct ahci_host_priv *hpriv = ap->host->private_data;
1786 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
5ca72c4f 1787 u32 qc_active = 0;
365cfa1e
AV		 1788 int rc;
1789
365cfa1e
AV		 1790 /* ignore BAD_PMP while resetting */
1791 if (unlikely(resetting))
1792 status &= ~PORT_IRQ_BAD_PMP;
1793
8393b811 1794 if (sata_lpm_ignore_phy_events(&ap->link)) {
365cfa1e 1795 status &= ~PORT_IRQ_PHYRDY;
6b7ae954 1796 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
365cfa1e
AV		 1797 }
1798
1799 if (unlikely(status & PORT_IRQ_ERROR)) {
1800 ahci_error_intr(ap, status);
1801 return;
1802 }
1803
1804 if (status & PORT_IRQ_SDB_FIS) {
1805 /* If SNotification is available, leave notification
1806 * handling to sata_async_notification(). If not,
1807 * emulate it by snooping SDB FIS RX area.
1808 *
1809 * Snooping FIS RX area is probably cheaper than
1810 * poking SNotification but some constrollers which
1811 * implement SNotification, ICH9 for example, don't
1812 * store AN SDB FIS into receive area.
1813 */
1814 if (hpriv->cap & HOST_CAP_SNTF)
1815 sata_async_notification(ap);
1816 else {
1817 /* If the 'N' bit in word 0 of the FIS is set,
1818 * we just received asynchronous notification.
1819 * Tell libata about it.
1820 *
1821 * Lack of SNotification should not appear in
1822 * ahci 1.2, so the workaround is unnecessary
1823 * when FBS is enabled.
1824 */
1825 if (pp->fbs_enabled)
1826 WARN_ON_ONCE(1);
1827 else {
1828 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1829 u32 f0 = le32_to_cpu(f[0]);
1830 if (f0 & (1 << 15))
1831 sata_async_notification(ap);
1832 }
1833 }
1834 }
1835
1836 /* pp->active_link is not reliable once FBS is enabled, both
1837 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1838 * NCQ and non-NCQ commands may be in flight at the same time.
1839 */
1840 if (pp->fbs_enabled) {
1841 if (ap->qc_active) {
1842 qc_active = readl(port_mmio + PORT_SCR_ACT);
1843 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1844 }
1845 } else {
1846 /* pp->active_link is valid iff any command is in flight */
1847 if (ap->qc_active && pp->active_link->sactive)
1848 qc_active = readl(port_mmio + PORT_SCR_ACT);
1849 else
1850 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1851 }
1852
1853
1854 rc = ata_qc_complete_multiple(ap, qc_active);
1855
1856 /* while resetting, invalid completions are expected */
1857 if (unlikely(rc < 0 && !resetting)) {
1858 ehi->err_mask |= AC_ERR_HSM;
1859 ehi->action |= ATA_EH_RESET;
1860 ata_port_freeze(ap);
1861 }
1862}
1863
7865f83f 1864static void ahci_port_intr(struct ata_port *ap)
5ca72c4f
AG		 1865{
1866 void __iomem *port_mmio = ahci_port_base(ap);
1867 u32 status;
1868
1869 status = readl(port_mmio + PORT_IRQ_STAT);
1870 writel(status, port_mmio + PORT_IRQ_STAT);
1871
7865f83f 1872 ahci_handle_port_interrupt(ap, port_mmio, status);
5ca72c4f
AG		 1873}
1874
a6b7fb76 1875static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
5ca72c4f
AG		 1876{
1877 struct ata_port *ap = dev_instance;
5ca72c4f 1878 void __iomem *port_mmio = ahci_port_base(ap);
5ca72c4f
AG		 1879 u32 status;
1880
5ca72c4f
AG		 1881 VPRINTK("ENTER\n");
1882
227dfb4d
AG		 1883 status = readl(port_mmio + PORT_IRQ_STAT);
1884 writel(status, port_mmio + PORT_IRQ_STAT);
5ca72c4f 1885
a6b7fb76
DW		 1886 spin_lock(ap->lock);
1887 ahci_handle_port_interrupt(ap, port_mmio, status);
1888 spin_unlock(ap->lock);
5ca72c4f
AG		 1889
1890 VPRINTK("EXIT\n");
1891
a6b7fb76 1892 return IRQ_HANDLED;
5ca72c4f 1893}
5ca72c4f 1894
f070d671 1895u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
365cfa1e 1896{
365cfa1e 1897 unsigned int i, handled = 0;
03e83cbd 1898
365cfa1e
AV		 1899 for (i = 0; i < host->n_ports; i++) {
1900 struct ata_port *ap;
1901
1902 if (!(irq_masked & (1 << i)))
1903 continue;
1904
1905 ap = host->ports[i];
1906 if (ap) {
7865f83f 1907 ahci_port_intr(ap);
365cfa1e
AV		 1908 VPRINTK("port %u\n", i);
1909 } else {
1910 VPRINTK("port %u (no irq)\n", i);
1911 if (ata_ratelimit())
a44fec1f
JP		 1912 dev_warn(host->dev,
1913 "interrupt on disabled port %u\n", i);
365cfa1e
AV		 1914 }
1915
1916 handled = 1;
1917 }
1918
a129db89
ST		 1919 return handled;
1920}
f070d671 1921EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
a129db89
ST		 1922
1923static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1924{
1925 struct ata_host *host = dev_instance;
1926 struct ahci_host_priv *hpriv;
1927 unsigned int rc = 0;
1928 void __iomem *mmio;
1929 u32 irq_stat, irq_masked;
1930
1931 VPRINTK("ENTER\n");
1932
1933 hpriv = host->private_data;
1934 mmio = hpriv->mmio;
1935
1936 /* sigh. 0xffffffff is a valid return from h/w */
1937 irq_stat = readl(mmio + HOST_IRQ_STAT);
1938 if (!irq_stat)
1939 return IRQ_NONE;
1940
1941 irq_masked = irq_stat & hpriv->port_map;
1942
1943 spin_lock(&host->lock);
1944
1945 rc = ahci_handle_port_intr(host, irq_masked);
365cfa1e
AV		 1946
1947 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1948 * it should be cleared after all the port events are cleared;
1949 * otherwise, it will raise a spurious interrupt after each
1950 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1951 * information.
1952 *
1953 * Also, use the unmasked value to clear interrupt as spurious
1954 * pending event on a dummy port might cause screaming IRQ.
1955 */
1956 writel(irq_stat, mmio + HOST_IRQ_STAT);
1957
03e83cbd
TH		 1958 spin_unlock(&host->lock);
1959
365cfa1e
AV		 1960 VPRINTK("EXIT\n");
1961
a129db89 1962 return IRQ_RETVAL(rc);
365cfa1e 1963}
365cfa1e 1964
39e0ee99 1965unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
365cfa1e
AV		 1966{
1967 struct ata_port *ap = qc->ap;
1968 void __iomem *port_mmio = ahci_port_base(ap);
1969 struct ahci_port_priv *pp = ap->private_data;
1970
1971 /* Keep track of the currently active link. It will be used
1972 * in completion path to determine whether NCQ phase is in
1973 * progress.
1974 */
1975 pp->active_link = qc->dev->link;
1976
1977 if (qc->tf.protocol == ATA_PROT_NCQ)
1978 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1979
1980 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1981 u32 fbs = readl(port_mmio + PORT_FBS);
1982 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1983 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1984 writel(fbs, port_mmio + PORT_FBS);
1985 pp->fbs_last_dev = qc->dev->link->pmp;
1986 }
1987
1988 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1989
1990 ahci_sw_activity(qc->dev->link);
1991
1992 return 0;
1993}
39e0ee99 1994EXPORT_SYMBOL_GPL(ahci_qc_issue);
365cfa1e
AV		 1995
1996static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1997{
1998 struct ahci_port_priv *pp = qc->ap->private_data;
6ad60195 1999 u8 *rx_fis = pp->rx_fis;
365cfa1e
AV		 2000
2001 if (pp->fbs_enabled)
6ad60195
TH		 2002 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2003
2004 /*
2005 * After a successful execution of an ATA PIO data-in command,
2006 * the device doesn't send D2H Reg FIS to update the TF and
2007 * the host should take TF and E_Status from the preceding PIO
2008 * Setup FIS.
2009 */
2010 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2011 !(qc->flags & ATA_QCFLAG_FAILED)) {
2012 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2013 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
2014 } else
2015 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
365cfa1e 2016
365cfa1e
AV		 2017 return true;
2018}
2019
2020static void ahci_freeze(struct ata_port *ap)
2021{
2022 void __iomem *port_mmio = ahci_port_base(ap);
2023
2024 /* turn IRQ off */
2025 writel(0, port_mmio + PORT_IRQ_MASK);
2026}
2027
2028static void ahci_thaw(struct ata_port *ap)
2029{
2030 struct ahci_host_priv *hpriv = ap->host->private_data;
2031 void __iomem *mmio = hpriv->mmio;
2032 void __iomem *port_mmio = ahci_port_base(ap);
2033 u32 tmp;
2034 struct ahci_port_priv *pp = ap->private_data;
2035
2036 /* clear IRQ */
2037 tmp = readl(port_mmio + PORT_IRQ_STAT);
2038 writel(tmp, port_mmio + PORT_IRQ_STAT);
2039 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2040
2041 /* turn IRQ back on */
2042 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2043}
2044
8b789d89 2045void ahci_error_handler(struct ata_port *ap)
365cfa1e 2046{
039ece38
HG		 2047 struct ahci_host_priv *hpriv = ap->host->private_data;
2048
365cfa1e
AV		 2049 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2050 /* restart engine */
2051 ahci_stop_engine(ap);
039ece38 2052 hpriv->start_engine(ap);
365cfa1e
AV		 2053 }
2054
2055 sata_pmp_error_handler(ap);
0ee71952
TH		 2056
2057 if (!ata_dev_enabled(ap->link.device))
2058 ahci_stop_engine(ap);
365cfa1e 2059}
8b789d89 2060EXPORT_SYMBOL_GPL(ahci_error_handler);
365cfa1e
AV		 2061
2062static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2063{
2064 struct ata_port *ap = qc->ap;
2065
2066 /* make DMA engine forget about the failed command */
2067 if (qc->flags & ATA_QCFLAG_FAILED)
2068 ahci_kick_engine(ap);
2069}
2070
65fe1f0f
SH		 2071static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2072{
039ece38 2073 struct ahci_host_priv *hpriv = ap->host->private_data;
65fe1f0f
SH		 2074 void __iomem *port_mmio = ahci_port_base(ap);
2075 struct ata_device *dev = ap->link.device;
2076 u32 devslp, dm, dito, mdat, deto;
2077 int rc;
2078 unsigned int err_mask;
2079
2080 devslp = readl(port_mmio + PORT_DEVSLP);
2081 if (!(devslp & PORT_DEVSLP_DSP)) {
95bbbe9a 2082 dev_info(ap->host->dev, "port does not support device sleep\n");
65fe1f0f
SH		 2083 return;
2084 }
2085
2086 /* disable device sleep */
2087 if (!sleep) {
2088 if (devslp & PORT_DEVSLP_ADSE) {
2089 writel(devslp & ~PORT_DEVSLP_ADSE,
2090 port_mmio + PORT_DEVSLP);
2091 err_mask = ata_dev_set_feature(dev,
2092 SETFEATURES_SATA_DISABLE,
2093 SATA_DEVSLP);
2094 if (err_mask && err_mask != AC_ERR_DEV)
2095 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2096 }
2097 return;
2098 }
2099
2100 /* device sleep was already enabled */
2101 if (devslp & PORT_DEVSLP_ADSE)
2102 return;
2103
2104 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2105 rc = ahci_stop_engine(ap);
2106 if (rc)
2107 return;
2108
2109 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2110 dito = devslp_idle_timeout / (dm + 1);
2111 if (dito > 0x3ff)
2112 dito = 0x3ff;
2113
2114 /* Use the nominal value 10 ms if the read MDAT is zero,
2115 * the nominal value of DETO is 20 ms.
2116 */
803739d2 2117 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
65fe1f0f 2118 ATA_LOG_DEVSLP_VALID_MASK) {
803739d2 2119 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
65fe1f0f
SH		 2120 ATA_LOG_DEVSLP_MDAT_MASK;
2121 if (!mdat)
2122 mdat = 10;
803739d2 2123 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
65fe1f0f
SH		 2124 if (!deto)
2125 deto = 20;
2126 } else {
2127 mdat = 10;
2128 deto = 20;
2129 }
2130
2131 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2132 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2133 (deto << PORT_DEVSLP_DETO_OFFSET) |
2134 PORT_DEVSLP_ADSE);
2135 writel(devslp, port_mmio + PORT_DEVSLP);
2136
039ece38 2137 hpriv->start_engine(ap);
65fe1f0f
SH		 2138
2139 /* enable device sleep feature for the drive */
2140 err_mask = ata_dev_set_feature(dev,
2141 SETFEATURES_SATA_ENABLE,
2142 SATA_DEVSLP);
2143 if (err_mask && err_mask != AC_ERR_DEV)
2144 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2145}
2146
365cfa1e
AV		 2147static void ahci_enable_fbs(struct ata_port *ap)
2148{
039ece38 2149 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 2150 struct ahci_port_priv *pp = ap->private_data;
2151 void __iomem *port_mmio = ahci_port_base(ap);
2152 u32 fbs;
2153 int rc;
2154
2155 if (!pp->fbs_supported)
2156 return;
2157
2158 fbs = readl(port_mmio + PORT_FBS);
2159 if (fbs & PORT_FBS_EN) {
2160 pp->fbs_enabled = true;
2161 pp->fbs_last_dev = -1; /* initialization */
2162 return;
2163 }
2164
2165 rc = ahci_stop_engine(ap);
2166 if (rc)
2167 return;
2168
2169 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2170 fbs = readl(port_mmio + PORT_FBS);
2171 if (fbs & PORT_FBS_EN) {
a44fec1f 2172 dev_info(ap->host->dev, "FBS is enabled\n");
365cfa1e
AV		 2173 pp->fbs_enabled = true;
2174 pp->fbs_last_dev = -1; /* initialization */
2175 } else
a44fec1f 2176 dev_err(ap->host->dev, "Failed to enable FBS\n");
365cfa1e 2177
039ece38 2178 hpriv->start_engine(ap);
365cfa1e
AV		 2179}
2180
2181static void ahci_disable_fbs(struct ata_port *ap)
2182{
039ece38 2183 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 2184 struct ahci_port_priv *pp = ap->private_data;
2185 void __iomem *port_mmio = ahci_port_base(ap);
2186 u32 fbs;
2187 int rc;
2188
2189 if (!pp->fbs_supported)
2190 return;
2191
2192 fbs = readl(port_mmio + PORT_FBS);
2193 if ((fbs & PORT_FBS_EN) == 0) {
2194 pp->fbs_enabled = false;
2195 return;
2196 }
2197
2198 rc = ahci_stop_engine(ap);
2199 if (rc)
2200 return;
2201
2202 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2203 fbs = readl(port_mmio + PORT_FBS);
2204 if (fbs & PORT_FBS_EN)
a44fec1f 2205 dev_err(ap->host->dev, "Failed to disable FBS\n");
365cfa1e 2206 else {
a44fec1f 2207 dev_info(ap->host->dev, "FBS is disabled\n");
365cfa1e
AV		 2208 pp->fbs_enabled = false;
2209 }
2210
039ece38 2211 hpriv->start_engine(ap);
365cfa1e
AV		 2212}
2213
2214static void ahci_pmp_attach(struct ata_port *ap)
2215{
2216 void __iomem *port_mmio = ahci_port_base(ap);
2217 struct ahci_port_priv *pp = ap->private_data;
2218 u32 cmd;
2219
2220 cmd = readl(port_mmio + PORT_CMD);
2221 cmd |= PORT_CMD_PMP;
2222 writel(cmd, port_mmio + PORT_CMD);
2223
2224 ahci_enable_fbs(ap);
2225
2226 pp->intr_mask |= PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 2227
2228 /*
2229 * We must not change the port interrupt mask register if the
2230 * port is marked frozen, the value in pp->intr_mask will be
2231 * restored later when the port is thawed.
2232 *
2233 * Note that during initialization, the port is marked as
2234 * frozen since the irq handler is not yet registered.
2235 */
2236 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2237 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 2238}
2239
2240static void ahci_pmp_detach(struct ata_port *ap)
2241{
2242 void __iomem *port_mmio = ahci_port_base(ap);
2243 struct ahci_port_priv *pp = ap->private_data;
2244 u32 cmd;
2245
2246 ahci_disable_fbs(ap);
2247
2248 cmd = readl(port_mmio + PORT_CMD);
2249 cmd &= ~PORT_CMD_PMP;
2250 writel(cmd, port_mmio + PORT_CMD);
2251
2252 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 2253
2254 /* see comment above in ahci_pmp_attach() */
2255 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2256 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 2257}
2258
02cdfcf0 2259int ahci_port_resume(struct ata_port *ap)
365cfa1e 2260{
bb03c640
MW		 2261 ahci_rpm_get_port(ap);
2262
365cfa1e
AV		 2263 ahci_power_up(ap);
2264 ahci_start_port(ap);
2265
2266 if (sata_pmp_attached(ap))
2267 ahci_pmp_attach(ap);
2268 else
2269 ahci_pmp_detach(ap);
2270
2271 return 0;
2272}
02cdfcf0 2273EXPORT_SYMBOL_GPL(ahci_port_resume);
365cfa1e
AV		 2274
2275#ifdef CONFIG_PM
2276static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2277{
2278 const char *emsg = NULL;
2279 int rc;
2280
2281 rc = ahci_deinit_port(ap, &emsg);
2282 if (rc == 0)
2283 ahci_power_down(ap);
2284 else {
a9a79dfe 2285 ata_port_err(ap, "%s (%d)\n", emsg, rc);
7faa33da 2286 ata_port_freeze(ap);
365cfa1e
AV		 2287 }
2288
bb03c640 2289 ahci_rpm_put_port(ap);
365cfa1e
AV		 2290 return rc;
2291}
2292#endif
2293
2294static int ahci_port_start(struct ata_port *ap)
2295{
2296 struct ahci_host_priv *hpriv = ap->host->private_data;
2297 struct device *dev = ap->host->dev;
2298 struct ahci_port_priv *pp;
2299 void *mem;
2300 dma_addr_t mem_dma;
2301 size_t dma_sz, rx_fis_sz;
2302
2303 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2304 if (!pp)
2305 return -ENOMEM;
2306
b29900e6
AG		 2307 if (ap->host->n_ports > 1) {
2308 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2309 if (!pp->irq_desc) {
2310 devm_kfree(dev, pp);
2311 return -ENOMEM;
2312 }
2313 snprintf(pp->irq_desc, 8,
2314 "%s%d", dev_driver_string(dev), ap->port_no);
2315 }
2316
365cfa1e
AV		 2317 /* check FBS capability */
2318 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2319 void __iomem *port_mmio = ahci_port_base(ap);
2320 u32 cmd = readl(port_mmio + PORT_CMD);
2321 if (cmd & PORT_CMD_FBSCP)
2322 pp->fbs_supported = true;
5f173107 2323 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
a44fec1f
JP		 2324 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2325 ap->port_no);
5f173107
TH		 2326 pp->fbs_supported = true;
2327 } else
a44fec1f
JP		 2328 dev_warn(dev, "port %d is not capable of FBS\n",
2329 ap->port_no);
365cfa1e
AV		 2330 }
2331
2332 if (pp->fbs_supported) {
2333 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2334 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2335 } else {
2336 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2337 rx_fis_sz = AHCI_RX_FIS_SZ;
2338 }
2339
2340 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2341 if (!mem)
2342 return -ENOMEM;
2343 memset(mem, 0, dma_sz);
2344
2345 /*
2346 * First item in chunk of DMA memory: 32-slot command table,
2347 * 32 bytes each in size
2348 */
2349 pp->cmd_slot = mem;
2350 pp->cmd_slot_dma = mem_dma;
2351
2352 mem += AHCI_CMD_SLOT_SZ;
2353 mem_dma += AHCI_CMD_SLOT_SZ;
2354
2355 /*
2356 * Second item: Received-FIS area
2357 */
2358 pp->rx_fis = mem;
2359 pp->rx_fis_dma = mem_dma;
2360
2361 mem += rx_fis_sz;
2362 mem_dma += rx_fis_sz;
2363
2364 /*
2365 * Third item: data area for storing a single command
2366 * and its scatter-gather table
2367 */
2368 pp->cmd_tbl = mem;
2369 pp->cmd_tbl_dma = mem_dma;
2370
2371 /*
2372 * Save off initial list of interrupts to be enabled.
2373 * This could be changed later
2374 */
2375 pp->intr_mask = DEF_PORT_IRQ;
2376
7865f83f
TH		 2377 /*
2378 * Switch to per-port locking in case each port has its own MSI vector.
2379 */
21bfd1aa 2380 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
7865f83f
TH		 2381 spin_lock_init(&pp->lock);
2382 ap->lock = &pp->lock;
2383 }
5ca72c4f 2384
365cfa1e
AV		 2385 ap->private_data = pp;
2386
2387 /* engage engines, captain */
2388 return ahci_port_resume(ap);
2389}
2390
2391static void ahci_port_stop(struct ata_port *ap)
2392{
2393 const char *emsg = NULL;
2394 int rc;
2395
2396 /* de-initialize port */
2397 rc = ahci_deinit_port(ap, &emsg);
2398 if (rc)
a9a79dfe 2399 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
365cfa1e
AV		 2400}
2401
2402void ahci_print_info(struct ata_host *host, const char *scc_s)
2403{
2404 struct ahci_host_priv *hpriv = host->private_data;
365cfa1e
AV		 2405 u32 vers, cap, cap2, impl, speed;
2406 const char *speed_s;
2407
8ea909cb 2408 vers = hpriv->version;
365cfa1e
AV		 2409 cap = hpriv->cap;
2410 cap2 = hpriv->cap2;
2411 impl = hpriv->port_map;
2412
2413 speed = (cap >> 20) & 0xf;
2414 if (speed == 1)
2415 speed_s = "1.5";
2416 else if (speed == 2)
2417 speed_s = "3";
2418 else if (speed == 3)
2419 speed_s = "6";
2420 else
2421 speed_s = "?";
2422
2423 dev_info(host->dev,
2424 "AHCI %02x%02x.%02x%02x "
2425 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2426 ,
2427
2428 (vers >> 24) & 0xff,
2429 (vers >> 16) & 0xff,
2430 (vers >> 8) & 0xff,
2431 vers & 0xff,
2432
2433 ((cap >> 8) & 0x1f) + 1,
2434 (cap & 0x1f) + 1,
2435 speed_s,
2436 impl,
2437 scc_s);
2438
2439 dev_info(host->dev,
2440 "flags: "
2441 "%s%s%s%s%s%s%s"
2442 "%s%s%s%s%s%s%s"
65fe1f0f
SH		 2443 "%s%s%s%s%s%s%s"
2444 "%s%s\n"
365cfa1e
AV		 2445 ,
2446
2447 cap & HOST_CAP_64 ? "64bit " : "",
2448 cap & HOST_CAP_NCQ ? "ncq " : "",
2449 cap & HOST_CAP_SNTF ? "sntf " : "",
2450 cap & HOST_CAP_MPS ? "ilck " : "",
2451 cap & HOST_CAP_SSS ? "stag " : "",
2452 cap & HOST_CAP_ALPM ? "pm " : "",
2453 cap & HOST_CAP_LED ? "led " : "",
2454 cap & HOST_CAP_CLO ? "clo " : "",
2455 cap & HOST_CAP_ONLY ? "only " : "",
2456 cap & HOST_CAP_PMP ? "pmp " : "",
2457 cap & HOST_CAP_FBS ? "fbs " : "",
2458 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2459 cap & HOST_CAP_SSC ? "slum " : "",
2460 cap & HOST_CAP_PART ? "part " : "",
2461 cap & HOST_CAP_CCC ? "ccc " : "",
2462 cap & HOST_CAP_EMS ? "ems " : "",
2463 cap & HOST_CAP_SXS ? "sxs " : "",
65fe1f0f
SH		 2464 cap2 & HOST_CAP2_DESO ? "deso " : "",
2465 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2466 cap2 & HOST_CAP2_SDS ? "sds " : "",
365cfa1e
AV		 2467 cap2 & HOST_CAP2_APST ? "apst " : "",
2468 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2469 cap2 & HOST_CAP2_BOH ? "boh " : ""
2470 );
2471}
2472EXPORT_SYMBOL_GPL(ahci_print_info);
2473
2474void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2475 struct ata_port_info *pi)
2476{
2477 u8 messages;
2478 void __iomem *mmio = hpriv->mmio;
2479 u32 em_loc = readl(mmio + HOST_EM_LOC);
2480 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2481
2482 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2483 return;
2484
2485 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2486
008dbd61 2487 if (messages) {
365cfa1e
AV		 2488 /* store em_loc */
2489 hpriv->em_loc = ((em_loc >> 16) * 4);
c0623166 2490 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
008dbd61 2491 hpriv->em_msg_type = messages;
365cfa1e
AV		 2492 pi->flags |= ATA_FLAG_EM;
2493 if (!(em_ctl & EM_CTL_ALHD))
2494 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2495 }
2496}
2497EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2498
d684a90d 2499static int ahci_host_activate_multi_irqs(struct ata_host *host,
d1028e2f 2500 struct scsi_host_template *sht)
1c62854f 2501{
d684a90d 2502 struct ahci_host_priv *hpriv = host->private_data;
1c62854f
AG		 2503 int i, rc;
2504
2505 rc = ata_host_start(host);
2506 if (rc)
2507 return rc;
21bfd1aa
RR		 2508 /*
2509 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2510 * allocated. That is one MSI per port, starting from @irq.
2511 */
1c62854f
AG		 2512 for (i = 0; i < host->n_ports; i++) {
2513 struct ahci_port_priv *pp = host->ports[i]->private_data;
f893180b 2514 int irq = ahci_irq_vector(hpriv, i);
1c62854f
AG		 2515
2516 /* Do not receive interrupts sent by dummy ports */
2517 if (!pp) {
2518 disable_irq(irq + i);
2519 continue;
2520 }
2521
a6b7fb76
DW		 2522 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2523 0, pp->irq_desc, host->ports[i]);
2524
1c62854f 2525 if (rc)
0a142b26 2526 return rc;
d684a90d 2527 ata_port_desc(host->ports[i], "irq %d", irq);
0a142b26 2528 }
d684a90d 2529
0a142b26 2530 return ata_host_register(host, sht);
1c62854f 2531}
d1028e2f
AG		 2532
2533/**
2534 * ahci_host_activate - start AHCI host, request IRQs and register it
2535 * @host: target ATA host
d1028e2f
AG		 2536 * @sht: scsi_host_template to use when registering the host
2537 *
d1028e2f
AG		 2538 * LOCKING:
2539 * Inherited from calling layer (may sleep).
2540 *
2541 * RETURNS:
2542 * 0 on success, -errno otherwise.
2543 */
21bfd1aa 2544int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
d1028e2f
AG		 2545{
2546 struct ahci_host_priv *hpriv = host->private_data;
21bfd1aa 2547 int irq = hpriv->irq;
d1028e2f
AG		 2548 int rc;
2549
f070d671
ST		 2550 if (hpriv->flags & (AHCI_HFLAG_MULTI_MSI | AHCI_HFLAG_MULTI_MSIX)) {
2551 if (hpriv->irq_handler)
2552 dev_warn(host->dev, "both AHCI_HFLAG_MULTI_MSI flag set \
2553 and custom irq handler implemented\n");
2554
d684a90d 2555 rc = ahci_host_activate_multi_irqs(host, sht);
f070d671
ST		 2556 } else {
2557 rc = ata_host_activate(host, irq, hpriv->irq_handler,
7865f83f 2558 IRQF_SHARED, sht);
f070d671
ST		 2559 }
2560
2561
d1028e2f
AG		 2562 return rc;
2563}
1c62854f
AG		 2564EXPORT_SYMBOL_GPL(ahci_host_activate);
2565
365cfa1e
AV		 2566MODULE_AUTHOR("Jeff Garzik");
2567MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2568MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)