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365cfa1e AV |
1 | /* |
2 | * libahci.c - Common AHCI SATA low-level routines | |
3 | * | |
8c3d3d4b | 4 | * Maintained by: Tejun Heo <tj@kernel.org> |
365cfa1e AV |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004-2005 Red Hat, Inc. | |
9 | * | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * AHCI hardware documentation: | |
30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf | |
31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf | |
32 | * | |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
fbaf666b | 36 | #include <linux/gfp.h> |
365cfa1e | 37 | #include <linux/module.h> |
365cfa1e AV |
38 | #include <linux/blkdev.h> |
39 | #include <linux/delay.h> | |
40 | #include <linux/interrupt.h> | |
41 | #include <linux/dma-mapping.h> | |
42 | #include <linux/device.h> | |
43 | #include <scsi/scsi_host.h> | |
44 | #include <scsi/scsi_cmnd.h> | |
45 | #include <linux/libata.h> | |
d684a90d | 46 | #include <linux/pci.h> |
365cfa1e | 47 | #include "ahci.h" |
65fe1f0f | 48 | #include "libata.h" |
365cfa1e AV |
49 | |
50 | static int ahci_skip_host_reset; | |
51 | int ahci_ignore_sss; | |
52 | EXPORT_SYMBOL_GPL(ahci_ignore_sss); | |
53 | ||
54 | module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); | |
55 | MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); | |
56 | ||
57 | module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); | |
58 | MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); | |
59 | ||
6b7ae954 TH |
60 | static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, |
61 | unsigned hints); | |
365cfa1e AV |
62 | static ssize_t ahci_led_show(struct ata_port *ap, char *buf); |
63 | static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, | |
64 | size_t size); | |
65 | static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, | |
66 | ssize_t size); | |
67 | ||
68 | ||
69 | ||
70 | static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); | |
71 | static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); | |
365cfa1e AV |
72 | static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); |
73 | static int ahci_port_start(struct ata_port *ap); | |
74 | static void ahci_port_stop(struct ata_port *ap); | |
75 | static void ahci_qc_prep(struct ata_queued_cmd *qc); | |
76 | static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc); | |
77 | static void ahci_freeze(struct ata_port *ap); | |
78 | static void ahci_thaw(struct ata_port *ap); | |
65fe1f0f | 79 | static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep); |
365cfa1e AV |
80 | static void ahci_enable_fbs(struct ata_port *ap); |
81 | static void ahci_disable_fbs(struct ata_port *ap); | |
82 | static void ahci_pmp_attach(struct ata_port *ap); | |
83 | static void ahci_pmp_detach(struct ata_port *ap); | |
84 | static int ahci_softreset(struct ata_link *link, unsigned int *class, | |
85 | unsigned long deadline); | |
345347c5 YHC |
86 | static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, |
87 | unsigned long deadline); | |
365cfa1e AV |
88 | static int ahci_hardreset(struct ata_link *link, unsigned int *class, |
89 | unsigned long deadline); | |
90 | static void ahci_postreset(struct ata_link *link, unsigned int *class); | |
365cfa1e | 91 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); |
365cfa1e | 92 | static void ahci_dev_config(struct ata_device *dev); |
365cfa1e AV |
93 | #ifdef CONFIG_PM |
94 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); | |
95 | #endif | |
96 | static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); | |
97 | static ssize_t ahci_activity_store(struct ata_device *dev, | |
98 | enum sw_activity val); | |
99 | static void ahci_init_sw_activity(struct ata_link *link); | |
100 | ||
101 | static ssize_t ahci_show_host_caps(struct device *dev, | |
102 | struct device_attribute *attr, char *buf); | |
103 | static ssize_t ahci_show_host_cap2(struct device *dev, | |
104 | struct device_attribute *attr, char *buf); | |
105 | static ssize_t ahci_show_host_version(struct device *dev, | |
106 | struct device_attribute *attr, char *buf); | |
107 | static ssize_t ahci_show_port_cmd(struct device *dev, | |
108 | struct device_attribute *attr, char *buf); | |
c0623166 HZ |
109 | static ssize_t ahci_read_em_buffer(struct device *dev, |
110 | struct device_attribute *attr, char *buf); | |
111 | static ssize_t ahci_store_em_buffer(struct device *dev, | |
112 | struct device_attribute *attr, | |
113 | const char *buf, size_t size); | |
6e5fe5b1 HR |
114 | static ssize_t ahci_show_em_supported(struct device *dev, |
115 | struct device_attribute *attr, char *buf); | |
f070d671 | 116 | static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance); |
365cfa1e AV |
117 | |
118 | static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL); | |
119 | static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL); | |
120 | static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL); | |
121 | static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL); | |
c0623166 HZ |
122 | static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO, |
123 | ahci_read_em_buffer, ahci_store_em_buffer); | |
6e5fe5b1 | 124 | static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL); |
365cfa1e | 125 | |
fad16e7a | 126 | struct device_attribute *ahci_shost_attrs[] = { |
365cfa1e AV |
127 | &dev_attr_link_power_management_policy, |
128 | &dev_attr_em_message_type, | |
129 | &dev_attr_em_message, | |
130 | &dev_attr_ahci_host_caps, | |
131 | &dev_attr_ahci_host_cap2, | |
132 | &dev_attr_ahci_host_version, | |
133 | &dev_attr_ahci_port_cmd, | |
c0623166 | 134 | &dev_attr_em_buffer, |
6e5fe5b1 | 135 | &dev_attr_em_message_supported, |
365cfa1e AV |
136 | NULL |
137 | }; | |
fad16e7a | 138 | EXPORT_SYMBOL_GPL(ahci_shost_attrs); |
365cfa1e | 139 | |
fad16e7a | 140 | struct device_attribute *ahci_sdev_attrs[] = { |
365cfa1e AV |
141 | &dev_attr_sw_activity, |
142 | &dev_attr_unload_heads, | |
84f95243 | 143 | &dev_attr_ncq_prio_enable, |
365cfa1e AV |
144 | NULL |
145 | }; | |
fad16e7a | 146 | EXPORT_SYMBOL_GPL(ahci_sdev_attrs); |
365cfa1e AV |
147 | |
148 | struct ata_port_operations ahci_ops = { | |
149 | .inherits = &sata_pmp_port_ops, | |
150 | ||
151 | .qc_defer = ahci_pmp_qc_defer, | |
152 | .qc_prep = ahci_qc_prep, | |
153 | .qc_issue = ahci_qc_issue, | |
154 | .qc_fill_rtf = ahci_qc_fill_rtf, | |
155 | ||
156 | .freeze = ahci_freeze, | |
157 | .thaw = ahci_thaw, | |
158 | .softreset = ahci_softreset, | |
159 | .hardreset = ahci_hardreset, | |
160 | .postreset = ahci_postreset, | |
161 | .pmp_softreset = ahci_softreset, | |
162 | .error_handler = ahci_error_handler, | |
163 | .post_internal_cmd = ahci_post_internal_cmd, | |
164 | .dev_config = ahci_dev_config, | |
165 | ||
166 | .scr_read = ahci_scr_read, | |
167 | .scr_write = ahci_scr_write, | |
168 | .pmp_attach = ahci_pmp_attach, | |
169 | .pmp_detach = ahci_pmp_detach, | |
170 | ||
6b7ae954 | 171 | .set_lpm = ahci_set_lpm, |
365cfa1e AV |
172 | .em_show = ahci_led_show, |
173 | .em_store = ahci_led_store, | |
174 | .sw_activity_show = ahci_activity_show, | |
175 | .sw_activity_store = ahci_activity_store, | |
439d7a35 | 176 | .transmit_led_message = ahci_transmit_led_message, |
365cfa1e AV |
177 | #ifdef CONFIG_PM |
178 | .port_suspend = ahci_port_suspend, | |
179 | .port_resume = ahci_port_resume, | |
180 | #endif | |
181 | .port_start = ahci_port_start, | |
182 | .port_stop = ahci_port_stop, | |
183 | }; | |
184 | EXPORT_SYMBOL_GPL(ahci_ops); | |
185 | ||
345347c5 YHC |
186 | struct ata_port_operations ahci_pmp_retry_srst_ops = { |
187 | .inherits = &ahci_ops, | |
188 | .softreset = ahci_pmp_retry_softreset, | |
189 | }; | |
190 | EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops); | |
191 | ||
ed08d40c | 192 | static bool ahci_em_messages __read_mostly = true; |
365cfa1e | 193 | EXPORT_SYMBOL_GPL(ahci_em_messages); |
ed08d40c | 194 | module_param(ahci_em_messages, bool, 0444); |
365cfa1e AV |
195 | /* add other LED protocol types when they become supported */ |
196 | MODULE_PARM_DESC(ahci_em_messages, | |
008dbd61 | 197 | "AHCI Enclosure Management Message control (0 = off, 1 = on)"); |
365cfa1e | 198 | |
ed08d40c CL |
199 | /* device sleep idle timeout in ms */ |
200 | static int devslp_idle_timeout __read_mostly = 1000; | |
65fe1f0f SH |
201 | module_param(devslp_idle_timeout, int, 0644); |
202 | MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout"); | |
203 | ||
365cfa1e AV |
204 | static void ahci_enable_ahci(void __iomem *mmio) |
205 | { | |
206 | int i; | |
207 | u32 tmp; | |
208 | ||
209 | /* turn on AHCI_EN */ | |
210 | tmp = readl(mmio + HOST_CTL); | |
211 | if (tmp & HOST_AHCI_EN) | |
212 | return; | |
213 | ||
214 | /* Some controllers need AHCI_EN to be written multiple times. | |
215 | * Try a few times before giving up. | |
216 | */ | |
217 | for (i = 0; i < 5; i++) { | |
218 | tmp |= HOST_AHCI_EN; | |
219 | writel(tmp, mmio + HOST_CTL); | |
220 | tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ | |
221 | if (tmp & HOST_AHCI_EN) | |
222 | return; | |
223 | msleep(10); | |
224 | } | |
225 | ||
226 | WARN_ON(1); | |
227 | } | |
228 | ||
bb03c640 MW |
229 | /** |
230 | * ahci_rpm_get_port - Make sure the port is powered on | |
231 | * @ap: Port to power on | |
232 | * | |
233 | * Whenever there is need to access the AHCI host registers outside of | |
234 | * normal execution paths, call this function to make sure the host is | |
235 | * actually powered on. | |
236 | */ | |
237 | static int ahci_rpm_get_port(struct ata_port *ap) | |
238 | { | |
239 | return pm_runtime_get_sync(ap->dev); | |
240 | } | |
241 | ||
242 | /** | |
243 | * ahci_rpm_put_port - Undoes ahci_rpm_get_port() | |
244 | * @ap: Port to power down | |
245 | * | |
246 | * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host | |
247 | * if it has no more active users. | |
248 | */ | |
249 | static void ahci_rpm_put_port(struct ata_port *ap) | |
250 | { | |
251 | pm_runtime_put(ap->dev); | |
252 | } | |
253 | ||
365cfa1e AV |
254 | static ssize_t ahci_show_host_caps(struct device *dev, |
255 | struct device_attribute *attr, char *buf) | |
256 | { | |
257 | struct Scsi_Host *shost = class_to_shost(dev); | |
258 | struct ata_port *ap = ata_shost_to_port(shost); | |
259 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
260 | ||
261 | return sprintf(buf, "%x\n", hpriv->cap); | |
262 | } | |
263 | ||
264 | static ssize_t ahci_show_host_cap2(struct device *dev, | |
265 | struct device_attribute *attr, char *buf) | |
266 | { | |
267 | struct Scsi_Host *shost = class_to_shost(dev); | |
268 | struct ata_port *ap = ata_shost_to_port(shost); | |
269 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
270 | ||
271 | return sprintf(buf, "%x\n", hpriv->cap2); | |
272 | } | |
273 | ||
274 | static ssize_t ahci_show_host_version(struct device *dev, | |
275 | struct device_attribute *attr, char *buf) | |
276 | { | |
277 | struct Scsi_Host *shost = class_to_shost(dev); | |
278 | struct ata_port *ap = ata_shost_to_port(shost); | |
279 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
365cfa1e | 280 | |
8ea909cb | 281 | return sprintf(buf, "%x\n", hpriv->version); |
365cfa1e AV |
282 | } |
283 | ||
284 | static ssize_t ahci_show_port_cmd(struct device *dev, | |
285 | struct device_attribute *attr, char *buf) | |
286 | { | |
287 | struct Scsi_Host *shost = class_to_shost(dev); | |
288 | struct ata_port *ap = ata_shost_to_port(shost); | |
289 | void __iomem *port_mmio = ahci_port_base(ap); | |
bb03c640 | 290 | ssize_t ret; |
365cfa1e | 291 | |
bb03c640 MW |
292 | ahci_rpm_get_port(ap); |
293 | ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); | |
294 | ahci_rpm_put_port(ap); | |
295 | ||
296 | return ret; | |
365cfa1e AV |
297 | } |
298 | ||
c0623166 HZ |
299 | static ssize_t ahci_read_em_buffer(struct device *dev, |
300 | struct device_attribute *attr, char *buf) | |
301 | { | |
302 | struct Scsi_Host *shost = class_to_shost(dev); | |
303 | struct ata_port *ap = ata_shost_to_port(shost); | |
304 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
305 | void __iomem *mmio = hpriv->mmio; | |
306 | void __iomem *em_mmio = mmio + hpriv->em_loc; | |
307 | u32 em_ctl, msg; | |
308 | unsigned long flags; | |
309 | size_t count; | |
310 | int i; | |
311 | ||
bb03c640 | 312 | ahci_rpm_get_port(ap); |
c0623166 HZ |
313 | spin_lock_irqsave(ap->lock, flags); |
314 | ||
315 | em_ctl = readl(mmio + HOST_EM_CTL); | |
316 | if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT || | |
317 | !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) { | |
318 | spin_unlock_irqrestore(ap->lock, flags); | |
bb03c640 | 319 | ahci_rpm_put_port(ap); |
c0623166 HZ |
320 | return -EINVAL; |
321 | } | |
322 | ||
323 | if (!(em_ctl & EM_CTL_MR)) { | |
324 | spin_unlock_irqrestore(ap->lock, flags); | |
bb03c640 | 325 | ahci_rpm_put_port(ap); |
c0623166 HZ |
326 | return -EAGAIN; |
327 | } | |
328 | ||
329 | if (!(em_ctl & EM_CTL_SMB)) | |
330 | em_mmio += hpriv->em_buf_sz; | |
331 | ||
332 | count = hpriv->em_buf_sz; | |
333 | ||
334 | /* the count should not be larger than PAGE_SIZE */ | |
335 | if (count > PAGE_SIZE) { | |
336 | if (printk_ratelimit()) | |
a9a79dfe JP |
337 | ata_port_warn(ap, |
338 | "EM read buffer size too large: " | |
339 | "buffer size %u, page size %lu\n", | |
340 | hpriv->em_buf_sz, PAGE_SIZE); | |
c0623166 HZ |
341 | count = PAGE_SIZE; |
342 | } | |
343 | ||
344 | for (i = 0; i < count; i += 4) { | |
345 | msg = readl(em_mmio + i); | |
346 | buf[i] = msg & 0xff; | |
347 | buf[i + 1] = (msg >> 8) & 0xff; | |
348 | buf[i + 2] = (msg >> 16) & 0xff; | |
349 | buf[i + 3] = (msg >> 24) & 0xff; | |
350 | } | |
351 | ||
352 | spin_unlock_irqrestore(ap->lock, flags); | |
bb03c640 | 353 | ahci_rpm_put_port(ap); |
c0623166 HZ |
354 | |
355 | return i; | |
356 | } | |
357 | ||
358 | static ssize_t ahci_store_em_buffer(struct device *dev, | |
359 | struct device_attribute *attr, | |
360 | const char *buf, size_t size) | |
361 | { | |
362 | struct Scsi_Host *shost = class_to_shost(dev); | |
363 | struct ata_port *ap = ata_shost_to_port(shost); | |
364 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
365 | void __iomem *mmio = hpriv->mmio; | |
366 | void __iomem *em_mmio = mmio + hpriv->em_loc; | |
f9ce889b | 367 | const unsigned char *msg_buf = buf; |
c0623166 HZ |
368 | u32 em_ctl, msg; |
369 | unsigned long flags; | |
370 | int i; | |
371 | ||
372 | /* check size validity */ | |
373 | if (!(ap->flags & ATA_FLAG_EM) || | |
374 | !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) || | |
375 | size % 4 || size > hpriv->em_buf_sz) | |
376 | return -EINVAL; | |
377 | ||
bb03c640 | 378 | ahci_rpm_get_port(ap); |
c0623166 HZ |
379 | spin_lock_irqsave(ap->lock, flags); |
380 | ||
381 | em_ctl = readl(mmio + HOST_EM_CTL); | |
382 | if (em_ctl & EM_CTL_TM) { | |
383 | spin_unlock_irqrestore(ap->lock, flags); | |
bb03c640 | 384 | ahci_rpm_put_port(ap); |
c0623166 HZ |
385 | return -EBUSY; |
386 | } | |
387 | ||
388 | for (i = 0; i < size; i += 4) { | |
f9ce889b HZ |
389 | msg = msg_buf[i] | msg_buf[i + 1] << 8 | |
390 | msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24; | |
c0623166 HZ |
391 | writel(msg, em_mmio + i); |
392 | } | |
393 | ||
394 | writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); | |
395 | ||
396 | spin_unlock_irqrestore(ap->lock, flags); | |
bb03c640 | 397 | ahci_rpm_put_port(ap); |
c0623166 HZ |
398 | |
399 | return size; | |
400 | } | |
401 | ||
6e5fe5b1 HR |
402 | static ssize_t ahci_show_em_supported(struct device *dev, |
403 | struct device_attribute *attr, char *buf) | |
404 | { | |
405 | struct Scsi_Host *shost = class_to_shost(dev); | |
406 | struct ata_port *ap = ata_shost_to_port(shost); | |
407 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
408 | void __iomem *mmio = hpriv->mmio; | |
409 | u32 em_ctl; | |
410 | ||
bb03c640 | 411 | ahci_rpm_get_port(ap); |
6e5fe5b1 | 412 | em_ctl = readl(mmio + HOST_EM_CTL); |
bb03c640 | 413 | ahci_rpm_put_port(ap); |
6e5fe5b1 HR |
414 | |
415 | return sprintf(buf, "%s%s%s%s\n", | |
416 | em_ctl & EM_CTL_LED ? "led " : "", | |
417 | em_ctl & EM_CTL_SAFTE ? "saf-te " : "", | |
418 | em_ctl & EM_CTL_SES ? "ses-2 " : "", | |
419 | em_ctl & EM_CTL_SGPIO ? "sgpio " : ""); | |
420 | } | |
421 | ||
365cfa1e AV |
422 | /** |
423 | * ahci_save_initial_config - Save and fixup initial config values | |
424 | * @dev: target AHCI device | |
425 | * @hpriv: host private area to store config values | |
365cfa1e AV |
426 | * |
427 | * Some registers containing configuration info might be setup by | |
428 | * BIOS and might be cleared on reset. This function saves the | |
429 | * initial values of those registers into @hpriv such that they | |
430 | * can be restored after controller reset. | |
431 | * | |
432 | * If inconsistent, config values are fixed up by this function. | |
433 | * | |
039ece38 HG |
434 | * If it is not set already this function sets hpriv->start_engine to |
435 | * ahci_start_engine. | |
436 | * | |
365cfa1e AV |
437 | * LOCKING: |
438 | * None. | |
439 | */ | |
725c7b57 | 440 | void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv) |
365cfa1e AV |
441 | { |
442 | void __iomem *mmio = hpriv->mmio; | |
443 | u32 cap, cap2, vers, port_map; | |
444 | int i; | |
445 | ||
446 | /* make sure AHCI mode is enabled before accessing CAP */ | |
447 | ahci_enable_ahci(mmio); | |
448 | ||
449 | /* Values prefixed with saved_ are written back to host after | |
450 | * reset. Values without are used for driver operation. | |
451 | */ | |
452 | hpriv->saved_cap = cap = readl(mmio + HOST_CAP); | |
453 | hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); | |
454 | ||
455 | /* CAP2 register is only defined for AHCI 1.2 and later */ | |
456 | vers = readl(mmio + HOST_VERSION); | |
457 | if ((vers >> 16) > 1 || | |
458 | ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200)) | |
459 | hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2); | |
460 | else | |
461 | hpriv->saved_cap2 = cap2 = 0; | |
462 | ||
463 | /* some chips have errata preventing 64bit use */ | |
464 | if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { | |
a44fec1f | 465 | dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n"); |
365cfa1e AV |
466 | cap &= ~HOST_CAP_64; |
467 | } | |
468 | ||
469 | if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { | |
a44fec1f | 470 | dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n"); |
365cfa1e AV |
471 | cap &= ~HOST_CAP_NCQ; |
472 | } | |
473 | ||
474 | if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { | |
a44fec1f | 475 | dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n"); |
365cfa1e AV |
476 | cap |= HOST_CAP_NCQ; |
477 | } | |
478 | ||
479 | if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { | |
a44fec1f | 480 | dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n"); |
365cfa1e AV |
481 | cap &= ~HOST_CAP_PMP; |
482 | } | |
483 | ||
484 | if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) { | |
a44fec1f JP |
485 | dev_info(dev, |
486 | "controller can't do SNTF, turning off CAP_SNTF\n"); | |
365cfa1e AV |
487 | cap &= ~HOST_CAP_SNTF; |
488 | } | |
489 | ||
0cf4a7d6 JP |
490 | if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) { |
491 | dev_info(dev, | |
492 | "controller can't do DEVSLP, turning off\n"); | |
493 | cap2 &= ~HOST_CAP2_SDS; | |
494 | cap2 &= ~HOST_CAP2_SADM; | |
495 | } | |
496 | ||
5f173107 | 497 | if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) { |
a44fec1f | 498 | dev_info(dev, "controller can do FBS, turning on CAP_FBS\n"); |
5f173107 TH |
499 | cap |= HOST_CAP_FBS; |
500 | } | |
501 | ||
888d91a0 KW |
502 | if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) { |
503 | dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n"); | |
504 | cap &= ~HOST_CAP_FBS; | |
505 | } | |
506 | ||
725c7b57 | 507 | if (hpriv->force_port_map && port_map != hpriv->force_port_map) { |
a44fec1f | 508 | dev_info(dev, "forcing port_map 0x%x -> 0x%x\n", |
725c7b57 AT |
509 | port_map, hpriv->force_port_map); |
510 | port_map = hpriv->force_port_map; | |
2fd0f46c | 511 | hpriv->saved_port_map = port_map; |
365cfa1e AV |
512 | } |
513 | ||
725c7b57 | 514 | if (hpriv->mask_port_map) { |
a44fec1f JP |
515 | dev_warn(dev, "masking port_map 0x%x -> 0x%x\n", |
516 | port_map, | |
725c7b57 AT |
517 | port_map & hpriv->mask_port_map); |
518 | port_map &= hpriv->mask_port_map; | |
365cfa1e AV |
519 | } |
520 | ||
521 | /* cross check port_map and cap.n_ports */ | |
522 | if (port_map) { | |
523 | int map_ports = 0; | |
524 | ||
525 | for (i = 0; i < AHCI_MAX_PORTS; i++) | |
526 | if (port_map & (1 << i)) | |
527 | map_ports++; | |
528 | ||
529 | /* If PI has more ports than n_ports, whine, clear | |
530 | * port_map and let it be generated from n_ports. | |
531 | */ | |
532 | if (map_ports > ahci_nr_ports(cap)) { | |
a44fec1f JP |
533 | dev_warn(dev, |
534 | "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n", | |
535 | port_map, ahci_nr_ports(cap)); | |
365cfa1e AV |
536 | port_map = 0; |
537 | } | |
538 | } | |
539 | ||
566d1827 TH |
540 | /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */ |
541 | if (!port_map && vers < 0x10300) { | |
365cfa1e | 542 | port_map = (1 << ahci_nr_ports(cap)) - 1; |
a44fec1f | 543 | dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map); |
365cfa1e AV |
544 | |
545 | /* write the fixed up value to the PI register */ | |
546 | hpriv->saved_port_map = port_map; | |
547 | } | |
548 | ||
549 | /* record values to use during operation */ | |
550 | hpriv->cap = cap; | |
551 | hpriv->cap2 = cap2; | |
8ea909cb | 552 | hpriv->version = readl(mmio + HOST_VERSION); |
365cfa1e | 553 | hpriv->port_map = port_map; |
039ece38 HG |
554 | |
555 | if (!hpriv->start_engine) | |
556 | hpriv->start_engine = ahci_start_engine; | |
f070d671 ST |
557 | |
558 | if (!hpriv->irq_handler) | |
d867b95f | 559 | hpriv->irq_handler = ahci_single_level_irq_intr; |
365cfa1e AV |
560 | } |
561 | EXPORT_SYMBOL_GPL(ahci_save_initial_config); | |
562 | ||
563 | /** | |
564 | * ahci_restore_initial_config - Restore initial config | |
565 | * @host: target ATA host | |
566 | * | |
567 | * Restore initial config stored by ahci_save_initial_config(). | |
568 | * | |
569 | * LOCKING: | |
570 | * None. | |
571 | */ | |
572 | static void ahci_restore_initial_config(struct ata_host *host) | |
573 | { | |
574 | struct ahci_host_priv *hpriv = host->private_data; | |
575 | void __iomem *mmio = hpriv->mmio; | |
576 | ||
577 | writel(hpriv->saved_cap, mmio + HOST_CAP); | |
578 | if (hpriv->saved_cap2) | |
579 | writel(hpriv->saved_cap2, mmio + HOST_CAP2); | |
580 | writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); | |
581 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ | |
582 | } | |
583 | ||
584 | static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) | |
585 | { | |
586 | static const int offset[] = { | |
587 | [SCR_STATUS] = PORT_SCR_STAT, | |
588 | [SCR_CONTROL] = PORT_SCR_CTL, | |
589 | [SCR_ERROR] = PORT_SCR_ERR, | |
590 | [SCR_ACTIVE] = PORT_SCR_ACT, | |
591 | [SCR_NOTIFICATION] = PORT_SCR_NTF, | |
592 | }; | |
593 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
594 | ||
595 | if (sc_reg < ARRAY_SIZE(offset) && | |
596 | (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) | |
597 | return offset[sc_reg]; | |
598 | return 0; | |
599 | } | |
600 | ||
601 | static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) | |
602 | { | |
603 | void __iomem *port_mmio = ahci_port_base(link->ap); | |
604 | int offset = ahci_scr_offset(link->ap, sc_reg); | |
605 | ||
606 | if (offset) { | |
607 | *val = readl(port_mmio + offset); | |
608 | return 0; | |
609 | } | |
610 | return -EINVAL; | |
611 | } | |
612 | ||
613 | static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) | |
614 | { | |
615 | void __iomem *port_mmio = ahci_port_base(link->ap); | |
616 | int offset = ahci_scr_offset(link->ap, sc_reg); | |
617 | ||
618 | if (offset) { | |
619 | writel(val, port_mmio + offset); | |
620 | return 0; | |
621 | } | |
622 | return -EINVAL; | |
623 | } | |
624 | ||
625 | void ahci_start_engine(struct ata_port *ap) | |
626 | { | |
627 | void __iomem *port_mmio = ahci_port_base(ap); | |
628 | u32 tmp; | |
629 | ||
630 | /* start DMA */ | |
631 | tmp = readl(port_mmio + PORT_CMD); | |
632 | tmp |= PORT_CMD_START; | |
633 | writel(tmp, port_mmio + PORT_CMD); | |
634 | readl(port_mmio + PORT_CMD); /* flush */ | |
635 | } | |
636 | EXPORT_SYMBOL_GPL(ahci_start_engine); | |
637 | ||
638 | int ahci_stop_engine(struct ata_port *ap) | |
639 | { | |
640 | void __iomem *port_mmio = ahci_port_base(ap); | |
fb329633 | 641 | struct ahci_host_priv *hpriv = ap->host->private_data; |
365cfa1e AV |
642 | u32 tmp; |
643 | ||
fb329633 DP |
644 | /* |
645 | * On some controllers, stopping a port's DMA engine while the port | |
646 | * is in ALPM state (partial or slumber) results in failures on | |
647 | * subsequent DMA engine starts. For those controllers, put the | |
648 | * port back in active state before stopping its DMA engine. | |
649 | */ | |
650 | if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) && | |
651 | (ap->link.lpm_policy > ATA_LPM_MAX_POWER) && | |
652 | ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) { | |
653 | dev_err(ap->host->dev, "Failed to wake up port before engine stop\n"); | |
654 | return -EIO; | |
655 | } | |
656 | ||
365cfa1e AV |
657 | tmp = readl(port_mmio + PORT_CMD); |
658 | ||
659 | /* check if the HBA is idle */ | |
660 | if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) | |
661 | return 0; | |
662 | ||
663 | /* setting HBA to idle */ | |
664 | tmp &= ~PORT_CMD_START; | |
665 | writel(tmp, port_mmio + PORT_CMD); | |
666 | ||
667 | /* wait for engine to stop. This could be as long as 500 msec */ | |
97750ceb | 668 | tmp = ata_wait_register(ap, port_mmio + PORT_CMD, |
365cfa1e AV |
669 | PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); |
670 | if (tmp & PORT_CMD_LIST_ON) | |
671 | return -EIO; | |
672 | ||
673 | return 0; | |
674 | } | |
675 | EXPORT_SYMBOL_GPL(ahci_stop_engine); | |
676 | ||
39e0ee99 | 677 | void ahci_start_fis_rx(struct ata_port *ap) |
365cfa1e AV |
678 | { |
679 | void __iomem *port_mmio = ahci_port_base(ap); | |
680 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
681 | struct ahci_port_priv *pp = ap->private_data; | |
682 | u32 tmp; | |
683 | ||
684 | /* set FIS registers */ | |
685 | if (hpriv->cap & HOST_CAP_64) | |
686 | writel((pp->cmd_slot_dma >> 16) >> 16, | |
687 | port_mmio + PORT_LST_ADDR_HI); | |
688 | writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); | |
689 | ||
690 | if (hpriv->cap & HOST_CAP_64) | |
691 | writel((pp->rx_fis_dma >> 16) >> 16, | |
692 | port_mmio + PORT_FIS_ADDR_HI); | |
693 | writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); | |
694 | ||
695 | /* enable FIS reception */ | |
696 | tmp = readl(port_mmio + PORT_CMD); | |
697 | tmp |= PORT_CMD_FIS_RX; | |
698 | writel(tmp, port_mmio + PORT_CMD); | |
699 | ||
700 | /* flush */ | |
701 | readl(port_mmio + PORT_CMD); | |
702 | } | |
39e0ee99 | 703 | EXPORT_SYMBOL_GPL(ahci_start_fis_rx); |
365cfa1e AV |
704 | |
705 | static int ahci_stop_fis_rx(struct ata_port *ap) | |
706 | { | |
707 | void __iomem *port_mmio = ahci_port_base(ap); | |
708 | u32 tmp; | |
709 | ||
710 | /* disable FIS reception */ | |
711 | tmp = readl(port_mmio + PORT_CMD); | |
712 | tmp &= ~PORT_CMD_FIS_RX; | |
713 | writel(tmp, port_mmio + PORT_CMD); | |
714 | ||
715 | /* wait for completion, spec says 500ms, give it 1000 */ | |
97750ceb | 716 | tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON, |
365cfa1e AV |
717 | PORT_CMD_FIS_ON, 10, 1000); |
718 | if (tmp & PORT_CMD_FIS_ON) | |
719 | return -EBUSY; | |
720 | ||
721 | return 0; | |
722 | } | |
723 | ||
724 | static void ahci_power_up(struct ata_port *ap) | |
725 | { | |
726 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
727 | void __iomem *port_mmio = ahci_port_base(ap); | |
728 | u32 cmd; | |
729 | ||
730 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
731 | ||
732 | /* spin up device */ | |
733 | if (hpriv->cap & HOST_CAP_SSS) { | |
734 | cmd |= PORT_CMD_SPIN_UP; | |
735 | writel(cmd, port_mmio + PORT_CMD); | |
736 | } | |
737 | ||
738 | /* wake up link */ | |
739 | writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); | |
740 | } | |
741 | ||
6b7ae954 TH |
742 | static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, |
743 | unsigned int hints) | |
365cfa1e | 744 | { |
6b7ae954 | 745 | struct ata_port *ap = link->ap; |
365cfa1e | 746 | struct ahci_host_priv *hpriv = ap->host->private_data; |
365cfa1e | 747 | struct ahci_port_priv *pp = ap->private_data; |
365cfa1e | 748 | void __iomem *port_mmio = ahci_port_base(ap); |
365cfa1e | 749 | |
6b7ae954 | 750 | if (policy != ATA_LPM_MAX_POWER) { |
fb329633 DP |
751 | /* wakeup flag only applies to the max power policy */ |
752 | hints &= ~ATA_LPM_WAKE_ONLY; | |
753 | ||
365cfa1e | 754 | /* |
6b7ae954 TH |
755 | * Disable interrupts on Phy Ready. This keeps us from |
756 | * getting woken up due to spurious phy ready | |
757 | * interrupts. | |
365cfa1e | 758 | */ |
6b7ae954 TH |
759 | pp->intr_mask &= ~PORT_IRQ_PHYRDY; |
760 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
761 | ||
762 | sata_link_scr_lpm(link, policy, false); | |
365cfa1e AV |
763 | } |
764 | ||
6b7ae954 TH |
765 | if (hpriv->cap & HOST_CAP_ALPM) { |
766 | u32 cmd = readl(port_mmio + PORT_CMD); | |
365cfa1e | 767 | |
6b7ae954 | 768 | if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) { |
fb329633 DP |
769 | if (!(hints & ATA_LPM_WAKE_ONLY)) |
770 | cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE); | |
6b7ae954 | 771 | cmd |= PORT_CMD_ICC_ACTIVE; |
365cfa1e | 772 | |
6b7ae954 TH |
773 | writel(cmd, port_mmio + PORT_CMD); |
774 | readl(port_mmio + PORT_CMD); | |
365cfa1e | 775 | |
6b7ae954 | 776 | /* wait 10ms to be sure we've come out of LPM state */ |
97750ceb | 777 | ata_msleep(ap, 10); |
fb329633 DP |
778 | |
779 | if (hints & ATA_LPM_WAKE_ONLY) | |
780 | return 0; | |
6b7ae954 TH |
781 | } else { |
782 | cmd |= PORT_CMD_ALPE; | |
783 | if (policy == ATA_LPM_MIN_POWER) | |
784 | cmd |= PORT_CMD_ASP; | |
365cfa1e | 785 | |
6b7ae954 TH |
786 | /* write out new cmd value */ |
787 | writel(cmd, port_mmio + PORT_CMD); | |
788 | } | |
789 | } | |
365cfa1e | 790 | |
65fe1f0f SH |
791 | /* set aggressive device sleep */ |
792 | if ((hpriv->cap2 & HOST_CAP2_SDS) && | |
793 | (hpriv->cap2 & HOST_CAP2_SADM) && | |
794 | (link->device->flags & ATA_DFLAG_DEVSLP)) { | |
795 | if (policy == ATA_LPM_MIN_POWER) | |
796 | ahci_set_aggressive_devslp(ap, true); | |
797 | else | |
798 | ahci_set_aggressive_devslp(ap, false); | |
799 | } | |
800 | ||
6b7ae954 TH |
801 | if (policy == ATA_LPM_MAX_POWER) { |
802 | sata_link_scr_lpm(link, policy, false); | |
803 | ||
804 | /* turn PHYRDY IRQ back on */ | |
805 | pp->intr_mask |= PORT_IRQ_PHYRDY; | |
806 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
807 | } | |
365cfa1e | 808 | |
365cfa1e AV |
809 | return 0; |
810 | } | |
811 | ||
812 | #ifdef CONFIG_PM | |
813 | static void ahci_power_down(struct ata_port *ap) | |
814 | { | |
815 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
816 | void __iomem *port_mmio = ahci_port_base(ap); | |
817 | u32 cmd, scontrol; | |
818 | ||
819 | if (!(hpriv->cap & HOST_CAP_SSS)) | |
820 | return; | |
821 | ||
822 | /* put device into listen mode, first set PxSCTL.DET to 0 */ | |
823 | scontrol = readl(port_mmio + PORT_SCR_CTL); | |
824 | scontrol &= ~0xf; | |
825 | writel(scontrol, port_mmio + PORT_SCR_CTL); | |
826 | ||
827 | /* then set PxCMD.SUD to 0 */ | |
828 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
829 | cmd &= ~PORT_CMD_SPIN_UP; | |
830 | writel(cmd, port_mmio + PORT_CMD); | |
831 | } | |
832 | #endif | |
833 | ||
834 | static void ahci_start_port(struct ata_port *ap) | |
835 | { | |
66583c9f | 836 | struct ahci_host_priv *hpriv = ap->host->private_data; |
365cfa1e AV |
837 | struct ahci_port_priv *pp = ap->private_data; |
838 | struct ata_link *link; | |
839 | struct ahci_em_priv *emp; | |
840 | ssize_t rc; | |
841 | int i; | |
842 | ||
843 | /* enable FIS reception */ | |
844 | ahci_start_fis_rx(ap); | |
845 | ||
66583c9f BN |
846 | /* enable DMA */ |
847 | if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE)) | |
039ece38 | 848 | hpriv->start_engine(ap); |
66583c9f | 849 | |
365cfa1e AV |
850 | /* turn on LEDs */ |
851 | if (ap->flags & ATA_FLAG_EM) { | |
852 | ata_for_each_link(link, ap, EDGE) { | |
853 | emp = &pp->em_priv[link->pmp]; | |
854 | ||
855 | /* EM Transmit bit maybe busy during init */ | |
856 | for (i = 0; i < EM_MAX_RETRY; i++) { | |
439d7a35 | 857 | rc = ap->ops->transmit_led_message(ap, |
365cfa1e AV |
858 | emp->led_state, |
859 | 4); | |
fa070ee6 LD |
860 | /* |
861 | * If busy, give a breather but do not | |
862 | * release EH ownership by using msleep() | |
863 | * instead of ata_msleep(). EM Transmit | |
864 | * bit is busy for the whole host and | |
865 | * releasing ownership will cause other | |
866 | * ports to fail the same way. | |
867 | */ | |
365cfa1e | 868 | if (rc == -EBUSY) |
fa070ee6 | 869 | msleep(1); |
365cfa1e AV |
870 | else |
871 | break; | |
872 | } | |
873 | } | |
874 | } | |
875 | ||
876 | if (ap->flags & ATA_FLAG_SW_ACTIVITY) | |
877 | ata_for_each_link(link, ap, EDGE) | |
878 | ahci_init_sw_activity(link); | |
879 | ||
880 | } | |
881 | ||
882 | static int ahci_deinit_port(struct ata_port *ap, const char **emsg) | |
883 | { | |
884 | int rc; | |
885 | ||
886 | /* disable DMA */ | |
887 | rc = ahci_stop_engine(ap); | |
888 | if (rc) { | |
889 | *emsg = "failed to stop engine"; | |
890 | return rc; | |
891 | } | |
892 | ||
893 | /* disable FIS reception */ | |
894 | rc = ahci_stop_fis_rx(ap); | |
895 | if (rc) { | |
896 | *emsg = "failed stop FIS RX"; | |
897 | return rc; | |
898 | } | |
899 | ||
900 | return 0; | |
901 | } | |
902 | ||
903 | int ahci_reset_controller(struct ata_host *host) | |
904 | { | |
905 | struct ahci_host_priv *hpriv = host->private_data; | |
906 | void __iomem *mmio = hpriv->mmio; | |
907 | u32 tmp; | |
908 | ||
909 | /* we must be in AHCI mode, before using anything | |
910 | * AHCI-specific, such as HOST_RESET. | |
911 | */ | |
912 | ahci_enable_ahci(mmio); | |
913 | ||
914 | /* global controller reset */ | |
915 | if (!ahci_skip_host_reset) { | |
916 | tmp = readl(mmio + HOST_CTL); | |
917 | if ((tmp & HOST_RESET) == 0) { | |
918 | writel(tmp | HOST_RESET, mmio + HOST_CTL); | |
919 | readl(mmio + HOST_CTL); /* flush */ | |
920 | } | |
921 | ||
922 | /* | |
923 | * to perform host reset, OS should set HOST_RESET | |
924 | * and poll until this bit is read to be "0". | |
925 | * reset must complete within 1 second, or | |
926 | * the hardware should be considered fried. | |
927 | */ | |
97750ceb | 928 | tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET, |
365cfa1e AV |
929 | HOST_RESET, 10, 1000); |
930 | ||
931 | if (tmp & HOST_RESET) { | |
a44fec1f JP |
932 | dev_err(host->dev, "controller reset failed (0x%x)\n", |
933 | tmp); | |
365cfa1e AV |
934 | return -EIO; |
935 | } | |
936 | ||
937 | /* turn on AHCI mode */ | |
938 | ahci_enable_ahci(mmio); | |
939 | ||
940 | /* Some registers might be cleared on reset. Restore | |
941 | * initial values. | |
942 | */ | |
943 | ahci_restore_initial_config(host); | |
944 | } else | |
a44fec1f | 945 | dev_info(host->dev, "skipping global host reset\n"); |
365cfa1e AV |
946 | |
947 | return 0; | |
948 | } | |
949 | EXPORT_SYMBOL_GPL(ahci_reset_controller); | |
950 | ||
951 | static void ahci_sw_activity(struct ata_link *link) | |
952 | { | |
953 | struct ata_port *ap = link->ap; | |
954 | struct ahci_port_priv *pp = ap->private_data; | |
955 | struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; | |
956 | ||
957 | if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) | |
958 | return; | |
959 | ||
960 | emp->activity++; | |
961 | if (!timer_pending(&emp->timer)) | |
962 | mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); | |
963 | } | |
964 | ||
965 | static void ahci_sw_activity_blink(unsigned long arg) | |
966 | { | |
967 | struct ata_link *link = (struct ata_link *)arg; | |
968 | struct ata_port *ap = link->ap; | |
969 | struct ahci_port_priv *pp = ap->private_data; | |
970 | struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; | |
971 | unsigned long led_message = emp->led_state; | |
972 | u32 activity_led_state; | |
973 | unsigned long flags; | |
974 | ||
975 | led_message &= EM_MSG_LED_VALUE; | |
976 | led_message |= ap->port_no | (link->pmp << 8); | |
977 | ||
978 | /* check to see if we've had activity. If so, | |
979 | * toggle state of LED and reset timer. If not, | |
980 | * turn LED to desired idle state. | |
981 | */ | |
982 | spin_lock_irqsave(ap->lock, flags); | |
983 | if (emp->saved_activity != emp->activity) { | |
984 | emp->saved_activity = emp->activity; | |
985 | /* get the current LED state */ | |
986 | activity_led_state = led_message & EM_MSG_LED_VALUE_ON; | |
987 | ||
988 | if (activity_led_state) | |
989 | activity_led_state = 0; | |
990 | else | |
991 | activity_led_state = 1; | |
992 | ||
993 | /* clear old state */ | |
994 | led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; | |
995 | ||
996 | /* toggle state */ | |
997 | led_message |= (activity_led_state << 16); | |
998 | mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); | |
999 | } else { | |
1000 | /* switch to idle */ | |
1001 | led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; | |
1002 | if (emp->blink_policy == BLINK_OFF) | |
1003 | led_message |= (1 << 16); | |
1004 | } | |
1005 | spin_unlock_irqrestore(ap->lock, flags); | |
439d7a35 | 1006 | ap->ops->transmit_led_message(ap, led_message, 4); |
365cfa1e AV |
1007 | } |
1008 | ||
1009 | static void ahci_init_sw_activity(struct ata_link *link) | |
1010 | { | |
1011 | struct ata_port *ap = link->ap; | |
1012 | struct ahci_port_priv *pp = ap->private_data; | |
1013 | struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; | |
1014 | ||
1015 | /* init activity stats, setup timer */ | |
1016 | emp->saved_activity = emp->activity = 0; | |
1017 | setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link); | |
1018 | ||
1019 | /* check our blink policy and set flag for link if it's enabled */ | |
1020 | if (emp->blink_policy) | |
1021 | link->flags |= ATA_LFLAG_SW_ACTIVITY; | |
1022 | } | |
1023 | ||
1024 | int ahci_reset_em(struct ata_host *host) | |
1025 | { | |
1026 | struct ahci_host_priv *hpriv = host->private_data; | |
1027 | void __iomem *mmio = hpriv->mmio; | |
1028 | u32 em_ctl; | |
1029 | ||
1030 | em_ctl = readl(mmio + HOST_EM_CTL); | |
1031 | if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) | |
1032 | return -EINVAL; | |
1033 | ||
1034 | writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); | |
1035 | return 0; | |
1036 | } | |
1037 | EXPORT_SYMBOL_GPL(ahci_reset_em); | |
1038 | ||
1039 | static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, | |
1040 | ssize_t size) | |
1041 | { | |
1042 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
1043 | struct ahci_port_priv *pp = ap->private_data; | |
1044 | void __iomem *mmio = hpriv->mmio; | |
1045 | u32 em_ctl; | |
1046 | u32 message[] = {0, 0}; | |
1047 | unsigned long flags; | |
1048 | int pmp; | |
1049 | struct ahci_em_priv *emp; | |
1050 | ||
1051 | /* get the slot number from the message */ | |
1052 | pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; | |
1053 | if (pmp < EM_MAX_SLOTS) | |
1054 | emp = &pp->em_priv[pmp]; | |
1055 | else | |
1056 | return -EINVAL; | |
1057 | ||
bb03c640 | 1058 | ahci_rpm_get_port(ap); |
365cfa1e AV |
1059 | spin_lock_irqsave(ap->lock, flags); |
1060 | ||
1061 | /* | |
1062 | * if we are still busy transmitting a previous message, | |
1063 | * do not allow | |
1064 | */ | |
1065 | em_ctl = readl(mmio + HOST_EM_CTL); | |
1066 | if (em_ctl & EM_CTL_TM) { | |
1067 | spin_unlock_irqrestore(ap->lock, flags); | |
bb03c640 | 1068 | ahci_rpm_put_port(ap); |
365cfa1e AV |
1069 | return -EBUSY; |
1070 | } | |
1071 | ||
008dbd61 HZ |
1072 | if (hpriv->em_msg_type & EM_MSG_TYPE_LED) { |
1073 | /* | |
1074 | * create message header - this is all zero except for | |
1075 | * the message size, which is 4 bytes. | |
1076 | */ | |
1077 | message[0] |= (4 << 8); | |
365cfa1e | 1078 | |
008dbd61 HZ |
1079 | /* ignore 0:4 of byte zero, fill in port info yourself */ |
1080 | message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); | |
365cfa1e | 1081 | |
008dbd61 HZ |
1082 | /* write message to EM_LOC */ |
1083 | writel(message[0], mmio + hpriv->em_loc); | |
1084 | writel(message[1], mmio + hpriv->em_loc+4); | |
1085 | ||
1086 | /* | |
1087 | * tell hardware to transmit the message | |
1088 | */ | |
1089 | writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); | |
1090 | } | |
365cfa1e AV |
1091 | |
1092 | /* save off new led state for port/slot */ | |
1093 | emp->led_state = state; | |
1094 | ||
365cfa1e | 1095 | spin_unlock_irqrestore(ap->lock, flags); |
bb03c640 MW |
1096 | ahci_rpm_put_port(ap); |
1097 | ||
365cfa1e AV |
1098 | return size; |
1099 | } | |
1100 | ||
1101 | static ssize_t ahci_led_show(struct ata_port *ap, char *buf) | |
1102 | { | |
1103 | struct ahci_port_priv *pp = ap->private_data; | |
1104 | struct ata_link *link; | |
1105 | struct ahci_em_priv *emp; | |
1106 | int rc = 0; | |
1107 | ||
1108 | ata_for_each_link(link, ap, EDGE) { | |
1109 | emp = &pp->em_priv[link->pmp]; | |
1110 | rc += sprintf(buf, "%lx\n", emp->led_state); | |
1111 | } | |
1112 | return rc; | |
1113 | } | |
1114 | ||
1115 | static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, | |
1116 | size_t size) | |
1117 | { | |
b2a52b6a | 1118 | unsigned int state; |
365cfa1e AV |
1119 | int pmp; |
1120 | struct ahci_port_priv *pp = ap->private_data; | |
1121 | struct ahci_em_priv *emp; | |
1122 | ||
b2a52b6a DY |
1123 | if (kstrtouint(buf, 0, &state) < 0) |
1124 | return -EINVAL; | |
365cfa1e AV |
1125 | |
1126 | /* get the slot number from the message */ | |
1127 | pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; | |
1128 | if (pmp < EM_MAX_SLOTS) | |
1129 | emp = &pp->em_priv[pmp]; | |
1130 | else | |
1131 | return -EINVAL; | |
1132 | ||
1133 | /* mask off the activity bits if we are in sw_activity | |
1134 | * mode, user should turn off sw_activity before setting | |
1135 | * activity led through em_message | |
1136 | */ | |
1137 | if (emp->blink_policy) | |
1138 | state &= ~EM_MSG_LED_VALUE_ACTIVITY; | |
1139 | ||
439d7a35 | 1140 | return ap->ops->transmit_led_message(ap, state, size); |
365cfa1e AV |
1141 | } |
1142 | ||
1143 | static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) | |
1144 | { | |
1145 | struct ata_link *link = dev->link; | |
1146 | struct ata_port *ap = link->ap; | |
1147 | struct ahci_port_priv *pp = ap->private_data; | |
1148 | struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; | |
1149 | u32 port_led_state = emp->led_state; | |
1150 | ||
1151 | /* save the desired Activity LED behavior */ | |
1152 | if (val == OFF) { | |
1153 | /* clear LFLAG */ | |
1154 | link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); | |
1155 | ||
1156 | /* set the LED to OFF */ | |
1157 | port_led_state &= EM_MSG_LED_VALUE_OFF; | |
1158 | port_led_state |= (ap->port_no | (link->pmp << 8)); | |
439d7a35 | 1159 | ap->ops->transmit_led_message(ap, port_led_state, 4); |
365cfa1e AV |
1160 | } else { |
1161 | link->flags |= ATA_LFLAG_SW_ACTIVITY; | |
1162 | if (val == BLINK_OFF) { | |
1163 | /* set LED to ON for idle */ | |
1164 | port_led_state &= EM_MSG_LED_VALUE_OFF; | |
1165 | port_led_state |= (ap->port_no | (link->pmp << 8)); | |
1166 | port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ | |
439d7a35 | 1167 | ap->ops->transmit_led_message(ap, port_led_state, 4); |
365cfa1e AV |
1168 | } |
1169 | } | |
1170 | emp->blink_policy = val; | |
1171 | return 0; | |
1172 | } | |
1173 | ||
1174 | static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) | |
1175 | { | |
1176 | struct ata_link *link = dev->link; | |
1177 | struct ata_port *ap = link->ap; | |
1178 | struct ahci_port_priv *pp = ap->private_data; | |
1179 | struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; | |
1180 | ||
1181 | /* display the saved value of activity behavior for this | |
1182 | * disk. | |
1183 | */ | |
1184 | return sprintf(buf, "%d\n", emp->blink_policy); | |
1185 | } | |
1186 | ||
1187 | static void ahci_port_init(struct device *dev, struct ata_port *ap, | |
1188 | int port_no, void __iomem *mmio, | |
1189 | void __iomem *port_mmio) | |
1190 | { | |
8a3e33cf | 1191 | struct ahci_host_priv *hpriv = ap->host->private_data; |
365cfa1e AV |
1192 | const char *emsg = NULL; |
1193 | int rc; | |
1194 | u32 tmp; | |
1195 | ||
1196 | /* make sure port is not active */ | |
1197 | rc = ahci_deinit_port(ap, &emsg); | |
1198 | if (rc) | |
1199 | dev_warn(dev, "%s (%d)\n", emsg, rc); | |
1200 | ||
1201 | /* clear SError */ | |
1202 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
1203 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); | |
1204 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
1205 | ||
1206 | /* clear port IRQ */ | |
1207 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1208 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
1209 | if (tmp) | |
1210 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
1211 | ||
1212 | writel(1 << port_no, mmio + HOST_IRQ_STAT); | |
8a3e33cf ML |
1213 | |
1214 | /* mark esata ports */ | |
1215 | tmp = readl(port_mmio + PORT_CMD); | |
dc8b4afc | 1216 | if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)) |
8a3e33cf | 1217 | ap->pflags |= ATA_PFLAG_EXTERNAL; |
365cfa1e AV |
1218 | } |
1219 | ||
1220 | void ahci_init_controller(struct ata_host *host) | |
1221 | { | |
1222 | struct ahci_host_priv *hpriv = host->private_data; | |
1223 | void __iomem *mmio = hpriv->mmio; | |
1224 | int i; | |
1225 | void __iomem *port_mmio; | |
1226 | u32 tmp; | |
1227 | ||
1228 | for (i = 0; i < host->n_ports; i++) { | |
1229 | struct ata_port *ap = host->ports[i]; | |
1230 | ||
1231 | port_mmio = ahci_port_base(ap); | |
1232 | if (ata_port_is_dummy(ap)) | |
1233 | continue; | |
1234 | ||
1235 | ahci_port_init(host->dev, ap, i, mmio, port_mmio); | |
1236 | } | |
1237 | ||
1238 | tmp = readl(mmio + HOST_CTL); | |
1239 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
1240 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); | |
1241 | tmp = readl(mmio + HOST_CTL); | |
1242 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
1243 | } | |
1244 | EXPORT_SYMBOL_GPL(ahci_init_controller); | |
1245 | ||
1246 | static void ahci_dev_config(struct ata_device *dev) | |
1247 | { | |
1248 | struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; | |
1249 | ||
1250 | if (hpriv->flags & AHCI_HFLAG_SECT255) { | |
1251 | dev->max_sectors = 255; | |
a9a79dfe JP |
1252 | ata_dev_info(dev, |
1253 | "SB600 AHCI: limiting to 255 sectors per cmd\n"); | |
365cfa1e AV |
1254 | } |
1255 | } | |
1256 | ||
bbb4ab43 | 1257 | unsigned int ahci_dev_classify(struct ata_port *ap) |
365cfa1e AV |
1258 | { |
1259 | void __iomem *port_mmio = ahci_port_base(ap); | |
1260 | struct ata_taskfile tf; | |
1261 | u32 tmp; | |
1262 | ||
1263 | tmp = readl(port_mmio + PORT_SIG); | |
1264 | tf.lbah = (tmp >> 24) & 0xff; | |
1265 | tf.lbam = (tmp >> 16) & 0xff; | |
1266 | tf.lbal = (tmp >> 8) & 0xff; | |
1267 | tf.nsect = (tmp) & 0xff; | |
1268 | ||
1269 | return ata_dev_classify(&tf); | |
1270 | } | |
bbb4ab43 | 1271 | EXPORT_SYMBOL_GPL(ahci_dev_classify); |
365cfa1e | 1272 | |
02cdfcf0 DM |
1273 | void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
1274 | u32 opts) | |
365cfa1e AV |
1275 | { |
1276 | dma_addr_t cmd_tbl_dma; | |
1277 | ||
1278 | cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; | |
1279 | ||
1280 | pp->cmd_slot[tag].opts = cpu_to_le32(opts); | |
1281 | pp->cmd_slot[tag].status = 0; | |
1282 | pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); | |
1283 | pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); | |
1284 | } | |
02cdfcf0 | 1285 | EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot); |
365cfa1e AV |
1286 | |
1287 | int ahci_kick_engine(struct ata_port *ap) | |
1288 | { | |
1289 | void __iomem *port_mmio = ahci_port_base(ap); | |
1290 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
1291 | u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; | |
1292 | u32 tmp; | |
1293 | int busy, rc; | |
1294 | ||
1295 | /* stop engine */ | |
1296 | rc = ahci_stop_engine(ap); | |
1297 | if (rc) | |
1298 | goto out_restart; | |
1299 | ||
1300 | /* need to do CLO? | |
1301 | * always do CLO if PMP is attached (AHCI-1.3 9.2) | |
1302 | */ | |
1303 | busy = status & (ATA_BUSY | ATA_DRQ); | |
1304 | if (!busy && !sata_pmp_attached(ap)) { | |
1305 | rc = 0; | |
1306 | goto out_restart; | |
1307 | } | |
1308 | ||
1309 | if (!(hpriv->cap & HOST_CAP_CLO)) { | |
1310 | rc = -EOPNOTSUPP; | |
1311 | goto out_restart; | |
1312 | } | |
1313 | ||
1314 | /* perform CLO */ | |
1315 | tmp = readl(port_mmio + PORT_CMD); | |
1316 | tmp |= PORT_CMD_CLO; | |
1317 | writel(tmp, port_mmio + PORT_CMD); | |
1318 | ||
1319 | rc = 0; | |
97750ceb | 1320 | tmp = ata_wait_register(ap, port_mmio + PORT_CMD, |
365cfa1e AV |
1321 | PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); |
1322 | if (tmp & PORT_CMD_CLO) | |
1323 | rc = -EIO; | |
1324 | ||
1325 | /* restart engine */ | |
1326 | out_restart: | |
039ece38 | 1327 | hpriv->start_engine(ap); |
365cfa1e AV |
1328 | return rc; |
1329 | } | |
1330 | EXPORT_SYMBOL_GPL(ahci_kick_engine); | |
1331 | ||
1332 | static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, | |
1333 | struct ata_taskfile *tf, int is_cmd, u16 flags, | |
1334 | unsigned long timeout_msec) | |
1335 | { | |
1336 | const u32 cmd_fis_len = 5; /* five dwords */ | |
1337 | struct ahci_port_priv *pp = ap->private_data; | |
1338 | void __iomem *port_mmio = ahci_port_base(ap); | |
1339 | u8 *fis = pp->cmd_tbl; | |
1340 | u32 tmp; | |
1341 | ||
1342 | /* prep the command */ | |
1343 | ata_tf_to_fis(tf, pmp, is_cmd, fis); | |
1344 | ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); | |
1345 | ||
023113d2 XY |
1346 | /* set port value for softreset of Port Multiplier */ |
1347 | if (pp->fbs_enabled && pp->fbs_last_dev != pmp) { | |
1348 | tmp = readl(port_mmio + PORT_FBS); | |
1349 | tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); | |
1350 | tmp |= pmp << PORT_FBS_DEV_OFFSET; | |
1351 | writel(tmp, port_mmio + PORT_FBS); | |
1352 | pp->fbs_last_dev = pmp; | |
1353 | } | |
1354 | ||
365cfa1e AV |
1355 | /* issue & wait */ |
1356 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
1357 | ||
1358 | if (timeout_msec) { | |
97750ceb TH |
1359 | tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE, |
1360 | 0x1, 0x1, 1, timeout_msec); | |
365cfa1e AV |
1361 | if (tmp & 0x1) { |
1362 | ahci_kick_engine(ap); | |
1363 | return -EBUSY; | |
1364 | } | |
1365 | } else | |
1366 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ | |
1367 | ||
1368 | return 0; | |
1369 | } | |
1370 | ||
1371 | int ahci_do_softreset(struct ata_link *link, unsigned int *class, | |
1372 | int pmp, unsigned long deadline, | |
1373 | int (*check_ready)(struct ata_link *link)) | |
1374 | { | |
1375 | struct ata_port *ap = link->ap; | |
1376 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
89dafa20 | 1377 | struct ahci_port_priv *pp = ap->private_data; |
365cfa1e AV |
1378 | const char *reason = NULL; |
1379 | unsigned long now, msecs; | |
1380 | struct ata_taskfile tf; | |
89dafa20 | 1381 | bool fbs_disabled = false; |
365cfa1e AV |
1382 | int rc; |
1383 | ||
1384 | DPRINTK("ENTER\n"); | |
1385 | ||
1386 | /* prepare for SRST (AHCI-1.1 10.4.1) */ | |
1387 | rc = ahci_kick_engine(ap); | |
1388 | if (rc && rc != -EOPNOTSUPP) | |
a9a79dfe | 1389 | ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc); |
365cfa1e | 1390 | |
89dafa20 | 1391 | /* |
1392 | * According to AHCI-1.2 9.3.9: if FBS is enable, software shall | |
1393 | * clear PxFBS.EN to '0' prior to issuing software reset to devices | |
1394 | * that is attached to port multiplier. | |
1395 | */ | |
1396 | if (!ata_is_host_link(link) && pp->fbs_enabled) { | |
1397 | ahci_disable_fbs(ap); | |
1398 | fbs_disabled = true; | |
1399 | } | |
1400 | ||
365cfa1e AV |
1401 | ata_tf_init(link->device, &tf); |
1402 | ||
1403 | /* issue the first D2H Register FIS */ | |
1404 | msecs = 0; | |
1405 | now = jiffies; | |
f1f5a807 | 1406 | if (time_after(deadline, now)) |
365cfa1e AV |
1407 | msecs = jiffies_to_msecs(deadline - now); |
1408 | ||
1409 | tf.ctl |= ATA_SRST; | |
1410 | if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, | |
1411 | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { | |
1412 | rc = -EIO; | |
1413 | reason = "1st FIS failed"; | |
1414 | goto fail; | |
1415 | } | |
1416 | ||
1417 | /* spec says at least 5us, but be generous and sleep for 1ms */ | |
97750ceb | 1418 | ata_msleep(ap, 1); |
365cfa1e AV |
1419 | |
1420 | /* issue the second D2H Register FIS */ | |
1421 | tf.ctl &= ~ATA_SRST; | |
1422 | ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); | |
1423 | ||
1424 | /* wait for link to become ready */ | |
1425 | rc = ata_wait_after_reset(link, deadline, check_ready); | |
1426 | if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) { | |
1427 | /* | |
1428 | * Workaround for cases where link online status can't | |
1429 | * be trusted. Treat device readiness timeout as link | |
1430 | * offline. | |
1431 | */ | |
a9a79dfe | 1432 | ata_link_info(link, "device not ready, treating as offline\n"); |
365cfa1e AV |
1433 | *class = ATA_DEV_NONE; |
1434 | } else if (rc) { | |
1435 | /* link occupied, -ENODEV too is an error */ | |
1436 | reason = "device not ready"; | |
1437 | goto fail; | |
1438 | } else | |
1439 | *class = ahci_dev_classify(ap); | |
1440 | ||
89dafa20 | 1441 | /* re-enable FBS if disabled before */ |
1442 | if (fbs_disabled) | |
1443 | ahci_enable_fbs(ap); | |
1444 | ||
365cfa1e AV |
1445 | DPRINTK("EXIT, class=%u\n", *class); |
1446 | return 0; | |
1447 | ||
1448 | fail: | |
a9a79dfe | 1449 | ata_link_err(link, "softreset failed (%s)\n", reason); |
365cfa1e AV |
1450 | return rc; |
1451 | } | |
1452 | ||
1453 | int ahci_check_ready(struct ata_link *link) | |
1454 | { | |
1455 | void __iomem *port_mmio = ahci_port_base(link->ap); | |
1456 | u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; | |
1457 | ||
1458 | return ata_check_ready(status); | |
1459 | } | |
1460 | EXPORT_SYMBOL_GPL(ahci_check_ready); | |
1461 | ||
1462 | static int ahci_softreset(struct ata_link *link, unsigned int *class, | |
1463 | unsigned long deadline) | |
1464 | { | |
1465 | int pmp = sata_srst_pmp(link); | |
1466 | ||
1467 | DPRINTK("ENTER\n"); | |
1468 | ||
1469 | return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); | |
1470 | } | |
1471 | EXPORT_SYMBOL_GPL(ahci_do_softreset); | |
1472 | ||
345347c5 YHC |
1473 | static int ahci_bad_pmp_check_ready(struct ata_link *link) |
1474 | { | |
1475 | void __iomem *port_mmio = ahci_port_base(link->ap); | |
1476 | u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; | |
1477 | u32 irq_status = readl(port_mmio + PORT_IRQ_STAT); | |
1478 | ||
1479 | /* | |
1480 | * There is no need to check TFDATA if BAD PMP is found due to HW bug, | |
1481 | * which can save timeout delay. | |
1482 | */ | |
1483 | if (irq_status & PORT_IRQ_BAD_PMP) | |
1484 | return -EIO; | |
1485 | ||
1486 | return ata_check_ready(status); | |
1487 | } | |
1488 | ||
35186d05 DY |
1489 | static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, |
1490 | unsigned long deadline) | |
345347c5 YHC |
1491 | { |
1492 | struct ata_port *ap = link->ap; | |
1493 | void __iomem *port_mmio = ahci_port_base(ap); | |
1494 | int pmp = sata_srst_pmp(link); | |
1495 | int rc; | |
1496 | u32 irq_sts; | |
1497 | ||
1498 | DPRINTK("ENTER\n"); | |
1499 | ||
1500 | rc = ahci_do_softreset(link, class, pmp, deadline, | |
1501 | ahci_bad_pmp_check_ready); | |
1502 | ||
1503 | /* | |
1504 | * Soft reset fails with IPMS set when PMP is enabled but | |
1505 | * SATA HDD/ODD is connected to SATA port, do soft reset | |
1506 | * again to port 0. | |
1507 | */ | |
1508 | if (rc == -EIO) { | |
1509 | irq_sts = readl(port_mmio + PORT_IRQ_STAT); | |
1510 | if (irq_sts & PORT_IRQ_BAD_PMP) { | |
39f80acb | 1511 | ata_link_warn(link, |
345347c5 YHC |
1512 | "applying PMP SRST workaround " |
1513 | "and retrying\n"); | |
1514 | rc = ahci_do_softreset(link, class, 0, deadline, | |
1515 | ahci_check_ready); | |
1516 | } | |
1517 | } | |
1518 | ||
1519 | return rc; | |
1520 | } | |
1521 | ||
d436501e BG |
1522 | int ahci_do_hardreset(struct ata_link *link, unsigned int *class, |
1523 | unsigned long deadline, bool *online) | |
365cfa1e AV |
1524 | { |
1525 | const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); | |
1526 | struct ata_port *ap = link->ap; | |
1527 | struct ahci_port_priv *pp = ap->private_data; | |
039ece38 | 1528 | struct ahci_host_priv *hpriv = ap->host->private_data; |
365cfa1e AV |
1529 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
1530 | struct ata_taskfile tf; | |
365cfa1e AV |
1531 | int rc; |
1532 | ||
1533 | DPRINTK("ENTER\n"); | |
1534 | ||
1535 | ahci_stop_engine(ap); | |
1536 | ||
1537 | /* clear D2H reception area to properly wait for D2H FIS */ | |
1538 | ata_tf_init(link->device, &tf); | |
9bbb1b0e | 1539 | tf.command = ATA_BUSY; |
365cfa1e AV |
1540 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); |
1541 | ||
d436501e | 1542 | rc = sata_link_hardreset(link, timing, deadline, online, |
365cfa1e AV |
1543 | ahci_check_ready); |
1544 | ||
039ece38 | 1545 | hpriv->start_engine(ap); |
365cfa1e | 1546 | |
d436501e | 1547 | if (*online) |
365cfa1e AV |
1548 | *class = ahci_dev_classify(ap); |
1549 | ||
1550 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); | |
1551 | return rc; | |
1552 | } | |
d436501e BG |
1553 | EXPORT_SYMBOL_GPL(ahci_do_hardreset); |
1554 | ||
1555 | static int ahci_hardreset(struct ata_link *link, unsigned int *class, | |
1556 | unsigned long deadline) | |
1557 | { | |
1558 | bool online; | |
1559 | ||
1560 | return ahci_do_hardreset(link, class, deadline, &online); | |
1561 | } | |
365cfa1e AV |
1562 | |
1563 | static void ahci_postreset(struct ata_link *link, unsigned int *class) | |
1564 | { | |
1565 | struct ata_port *ap = link->ap; | |
1566 | void __iomem *port_mmio = ahci_port_base(ap); | |
1567 | u32 new_tmp, tmp; | |
1568 | ||
1569 | ata_std_postreset(link, class); | |
1570 | ||
1571 | /* Make sure port's ATAPI bit is set appropriately */ | |
1572 | new_tmp = tmp = readl(port_mmio + PORT_CMD); | |
1573 | if (*class == ATA_DEV_ATAPI) | |
1574 | new_tmp |= PORT_CMD_ATAPI; | |
1575 | else | |
1576 | new_tmp &= ~PORT_CMD_ATAPI; | |
1577 | if (new_tmp != tmp) { | |
1578 | writel(new_tmp, port_mmio + PORT_CMD); | |
1579 | readl(port_mmio + PORT_CMD); /* flush */ | |
1580 | } | |
1581 | } | |
1582 | ||
1583 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) | |
1584 | { | |
1585 | struct scatterlist *sg; | |
1586 | struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; | |
1587 | unsigned int si; | |
1588 | ||
1589 | VPRINTK("ENTER\n"); | |
1590 | ||
1591 | /* | |
1592 | * Next, the S/G list. | |
1593 | */ | |
1594 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
1595 | dma_addr_t addr = sg_dma_address(sg); | |
1596 | u32 sg_len = sg_dma_len(sg); | |
1597 | ||
1598 | ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); | |
1599 | ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); | |
1600 | ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); | |
1601 | } | |
1602 | ||
1603 | return si; | |
1604 | } | |
1605 | ||
1606 | static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc) | |
1607 | { | |
1608 | struct ata_port *ap = qc->ap; | |
1609 | struct ahci_port_priv *pp = ap->private_data; | |
1610 | ||
1611 | if (!sata_pmp_attached(ap) || pp->fbs_enabled) | |
1612 | return ata_std_qc_defer(qc); | |
1613 | else | |
1614 | return sata_pmp_qc_defer_cmd_switch(qc); | |
1615 | } | |
1616 | ||
1617 | static void ahci_qc_prep(struct ata_queued_cmd *qc) | |
1618 | { | |
1619 | struct ata_port *ap = qc->ap; | |
1620 | struct ahci_port_priv *pp = ap->private_data; | |
1621 | int is_atapi = ata_is_atapi(qc->tf.protocol); | |
1622 | void *cmd_tbl; | |
1623 | u32 opts; | |
1624 | const u32 cmd_fis_len = 5; /* five dwords */ | |
1625 | unsigned int n_elem; | |
1626 | ||
1627 | /* | |
1628 | * Fill in command table information. First, the header, | |
1629 | * a SATA Register - Host to Device command FIS. | |
1630 | */ | |
1631 | cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; | |
1632 | ||
1633 | ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); | |
1634 | if (is_atapi) { | |
1635 | memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); | |
1636 | memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); | |
1637 | } | |
1638 | ||
1639 | n_elem = 0; | |
1640 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
1641 | n_elem = ahci_fill_sg(qc, cmd_tbl); | |
1642 | ||
1643 | /* | |
1644 | * Fill in command slot information. | |
1645 | */ | |
1646 | opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); | |
1647 | if (qc->tf.flags & ATA_TFLAG_WRITE) | |
1648 | opts |= AHCI_CMD_WRITE; | |
1649 | if (is_atapi) | |
1650 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; | |
1651 | ||
1652 | ahci_fill_cmd_slot(pp, qc->tag, opts); | |
1653 | } | |
1654 | ||
1655 | static void ahci_fbs_dec_intr(struct ata_port *ap) | |
1656 | { | |
1657 | struct ahci_port_priv *pp = ap->private_data; | |
1658 | void __iomem *port_mmio = ahci_port_base(ap); | |
1659 | u32 fbs = readl(port_mmio + PORT_FBS); | |
1660 | int retries = 3; | |
1661 | ||
1662 | DPRINTK("ENTER\n"); | |
1663 | BUG_ON(!pp->fbs_enabled); | |
1664 | ||
1665 | /* time to wait for DEC is not specified by AHCI spec, | |
1666 | * add a retry loop for safety. | |
1667 | */ | |
1668 | writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS); | |
1669 | fbs = readl(port_mmio + PORT_FBS); | |
1670 | while ((fbs & PORT_FBS_DEC) && retries--) { | |
1671 | udelay(1); | |
1672 | fbs = readl(port_mmio + PORT_FBS); | |
1673 | } | |
1674 | ||
1675 | if (fbs & PORT_FBS_DEC) | |
a44fec1f | 1676 | dev_err(ap->host->dev, "failed to clear device error\n"); |
365cfa1e AV |
1677 | } |
1678 | ||
1679 | static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) | |
1680 | { | |
1681 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
1682 | struct ahci_port_priv *pp = ap->private_data; | |
1683 | struct ata_eh_info *host_ehi = &ap->link.eh_info; | |
1684 | struct ata_link *link = NULL; | |
1685 | struct ata_queued_cmd *active_qc; | |
1686 | struct ata_eh_info *active_ehi; | |
1687 | bool fbs_need_dec = false; | |
1688 | u32 serror; | |
1689 | ||
1690 | /* determine active link with error */ | |
1691 | if (pp->fbs_enabled) { | |
1692 | void __iomem *port_mmio = ahci_port_base(ap); | |
1693 | u32 fbs = readl(port_mmio + PORT_FBS); | |
1694 | int pmp = fbs >> PORT_FBS_DWE_OFFSET; | |
1695 | ||
912b9ac6 | 1696 | if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) { |
365cfa1e AV |
1697 | link = &ap->pmp_link[pmp]; |
1698 | fbs_need_dec = true; | |
1699 | } | |
1700 | ||
1701 | } else | |
1702 | ata_for_each_link(link, ap, EDGE) | |
1703 | if (ata_link_active(link)) | |
1704 | break; | |
1705 | ||
1706 | if (!link) | |
1707 | link = &ap->link; | |
1708 | ||
1709 | active_qc = ata_qc_from_tag(ap, link->active_tag); | |
1710 | active_ehi = &link->eh_info; | |
1711 | ||
1712 | /* record irq stat */ | |
1713 | ata_ehi_clear_desc(host_ehi); | |
1714 | ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); | |
1715 | ||
1716 | /* AHCI needs SError cleared; otherwise, it might lock up */ | |
1717 | ahci_scr_read(&ap->link, SCR_ERROR, &serror); | |
1718 | ahci_scr_write(&ap->link, SCR_ERROR, serror); | |
1719 | host_ehi->serror |= serror; | |
1720 | ||
1721 | /* some controllers set IRQ_IF_ERR on device errors, ignore it */ | |
1722 | if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) | |
1723 | irq_stat &= ~PORT_IRQ_IF_ERR; | |
1724 | ||
1725 | if (irq_stat & PORT_IRQ_TF_ERR) { | |
1726 | /* If qc is active, charge it; otherwise, the active | |
1727 | * link. There's no active qc on NCQ errors. It will | |
1728 | * be determined by EH by reading log page 10h. | |
1729 | */ | |
1730 | if (active_qc) | |
1731 | active_qc->err_mask |= AC_ERR_DEV; | |
1732 | else | |
1733 | active_ehi->err_mask |= AC_ERR_DEV; | |
1734 | ||
1735 | if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) | |
1736 | host_ehi->serror &= ~SERR_INTERNAL; | |
1737 | } | |
1738 | ||
1739 | if (irq_stat & PORT_IRQ_UNK_FIS) { | |
d5185d65 | 1740 | u32 *unk = pp->rx_fis + RX_FIS_UNK; |
365cfa1e AV |
1741 | |
1742 | active_ehi->err_mask |= AC_ERR_HSM; | |
1743 | active_ehi->action |= ATA_EH_RESET; | |
1744 | ata_ehi_push_desc(active_ehi, | |
1745 | "unknown FIS %08x %08x %08x %08x" , | |
1746 | unk[0], unk[1], unk[2], unk[3]); | |
1747 | } | |
1748 | ||
1749 | if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { | |
1750 | active_ehi->err_mask |= AC_ERR_HSM; | |
1751 | active_ehi->action |= ATA_EH_RESET; | |
1752 | ata_ehi_push_desc(active_ehi, "incorrect PMP"); | |
1753 | } | |
1754 | ||
1755 | if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { | |
1756 | host_ehi->err_mask |= AC_ERR_HOST_BUS; | |
1757 | host_ehi->action |= ATA_EH_RESET; | |
1758 | ata_ehi_push_desc(host_ehi, "host bus error"); | |
1759 | } | |
1760 | ||
1761 | if (irq_stat & PORT_IRQ_IF_ERR) { | |
1762 | if (fbs_need_dec) | |
1763 | active_ehi->err_mask |= AC_ERR_DEV; | |
1764 | else { | |
1765 | host_ehi->err_mask |= AC_ERR_ATA_BUS; | |
1766 | host_ehi->action |= ATA_EH_RESET; | |
1767 | } | |
1768 | ||
1769 | ata_ehi_push_desc(host_ehi, "interface fatal error"); | |
1770 | } | |
1771 | ||
1772 | if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { | |
1773 | ata_ehi_hotplugged(host_ehi); | |
1774 | ata_ehi_push_desc(host_ehi, "%s", | |
1775 | irq_stat & PORT_IRQ_CONNECT ? | |
1776 | "connection status changed" : "PHY RDY changed"); | |
1777 | } | |
1778 | ||
1779 | /* okay, let's hand over to EH */ | |
1780 | ||
1781 | if (irq_stat & PORT_IRQ_FREEZE) | |
1782 | ata_port_freeze(ap); | |
1783 | else if (fbs_need_dec) { | |
1784 | ata_link_abort(link); | |
1785 | ahci_fbs_dec_intr(ap); | |
1786 | } else | |
1787 | ata_port_abort(ap); | |
1788 | } | |
1789 | ||
5ca72c4f AG |
1790 | static void ahci_handle_port_interrupt(struct ata_port *ap, |
1791 | void __iomem *port_mmio, u32 status) | |
365cfa1e | 1792 | { |
365cfa1e AV |
1793 | struct ata_eh_info *ehi = &ap->link.eh_info; |
1794 | struct ahci_port_priv *pp = ap->private_data; | |
1795 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
1796 | int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); | |
5ca72c4f | 1797 | u32 qc_active = 0; |
365cfa1e AV |
1798 | int rc; |
1799 | ||
365cfa1e AV |
1800 | /* ignore BAD_PMP while resetting */ |
1801 | if (unlikely(resetting)) | |
1802 | status &= ~PORT_IRQ_BAD_PMP; | |
1803 | ||
8393b811 | 1804 | if (sata_lpm_ignore_phy_events(&ap->link)) { |
365cfa1e | 1805 | status &= ~PORT_IRQ_PHYRDY; |
6b7ae954 | 1806 | ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG); |
365cfa1e AV |
1807 | } |
1808 | ||
1809 | if (unlikely(status & PORT_IRQ_ERROR)) { | |
1810 | ahci_error_intr(ap, status); | |
1811 | return; | |
1812 | } | |
1813 | ||
1814 | if (status & PORT_IRQ_SDB_FIS) { | |
1815 | /* If SNotification is available, leave notification | |
1816 | * handling to sata_async_notification(). If not, | |
1817 | * emulate it by snooping SDB FIS RX area. | |
1818 | * | |
1819 | * Snooping FIS RX area is probably cheaper than | |
1820 | * poking SNotification but some constrollers which | |
1821 | * implement SNotification, ICH9 for example, don't | |
1822 | * store AN SDB FIS into receive area. | |
1823 | */ | |
1824 | if (hpriv->cap & HOST_CAP_SNTF) | |
1825 | sata_async_notification(ap); | |
1826 | else { | |
1827 | /* If the 'N' bit in word 0 of the FIS is set, | |
1828 | * we just received asynchronous notification. | |
1829 | * Tell libata about it. | |
1830 | * | |
1831 | * Lack of SNotification should not appear in | |
1832 | * ahci 1.2, so the workaround is unnecessary | |
1833 | * when FBS is enabled. | |
1834 | */ | |
1835 | if (pp->fbs_enabled) | |
1836 | WARN_ON_ONCE(1); | |
1837 | else { | |
1838 | const __le32 *f = pp->rx_fis + RX_FIS_SDB; | |
1839 | u32 f0 = le32_to_cpu(f[0]); | |
1840 | if (f0 & (1 << 15)) | |
1841 | sata_async_notification(ap); | |
1842 | } | |
1843 | } | |
1844 | } | |
1845 | ||
1846 | /* pp->active_link is not reliable once FBS is enabled, both | |
1847 | * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because | |
1848 | * NCQ and non-NCQ commands may be in flight at the same time. | |
1849 | */ | |
1850 | if (pp->fbs_enabled) { | |
1851 | if (ap->qc_active) { | |
1852 | qc_active = readl(port_mmio + PORT_SCR_ACT); | |
1853 | qc_active |= readl(port_mmio + PORT_CMD_ISSUE); | |
1854 | } | |
1855 | } else { | |
1856 | /* pp->active_link is valid iff any command is in flight */ | |
1857 | if (ap->qc_active && pp->active_link->sactive) | |
1858 | qc_active = readl(port_mmio + PORT_SCR_ACT); | |
1859 | else | |
1860 | qc_active = readl(port_mmio + PORT_CMD_ISSUE); | |
1861 | } | |
1862 | ||
1863 | ||
1864 | rc = ata_qc_complete_multiple(ap, qc_active); | |
1865 | ||
1866 | /* while resetting, invalid completions are expected */ | |
1867 | if (unlikely(rc < 0 && !resetting)) { | |
1868 | ehi->err_mask |= AC_ERR_HSM; | |
1869 | ehi->action |= ATA_EH_RESET; | |
1870 | ata_port_freeze(ap); | |
1871 | } | |
1872 | } | |
1873 | ||
7865f83f | 1874 | static void ahci_port_intr(struct ata_port *ap) |
5ca72c4f AG |
1875 | { |
1876 | void __iomem *port_mmio = ahci_port_base(ap); | |
1877 | u32 status; | |
1878 | ||
1879 | status = readl(port_mmio + PORT_IRQ_STAT); | |
1880 | writel(status, port_mmio + PORT_IRQ_STAT); | |
1881 | ||
7865f83f | 1882 | ahci_handle_port_interrupt(ap, port_mmio, status); |
5ca72c4f AG |
1883 | } |
1884 | ||
a6b7fb76 | 1885 | static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance) |
5ca72c4f AG |
1886 | { |
1887 | struct ata_port *ap = dev_instance; | |
5ca72c4f | 1888 | void __iomem *port_mmio = ahci_port_base(ap); |
5ca72c4f AG |
1889 | u32 status; |
1890 | ||
5ca72c4f AG |
1891 | VPRINTK("ENTER\n"); |
1892 | ||
227dfb4d AG |
1893 | status = readl(port_mmio + PORT_IRQ_STAT); |
1894 | writel(status, port_mmio + PORT_IRQ_STAT); | |
5ca72c4f | 1895 | |
a6b7fb76 DW |
1896 | spin_lock(ap->lock); |
1897 | ahci_handle_port_interrupt(ap, port_mmio, status); | |
1898 | spin_unlock(ap->lock); | |
5ca72c4f AG |
1899 | |
1900 | VPRINTK("EXIT\n"); | |
1901 | ||
a6b7fb76 | 1902 | return IRQ_HANDLED; |
5ca72c4f | 1903 | } |
5ca72c4f | 1904 | |
f070d671 | 1905 | u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked) |
365cfa1e | 1906 | { |
365cfa1e | 1907 | unsigned int i, handled = 0; |
03e83cbd | 1908 | |
365cfa1e AV |
1909 | for (i = 0; i < host->n_ports; i++) { |
1910 | struct ata_port *ap; | |
1911 | ||
1912 | if (!(irq_masked & (1 << i))) | |
1913 | continue; | |
1914 | ||
1915 | ap = host->ports[i]; | |
1916 | if (ap) { | |
7865f83f | 1917 | ahci_port_intr(ap); |
365cfa1e AV |
1918 | VPRINTK("port %u\n", i); |
1919 | } else { | |
1920 | VPRINTK("port %u (no irq)\n", i); | |
1921 | if (ata_ratelimit()) | |
a44fec1f JP |
1922 | dev_warn(host->dev, |
1923 | "interrupt on disabled port %u\n", i); | |
365cfa1e AV |
1924 | } |
1925 | ||
1926 | handled = 1; | |
1927 | } | |
1928 | ||
a129db89 ST |
1929 | return handled; |
1930 | } | |
f070d671 | 1931 | EXPORT_SYMBOL_GPL(ahci_handle_port_intr); |
a129db89 ST |
1932 | |
1933 | static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance) | |
1934 | { | |
1935 | struct ata_host *host = dev_instance; | |
1936 | struct ahci_host_priv *hpriv; | |
1937 | unsigned int rc = 0; | |
1938 | void __iomem *mmio; | |
1939 | u32 irq_stat, irq_masked; | |
1940 | ||
1941 | VPRINTK("ENTER\n"); | |
1942 | ||
1943 | hpriv = host->private_data; | |
1944 | mmio = hpriv->mmio; | |
1945 | ||
1946 | /* sigh. 0xffffffff is a valid return from h/w */ | |
1947 | irq_stat = readl(mmio + HOST_IRQ_STAT); | |
1948 | if (!irq_stat) | |
1949 | return IRQ_NONE; | |
1950 | ||
1951 | irq_masked = irq_stat & hpriv->port_map; | |
1952 | ||
1953 | spin_lock(&host->lock); | |
1954 | ||
1955 | rc = ahci_handle_port_intr(host, irq_masked); | |
365cfa1e AV |
1956 | |
1957 | /* HOST_IRQ_STAT behaves as level triggered latch meaning that | |
1958 | * it should be cleared after all the port events are cleared; | |
1959 | * otherwise, it will raise a spurious interrupt after each | |
1960 | * valid one. Please read section 10.6.2 of ahci 1.1 for more | |
1961 | * information. | |
1962 | * | |
1963 | * Also, use the unmasked value to clear interrupt as spurious | |
1964 | * pending event on a dummy port might cause screaming IRQ. | |
1965 | */ | |
1966 | writel(irq_stat, mmio + HOST_IRQ_STAT); | |
1967 | ||
03e83cbd TH |
1968 | spin_unlock(&host->lock); |
1969 | ||
365cfa1e AV |
1970 | VPRINTK("EXIT\n"); |
1971 | ||
a129db89 | 1972 | return IRQ_RETVAL(rc); |
365cfa1e | 1973 | } |
365cfa1e | 1974 | |
39e0ee99 | 1975 | unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
365cfa1e AV |
1976 | { |
1977 | struct ata_port *ap = qc->ap; | |
1978 | void __iomem *port_mmio = ahci_port_base(ap); | |
1979 | struct ahci_port_priv *pp = ap->private_data; | |
1980 | ||
1981 | /* Keep track of the currently active link. It will be used | |
1982 | * in completion path to determine whether NCQ phase is in | |
1983 | * progress. | |
1984 | */ | |
1985 | pp->active_link = qc->dev->link; | |
1986 | ||
179b310a | 1987 | if (ata_is_ncq(qc->tf.protocol)) |
365cfa1e AV |
1988 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); |
1989 | ||
1990 | if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) { | |
1991 | u32 fbs = readl(port_mmio + PORT_FBS); | |
1992 | fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); | |
1993 | fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET; | |
1994 | writel(fbs, port_mmio + PORT_FBS); | |
1995 | pp->fbs_last_dev = qc->dev->link->pmp; | |
1996 | } | |
1997 | ||
1998 | writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); | |
1999 | ||
2000 | ahci_sw_activity(qc->dev->link); | |
2001 | ||
2002 | return 0; | |
2003 | } | |
39e0ee99 | 2004 | EXPORT_SYMBOL_GPL(ahci_qc_issue); |
365cfa1e AV |
2005 | |
2006 | static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) | |
2007 | { | |
2008 | struct ahci_port_priv *pp = qc->ap->private_data; | |
6ad60195 | 2009 | u8 *rx_fis = pp->rx_fis; |
365cfa1e AV |
2010 | |
2011 | if (pp->fbs_enabled) | |
6ad60195 TH |
2012 | rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; |
2013 | ||
2014 | /* | |
2015 | * After a successful execution of an ATA PIO data-in command, | |
2016 | * the device doesn't send D2H Reg FIS to update the TF and | |
2017 | * the host should take TF and E_Status from the preceding PIO | |
2018 | * Setup FIS. | |
2019 | */ | |
2020 | if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && | |
2021 | !(qc->flags & ATA_QCFLAG_FAILED)) { | |
2022 | ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); | |
2023 | qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15]; | |
2024 | } else | |
2025 | ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); | |
365cfa1e | 2026 | |
365cfa1e AV |
2027 | return true; |
2028 | } | |
2029 | ||
2030 | static void ahci_freeze(struct ata_port *ap) | |
2031 | { | |
2032 | void __iomem *port_mmio = ahci_port_base(ap); | |
2033 | ||
2034 | /* turn IRQ off */ | |
2035 | writel(0, port_mmio + PORT_IRQ_MASK); | |
2036 | } | |
2037 | ||
2038 | static void ahci_thaw(struct ata_port *ap) | |
2039 | { | |
2040 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
2041 | void __iomem *mmio = hpriv->mmio; | |
2042 | void __iomem *port_mmio = ahci_port_base(ap); | |
2043 | u32 tmp; | |
2044 | struct ahci_port_priv *pp = ap->private_data; | |
2045 | ||
2046 | /* clear IRQ */ | |
2047 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
2048 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
2049 | writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); | |
2050 | ||
2051 | /* turn IRQ back on */ | |
2052 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
2053 | } | |
2054 | ||
8b789d89 | 2055 | void ahci_error_handler(struct ata_port *ap) |
365cfa1e | 2056 | { |
039ece38 HG |
2057 | struct ahci_host_priv *hpriv = ap->host->private_data; |
2058 | ||
365cfa1e AV |
2059 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
2060 | /* restart engine */ | |
2061 | ahci_stop_engine(ap); | |
039ece38 | 2062 | hpriv->start_engine(ap); |
365cfa1e AV |
2063 | } |
2064 | ||
2065 | sata_pmp_error_handler(ap); | |
0ee71952 TH |
2066 | |
2067 | if (!ata_dev_enabled(ap->link.device)) | |
2068 | ahci_stop_engine(ap); | |
365cfa1e | 2069 | } |
8b789d89 | 2070 | EXPORT_SYMBOL_GPL(ahci_error_handler); |
365cfa1e AV |
2071 | |
2072 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) | |
2073 | { | |
2074 | struct ata_port *ap = qc->ap; | |
2075 | ||
2076 | /* make DMA engine forget about the failed command */ | |
2077 | if (qc->flags & ATA_QCFLAG_FAILED) | |
2078 | ahci_kick_engine(ap); | |
2079 | } | |
2080 | ||
65fe1f0f SH |
2081 | static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep) |
2082 | { | |
039ece38 | 2083 | struct ahci_host_priv *hpriv = ap->host->private_data; |
65fe1f0f SH |
2084 | void __iomem *port_mmio = ahci_port_base(ap); |
2085 | struct ata_device *dev = ap->link.device; | |
2086 | u32 devslp, dm, dito, mdat, deto; | |
2087 | int rc; | |
2088 | unsigned int err_mask; | |
2089 | ||
2090 | devslp = readl(port_mmio + PORT_DEVSLP); | |
2091 | if (!(devslp & PORT_DEVSLP_DSP)) { | |
95bbbe9a | 2092 | dev_info(ap->host->dev, "port does not support device sleep\n"); |
65fe1f0f SH |
2093 | return; |
2094 | } | |
2095 | ||
2096 | /* disable device sleep */ | |
2097 | if (!sleep) { | |
2098 | if (devslp & PORT_DEVSLP_ADSE) { | |
2099 | writel(devslp & ~PORT_DEVSLP_ADSE, | |
2100 | port_mmio + PORT_DEVSLP); | |
2101 | err_mask = ata_dev_set_feature(dev, | |
2102 | SETFEATURES_SATA_DISABLE, | |
2103 | SATA_DEVSLP); | |
2104 | if (err_mask && err_mask != AC_ERR_DEV) | |
2105 | ata_dev_warn(dev, "failed to disable DEVSLP\n"); | |
2106 | } | |
2107 | return; | |
2108 | } | |
2109 | ||
2110 | /* device sleep was already enabled */ | |
2111 | if (devslp & PORT_DEVSLP_ADSE) | |
2112 | return; | |
2113 | ||
2114 | /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */ | |
2115 | rc = ahci_stop_engine(ap); | |
2116 | if (rc) | |
2117 | return; | |
2118 | ||
2119 | dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET; | |
2120 | dito = devslp_idle_timeout / (dm + 1); | |
2121 | if (dito > 0x3ff) | |
2122 | dito = 0x3ff; | |
2123 | ||
2124 | /* Use the nominal value 10 ms if the read MDAT is zero, | |
2125 | * the nominal value of DETO is 20 ms. | |
2126 | */ | |
803739d2 | 2127 | if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] & |
65fe1f0f | 2128 | ATA_LOG_DEVSLP_VALID_MASK) { |
803739d2 | 2129 | mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] & |
65fe1f0f SH |
2130 | ATA_LOG_DEVSLP_MDAT_MASK; |
2131 | if (!mdat) | |
2132 | mdat = 10; | |
803739d2 | 2133 | deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO]; |
65fe1f0f SH |
2134 | if (!deto) |
2135 | deto = 20; | |
2136 | } else { | |
2137 | mdat = 10; | |
2138 | deto = 20; | |
2139 | } | |
2140 | ||
2141 | devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) | | |
2142 | (mdat << PORT_DEVSLP_MDAT_OFFSET) | | |
2143 | (deto << PORT_DEVSLP_DETO_OFFSET) | | |
2144 | PORT_DEVSLP_ADSE); | |
2145 | writel(devslp, port_mmio + PORT_DEVSLP); | |
2146 | ||
039ece38 | 2147 | hpriv->start_engine(ap); |
65fe1f0f SH |
2148 | |
2149 | /* enable device sleep feature for the drive */ | |
2150 | err_mask = ata_dev_set_feature(dev, | |
2151 | SETFEATURES_SATA_ENABLE, | |
2152 | SATA_DEVSLP); | |
2153 | if (err_mask && err_mask != AC_ERR_DEV) | |
2154 | ata_dev_warn(dev, "failed to enable DEVSLP\n"); | |
2155 | } | |
2156 | ||
365cfa1e AV |
2157 | static void ahci_enable_fbs(struct ata_port *ap) |
2158 | { | |
039ece38 | 2159 | struct ahci_host_priv *hpriv = ap->host->private_data; |
365cfa1e AV |
2160 | struct ahci_port_priv *pp = ap->private_data; |
2161 | void __iomem *port_mmio = ahci_port_base(ap); | |
2162 | u32 fbs; | |
2163 | int rc; | |
2164 | ||
2165 | if (!pp->fbs_supported) | |
2166 | return; | |
2167 | ||
2168 | fbs = readl(port_mmio + PORT_FBS); | |
2169 | if (fbs & PORT_FBS_EN) { | |
2170 | pp->fbs_enabled = true; | |
2171 | pp->fbs_last_dev = -1; /* initialization */ | |
2172 | return; | |
2173 | } | |
2174 | ||
2175 | rc = ahci_stop_engine(ap); | |
2176 | if (rc) | |
2177 | return; | |
2178 | ||
2179 | writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); | |
2180 | fbs = readl(port_mmio + PORT_FBS); | |
2181 | if (fbs & PORT_FBS_EN) { | |
a44fec1f | 2182 | dev_info(ap->host->dev, "FBS is enabled\n"); |
365cfa1e AV |
2183 | pp->fbs_enabled = true; |
2184 | pp->fbs_last_dev = -1; /* initialization */ | |
2185 | } else | |
a44fec1f | 2186 | dev_err(ap->host->dev, "Failed to enable FBS\n"); |
365cfa1e | 2187 | |
039ece38 | 2188 | hpriv->start_engine(ap); |
365cfa1e AV |
2189 | } |
2190 | ||
2191 | static void ahci_disable_fbs(struct ata_port *ap) | |
2192 | { | |
039ece38 | 2193 | struct ahci_host_priv *hpriv = ap->host->private_data; |
365cfa1e AV |
2194 | struct ahci_port_priv *pp = ap->private_data; |
2195 | void __iomem *port_mmio = ahci_port_base(ap); | |
2196 | u32 fbs; | |
2197 | int rc; | |
2198 | ||
2199 | if (!pp->fbs_supported) | |
2200 | return; | |
2201 | ||
2202 | fbs = readl(port_mmio + PORT_FBS); | |
2203 | if ((fbs & PORT_FBS_EN) == 0) { | |
2204 | pp->fbs_enabled = false; | |
2205 | return; | |
2206 | } | |
2207 | ||
2208 | rc = ahci_stop_engine(ap); | |
2209 | if (rc) | |
2210 | return; | |
2211 | ||
2212 | writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS); | |
2213 | fbs = readl(port_mmio + PORT_FBS); | |
2214 | if (fbs & PORT_FBS_EN) | |
a44fec1f | 2215 | dev_err(ap->host->dev, "Failed to disable FBS\n"); |
365cfa1e | 2216 | else { |
a44fec1f | 2217 | dev_info(ap->host->dev, "FBS is disabled\n"); |
365cfa1e AV |
2218 | pp->fbs_enabled = false; |
2219 | } | |
2220 | ||
039ece38 | 2221 | hpriv->start_engine(ap); |
365cfa1e AV |
2222 | } |
2223 | ||
2224 | static void ahci_pmp_attach(struct ata_port *ap) | |
2225 | { | |
2226 | void __iomem *port_mmio = ahci_port_base(ap); | |
2227 | struct ahci_port_priv *pp = ap->private_data; | |
2228 | u32 cmd; | |
2229 | ||
2230 | cmd = readl(port_mmio + PORT_CMD); | |
2231 | cmd |= PORT_CMD_PMP; | |
2232 | writel(cmd, port_mmio + PORT_CMD); | |
2233 | ||
2234 | ahci_enable_fbs(ap); | |
2235 | ||
2236 | pp->intr_mask |= PORT_IRQ_BAD_PMP; | |
7b3a24c5 MB |
2237 | |
2238 | /* | |
2239 | * We must not change the port interrupt mask register if the | |
2240 | * port is marked frozen, the value in pp->intr_mask will be | |
2241 | * restored later when the port is thawed. | |
2242 | * | |
2243 | * Note that during initialization, the port is marked as | |
2244 | * frozen since the irq handler is not yet registered. | |
2245 | */ | |
2246 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) | |
2247 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
365cfa1e AV |
2248 | } |
2249 | ||
2250 | static void ahci_pmp_detach(struct ata_port *ap) | |
2251 | { | |
2252 | void __iomem *port_mmio = ahci_port_base(ap); | |
2253 | struct ahci_port_priv *pp = ap->private_data; | |
2254 | u32 cmd; | |
2255 | ||
2256 | ahci_disable_fbs(ap); | |
2257 | ||
2258 | cmd = readl(port_mmio + PORT_CMD); | |
2259 | cmd &= ~PORT_CMD_PMP; | |
2260 | writel(cmd, port_mmio + PORT_CMD); | |
2261 | ||
2262 | pp->intr_mask &= ~PORT_IRQ_BAD_PMP; | |
7b3a24c5 MB |
2263 | |
2264 | /* see comment above in ahci_pmp_attach() */ | |
2265 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) | |
2266 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
365cfa1e AV |
2267 | } |
2268 | ||
02cdfcf0 | 2269 | int ahci_port_resume(struct ata_port *ap) |
365cfa1e | 2270 | { |
bb03c640 MW |
2271 | ahci_rpm_get_port(ap); |
2272 | ||
365cfa1e AV |
2273 | ahci_power_up(ap); |
2274 | ahci_start_port(ap); | |
2275 | ||
2276 | if (sata_pmp_attached(ap)) | |
2277 | ahci_pmp_attach(ap); | |
2278 | else | |
2279 | ahci_pmp_detach(ap); | |
2280 | ||
2281 | return 0; | |
2282 | } | |
02cdfcf0 | 2283 | EXPORT_SYMBOL_GPL(ahci_port_resume); |
365cfa1e AV |
2284 | |
2285 | #ifdef CONFIG_PM | |
2286 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) | |
2287 | { | |
2288 | const char *emsg = NULL; | |
2289 | int rc; | |
2290 | ||
2291 | rc = ahci_deinit_port(ap, &emsg); | |
2292 | if (rc == 0) | |
2293 | ahci_power_down(ap); | |
2294 | else { | |
a9a79dfe | 2295 | ata_port_err(ap, "%s (%d)\n", emsg, rc); |
7faa33da | 2296 | ata_port_freeze(ap); |
365cfa1e AV |
2297 | } |
2298 | ||
bb03c640 | 2299 | ahci_rpm_put_port(ap); |
365cfa1e AV |
2300 | return rc; |
2301 | } | |
2302 | #endif | |
2303 | ||
2304 | static int ahci_port_start(struct ata_port *ap) | |
2305 | { | |
2306 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
2307 | struct device *dev = ap->host->dev; | |
2308 | struct ahci_port_priv *pp; | |
2309 | void *mem; | |
2310 | dma_addr_t mem_dma; | |
2311 | size_t dma_sz, rx_fis_sz; | |
2312 | ||
2313 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); | |
2314 | if (!pp) | |
2315 | return -ENOMEM; | |
2316 | ||
b29900e6 AG |
2317 | if (ap->host->n_ports > 1) { |
2318 | pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL); | |
2319 | if (!pp->irq_desc) { | |
2320 | devm_kfree(dev, pp); | |
2321 | return -ENOMEM; | |
2322 | } | |
2323 | snprintf(pp->irq_desc, 8, | |
2324 | "%s%d", dev_driver_string(dev), ap->port_no); | |
2325 | } | |
2326 | ||
365cfa1e AV |
2327 | /* check FBS capability */ |
2328 | if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { | |
2329 | void __iomem *port_mmio = ahci_port_base(ap); | |
2330 | u32 cmd = readl(port_mmio + PORT_CMD); | |
2331 | if (cmd & PORT_CMD_FBSCP) | |
2332 | pp->fbs_supported = true; | |
5f173107 | 2333 | else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { |
a44fec1f JP |
2334 | dev_info(dev, "port %d can do FBS, forcing FBSCP\n", |
2335 | ap->port_no); | |
5f173107 TH |
2336 | pp->fbs_supported = true; |
2337 | } else | |
a44fec1f JP |
2338 | dev_warn(dev, "port %d is not capable of FBS\n", |
2339 | ap->port_no); | |
365cfa1e AV |
2340 | } |
2341 | ||
2342 | if (pp->fbs_supported) { | |
2343 | dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; | |
2344 | rx_fis_sz = AHCI_RX_FIS_SZ * 16; | |
2345 | } else { | |
2346 | dma_sz = AHCI_PORT_PRIV_DMA_SZ; | |
2347 | rx_fis_sz = AHCI_RX_FIS_SZ; | |
2348 | } | |
2349 | ||
2350 | mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); | |
2351 | if (!mem) | |
2352 | return -ENOMEM; | |
2353 | memset(mem, 0, dma_sz); | |
2354 | ||
2355 | /* | |
2356 | * First item in chunk of DMA memory: 32-slot command table, | |
2357 | * 32 bytes each in size | |
2358 | */ | |
2359 | pp->cmd_slot = mem; | |
2360 | pp->cmd_slot_dma = mem_dma; | |
2361 | ||
2362 | mem += AHCI_CMD_SLOT_SZ; | |
2363 | mem_dma += AHCI_CMD_SLOT_SZ; | |
2364 | ||
2365 | /* | |
2366 | * Second item: Received-FIS area | |
2367 | */ | |
2368 | pp->rx_fis = mem; | |
2369 | pp->rx_fis_dma = mem_dma; | |
2370 | ||
2371 | mem += rx_fis_sz; | |
2372 | mem_dma += rx_fis_sz; | |
2373 | ||
2374 | /* | |
2375 | * Third item: data area for storing a single command | |
2376 | * and its scatter-gather table | |
2377 | */ | |
2378 | pp->cmd_tbl = mem; | |
2379 | pp->cmd_tbl_dma = mem_dma; | |
2380 | ||
2381 | /* | |
2382 | * Save off initial list of interrupts to be enabled. | |
2383 | * This could be changed later | |
2384 | */ | |
2385 | pp->intr_mask = DEF_PORT_IRQ; | |
2386 | ||
7865f83f TH |
2387 | /* |
2388 | * Switch to per-port locking in case each port has its own MSI vector. | |
2389 | */ | |
0b9e2988 | 2390 | if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { |
7865f83f TH |
2391 | spin_lock_init(&pp->lock); |
2392 | ap->lock = &pp->lock; | |
2393 | } | |
5ca72c4f | 2394 | |
365cfa1e AV |
2395 | ap->private_data = pp; |
2396 | ||
2397 | /* engage engines, captain */ | |
2398 | return ahci_port_resume(ap); | |
2399 | } | |
2400 | ||
2401 | static void ahci_port_stop(struct ata_port *ap) | |
2402 | { | |
2403 | const char *emsg = NULL; | |
0516900a PR |
2404 | struct ahci_host_priv *hpriv = ap->host->private_data; |
2405 | void __iomem *host_mmio = hpriv->mmio; | |
365cfa1e AV |
2406 | int rc; |
2407 | ||
2408 | /* de-initialize port */ | |
2409 | rc = ahci_deinit_port(ap, &emsg); | |
2410 | if (rc) | |
a9a79dfe | 2411 | ata_port_warn(ap, "%s (%d)\n", emsg, rc); |
0516900a PR |
2412 | |
2413 | /* | |
2414 | * Clear GHC.IS to prevent stuck INTx after disabling MSI and | |
2415 | * re-enabling INTx. | |
2416 | */ | |
2417 | writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT); | |
365cfa1e AV |
2418 | } |
2419 | ||
2420 | void ahci_print_info(struct ata_host *host, const char *scc_s) | |
2421 | { | |
2422 | struct ahci_host_priv *hpriv = host->private_data; | |
365cfa1e AV |
2423 | u32 vers, cap, cap2, impl, speed; |
2424 | const char *speed_s; | |
2425 | ||
8ea909cb | 2426 | vers = hpriv->version; |
365cfa1e AV |
2427 | cap = hpriv->cap; |
2428 | cap2 = hpriv->cap2; | |
2429 | impl = hpriv->port_map; | |
2430 | ||
2431 | speed = (cap >> 20) & 0xf; | |
2432 | if (speed == 1) | |
2433 | speed_s = "1.5"; | |
2434 | else if (speed == 2) | |
2435 | speed_s = "3"; | |
2436 | else if (speed == 3) | |
2437 | speed_s = "6"; | |
2438 | else | |
2439 | speed_s = "?"; | |
2440 | ||
2441 | dev_info(host->dev, | |
2442 | "AHCI %02x%02x.%02x%02x " | |
2443 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" | |
2444 | , | |
2445 | ||
2446 | (vers >> 24) & 0xff, | |
2447 | (vers >> 16) & 0xff, | |
2448 | (vers >> 8) & 0xff, | |
2449 | vers & 0xff, | |
2450 | ||
2451 | ((cap >> 8) & 0x1f) + 1, | |
2452 | (cap & 0x1f) + 1, | |
2453 | speed_s, | |
2454 | impl, | |
2455 | scc_s); | |
2456 | ||
2457 | dev_info(host->dev, | |
2458 | "flags: " | |
2459 | "%s%s%s%s%s%s%s" | |
2460 | "%s%s%s%s%s%s%s" | |
65fe1f0f SH |
2461 | "%s%s%s%s%s%s%s" |
2462 | "%s%s\n" | |
365cfa1e AV |
2463 | , |
2464 | ||
2465 | cap & HOST_CAP_64 ? "64bit " : "", | |
2466 | cap & HOST_CAP_NCQ ? "ncq " : "", | |
2467 | cap & HOST_CAP_SNTF ? "sntf " : "", | |
2468 | cap & HOST_CAP_MPS ? "ilck " : "", | |
2469 | cap & HOST_CAP_SSS ? "stag " : "", | |
2470 | cap & HOST_CAP_ALPM ? "pm " : "", | |
2471 | cap & HOST_CAP_LED ? "led " : "", | |
2472 | cap & HOST_CAP_CLO ? "clo " : "", | |
2473 | cap & HOST_CAP_ONLY ? "only " : "", | |
2474 | cap & HOST_CAP_PMP ? "pmp " : "", | |
2475 | cap & HOST_CAP_FBS ? "fbs " : "", | |
2476 | cap & HOST_CAP_PIO_MULTI ? "pio " : "", | |
2477 | cap & HOST_CAP_SSC ? "slum " : "", | |
2478 | cap & HOST_CAP_PART ? "part " : "", | |
2479 | cap & HOST_CAP_CCC ? "ccc " : "", | |
2480 | cap & HOST_CAP_EMS ? "ems " : "", | |
2481 | cap & HOST_CAP_SXS ? "sxs " : "", | |
65fe1f0f SH |
2482 | cap2 & HOST_CAP2_DESO ? "deso " : "", |
2483 | cap2 & HOST_CAP2_SADM ? "sadm " : "", | |
2484 | cap2 & HOST_CAP2_SDS ? "sds " : "", | |
365cfa1e AV |
2485 | cap2 & HOST_CAP2_APST ? "apst " : "", |
2486 | cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "", | |
2487 | cap2 & HOST_CAP2_BOH ? "boh " : "" | |
2488 | ); | |
2489 | } | |
2490 | EXPORT_SYMBOL_GPL(ahci_print_info); | |
2491 | ||
2492 | void ahci_set_em_messages(struct ahci_host_priv *hpriv, | |
2493 | struct ata_port_info *pi) | |
2494 | { | |
2495 | u8 messages; | |
2496 | void __iomem *mmio = hpriv->mmio; | |
2497 | u32 em_loc = readl(mmio + HOST_EM_LOC); | |
2498 | u32 em_ctl = readl(mmio + HOST_EM_CTL); | |
2499 | ||
2500 | if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS)) | |
2501 | return; | |
2502 | ||
2503 | messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; | |
2504 | ||
008dbd61 | 2505 | if (messages) { |
365cfa1e AV |
2506 | /* store em_loc */ |
2507 | hpriv->em_loc = ((em_loc >> 16) * 4); | |
c0623166 | 2508 | hpriv->em_buf_sz = ((em_loc & 0xff) * 4); |
008dbd61 | 2509 | hpriv->em_msg_type = messages; |
365cfa1e AV |
2510 | pi->flags |= ATA_FLAG_EM; |
2511 | if (!(em_ctl & EM_CTL_ALHD)) | |
2512 | pi->flags |= ATA_FLAG_SW_ACTIVITY; | |
2513 | } | |
2514 | } | |
2515 | EXPORT_SYMBOL_GPL(ahci_set_em_messages); | |
2516 | ||
d684a90d | 2517 | static int ahci_host_activate_multi_irqs(struct ata_host *host, |
d1028e2f | 2518 | struct scsi_host_template *sht) |
1c62854f | 2519 | { |
d684a90d | 2520 | struct ahci_host_priv *hpriv = host->private_data; |
1c62854f AG |
2521 | int i, rc; |
2522 | ||
2523 | rc = ata_host_start(host); | |
2524 | if (rc) | |
2525 | return rc; | |
21bfd1aa RR |
2526 | /* |
2527 | * Requests IRQs according to AHCI-1.1 when multiple MSIs were | |
2528 | * allocated. That is one MSI per port, starting from @irq. | |
2529 | */ | |
1c62854f AG |
2530 | for (i = 0; i < host->n_ports; i++) { |
2531 | struct ahci_port_priv *pp = host->ports[i]->private_data; | |
0b9e2988 | 2532 | int irq = hpriv->get_irq_vector(host, i); |
1c62854f AG |
2533 | |
2534 | /* Do not receive interrupts sent by dummy ports */ | |
2535 | if (!pp) { | |
9b4b3f6a | 2536 | disable_irq(irq); |
1c62854f AG |
2537 | continue; |
2538 | } | |
2539 | ||
a6b7fb76 DW |
2540 | rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard, |
2541 | 0, pp->irq_desc, host->ports[i]); | |
2542 | ||
1c62854f | 2543 | if (rc) |
0a142b26 | 2544 | return rc; |
d684a90d | 2545 | ata_port_desc(host->ports[i], "irq %d", irq); |
0a142b26 | 2546 | } |
d684a90d | 2547 | |
0a142b26 | 2548 | return ata_host_register(host, sht); |
1c62854f | 2549 | } |
d1028e2f AG |
2550 | |
2551 | /** | |
2552 | * ahci_host_activate - start AHCI host, request IRQs and register it | |
2553 | * @host: target ATA host | |
d1028e2f AG |
2554 | * @sht: scsi_host_template to use when registering the host |
2555 | * | |
d1028e2f AG |
2556 | * LOCKING: |
2557 | * Inherited from calling layer (may sleep). | |
2558 | * | |
2559 | * RETURNS: | |
2560 | * 0 on success, -errno otherwise. | |
2561 | */ | |
21bfd1aa | 2562 | int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht) |
d1028e2f AG |
2563 | { |
2564 | struct ahci_host_priv *hpriv = host->private_data; | |
21bfd1aa | 2565 | int irq = hpriv->irq; |
d1028e2f AG |
2566 | int rc; |
2567 | ||
0b9e2988 | 2568 | if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { |
f070d671 | 2569 | if (hpriv->irq_handler) |
d991c872 SE |
2570 | dev_warn(host->dev, |
2571 | "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n"); | |
0b9e2988 CH |
2572 | if (!hpriv->get_irq_vector) { |
2573 | dev_err(host->dev, | |
2574 | "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n"); | |
2575 | return -EIO; | |
2576 | } | |
f070d671 | 2577 | |
d684a90d | 2578 | rc = ahci_host_activate_multi_irqs(host, sht); |
f070d671 ST |
2579 | } else { |
2580 | rc = ata_host_activate(host, irq, hpriv->irq_handler, | |
7865f83f | 2581 | IRQF_SHARED, sht); |
f070d671 ST |
2582 | } |
2583 | ||
2584 | ||
d1028e2f AG |
2585 | return rc; |
2586 | } | |
1c62854f AG |
2587 | EXPORT_SYMBOL_GPL(ahci_host_activate); |
2588 | ||
365cfa1e AV |
2589 | MODULE_AUTHOR("Jeff Garzik"); |
2590 | MODULE_DESCRIPTION("Common AHCI SATA low-level routines"); | |
2591 | MODULE_LICENSE("GPL"); |