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Merge branch 'for-linus' of master.kernel.org:/pub/scm/linux/kernel/git/roland/infiniband
[linux-2.6-block.git] / drivers / ata / ata_piix.c
CommitLineData
1da177e4 1/*
af36d7f0
JG		 2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
d96212ed
AC		 40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
2c5ff671 43 * driver the list of errata that are relevant is below, going back to
d96212ed
AC		 44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
1da177e4
LT		 83 */
84
85#include <linux/kernel.h>
86#include <linux/module.h>
87#include <linux/pci.h>
88#include <linux/init.h>
89#include <linux/blkdev.h>
90#include <linux/delay.h>
6248e647 91#include <linux/device.h>
1da177e4
LT		 92#include <scsi/scsi_host.h>
93#include <linux/libata.h>
94
95#define DRV_NAME "ata_piix"
cb48cab7 96#define DRV_VERSION "2.10"
1da177e4
LT		 97
98enum {
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
7b6dbd68 102 PIIX_SCC = 0x0A, /* sub-class code register */
1da177e4 103
d4358048 104 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
ff0fc146
TH		 105 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
106 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
1da177e4 107
800b3996
TH		 108 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
109 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
b3362f88 110
1da177e4
LT		 111 /* combined mode. if set, PATA is channel 0.
112 * if clear, PATA is channel 1.
113 */
6a690df5
HR		 114 PIIX_PORT_ENABLED = (1 << 0),
115 PIIX_PORT_PRESENT = (1 << 4),
1da177e4
LT		 116
117 PIIX_80C_PRI = (1 << 5) | (1 << 4),
118 PIIX_80C_SEC = (1 << 7) | (1 << 6),
119
1d076e5b 120 /* controller IDs */
d2cdfc0d 121 piix_pata_33 = 0, /* PIIX4 at 33Mhz */
669a5db4
JG		 122 ich_pata_33 = 1, /* ICH up to UDMA 33 only */
123 ich_pata_66 = 2, /* ICH up to 66 Mhz */
124 ich_pata_100 = 3, /* ICH up to UDMA 100 */
125 ich_pata_133 = 4, /* ICH up to UDMA 133 */
126 ich5_sata = 5,
5e56a37c
TH		 127 ich6_sata = 6,
128 ich6_sata_ahci = 7,
129 ich6m_sata_ahci = 8,
130 ich8_sata_ahci = 9,
d2cdfc0d 131 piix_pata_mwdma = 10, /* PIIX3 MWDMA only */
85cd7251 132
d33f58b8
TH		 133 /* constants for mapping table */
134 P0 = 0, /* port 0 */
135 P1 = 1, /* port 1 */
136 P2 = 2, /* port 2 */
137 P3 = 3, /* port 3 */
138 IDE = -1, /* IDE */
139 NA = -2, /* not avaliable */
140 RV = -3, /* reserved */
141
7b6dbd68 142 PIIX_AHCI_DEVICE = 6,
1da177e4
LT		 143};
144
d33f58b8
TH		 145struct piix_map_db {
146 const u32 mask;
73291a1c 147 const u16 port_enable;
d33f58b8
TH		 148 const int map[][4];
149};
150
d96715c1
TH		 151struct piix_host_priv {
152 const int *map;
153};
154
1da177e4
LT		 155static int piix_init_one (struct pci_dev *pdev,
156 const struct pci_device_id *ent);
ccc4672a 157static void piix_pata_error_handler(struct ata_port *ap);
669a5db4 158static void ich_pata_error_handler(struct ata_port *ap);
ccc4672a 159static void piix_sata_error_handler(struct ata_port *ap);
669a5db4
JG		 160static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
161static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
162static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev);
1da177e4
LT		 163
164static unsigned int in_module_init = 1;
165
3b7d697d 166static const struct pci_device_id piix_pci_tbl[] = {
d2cdfc0d
A		 167 /* Intel PIIX3 for the 430HX etc */
168 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
669a5db4
JG		 169 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
170 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
171 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
669a5db4
JG		 172 /* Intel PIIX4 */
173 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
174 /* Intel PIIX4 */
175 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
176 /* Intel PIIX */
177 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
178 /* Intel ICH (i810, i815, i840) UDMA 66*/
179 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
180 /* Intel ICH0 : UDMA 33*/
181 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
182 /* Intel ICH2M */
183 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
184 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
185 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
186 /* Intel ICH3M */
187 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
188 /* Intel ICH3 (E7500/1) UDMA 100 */
189 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
190 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
191 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
192 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
193 /* Intel ICH5 */
194 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
195 /* C-ICH (i810E2) */
196 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
85cd7251 197 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
669a5db4
JG		 198 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
199 /* ICH6 (and 6) (i915) UDMA 100 */
200 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* ICH7/7-R (i945, i975) UDMA 100*/
202 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
203 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
1da177e4
LT		 204
205 /* NOTE: The following PCI ids must be kept in sync with the
206 * list in drivers/pci/quirks.c.
207 */
208
1d076e5b 209 /* 82801EB (ICH5) */
1da177e4 210 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 211 /* 82801EB (ICH5) */
1da177e4 212 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 213 /* 6300ESB (ICH5 variant with broken PCS present bits) */
5e56a37c 214 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 215 /* 6300ESB pretending RAID */
5e56a37c 216 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 217 /* 82801FB/FW (ICH6/ICH6W) */
1da177e4 218 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
1d076e5b 219 /* 82801FR/FRW (ICH6R/ICH6RW) */
1c24a412 220 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 221 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
222 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
223 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
1c24a412 224 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 225 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
c6446a4c 226 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
f98b6573 227 /* Enterprise Southbridge 2 (631xESB/632xESB) */
1c24a412 228 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
f98b6573 229 /* SATA Controller 1 IDE (ICH8) */
08f12edc 230 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
f98b6573 231 /* SATA Controller 2 IDE (ICH8) */
08f12edc 232 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
f98b6573 233 /* Mobile SATA Controller IDE (ICH8M) */
08f12edc 234 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
f98b6573
JG		 235 /* SATA Controller IDE (ICH9) */
236 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
237 /* SATA Controller IDE (ICH9) */
238 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
239 /* SATA Controller IDE (ICH9) */
240 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
241 /* SATA Controller IDE (ICH9M) */
242 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
243 /* SATA Controller IDE (ICH9M) */
244 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
245 /* SATA Controller IDE (ICH9M) */
246 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
1da177e4
LT		 247
248 { } /* terminate list */
249};
250
251static struct pci_driver piix_pci_driver = {
252 .name = DRV_NAME,
253 .id_table = piix_pci_tbl,
254 .probe = piix_init_one,
255 .remove = ata_pci_remove_one,
438ac6d5 256#ifdef CONFIG_PM
9b847548
JA		 257 .suspend = ata_pci_device_suspend,
258 .resume = ata_pci_device_resume,
438ac6d5 259#endif
1da177e4
LT		 260};
261
193515d5 262static struct scsi_host_template piix_sht = {
1da177e4
LT		 263 .module = THIS_MODULE,
264 .name = DRV_NAME,
265 .ioctl = ata_scsi_ioctl,
266 .queuecommand = ata_scsi_queuecmd,
1da177e4
LT		 267 .can_queue = ATA_DEF_QUEUE,
268 .this_id = ATA_SHT_THIS_ID,
269 .sg_tablesize = LIBATA_MAX_PRD,
1da177e4
LT		 270 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
271 .emulated = ATA_SHT_EMULATED,
272 .use_clustering = ATA_SHT_USE_CLUSTERING,
273 .proc_name = DRV_NAME,
274 .dma_boundary = ATA_DMA_BOUNDARY,
275 .slave_configure = ata_scsi_slave_config,
ccf68c34 276 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 277 .bios_param = ata_std_bios_param,
438ac6d5 278#ifdef CONFIG_PM
9b847548
JA		 279 .resume = ata_scsi_device_resume,
280 .suspend = ata_scsi_device_suspend,
438ac6d5 281#endif
1da177e4
LT		 282};
283
057ace5e 284static const struct ata_port_operations piix_pata_ops = {
1da177e4
LT		 285 .port_disable = ata_port_disable,
286 .set_piomode = piix_set_piomode,
287 .set_dmamode = piix_set_dmamode,
89bad589 288 .mode_filter = ata_pci_default_filter,
1da177e4
LT		 289
290 .tf_load = ata_tf_load,
291 .tf_read = ata_tf_read,
292 .check_status = ata_check_status,
293 .exec_command = ata_exec_command,
294 .dev_select = ata_std_dev_select,
295
1da177e4
LT		 296 .bmdma_setup = ata_bmdma_setup,
297 .bmdma_start = ata_bmdma_start,
298 .bmdma_stop = ata_bmdma_stop,
299 .bmdma_status = ata_bmdma_status,
300 .qc_prep = ata_qc_prep,
301 .qc_issue = ata_qc_issue_prot,
0d5ff566 302 .data_xfer = ata_data_xfer,
1da177e4 303
3f037db0
TH		 304 .freeze = ata_bmdma_freeze,
305 .thaw = ata_bmdma_thaw,
ccc4672a 306 .error_handler = piix_pata_error_handler,
3f037db0 307 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4
LT		 308
309 .irq_handler = ata_interrupt,
310 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 311 .irq_on = ata_irq_on,
312 .irq_ack = ata_irq_ack,
1da177e4
LT		 313
314 .port_start = ata_port_start,
1da177e4
LT		 315};
316
669a5db4
JG		 317static const struct ata_port_operations ich_pata_ops = {
318 .port_disable = ata_port_disable,
319 .set_piomode = piix_set_piomode,
320 .set_dmamode = ich_set_dmamode,
321 .mode_filter = ata_pci_default_filter,
322
323 .tf_load = ata_tf_load,
324 .tf_read = ata_tf_read,
325 .check_status = ata_check_status,
326 .exec_command = ata_exec_command,
327 .dev_select = ata_std_dev_select,
328
329 .bmdma_setup = ata_bmdma_setup,
330 .bmdma_start = ata_bmdma_start,
331 .bmdma_stop = ata_bmdma_stop,
332 .bmdma_status = ata_bmdma_status,
333 .qc_prep = ata_qc_prep,
334 .qc_issue = ata_qc_issue_prot,
0d5ff566 335 .data_xfer = ata_data_xfer,
669a5db4
JG		 336
337 .freeze = ata_bmdma_freeze,
338 .thaw = ata_bmdma_thaw,
339 .error_handler = ich_pata_error_handler,
340 .post_internal_cmd = ata_bmdma_post_internal_cmd,
341
342 .irq_handler = ata_interrupt,
343 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 344 .irq_on = ata_irq_on,
345 .irq_ack = ata_irq_ack,
669a5db4
JG		 346
347 .port_start = ata_port_start,
669a5db4
JG		 348};
349
057ace5e 350static const struct ata_port_operations piix_sata_ops = {
1da177e4
LT		 351 .port_disable = ata_port_disable,
352
353 .tf_load = ata_tf_load,
354 .tf_read = ata_tf_read,
355 .check_status = ata_check_status,
356 .exec_command = ata_exec_command,
357 .dev_select = ata_std_dev_select,
358
1da177e4
LT		 359 .bmdma_setup = ata_bmdma_setup,
360 .bmdma_start = ata_bmdma_start,
361 .bmdma_stop = ata_bmdma_stop,
362 .bmdma_status = ata_bmdma_status,
363 .qc_prep = ata_qc_prep,
364 .qc_issue = ata_qc_issue_prot,
0d5ff566 365 .data_xfer = ata_data_xfer,
1da177e4 366
3f037db0
TH		 367 .freeze = ata_bmdma_freeze,
368 .thaw = ata_bmdma_thaw,
ccc4672a 369 .error_handler = piix_sata_error_handler,
3f037db0 370 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4
LT		 371
372 .irq_handler = ata_interrupt,
373 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 374 .irq_on = ata_irq_on,
375 .irq_ack = ata_irq_ack,
1da177e4
LT		 376
377 .port_start = ata_port_start,
1da177e4
LT		 378};
379
d96715c1 380static const struct piix_map_db ich5_map_db = {
d33f58b8 381 .mask = 0x7,
ea35d29e 382 .port_enable = 0x3,
d33f58b8
TH		 383 .map = {
384 /* PM PS SM SS MAP */
385 { P0, NA, P1, NA }, /* 000b */
386 { P1, NA, P0, NA }, /* 001b */
387 { RV, RV, RV, RV },
388 { RV, RV, RV, RV },
389 { P0, P1, IDE, IDE }, /* 100b */
390 { P1, P0, IDE, IDE }, /* 101b */
391 { IDE, IDE, P0, P1 }, /* 110b */
392 { IDE, IDE, P1, P0 }, /* 111b */
393 },
394};
395
d96715c1 396static const struct piix_map_db ich6_map_db = {
d33f58b8 397 .mask = 0x3,
ea35d29e 398 .port_enable = 0xf,
d33f58b8
TH		 399 .map = {
400 /* PM PS SM SS MAP */
79ea24e7 401 { P0, P2, P1, P3 }, /* 00b */
d33f58b8
TH		 402 { IDE, IDE, P1, P3 }, /* 01b */
403 { P0, P2, IDE, IDE }, /* 10b */
404 { RV, RV, RV, RV },
405 },
406};
407
d96715c1 408static const struct piix_map_db ich6m_map_db = {
d33f58b8 409 .mask = 0x3,
ea35d29e 410 .port_enable = 0x5,
67083741
TH		 411
412 /* Map 01b isn't specified in the doc but some notebooks use
c6446a4c
TH		 413 * it anyway. MAP 01b have been spotted on both ICH6M and
414 * ICH7M.
67083741
TH		 415 */
416 .map = {
417 /* PM PS SM SS MAP */
418 { P0, P2, RV, RV }, /* 00b */
419 { IDE, IDE, P1, P3 }, /* 01b */
420 { P0, P2, IDE, IDE }, /* 10b */
421 { RV, RV, RV, RV },
422 },
423};
424
08f12edc
JG		 425static const struct piix_map_db ich8_map_db = {
426 .mask = 0x3,
427 .port_enable = 0x3,
08f12edc
JG		 428 .map = {
429 /* PM PS SM SS MAP */
158f30c8 430 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
08f12edc 431 { RV, RV, RV, RV },
158f30c8 432 { IDE, IDE, NA, NA }, /* 10b (IDE mode) */
08f12edc
JG		 433 { RV, RV, RV, RV },
434 },
435};
436
d96715c1
TH		 437static const struct piix_map_db *piix_map_db_table[] = {
438 [ich5_sata] = &ich5_map_db,
d96715c1
TH		 439 [ich6_sata] = &ich6_map_db,
440 [ich6_sata_ahci] = &ich6_map_db,
441 [ich6m_sata_ahci] = &ich6m_map_db,
08f12edc 442 [ich8_sata_ahci] = &ich8_map_db,
d96715c1
TH		 443};
444
1da177e4 445static struct ata_port_info piix_port_info[] = {
d2cdfc0d 446 /* piix_pata_33: 0: PIIX4 at 33MHz */
1d076e5b
TH		 447 {
448 .sht = &piix_sht,
b3362f88 449 .flags = PIIX_PATA_FLAGS,
1d076e5b 450 .pio_mask = 0x1f, /* pio0-4 */
669a5db4 451 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1d076e5b
TH		 452 .udma_mask = ATA_UDMA_MASK_40C,
453 .port_ops = &piix_pata_ops,
454 },
455
669a5db4
JG		 456 /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/
457 {
458 .sht = &piix_sht,
b3362f88 459 .flags = PIIX_PATA_FLAGS,
669a5db4
JG		 460 .pio_mask = 0x1f, /* pio 0-4 */
461 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
462 .udma_mask = ATA_UDMA2, /* UDMA33 */
463 .port_ops = &ich_pata_ops,
464 },
465 /* ich_pata_66: 2 ICH controllers up to 66MHz */
1da177e4
LT		 466 {
467 .sht = &piix_sht,
b3362f88 468 .flags = PIIX_PATA_FLAGS,
669a5db4
JG		 469 .pio_mask = 0x1f, /* pio 0-4 */
470 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
471 .udma_mask = ATA_UDMA4,
472 .port_ops = &ich_pata_ops,
473 },
85cd7251 474
669a5db4
JG		 475 /* ich_pata_100: 3 */
476 {
477 .sht = &piix_sht,
b3362f88 478 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1da177e4 479 .pio_mask = 0x1f, /* pio0-4 */
1da177e4 480 .mwdma_mask = 0x06, /* mwdma1-2 */
669a5db4
JG		 481 .udma_mask = ATA_UDMA5, /* udma0-5 */
482 .port_ops = &ich_pata_ops,
1da177e4
LT		 483 },
484
669a5db4
JG		 485 /* ich_pata_133: 4 ICH with full UDMA6 */
486 {
487 .sht = &piix_sht,
b3362f88 488 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
669a5db4
JG		 489 .pio_mask = 0x1f, /* pio 0-4 */
490 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
491 .udma_mask = ATA_UDMA6, /* UDMA133 */
492 .port_ops = &ich_pata_ops,
493 },
494
495 /* ich5_sata: 5 */
1da177e4
LT		 496 {
497 .sht = &piix_sht,
228c1590 498 .flags = PIIX_SATA_FLAGS,
1da177e4
LT		 499 .pio_mask = 0x1f, /* pio0-4 */
500 .mwdma_mask = 0x07, /* mwdma0-2 */
501 .udma_mask = 0x7f, /* udma0-6 */
502 .port_ops = &piix_sata_ops,
503 },
504
5e56a37c 505 /* ich6_sata: 6 */
1da177e4
LT		 506 {
507 .sht = &piix_sht,
b3362f88 508 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
1da177e4
LT		 509 .pio_mask = 0x1f, /* pio0-4 */
510 .mwdma_mask = 0x07, /* mwdma0-2 */
511 .udma_mask = 0x7f, /* udma0-6 */
512 .port_ops = &piix_sata_ops,
513 },
514
5e56a37c 515 /* ich6_sata_ahci: 7 */
c368ca4e
JG		 516 {
517 .sht = &piix_sht,
b3362f88 518 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
d33f58b8 519 PIIX_FLAG_AHCI,
c368ca4e
JG		 520 .pio_mask = 0x1f, /* pio0-4 */
521 .mwdma_mask = 0x07, /* mwdma0-2 */
522 .udma_mask = 0x7f, /* udma0-6 */
523 .port_ops = &piix_sata_ops,
524 },
1d076e5b 525
5e56a37c 526 /* ich6m_sata_ahci: 8 */
1d076e5b
TH		 527 {
528 .sht = &piix_sht,
b3362f88 529 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
d33f58b8 530 PIIX_FLAG_AHCI,
1d076e5b
TH		 531 .pio_mask = 0x1f, /* pio0-4 */
532 .mwdma_mask = 0x07, /* mwdma0-2 */
533 .udma_mask = 0x7f, /* udma0-6 */
534 .port_ops = &piix_sata_ops,
535 },
08f12edc 536
5e56a37c 537 /* ich8_sata_ahci: 9 */
08f12edc
JG		 538 {
539 .sht = &piix_sht,
b3362f88 540 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
08f12edc
JG		 541 PIIX_FLAG_AHCI,
542 .pio_mask = 0x1f, /* pio0-4 */
543 .mwdma_mask = 0x07, /* mwdma0-2 */
544 .udma_mask = 0x7f, /* udma0-6 */
545 .port_ops = &piix_sata_ops,
546 },
669a5db4 547
d2cdfc0d
A		 548 /* piix_pata_mwdma: 10: PIIX3 MWDMA only */
549 {
550 .sht = &piix_sht,
551 .flags = PIIX_PATA_FLAGS,
552 .pio_mask = 0x1f, /* pio0-4 */
553 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
554 .port_ops = &piix_pata_ops,
555 },
1da177e4
LT		 556};
557
558static struct pci_bits piix_enable_bits[] = {
559 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
560 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
561};
562
563MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
564MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
565MODULE_LICENSE("GPL");
566MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
567MODULE_VERSION(DRV_VERSION);
568
fc085150
AC		 569struct ich_laptop {
570 u16 device;
571 u16 subvendor;
572 u16 subdevice;
573};
574
575/*
576 * List of laptops that use short cables rather than 80 wire
577 */
578
579static const struct ich_laptop ich_laptop[] = {
580 /* devid, subvendor, subdev */
581 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
babfb682 582 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
fc085150
AC		 583 /* end marker */
584 { 0, }
585};
586
1da177e4
LT		 587/**
588 * piix_pata_cbl_detect - Probe host controller cable detect info
589 * @ap: Port for which cable detect info is desired
590 *
591 * Read 80c cable indicator from ATA PCI device's PCI config
592 * register. This register is normally set by firmware (BIOS).
593 *
594 * LOCKING:
595 * None (inherited from caller).
596 */
669a5db4
JG		 597
598static void ich_pata_cbl_detect(struct ata_port *ap)
1da177e4 599{
cca3974e 600 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
fc085150 601 const struct ich_laptop *lap = &ich_laptop[0];
1da177e4
LT		 602 u8 tmp, mask;
603
604 /* no 80c support in host controller? */
605 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
606 goto cbl40;
607
fc085150
AC		 608 /* Check for specials - Acer Aspire 5602WLMi */
609 while (lap->device) {
610 if (lap->device == pdev->device &&
611 lap->subvendor == pdev->subsystem_vendor &&
612 lap->subdevice == pdev->subsystem_device) {
613 ap->cbl = ATA_CBL_PATA40_SHORT;
614 return;
615 }
616 lap++;
617 }
618
1da177e4 619 /* check BIOS cable detect results */
2a88d1ac 620 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
1da177e4
LT		 621 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
622 if ((tmp & mask) == 0)
623 goto cbl40;
624
625 ap->cbl = ATA_CBL_PATA80;
626 return;
627
628cbl40:
629 ap->cbl = ATA_CBL_PATA40;
1da177e4
LT		 630}
631
632/**
ccc4672a 633 * piix_pata_prereset - prereset for PATA host controller
573db6b8 634 * @ap: Target port
1da177e4 635 *
573db6b8
TH		 636 *
637 * LOCKING:
638 * None (inherited from caller).
639 */
ccc4672a 640static int piix_pata_prereset(struct ata_port *ap)
1da177e4 641{
cca3974e 642 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1da177e4 643
c961922b
AC		 644 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
645 return -ENOENT;
f20b16ff 646
669a5db4 647 ap->cbl = ATA_CBL_PATA40;
ccc4672a
TH		 648 return ata_std_prereset(ap);
649}
650
651static void piix_pata_error_handler(struct ata_port *ap)
652{
653 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
654 ata_std_postreset);
1da177e4
LT		 655}
656
669a5db4
JG		 657
658/**
659 * ich_pata_prereset - prereset for PATA host controller
660 * @ap: Target port
661 *
662 *
663 * LOCKING:
664 * None (inherited from caller).
665 */
666static int ich_pata_prereset(struct ata_port *ap)
667{
668 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
669
670 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) {
671 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n");
672 ap->eh_context.i.action &= ~ATA_EH_RESET_MASK;
673 return 0;
674 }
675
676 ich_pata_cbl_detect(ap);
677
678 return ata_std_prereset(ap);
679}
680
681static void ich_pata_error_handler(struct ata_port *ap)
682{
683 ata_bmdma_drive_eh(ap, ich_pata_prereset, ata_std_softreset, NULL,
684 ata_std_postreset);
685}
686
ccc4672a
TH		 687static void piix_sata_error_handler(struct ata_port *ap)
688{
228c1590 689 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, NULL,
ccc4672a 690 ata_std_postreset);
1da177e4
LT		 691}
692
693/**
694 * piix_set_piomode - Initialize host controller PATA PIO timings
695 * @ap: Port whose timings we are configuring
696 * @adev: um
1da177e4
LT		 697 *
698 * Set PIO mode for device, in host controller PCI config space.
699 *
700 * LOCKING:
701 * None (inherited from caller).
702 */
703
704static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
705{
706 unsigned int pio = adev->pio_mode - XFER_PIO_0;
cca3974e 707 struct pci_dev *dev = to_pci_dev(ap->host->dev);
1da177e4 708 unsigned int is_slave = (adev->devno != 0);
2a88d1ac 709 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
1da177e4
LT		 710 unsigned int slave_port = 0x44;
711 u16 master_data;
712 u8 slave_data;
669a5db4
JG		 713 u8 udma_enable;
714 int control = 0;
85cd7251 715
669a5db4
JG		 716 /*
717 * See Intel Document 298600-004 for the timing programing rules
718 * for ICH controllers.
719 */
1da177e4
LT		 720
721 static const /* ISP RTC */
722 u8 timings[][2] = { { 0, 0 },
723 { 0, 0 },
724 { 1, 0 },
725 { 2, 1 },
726 { 2, 3 }, };
727
669a5db4
JG		 728 if (pio >= 2)
729 control |= 1; /* TIME1 enable */
730 if (ata_pio_need_iordy(adev))
731 control |= 2; /* IE enable */
732
85cd7251 733 /* Intel specifies that the PPE functionality is for disk only */
669a5db4
JG		 734 if (adev->class == ATA_DEV_ATA)
735 control |= 4; /* PPE enable */
736
1da177e4
LT		 737 pci_read_config_word(dev, master_port, &master_data);
738 if (is_slave) {
669a5db4 739 /* Enable SITRE (seperate slave timing register) */
1da177e4 740 master_data |= 0x4000;
669a5db4
JG		 741 /* enable PPE1, IE1 and TIME1 as needed */
742 master_data |= (control << 4);
1da177e4 743 pci_read_config_byte(dev, slave_port, &slave_data);
2a88d1ac 744 slave_data &= (ap->port_no ? 0x0f : 0xf0);
669a5db4
JG		 745 /* Load the timing nibble for this slave */
746 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
1da177e4 747 } else {
669a5db4 748 /* Master keeps the bits in a different format */
1da177e4 749 master_data &= 0xccf8;
669a5db4
JG		 750 /* Enable PPE, IE and TIME as appropriate */
751 master_data |= control;
1da177e4
LT		 752 master_data |=
753 (timings[pio][0] << 12) |
754 (timings[pio][1] << 8);
755 }
756 pci_write_config_word(dev, master_port, master_data);
757 if (is_slave)
758 pci_write_config_byte(dev, slave_port, slave_data);
669a5db4
JG		 759
760 /* Ensure the UDMA bit is off - it will be turned back on if
761 UDMA is selected */
85cd7251 762
669a5db4
JG		 763 if (ap->udma_mask) {
764 pci_read_config_byte(dev, 0x48, &udma_enable);
765 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
766 pci_write_config_byte(dev, 0x48, udma_enable);
767 }
1da177e4
LT		 768}
769
770/**
669a5db4 771 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
1da177e4 772 * @ap: Port whose timings we are configuring
669a5db4 773 * @adev: Drive in question
1da177e4 774 * @udma: udma mode, 0 - 6
c32a8fd7 775 * @isich: set if the chip is an ICH device
1da177e4
LT		 776 *
777 * Set UDMA mode for device, in host controller PCI config space.
778 *
779 * LOCKING:
780 * None (inherited from caller).
781 */
782
669a5db4 783static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich)
1da177e4 784{
cca3974e 785 struct pci_dev *dev = to_pci_dev(ap->host->dev);
669a5db4
JG		 786 u8 master_port = ap->port_no ? 0x42 : 0x40;
787 u16 master_data;
788 u8 speed = adev->dma_mode;
789 int devid = adev->devno + 2 * ap->port_no;
dedf61db 790 u8 udma_enable = 0;
85cd7251 791
669a5db4
JG		 792 static const /* ISP RTC */
793 u8 timings[][2] = { { 0, 0 },
794 { 0, 0 },
795 { 1, 0 },
796 { 2, 1 },
797 { 2, 3 }, };
798
799 pci_read_config_word(dev, master_port, &master_data);
d2cdfc0d
A		 800 if (ap->udma_mask)
801 pci_read_config_byte(dev, 0x48, &udma_enable);
1da177e4
LT		 802
803 if (speed >= XFER_UDMA_0) {
669a5db4
JG		 804 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
805 u16 udma_timing;
806 u16 ideconf;
807 int u_clock, u_speed;
85cd7251 808
669a5db4
JG		 809 /*
810 * UDMA is handled by a combination of clock switching and
85cd7251
JG		 811 * selection of dividers
812 *
669a5db4 813 * Handy rule: Odd modes are UDMATIMx 01, even are 02
85cd7251 814 * except UDMA0 which is 00
669a5db4
JG		 815 */
816 u_speed = min(2 - (udma & 1), udma);
817 if (udma == 5)
818 u_clock = 0x1000; /* 100Mhz */
819 else if (udma > 2)
820 u_clock = 1; /* 66Mhz */
821 else
822 u_clock = 0; /* 33Mhz */
85cd7251 823
669a5db4 824 udma_enable |= (1 << devid);
85cd7251 825
669a5db4
JG		 826 /* Load the CT/RP selection */
827 pci_read_config_word(dev, 0x4A, &udma_timing);
828 udma_timing &= ~(3 << (4 * devid));
829 udma_timing |= u_speed << (4 * devid);
830 pci_write_config_word(dev, 0x4A, udma_timing);
831
85cd7251 832 if (isich) {
669a5db4
JG		 833 /* Select a 33/66/100Mhz clock */
834 pci_read_config_word(dev, 0x54, &ideconf);
835 ideconf &= ~(0x1001 << devid);
836 ideconf |= u_clock << devid;
837 /* For ICH or later we should set bit 10 for better
838 performance (WR_PingPong_En) */
839 pci_write_config_word(dev, 0x54, ideconf);
1da177e4 840 }
1da177e4 841 } else {
669a5db4
JG		 842 /*
843 * MWDMA is driven by the PIO timings. We must also enable
844 * IORDY unconditionally along with TIME1. PPE has already
845 * been set when the PIO timing was set.
846 */
847 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
848 unsigned int control;
849 u8 slave_data;
850 const unsigned int needed_pio[3] = {
851 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
852 };
853 int pio = needed_pio[mwdma] - XFER_PIO_0;
85cd7251 854
669a5db4 855 control = 3; /* IORDY|TIME1 */
85cd7251 856
669a5db4
JG		 857 /* If the drive MWDMA is faster than it can do PIO then
858 we must force PIO into PIO0 */
85cd7251 859
669a5db4
JG		 860 if (adev->pio_mode < needed_pio[mwdma])
861 /* Enable DMA timing only */
862 control |= 8; /* PIO cycles in PIO0 */
863
864 if (adev->devno) { /* Slave */
865 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
866 master_data |= control << 4;
867 pci_read_config_byte(dev, 0x44, &slave_data);
868 slave_data &= (0x0F + 0xE1 * ap->port_no);
869 /* Load the matching timing */
870 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
871 pci_write_config_byte(dev, 0x44, slave_data);
872 } else { /* Master */
85cd7251 873 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
669a5db4
JG		 874 and master timing bits */
875 master_data |= control;
876 master_data |=
877 (timings[pio][0] << 12) |
878 (timings[pio][1] << 8);
879 }
880 udma_enable &= ~(1 << devid);
881 pci_write_config_word(dev, master_port, master_data);
1da177e4 882 }
669a5db4
JG		 883 /* Don't scribble on 0x48 if the controller does not support UDMA */
884 if (ap->udma_mask)
885 pci_write_config_byte(dev, 0x48, udma_enable);
886}
887
888/**
889 * piix_set_dmamode - Initialize host controller PATA DMA timings
890 * @ap: Port whose timings we are configuring
891 * @adev: um
892 *
893 * Set MW/UDMA mode for device, in host controller PCI config space.
894 *
895 * LOCKING:
896 * None (inherited from caller).
897 */
898
899static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
900{
901 do_pata_set_dmamode(ap, adev, 0);
902}
903
904/**
905 * ich_set_dmamode - Initialize host controller PATA DMA timings
906 * @ap: Port whose timings we are configuring
907 * @adev: um
908 *
909 * Set MW/UDMA mode for device, in host controller PCI config space.
910 *
911 * LOCKING:
912 * None (inherited from caller).
913 */
914
915static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev)
916{
917 do_pata_set_dmamode(ap, adev, 1);
1da177e4
LT		 918}
919
1da177e4
LT		 920#define AHCI_PCI_BAR 5
921#define AHCI_GLOBAL_CTL 0x04
922#define AHCI_ENABLE (1 << 31)
923static int piix_disable_ahci(struct pci_dev *pdev)
924{
ea6ba10b 925 void __iomem *mmio;
1da177e4
LT		 926 u32 tmp;
927 int rc = 0;
928
929 /* BUG: pci_enable_device has not yet been called. This
930 * works because this device is usually set up by BIOS.
931 */
932
374b1873
JG		 933 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
934 !pci_resource_len(pdev, AHCI_PCI_BAR))
1da177e4 935 return 0;
7b6dbd68 936
374b1873 937 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1da177e4
LT		 938 if (!mmio)
939 return -ENOMEM;
7b6dbd68 940
1da177e4
LT		 941 tmp = readl(mmio + AHCI_GLOBAL_CTL);
942 if (tmp & AHCI_ENABLE) {
943 tmp &= ~AHCI_ENABLE;
944 writel(tmp, mmio + AHCI_GLOBAL_CTL);
945
946 tmp = readl(mmio + AHCI_GLOBAL_CTL);
947 if (tmp & AHCI_ENABLE)
948 rc = -EIO;
949 }
7b6dbd68 950
374b1873 951 pci_iounmap(pdev, mmio);
1da177e4
LT		 952 return rc;
953}
954
c621b140
AC		 955/**
956 * piix_check_450nx_errata - Check for problem 450NX setup
c893a3ae 957 * @ata_dev: the PCI device to check
2e9edbf8 958 *
c621b140
AC		 959 * Check for the present of 450NX errata #19 and errata #25. If
960 * they are found return an error code so we can turn off DMA
961 */
962
963static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
964{
965 struct pci_dev *pdev = NULL;
966 u16 cfg;
967 u8 rev;
968 int no_piix_dma = 0;
2e9edbf8 969
c621b140
AC		 970 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
971 {
972 /* Look for 450NX PXB. Check for problem configurations
973 A PCI quirk checks bit 6 already */
974 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
975 pci_read_config_word(pdev, 0x41, &cfg);
976 /* Only on the original revision: IDE DMA can hang */
31a34fe7 977 if (rev == 0x00)
c621b140
AC		 978 no_piix_dma = 1;
979 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
31a34fe7 980 else if (cfg & (1<<14) && rev < 5)
c621b140
AC		 981 no_piix_dma = 2;
982 }
31a34fe7 983 if (no_piix_dma)
c621b140 984 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
31a34fe7 985 if (no_piix_dma == 2)
c621b140
AC		 986 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
987 return no_piix_dma;
2e9edbf8 988}
c621b140 989
ea35d29e 990static void __devinit piix_init_pcs(struct pci_dev *pdev,
9dd9c164 991 struct ata_port_info *pinfo,
ea35d29e
JG		 992 const struct piix_map_db *map_db)
993{
994 u16 pcs, new_pcs;
995
996 pci_read_config_word(pdev, ICH5_PCS, &pcs);
997
998 new_pcs = pcs | map_db->port_enable;
999
1000 if (new_pcs != pcs) {
1001 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1002 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1003 msleep(150);
1004 }
1005}
1006
d33f58b8 1007static void __devinit piix_init_sata_map(struct pci_dev *pdev,
d96715c1
TH		 1008 struct ata_port_info *pinfo,
1009 const struct piix_map_db *map_db)
d33f58b8 1010{
d96715c1 1011 struct piix_host_priv *hpriv = pinfo[0].private_data;
d33f58b8
TH		 1012 const unsigned int *map;
1013 int i, invalid_map = 0;
1014 u8 map_value;
1015
1016 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1017
1018 map = map_db->map[map_value & map_db->mask];
1019
1020 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1021 for (i = 0; i < 4; i++) {
1022 switch (map[i]) {
1023 case RV:
1024 invalid_map = 1;
1025 printk(" XX");
1026 break;
1027
1028 case NA:
1029 printk(" --");
1030 break;
1031
1032 case IDE:
1033 WARN_ON((i & 1) || map[i + 1] != IDE);
669a5db4 1034 pinfo[i / 2] = piix_port_info[ich_pata_100];
f814b75f 1035 pinfo[i / 2].private_data = hpriv;
d33f58b8
TH		 1036 i++;
1037 printk(" IDE IDE");
1038 break;
1039
1040 default:
1041 printk(" P%d", map[i]);
1042 if (i & 1)
cca3974e 1043 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
d33f58b8
TH		 1044 break;
1045 }
1046 }
1047 printk(" ]\n");
1048
1049 if (invalid_map)
1050 dev_printk(KERN_ERR, &pdev->dev,
1051 "invalid MAP value %u\n", map_value);
1052
d96715c1 1053 hpriv->map = map;
d33f58b8
TH		 1054}
1055
1da177e4
LT		 1056/**
1057 * piix_init_one - Register PIIX ATA PCI device with kernel services
1058 * @pdev: PCI device to register
1059 * @ent: Entry in piix_pci_tbl matching with @pdev
1060 *
1061 * Called from kernel PCI layer. We probe for combined mode (sigh),
1062 * and then hand over control to libata, for it to do the rest.
1063 *
1064 * LOCKING:
1065 * Inherited from PCI layer (may sleep).
1066 *
1067 * RETURNS:
1068 * Zero on success, or -ERRNO value.
1069 */
1070
1071static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1072{
1073 static int printed_version;
24dc5f33 1074 struct device *dev = &pdev->dev;
d33f58b8
TH		 1075 struct ata_port_info port_info[2];
1076 struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] };
d96715c1 1077 struct piix_host_priv *hpriv;
cca3974e 1078 unsigned long port_flags;
1da177e4
LT		 1079
1080 if (!printed_version++)
6248e647
JG		 1081 dev_printk(KERN_DEBUG, &pdev->dev,
1082 "version " DRV_VERSION "\n");
1da177e4
LT		 1083
1084 /* no hotplugging support (FIXME) */
1085 if (!in_module_init)
1086 return -ENODEV;
1087
24dc5f33 1088 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
d96715c1
TH		 1089 if (!hpriv)
1090 return -ENOMEM;
1091
d33f58b8
TH		 1092 port_info[0] = piix_port_info[ent->driver_data];
1093 port_info[1] = piix_port_info[ent->driver_data];
d96715c1
TH		 1094 port_info[0].private_data = hpriv;
1095 port_info[1].private_data = hpriv;
1da177e4 1096
cca3974e 1097 port_flags = port_info[0].flags;
ff0fc146 1098
cca3974e 1099 if (port_flags & PIIX_FLAG_AHCI) {
8a60a071
JG		 1100 u8 tmp;
1101 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1102 if (tmp == PIIX_AHCI_DEVICE) {
1103 int rc = piix_disable_ahci(pdev);
1104 if (rc)
1105 return rc;
1106 }
1da177e4
LT		 1107 }
1108
d33f58b8 1109 /* Initialize SATA map */
cca3974e 1110 if (port_flags & ATA_FLAG_SATA) {
d96715c1
TH		 1111 piix_init_sata_map(pdev, port_info,
1112 piix_map_db_table[ent->driver_data]);
9dd9c164
TH		 1113 piix_init_pcs(pdev, port_info,
1114 piix_map_db_table[ent->driver_data]);
ea35d29e 1115 }
1da177e4
LT		 1116
1117 /* On ICH5, some BIOSen disable the interrupt using the
1118 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1119 * On ICH6, this bit has the same effect, but only when
1120 * MSI is disabled (and it is disabled, as we don't use
1121 * message-signalled interrupts currently).
1122 */
cca3974e 1123 if (port_flags & PIIX_FLAG_CHECKINTR)
a04ce0ff 1124 pci_intx(pdev, 1);
1da177e4 1125
c621b140
AC		 1126 if (piix_check_450nx_errata(pdev)) {
1127 /* This writes into the master table but it does not
1128 really matter for this errata as we will apply it to
1129 all the PIIX devices on the board */
d33f58b8
TH		 1130 port_info[0].mwdma_mask = 0;
1131 port_info[0].udma_mask = 0;
1132 port_info[1].mwdma_mask = 0;
1133 port_info[1].udma_mask = 0;
c621b140 1134 }
d33f58b8 1135 return ata_pci_init_one(pdev, ppinfo, 2);
1da177e4
LT		 1136}
1137
1da177e4
LT		 1138static int __init piix_init(void)
1139{
1140 int rc;
1141
b7887196
PR		 1142 DPRINTK("pci_register_driver\n");
1143 rc = pci_register_driver(&piix_pci_driver);
1da177e4
LT		 1144 if (rc)
1145 return rc;
1146
1147 in_module_init = 0;
1148
1149 DPRINTK("done\n");
1150 return 0;
1151}
1152
1da177e4
LT		 1153static void __exit piix_exit(void)
1154{
1155 pci_unregister_driver(&piix_pci_driver);
1156}
1157
1158module_init(piix_init);
1159module_exit(piix_exit);
Linux 6.x block layer and io_uring tree(s)