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libata: normalize port_info, port_operations and sht tables
[linux-2.6-block.git] / drivers / ata / ata_piix.c
CommitLineData
1da177e4 1/*
af36d7f0
JG		 2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
d96212ed
AC		 40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
2c5ff671 43 * driver the list of errata that are relevant is below, going back to
d96212ed
AC		 44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
1da177e4
LT		 83 */
84
85#include <linux/kernel.h>
86#include <linux/module.h>
87#include <linux/pci.h>
88#include <linux/init.h>
89#include <linux/blkdev.h>
90#include <linux/delay.h>
6248e647 91#include <linux/device.h>
1da177e4
LT		 92#include <scsi/scsi_host.h>
93#include <linux/libata.h>
b8b275ef 94#include <linux/dmi.h>
1da177e4
LT		 95
96#define DRV_NAME "ata_piix"
2a3103ce 97#define DRV_VERSION "2.12"
1da177e4
LT		 98
99enum {
100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
101 ICH5_PMR = 0x90, /* port mapping register */
102 ICH5_PCS = 0x92, /* port control and status */
7b6dbd68 103 PIIX_SCC = 0x0A, /* sub-class code register */
c7290724
TH		 104 PIIX_SIDPR_BAR = 5,
105 PIIX_SIDPR_LEN = 16,
106 PIIX_SIDPR_IDX = 0,
107 PIIX_SIDPR_DATA = 4,
1da177e4 108
ff0fc146
TH		 109 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
110 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
c7290724 111 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
1da177e4 112
800b3996
TH		 113 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
114 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
b3362f88 115
1da177e4
LT		 116 PIIX_80C_PRI = (1 << 5) | (1 << 4),
117 PIIX_80C_SEC = (1 << 7) | (1 << 6),
118
d33f58b8
TH		 119 /* constants for mapping table */
120 P0 = 0, /* port 0 */
121 P1 = 1, /* port 1 */
122 P2 = 2, /* port 2 */
123 P3 = 3, /* port 3 */
124 IDE = -1, /* IDE */
125 NA = -2, /* not avaliable */
126 RV = -3, /* reserved */
127
7b6dbd68 128 PIIX_AHCI_DEVICE = 6,
b8b275ef
TH		 129
130 /* host->flags bits */
131 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
1da177e4
LT		 132};
133
9cde9ed1
TH		 134enum piix_controller_ids {
135 /* controller IDs */
136 piix_pata_mwdma, /* PIIX3 MWDMA only */
137 piix_pata_33, /* PIIX4 at 33Mhz */
138 ich_pata_33, /* ICH up to UDMA 33 only */
139 ich_pata_66, /* ICH up to 66 Mhz */
140 ich_pata_100, /* ICH up to UDMA 100 */
141 ich5_sata,
142 ich6_sata,
143 ich6_sata_ahci,
144 ich6m_sata_ahci,
145 ich8_sata_ahci,
146 ich8_2port_sata,
147 ich8m_apple_sata_ahci, /* locks up on second port enable */
148 tolapai_sata_ahci,
149 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
150};
151
d33f58b8
TH		 152struct piix_map_db {
153 const u32 mask;
73291a1c 154 const u16 port_enable;
d33f58b8
TH		 155 const int map[][4];
156};
157
d96715c1
TH		 158struct piix_host_priv {
159 const int *map;
c7290724 160 void __iomem *sidpr;
d96715c1
TH		 161};
162
2dcb407e
JG		 163static int piix_init_one(struct pci_dev *pdev,
164 const struct pci_device_id *ent);
ccc4672a 165static void piix_pata_error_handler(struct ata_port *ap);
2dcb407e
JG		 166static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
167static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
168static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
eb4a2c7f 169static int ich_pata_cable_detect(struct ata_port *ap);
25f98131 170static u8 piix_vmw_bmdma_status(struct ata_port *ap);
c7290724
TH		 171static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val);
172static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val);
173static void piix_sidpr_error_handler(struct ata_port *ap);
b8b275ef
TH		 174#ifdef CONFIG_PM
175static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
176static int piix_pci_device_resume(struct pci_dev *pdev);
177#endif
1da177e4
LT		 178
179static unsigned int in_module_init = 1;
180
3b7d697d 181static const struct pci_device_id piix_pci_tbl[] = {
d2cdfc0d
A		 182 /* Intel PIIX3 for the 430HX etc */
183 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
25f98131
TH		 184 /* VMware ICH4 */
185 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
669a5db4
JG		 186 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
187 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
188 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
669a5db4
JG		 189 /* Intel PIIX4 */
190 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
191 /* Intel PIIX4 */
192 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
193 /* Intel PIIX */
194 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
195 /* Intel ICH (i810, i815, i840) UDMA 66*/
196 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
197 /* Intel ICH0 : UDMA 33*/
198 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
199 /* Intel ICH2M */
200 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
202 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
203 /* Intel ICH3M */
204 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
205 /* Intel ICH3 (E7500/1) UDMA 100 */
206 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
207 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
208 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
209 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
210 /* Intel ICH5 */
2eb829e9 211 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
669a5db4
JG		 212 /* C-ICH (i810E2) */
213 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
85cd7251 214 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
669a5db4
JG		 215 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
216 /* ICH6 (and 6) (i915) UDMA 100 */
217 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
218 /* ICH7/7-R (i945, i975) UDMA 100*/
2eb829e9 219 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
669a5db4 220 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
c1e6f28c
CL		 221 /* ICH8 Mobile PATA Controller */
222 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
1da177e4
LT		 223
224 /* NOTE: The following PCI ids must be kept in sync with the
225 * list in drivers/pci/quirks.c.
226 */
227
1d076e5b 228 /* 82801EB (ICH5) */
1da177e4 229 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 230 /* 82801EB (ICH5) */
1da177e4 231 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 232 /* 6300ESB (ICH5 variant with broken PCS present bits) */
5e56a37c 233 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 234 /* 6300ESB pretending RAID */
5e56a37c 235 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 236 /* 82801FB/FW (ICH6/ICH6W) */
1da177e4 237 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
1d076e5b 238 /* 82801FR/FRW (ICH6R/ICH6RW) */
1c24a412 239 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 240 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
241 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
242 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
1c24a412 243 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 244 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
c6446a4c 245 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
f98b6573 246 /* Enterprise Southbridge 2 (631xESB/632xESB) */
1c24a412 247 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
f98b6573 248 /* SATA Controller 1 IDE (ICH8) */
08f12edc 249 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
f98b6573 250 /* SATA Controller 2 IDE (ICH8) */
00242ec8 251 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573 252 /* Mobile SATA Controller IDE (ICH8M) */
08f12edc 253 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
8d8ef2fb
TR		 254 /* Mobile SATA Controller IDE (ICH8M), Apple */
255 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata_ahci },
f98b6573
JG		 256 /* SATA Controller IDE (ICH9) */
257 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
258 /* SATA Controller IDE (ICH9) */
00242ec8 259 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573 260 /* SATA Controller IDE (ICH9) */
00242ec8 261 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573 262 /* SATA Controller IDE (ICH9M) */
00242ec8 263 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573 264 /* SATA Controller IDE (ICH9M) */
00242ec8 265 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573
JG		 266 /* SATA Controller IDE (ICH9M) */
267 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
c5cf0ffa
JG		 268 /* SATA Controller IDE (Tolapai) */
269 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci },
bf7f22b9
JG		 270 /* SATA Controller IDE (ICH10) */
271 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
272 /* SATA Controller IDE (ICH10) */
273 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
274 /* SATA Controller IDE (ICH10) */
275 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
276 /* SATA Controller IDE (ICH10) */
277 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
1da177e4
LT		 278
279 { } /* terminate list */
280};
281
282static struct pci_driver piix_pci_driver = {
283 .name = DRV_NAME,
284 .id_table = piix_pci_tbl,
285 .probe = piix_init_one,
286 .remove = ata_pci_remove_one,
438ac6d5 287#ifdef CONFIG_PM
b8b275ef
TH		 288 .suspend = piix_pci_device_suspend,
289 .resume = piix_pci_device_resume,
438ac6d5 290#endif
1da177e4
LT		 291};
292
193515d5 293static struct scsi_host_template piix_sht = {
1da177e4
LT		 294 .module = THIS_MODULE,
295 .name = DRV_NAME,
296 .ioctl = ata_scsi_ioctl,
297 .queuecommand = ata_scsi_queuecmd,
1da177e4
LT		 298 .can_queue = ATA_DEF_QUEUE,
299 .this_id = ATA_SHT_THIS_ID,
300 .sg_tablesize = LIBATA_MAX_PRD,
1da177e4
LT		 301 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
302 .emulated = ATA_SHT_EMULATED,
303 .use_clustering = ATA_SHT_USE_CLUSTERING,
304 .proc_name = DRV_NAME,
305 .dma_boundary = ATA_DMA_BOUNDARY,
306 .slave_configure = ata_scsi_slave_config,
ccf68c34 307 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 308 .bios_param = ata_std_bios_param,
1da177e4
LT		 309};
310
057ace5e 311static const struct ata_port_operations piix_pata_ops = {
1da177e4
LT		 312 .set_piomode = piix_set_piomode,
313 .set_dmamode = piix_set_dmamode,
89bad589 314 .mode_filter = ata_pci_default_filter,
1da177e4
LT		 315
316 .tf_load = ata_tf_load,
317 .tf_read = ata_tf_read,
318 .check_status = ata_check_status,
319 .exec_command = ata_exec_command,
320 .dev_select = ata_std_dev_select,
321
1da177e4
LT		 322 .bmdma_setup = ata_bmdma_setup,
323 .bmdma_start = ata_bmdma_start,
324 .bmdma_stop = ata_bmdma_stop,
325 .bmdma_status = ata_bmdma_status,
326 .qc_prep = ata_qc_prep,
327 .qc_issue = ata_qc_issue_prot,
0d5ff566 328 .data_xfer = ata_data_xfer,
1da177e4 329
3f037db0
TH		 330 .freeze = ata_bmdma_freeze,
331 .thaw = ata_bmdma_thaw,
ccc4672a 332 .error_handler = piix_pata_error_handler,
3f037db0 333 .post_internal_cmd = ata_bmdma_post_internal_cmd,
eb4a2c7f 334 .cable_detect = ata_cable_40wire,
1da177e4 335
1da177e4 336 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 337 .irq_on = ata_irq_on,
1da177e4 338
6bd99b4e 339 .port_start = ata_sff_port_start,
1da177e4
LT		 340};
341
669a5db4 342static const struct ata_port_operations ich_pata_ops = {
669a5db4
JG		 343 .set_piomode = piix_set_piomode,
344 .set_dmamode = ich_set_dmamode,
345 .mode_filter = ata_pci_default_filter,
346
347 .tf_load = ata_tf_load,
348 .tf_read = ata_tf_read,
349 .check_status = ata_check_status,
350 .exec_command = ata_exec_command,
351 .dev_select = ata_std_dev_select,
352
353 .bmdma_setup = ata_bmdma_setup,
354 .bmdma_start = ata_bmdma_start,
355 .bmdma_stop = ata_bmdma_stop,
356 .bmdma_status = ata_bmdma_status,
357 .qc_prep = ata_qc_prep,
358 .qc_issue = ata_qc_issue_prot,
0d5ff566 359 .data_xfer = ata_data_xfer,
669a5db4
JG		 360
361 .freeze = ata_bmdma_freeze,
362 .thaw = ata_bmdma_thaw,
eb4a2c7f 363 .error_handler = piix_pata_error_handler,
669a5db4 364 .post_internal_cmd = ata_bmdma_post_internal_cmd,
eb4a2c7f 365 .cable_detect = ich_pata_cable_detect,
669a5db4 366
669a5db4 367 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 368 .irq_on = ata_irq_on,
669a5db4 369
6bd99b4e 370 .port_start = ata_sff_port_start,
669a5db4
JG		 371};
372
057ace5e 373static const struct ata_port_operations piix_sata_ops = {
1da177e4
LT		 374 .tf_load = ata_tf_load,
375 .tf_read = ata_tf_read,
376 .check_status = ata_check_status,
377 .exec_command = ata_exec_command,
378 .dev_select = ata_std_dev_select,
379
1da177e4
LT		 380 .bmdma_setup = ata_bmdma_setup,
381 .bmdma_start = ata_bmdma_start,
382 .bmdma_stop = ata_bmdma_stop,
383 .bmdma_status = ata_bmdma_status,
384 .qc_prep = ata_qc_prep,
385 .qc_issue = ata_qc_issue_prot,
0d5ff566 386 .data_xfer = ata_data_xfer,
1da177e4 387
6bd99b4e 388 .mode_filter = ata_pci_default_filter,
3f037db0
TH		 389 .freeze = ata_bmdma_freeze,
390 .thaw = ata_bmdma_thaw,
2f91d81d 391 .error_handler = ata_bmdma_error_handler,
3f037db0 392 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4 393
1da177e4 394 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 395 .irq_on = ata_irq_on,
1da177e4 396
6bd99b4e 397 .port_start = ata_sff_port_start,
1da177e4
LT		 398};
399
25f98131
TH		 400static const struct ata_port_operations piix_vmw_ops = {
401 .set_piomode = piix_set_piomode,
402 .set_dmamode = piix_set_dmamode,
403 .mode_filter = ata_pci_default_filter,
404
405 .tf_load = ata_tf_load,
406 .tf_read = ata_tf_read,
407 .check_status = ata_check_status,
408 .exec_command = ata_exec_command,
409 .dev_select = ata_std_dev_select,
410
411 .bmdma_setup = ata_bmdma_setup,
412 .bmdma_start = ata_bmdma_start,
413 .bmdma_stop = ata_bmdma_stop,
414 .bmdma_status = piix_vmw_bmdma_status,
415 .qc_prep = ata_qc_prep,
416 .qc_issue = ata_qc_issue_prot,
417 .data_xfer = ata_data_xfer,
418
419 .freeze = ata_bmdma_freeze,
420 .thaw = ata_bmdma_thaw,
421 .error_handler = piix_pata_error_handler,
422 .post_internal_cmd = ata_bmdma_post_internal_cmd,
423 .cable_detect = ata_cable_40wire,
424
425 .irq_handler = ata_interrupt,
426 .irq_clear = ata_bmdma_irq_clear,
427 .irq_on = ata_irq_on,
428
6bd99b4e 429 .port_start = ata_sff_port_start,
25f98131
TH		 430};
431
c7290724
TH		 432static const struct ata_port_operations piix_sidpr_sata_ops = {
433 .tf_load = ata_tf_load,
434 .tf_read = ata_tf_read,
435 .check_status = ata_check_status,
436 .exec_command = ata_exec_command,
437 .dev_select = ata_std_dev_select,
438
439 .bmdma_setup = ata_bmdma_setup,
440 .bmdma_start = ata_bmdma_start,
441 .bmdma_stop = ata_bmdma_stop,
442 .bmdma_status = ata_bmdma_status,
443 .qc_prep = ata_qc_prep,
444 .qc_issue = ata_qc_issue_prot,
445 .data_xfer = ata_data_xfer,
446
447 .scr_read = piix_sidpr_scr_read,
448 .scr_write = piix_sidpr_scr_write,
449
6bd99b4e 450 .mode_filter = ata_pci_default_filter,
c7290724
TH		 451 .freeze = ata_bmdma_freeze,
452 .thaw = ata_bmdma_thaw,
453 .error_handler = piix_sidpr_error_handler,
454 .post_internal_cmd = ata_bmdma_post_internal_cmd,
455
456 .irq_clear = ata_bmdma_irq_clear,
457 .irq_on = ata_irq_on,
458
6bd99b4e 459 .port_start = ata_sff_port_start,
c7290724
TH		 460};
461
d96715c1 462static const struct piix_map_db ich5_map_db = {
d33f58b8 463 .mask = 0x7,
ea35d29e 464 .port_enable = 0x3,
d33f58b8
TH		 465 .map = {
466 /* PM PS SM SS MAP */
467 { P0, NA, P1, NA }, /* 000b */
468 { P1, NA, P0, NA }, /* 001b */
469 { RV, RV, RV, RV },
470 { RV, RV, RV, RV },
471 { P0, P1, IDE, IDE }, /* 100b */
472 { P1, P0, IDE, IDE }, /* 101b */
473 { IDE, IDE, P0, P1 }, /* 110b */
474 { IDE, IDE, P1, P0 }, /* 111b */
475 },
476};
477
d96715c1 478static const struct piix_map_db ich6_map_db = {
d33f58b8 479 .mask = 0x3,
ea35d29e 480 .port_enable = 0xf,
d33f58b8
TH		 481 .map = {
482 /* PM PS SM SS MAP */
79ea24e7 483 { P0, P2, P1, P3 }, /* 00b */
d33f58b8
TH		 484 { IDE, IDE, P1, P3 }, /* 01b */
485 { P0, P2, IDE, IDE }, /* 10b */
486 { RV, RV, RV, RV },
487 },
488};
489
d96715c1 490static const struct piix_map_db ich6m_map_db = {
d33f58b8 491 .mask = 0x3,
ea35d29e 492 .port_enable = 0x5,
67083741
TH		 493
494 /* Map 01b isn't specified in the doc but some notebooks use
c6446a4c
TH		 495 * it anyway. MAP 01b have been spotted on both ICH6M and
496 * ICH7M.
67083741
TH		 497 */
498 .map = {
499 /* PM PS SM SS MAP */
e04b3b9d 500 { P0, P2, NA, NA }, /* 00b */
67083741
TH		 501 { IDE, IDE, P1, P3 }, /* 01b */
502 { P0, P2, IDE, IDE }, /* 10b */
503 { RV, RV, RV, RV },
504 },
505};
506
08f12edc
JG		 507static const struct piix_map_db ich8_map_db = {
508 .mask = 0x3,
a0ce9aca 509 .port_enable = 0xf,
08f12edc
JG		 510 .map = {
511 /* PM PS SM SS MAP */
158f30c8 512 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
08f12edc 513 { RV, RV, RV, RV },
ac2b0437 514 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
08f12edc
JG		 515 { RV, RV, RV, RV },
516 },
517};
518
00242ec8 519static const struct piix_map_db ich8_2port_map_db = {
e2d352af
JG		 520 .mask = 0x3,
521 .port_enable = 0x3,
522 .map = {
523 /* PM PS SM SS MAP */
524 { P0, NA, P1, NA }, /* 00b */
525 { RV, RV, RV, RV }, /* 01b */
526 { RV, RV, RV, RV }, /* 10b */
527 { RV, RV, RV, RV },
528 },
c5cf0ffa
JG		 529};
530
8d8ef2fb
TR		 531static const struct piix_map_db ich8m_apple_map_db = {
532 .mask = 0x3,
533 .port_enable = 0x1,
534 .map = {
535 /* PM PS SM SS MAP */
536 { P0, NA, NA, NA }, /* 00b */
537 { RV, RV, RV, RV },
538 { P0, P2, IDE, IDE }, /* 10b */
539 { RV, RV, RV, RV },
540 },
541};
542
00242ec8 543static const struct piix_map_db tolapai_map_db = {
8f73a688
JG		 544 .mask = 0x3,
545 .port_enable = 0x3,
546 .map = {
547 /* PM PS SM SS MAP */
548 { P0, NA, P1, NA }, /* 00b */
549 { RV, RV, RV, RV }, /* 01b */
550 { RV, RV, RV, RV }, /* 10b */
551 { RV, RV, RV, RV },
552 },
553};
554
d96715c1
TH		 555static const struct piix_map_db *piix_map_db_table[] = {
556 [ich5_sata] = &ich5_map_db,
d96715c1
TH		 557 [ich6_sata] = &ich6_map_db,
558 [ich6_sata_ahci] = &ich6_map_db,
559 [ich6m_sata_ahci] = &ich6m_map_db,
08f12edc 560 [ich8_sata_ahci] = &ich8_map_db,
00242ec8 561 [ich8_2port_sata] = &ich8_2port_map_db,
8d8ef2fb 562 [ich8m_apple_sata_ahci] = &ich8m_apple_map_db,
c5cf0ffa 563 [tolapai_sata_ahci] = &tolapai_map_db,
d96715c1
TH		 564};
565
1da177e4 566static struct ata_port_info piix_port_info[] = {
00242ec8
TH		 567 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
568 {
00242ec8
TH		 569 .flags = PIIX_PATA_FLAGS,
570 .pio_mask = 0x1f, /* pio0-4 */
571 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
572 .port_ops = &piix_pata_ops,
573 },
574
ec300d99 575 [piix_pata_33] = /* PIIX4 at 33MHz */
1d076e5b 576 {
b3362f88 577 .flags = PIIX_PATA_FLAGS,
1d076e5b 578 .pio_mask = 0x1f, /* pio0-4 */
669a5db4 579 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1d076e5b
TH		 580 .udma_mask = ATA_UDMA_MASK_40C,
581 .port_ops = &piix_pata_ops,
582 },
583
ec300d99 584 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
669a5db4 585 {
b3362f88 586 .flags = PIIX_PATA_FLAGS,
669a5db4
JG		 587 .pio_mask = 0x1f, /* pio 0-4 */
588 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
589 .udma_mask = ATA_UDMA2, /* UDMA33 */
590 .port_ops = &ich_pata_ops,
591 },
ec300d99
JG		 592
593 [ich_pata_66] = /* ICH controllers up to 66MHz */
1da177e4 594 {
b3362f88 595 .flags = PIIX_PATA_FLAGS,
669a5db4
JG		 596 .pio_mask = 0x1f, /* pio 0-4 */
597 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
598 .udma_mask = ATA_UDMA4,
599 .port_ops = &ich_pata_ops,
600 },
85cd7251 601
ec300d99 602 [ich_pata_100] =
669a5db4 603 {
b3362f88 604 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1da177e4 605 .pio_mask = 0x1f, /* pio0-4 */
1da177e4 606 .mwdma_mask = 0x06, /* mwdma1-2 */
669a5db4
JG		 607 .udma_mask = ATA_UDMA5, /* udma0-5 */
608 .port_ops = &ich_pata_ops,
1da177e4
LT		 609 },
610
ec300d99 611 [ich5_sata] =
1da177e4 612 {
228c1590 613 .flags = PIIX_SATA_FLAGS,
1da177e4
LT		 614 .pio_mask = 0x1f, /* pio0-4 */
615 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 616 .udma_mask = ATA_UDMA6,
1da177e4
LT		 617 .port_ops = &piix_sata_ops,
618 },
619
ec300d99 620 [ich6_sata] =
1da177e4 621 {
723159c5 622 .flags = PIIX_SATA_FLAGS,
1da177e4
LT		 623 .pio_mask = 0x1f, /* pio0-4 */
624 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 625 .udma_mask = ATA_UDMA6,
1da177e4
LT		 626 .port_ops = &piix_sata_ops,
627 },
628
ec300d99 629 [ich6_sata_ahci] =
c368ca4e 630 {
723159c5 631 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI,
c368ca4e
JG		 632 .pio_mask = 0x1f, /* pio0-4 */
633 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 634 .udma_mask = ATA_UDMA6,
c368ca4e
JG		 635 .port_ops = &piix_sata_ops,
636 },
1d076e5b 637
ec300d99 638 [ich6m_sata_ahci] =
1d076e5b 639 {
723159c5 640 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI,
1d076e5b
TH		 641 .pio_mask = 0x1f, /* pio0-4 */
642 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 643 .udma_mask = ATA_UDMA6,
1d076e5b
TH		 644 .port_ops = &piix_sata_ops,
645 },
08f12edc 646
ec300d99 647 [ich8_sata_ahci] =
08f12edc 648 {
c7290724
TH		 649 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI |
650 PIIX_FLAG_SIDPR,
08f12edc
JG		 651 .pio_mask = 0x1f, /* pio0-4 */
652 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 653 .udma_mask = ATA_UDMA6,
08f12edc
JG		 654 .port_ops = &piix_sata_ops,
655 },
669a5db4 656
00242ec8 657 [ich8_2port_sata] =
c5cf0ffa 658 {
c7290724
TH		 659 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI |
660 PIIX_FLAG_SIDPR,
c5cf0ffa
JG		 661 .pio_mask = 0x1f, /* pio0-4 */
662 .mwdma_mask = 0x07, /* mwdma0-2 */
663 .udma_mask = ATA_UDMA6,
664 .port_ops = &piix_sata_ops,
665 },
8f73a688 666
00242ec8 667 [tolapai_sata_ahci] =
8f73a688 668 {
723159c5 669 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI,
8f73a688
JG		 670 .pio_mask = 0x1f, /* pio0-4 */
671 .mwdma_mask = 0x07, /* mwdma0-2 */
672 .udma_mask = ATA_UDMA6,
673 .port_ops = &piix_sata_ops,
674 },
8d8ef2fb
TR		 675
676 [ich8m_apple_sata_ahci] =
677 {
c7290724
TH		 678 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI |
679 PIIX_FLAG_SIDPR,
8d8ef2fb
TR		 680 .pio_mask = 0x1f, /* pio0-4 */
681 .mwdma_mask = 0x07, /* mwdma0-2 */
682 .udma_mask = ATA_UDMA6,
683 .port_ops = &piix_sata_ops,
684 },
685
25f98131
TH		 686 [piix_pata_vmw] =
687 {
25f98131
TH		 688 .flags = PIIX_PATA_FLAGS,
689 .pio_mask = 0x1f, /* pio0-4 */
690 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
691 .udma_mask = ATA_UDMA_MASK_40C,
692 .port_ops = &piix_vmw_ops,
693 },
694
1da177e4
LT		 695};
696
697static struct pci_bits piix_enable_bits[] = {
698 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
699 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
700};
701
702MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
703MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
704MODULE_LICENSE("GPL");
705MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
706MODULE_VERSION(DRV_VERSION);
707
fc085150
AC		 708struct ich_laptop {
709 u16 device;
710 u16 subvendor;
711 u16 subdevice;
712};
713
714/*
715 * List of laptops that use short cables rather than 80 wire
716 */
717
718static const struct ich_laptop ich_laptop[] = {
719 /* devid, subvendor, subdev */
720 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
2655e2ce 721 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
babfb682 722 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
12340106 723 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
54174db3 724 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
b33620f9 725 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
fc085150
AC		 726 /* end marker */
727 { 0, }
728};
729
1da177e4 730/**
eb4a2c7f 731 * ich_pata_cable_detect - Probe host controller cable detect info
1da177e4
LT		 732 * @ap: Port for which cable detect info is desired
733 *
734 * Read 80c cable indicator from ATA PCI device's PCI config
735 * register. This register is normally set by firmware (BIOS).
736 *
737 * LOCKING:
738 * None (inherited from caller).
739 */
669a5db4 740
eb4a2c7f 741static int ich_pata_cable_detect(struct ata_port *ap)
1da177e4 742{
cca3974e 743 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
fc085150 744 const struct ich_laptop *lap = &ich_laptop[0];
1da177e4
LT		 745 u8 tmp, mask;
746
fc085150
AC		 747 /* Check for specials - Acer Aspire 5602WLMi */
748 while (lap->device) {
749 if (lap->device == pdev->device &&
750 lap->subvendor == pdev->subsystem_vendor &&
2dcb407e 751 lap->subdevice == pdev->subsystem_device)
eb4a2c7f 752 return ATA_CBL_PATA40_SHORT;
2dcb407e 753
fc085150
AC		 754 lap++;
755 }
756
1da177e4 757 /* check BIOS cable detect results */
2a88d1ac 758 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
1da177e4
LT		 759 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
760 if ((tmp & mask) == 0)
eb4a2c7f
AC		 761 return ATA_CBL_PATA40;
762 return ATA_CBL_PATA80;
1da177e4
LT		 763}
764
765/**
ccc4672a 766 * piix_pata_prereset - prereset for PATA host controller
cc0680a5 767 * @link: Target link
d4b2bab4 768 * @deadline: deadline jiffies for the operation
1da177e4 769 *
573db6b8
TH		 770 * LOCKING:
771 * None (inherited from caller).
772 */
cc0680a5 773static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
1da177e4 774{
cc0680a5 775 struct ata_port *ap = link->ap;
cca3974e 776 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1da177e4 777
c961922b
AC		 778 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
779 return -ENOENT;
cc0680a5 780 return ata_std_prereset(link, deadline);
ccc4672a
TH		 781}
782
783static void piix_pata_error_handler(struct ata_port *ap)
784{
785 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
786 ata_std_postreset);
1da177e4
LT		 787}
788
1da177e4
LT		 789/**
790 * piix_set_piomode - Initialize host controller PATA PIO timings
791 * @ap: Port whose timings we are configuring
792 * @adev: um
1da177e4
LT		 793 *
794 * Set PIO mode for device, in host controller PCI config space.
795 *
796 * LOCKING:
797 * None (inherited from caller).
798 */
799
2dcb407e 800static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
1da177e4
LT		 801{
802 unsigned int pio = adev->pio_mode - XFER_PIO_0;
cca3974e 803 struct pci_dev *dev = to_pci_dev(ap->host->dev);
1da177e4 804 unsigned int is_slave = (adev->devno != 0);
2a88d1ac 805 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
1da177e4
LT		 806 unsigned int slave_port = 0x44;
807 u16 master_data;
808 u8 slave_data;
669a5db4
JG		 809 u8 udma_enable;
810 int control = 0;
85cd7251 811
669a5db4
JG		 812 /*
813 * See Intel Document 298600-004 for the timing programing rules
814 * for ICH controllers.
815 */
1da177e4
LT		 816
817 static const /* ISP RTC */
818 u8 timings[][2] = { { 0, 0 },
819 { 0, 0 },
820 { 1, 0 },
821 { 2, 1 },
822 { 2, 3 }, };
823
669a5db4
JG		 824 if (pio >= 2)
825 control |= 1; /* TIME1 enable */
826 if (ata_pio_need_iordy(adev))
827 control |= 2; /* IE enable */
828
85cd7251 829 /* Intel specifies that the PPE functionality is for disk only */
669a5db4
JG		 830 if (adev->class == ATA_DEV_ATA)
831 control |= 4; /* PPE enable */
832
a5bf5f5a
TH		 833 /* PIO configuration clears DTE unconditionally. It will be
834 * programmed in set_dmamode which is guaranteed to be called
835 * after set_piomode if any DMA mode is available.
836 */
1da177e4
LT		 837 pci_read_config_word(dev, master_port, &master_data);
838 if (is_slave) {
a5bf5f5a
TH		 839 /* clear TIME1|IE1|PPE1|DTE1 */
840 master_data &= 0xff0f;
1967b7ff 841 /* Enable SITRE (separate slave timing register) */
1da177e4 842 master_data |= 0x4000;
669a5db4
JG		 843 /* enable PPE1, IE1 and TIME1 as needed */
844 master_data |= (control << 4);
1da177e4 845 pci_read_config_byte(dev, slave_port, &slave_data);
2a88d1ac 846 slave_data &= (ap->port_no ? 0x0f : 0xf0);
669a5db4 847 /* Load the timing nibble for this slave */
a5bf5f5a
TH		 848 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
849 << (ap->port_no ? 4 : 0);
1da177e4 850 } else {
a5bf5f5a
TH		 851 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
852 master_data &= 0xccf0;
669a5db4
JG		 853 /* Enable PPE, IE and TIME as appropriate */
854 master_data |= control;
a5bf5f5a 855 /* load ISP and RCT */
1da177e4
LT		 856 master_data |=
857 (timings[pio][0] << 12) |
858 (timings[pio][1] << 8);
859 }
860 pci_write_config_word(dev, master_port, master_data);
861 if (is_slave)
862 pci_write_config_byte(dev, slave_port, slave_data);
669a5db4
JG		 863
864 /* Ensure the UDMA bit is off - it will be turned back on if
865 UDMA is selected */
85cd7251 866
669a5db4
JG		 867 if (ap->udma_mask) {
868 pci_read_config_byte(dev, 0x48, &udma_enable);
869 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
870 pci_write_config_byte(dev, 0x48, udma_enable);
871 }
1da177e4
LT		 872}
873
874/**
669a5db4 875 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
1da177e4 876 * @ap: Port whose timings we are configuring
669a5db4 877 * @adev: Drive in question
1da177e4 878 * @udma: udma mode, 0 - 6
c32a8fd7 879 * @isich: set if the chip is an ICH device
1da177e4
LT		 880 *
881 * Set UDMA mode for device, in host controller PCI config space.
882 *
883 * LOCKING:
884 * None (inherited from caller).
885 */
886
2dcb407e 887static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
1da177e4 888{
cca3974e 889 struct pci_dev *dev = to_pci_dev(ap->host->dev);
669a5db4
JG		 890 u8 master_port = ap->port_no ? 0x42 : 0x40;
891 u16 master_data;
892 u8 speed = adev->dma_mode;
893 int devid = adev->devno + 2 * ap->port_no;
dedf61db 894 u8 udma_enable = 0;
85cd7251 895
669a5db4
JG		 896 static const /* ISP RTC */
897 u8 timings[][2] = { { 0, 0 },
898 { 0, 0 },
899 { 1, 0 },
900 { 2, 1 },
901 { 2, 3 }, };
902
903 pci_read_config_word(dev, master_port, &master_data);
d2cdfc0d
A		 904 if (ap->udma_mask)
905 pci_read_config_byte(dev, 0x48, &udma_enable);
1da177e4
LT		 906
907 if (speed >= XFER_UDMA_0) {
669a5db4
JG		 908 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
909 u16 udma_timing;
910 u16 ideconf;
911 int u_clock, u_speed;
85cd7251 912
669a5db4 913 /*
2dcb407e 914 * UDMA is handled by a combination of clock switching and
85cd7251
JG		 915 * selection of dividers
916 *
669a5db4 917 * Handy rule: Odd modes are UDMATIMx 01, even are 02
85cd7251 918 * except UDMA0 which is 00
669a5db4
JG		 919 */
920 u_speed = min(2 - (udma & 1), udma);
921 if (udma == 5)
922 u_clock = 0x1000; /* 100Mhz */
923 else if (udma > 2)
924 u_clock = 1; /* 66Mhz */
925 else
926 u_clock = 0; /* 33Mhz */
85cd7251 927
669a5db4 928 udma_enable |= (1 << devid);
85cd7251 929
669a5db4
JG		 930 /* Load the CT/RP selection */
931 pci_read_config_word(dev, 0x4A, &udma_timing);
932 udma_timing &= ~(3 << (4 * devid));
933 udma_timing |= u_speed << (4 * devid);
934 pci_write_config_word(dev, 0x4A, udma_timing);
935
85cd7251 936 if (isich) {
669a5db4
JG		 937 /* Select a 33/66/100Mhz clock */
938 pci_read_config_word(dev, 0x54, &ideconf);
939 ideconf &= ~(0x1001 << devid);
940 ideconf |= u_clock << devid;
941 /* For ICH or later we should set bit 10 for better
942 performance (WR_PingPong_En) */
943 pci_write_config_word(dev, 0x54, ideconf);
1da177e4 944 }
1da177e4 945 } else {
669a5db4
JG		 946 /*
947 * MWDMA is driven by the PIO timings. We must also enable
948 * IORDY unconditionally along with TIME1. PPE has already
949 * been set when the PIO timing was set.
950 */
951 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
952 unsigned int control;
953 u8 slave_data;
954 const unsigned int needed_pio[3] = {
955 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
956 };
957 int pio = needed_pio[mwdma] - XFER_PIO_0;
85cd7251 958
669a5db4 959 control = 3; /* IORDY|TIME1 */
85cd7251 960
669a5db4
JG		 961 /* If the drive MWDMA is faster than it can do PIO then
962 we must force PIO into PIO0 */
85cd7251 963
669a5db4
JG		 964 if (adev->pio_mode < needed_pio[mwdma])
965 /* Enable DMA timing only */
966 control |= 8; /* PIO cycles in PIO0 */
967
968 if (adev->devno) { /* Slave */
969 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
970 master_data |= control << 4;
971 pci_read_config_byte(dev, 0x44, &slave_data);
a5bf5f5a 972 slave_data &= (ap->port_no ? 0x0f : 0xf0);
669a5db4
JG		 973 /* Load the matching timing */
974 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
975 pci_write_config_byte(dev, 0x44, slave_data);
976 } else { /* Master */
85cd7251 977 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
669a5db4
JG		 978 and master timing bits */
979 master_data |= control;
980 master_data |=
981 (timings[pio][0] << 12) |
982 (timings[pio][1] << 8);
983 }
a5bf5f5a
TH		 984
985 if (ap->udma_mask) {
986 udma_enable &= ~(1 << devid);
987 pci_write_config_word(dev, master_port, master_data);
988 }
1da177e4 989 }
669a5db4
JG		 990 /* Don't scribble on 0x48 if the controller does not support UDMA */
991 if (ap->udma_mask)
992 pci_write_config_byte(dev, 0x48, udma_enable);
993}
994
995/**
996 * piix_set_dmamode - Initialize host controller PATA DMA timings
997 * @ap: Port whose timings we are configuring
998 * @adev: um
999 *
1000 * Set MW/UDMA mode for device, in host controller PCI config space.
1001 *
1002 * LOCKING:
1003 * None (inherited from caller).
1004 */
1005
2dcb407e 1006static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
669a5db4
JG		 1007{
1008 do_pata_set_dmamode(ap, adev, 0);
1009}
1010
1011/**
1012 * ich_set_dmamode - Initialize host controller PATA DMA timings
1013 * @ap: Port whose timings we are configuring
1014 * @adev: um
1015 *
1016 * Set MW/UDMA mode for device, in host controller PCI config space.
1017 *
1018 * LOCKING:
1019 * None (inherited from caller).
1020 */
1021
2dcb407e 1022static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
669a5db4
JG		 1023{
1024 do_pata_set_dmamode(ap, adev, 1);
1da177e4
LT		 1025}
1026
c7290724
TH		 1027/*
1028 * Serial ATA Index/Data Pair Superset Registers access
1029 *
1030 * Beginning from ICH8, there's a sane way to access SCRs using index
1031 * and data register pair located at BAR5. This creates an
1032 * interesting problem of mapping two SCRs to one port.
1033 *
1034 * Although they have separate SCRs, the master and slave aren't
1035 * independent enough to be treated as separate links - e.g. softreset
1036 * resets both. Also, there's no protocol defined for hard resetting
1037 * singled device sharing the virtual port (no defined way to acquire
1038 * device signature). This is worked around by merging the SCR values
1039 * into one sensible value and requesting follow-up SRST after
1040 * hardreset.
1041 *
1042 * SCR merging is perfomed in nibbles which is the unit contents in
1043 * SCRs are organized. If two values are equal, the value is used.
1044 * When they differ, merge table which lists precedence of possible
1045 * values is consulted and the first match or the last entry when
1046 * nothing matches is used. When there's no merge table for the
1047 * specific nibble, value from the first port is used.
1048 */
1049static const int piix_sidx_map[] = {
1050 [SCR_STATUS] = 0,
1051 [SCR_ERROR] = 2,
1052 [SCR_CONTROL] = 1,
1053};
1054
1055static void piix_sidpr_sel(struct ata_device *dev, unsigned int reg)
1056{
1057 struct ata_port *ap = dev->link->ap;
1058 struct piix_host_priv *hpriv = ap->host->private_data;
1059
1060 iowrite32(((ap->port_no * 2 + dev->devno) << 8) | piix_sidx_map[reg],
1061 hpriv->sidpr + PIIX_SIDPR_IDX);
1062}
1063
1064static int piix_sidpr_read(struct ata_device *dev, unsigned int reg)
1065{
1066 struct piix_host_priv *hpriv = dev->link->ap->host->private_data;
1067
1068 piix_sidpr_sel(dev, reg);
1069 return ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
1070}
1071
1072static void piix_sidpr_write(struct ata_device *dev, unsigned int reg, u32 val)
1073{
1074 struct piix_host_priv *hpriv = dev->link->ap->host->private_data;
1075
1076 piix_sidpr_sel(dev, reg);
1077 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
1078}
1079
4a537a55 1080static u32 piix_merge_scr(u32 val0, u32 val1, const int * const *merge_tbl)
c7290724
TH		 1081{
1082 u32 val = 0;
1083 int i, mi;
1084
1085 for (i = 0, mi = 0; i < 32 / 4; i++) {
1086 u8 c0 = (val0 >> (i * 4)) & 0xf;
1087 u8 c1 = (val1 >> (i * 4)) & 0xf;
1088 u8 merged = c0;
1089 const int *cur;
1090
1091 /* if no merge preference, assume the first value */
1092 cur = merge_tbl[mi];
1093 if (!cur)
1094 goto done;
1095 mi++;
1096
1097 /* if two values equal, use it */
1098 if (c0 == c1)
1099 goto done;
1100
1101 /* choose the first match or the last from the merge table */
1102 while (*cur != -1) {
1103 if (c0 == *cur || c1 == *cur)
1104 break;
1105 cur++;
1106 }
1107 if (*cur == -1)
1108 cur--;
1109 merged = *cur;
1110 done:
1111 val |= merged << (i * 4);
1112 }
1113
1114 return val;
1115}
1116
1117static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val)
1118{
1119 const int * const sstatus_merge_tbl[] = {
1120 /* DET */ (const int []){ 1, 3, 0, 4, 3, -1 },
1121 /* SPD */ (const int []){ 2, 1, 0, -1 },
1122 /* IPM */ (const int []){ 6, 2, 1, 0, -1 },
1123 NULL,
1124 };
1125 const int * const scontrol_merge_tbl[] = {
1126 /* DET */ (const int []){ 1, 0, 4, 0, -1 },
1127 /* SPD */ (const int []){ 0, 2, 1, 0, -1 },
1128 /* IPM */ (const int []){ 0, 1, 2, 3, 0, -1 },
1129 NULL,
1130 };
1131 u32 v0, v1;
1132
1133 if (reg >= ARRAY_SIZE(piix_sidx_map))
1134 return -EINVAL;
1135
1136 if (!(ap->flags & ATA_FLAG_SLAVE_POSS)) {
1137 *val = piix_sidpr_read(&ap->link.device[0], reg);
1138 return 0;
1139 }
1140
1141 v0 = piix_sidpr_read(&ap->link.device[0], reg);
1142 v1 = piix_sidpr_read(&ap->link.device[1], reg);
1143
1144 switch (reg) {
1145 case SCR_STATUS:
1146 *val = piix_merge_scr(v0, v1, sstatus_merge_tbl);
1147 break;
1148 case SCR_ERROR:
1149 *val = v0 | v1;
1150 break;
1151 case SCR_CONTROL:
1152 *val = piix_merge_scr(v0, v1, scontrol_merge_tbl);
1153 break;
1154 }
1155
1156 return 0;
1157}
1158
1159static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val)
1160{
1161 if (reg >= ARRAY_SIZE(piix_sidx_map))
1162 return -EINVAL;
1163
1164 piix_sidpr_write(&ap->link.device[0], reg, val);
1165
1166 if (ap->flags & ATA_FLAG_SLAVE_POSS)
1167 piix_sidpr_write(&ap->link.device[1], reg, val);
1168
1169 return 0;
1170}
1171
1172static int piix_sidpr_hardreset(struct ata_link *link, unsigned int *class,
1173 unsigned long deadline)
1174{
1175 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1176 int rc;
1177
1178 /* do hardreset */
1179 rc = sata_link_hardreset(link, timing, deadline);
1180 if (rc) {
1181 ata_link_printk(link, KERN_ERR,
1182 "COMRESET failed (errno=%d)\n", rc);
1183 return rc;
1184 }
1185
1186 /* TODO: phy layer with polling, timeouts, etc. */
1187 if (ata_link_offline(link)) {
1188 *class = ATA_DEV_NONE;
1189 return 0;
1190 }
1191
1192 return -EAGAIN;
1193}
1194
1195static void piix_sidpr_error_handler(struct ata_port *ap)
1196{
1197 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
1198 piix_sidpr_hardreset, ata_std_postreset);
1199}
1200
b8b275ef 1201#ifdef CONFIG_PM
8c3832eb
TH		 1202static int piix_broken_suspend(void)
1203{
1855256c 1204 static const struct dmi_system_id sysids[] = {
4c74d4ec
TH		 1205 {
1206 .ident = "TECRA M3",
1207 .matches = {
1208 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1209 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
1210 },
1211 },
04d86d6f
PS		 1212 {
1213 .ident = "TECRA M3",
1214 .matches = {
1215 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1216 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
1217 },
1218 },
d1aa690a
PS		 1219 {
1220 .ident = "TECRA M4",
1221 .matches = {
1222 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1223 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
1224 },
1225 },
8c3832eb
TH		 1226 {
1227 .ident = "TECRA M5",
1228 .matches = {
1229 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1230 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1231 },
b8b275ef 1232 },
ffe188dd
PS		 1233 {
1234 .ident = "TECRA M6",
1235 .matches = {
1236 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1237 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
1238 },
1239 },
5c08ea01
TH		 1240 {
1241 .ident = "TECRA M7",
1242 .matches = {
1243 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1244 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1245 },
1246 },
04d86d6f
PS		 1247 {
1248 .ident = "TECRA A8",
1249 .matches = {
1250 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1251 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1252 },
1253 },
ffe188dd
PS		 1254 {
1255 .ident = "Satellite R20",
1256 .matches = {
1257 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1258 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1259 },
1260 },
04d86d6f
PS		 1261 {
1262 .ident = "Satellite R25",
1263 .matches = {
1264 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1265 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1266 },
1267 },
3cc0b9d3
TH		 1268 {
1269 .ident = "Satellite U200",
1270 .matches = {
1271 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1272 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1273 },
1274 },
04d86d6f
PS		 1275 {
1276 .ident = "Satellite U200",
1277 .matches = {
1278 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1279 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1280 },
1281 },
62320e23
YC		 1282 {
1283 .ident = "Satellite Pro U200",
1284 .matches = {
1285 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1286 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1287 },
1288 },
8c3832eb
TH		 1289 {
1290 .ident = "Satellite U205",
1291 .matches = {
1292 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1293 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1294 },
b8b275ef 1295 },
de753e5e
TH		 1296 {
1297 .ident = "SATELLITE U205",
1298 .matches = {
1299 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1300 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1301 },
1302 },
8c3832eb
TH		 1303 {
1304 .ident = "Portege M500",
1305 .matches = {
1306 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1307 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1308 },
b8b275ef 1309 },
7d051548
JG		 1310
1311 { } /* terminate list */
8c3832eb 1312 };
7abe79c3
TH		 1313 static const char *oemstrs[] = {
1314 "Tecra M3,",
1315 };
1316 int i;
8c3832eb
TH		 1317
1318 if (dmi_check_system(sysids))
1319 return 1;
1320
7abe79c3
TH		 1321 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1322 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1323 return 1;
1324
8c3832eb
TH		 1325 return 0;
1326}
b8b275ef
TH		 1327
1328static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1329{
1330 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1331 unsigned long flags;
1332 int rc = 0;
1333
1334 rc = ata_host_suspend(host, mesg);
1335 if (rc)
1336 return rc;
1337
1338 /* Some braindamaged ACPI suspend implementations expect the
1339 * controller to be awake on entry; otherwise, it burns cpu
1340 * cycles and power trying to do something to the sleeping
1341 * beauty.
1342 */
3a2d5b70 1343 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
b8b275ef
TH		 1344 pci_save_state(pdev);
1345
1346 /* mark its power state as "unknown", since we don't
1347 * know if e.g. the BIOS will change its device state
1348 * when we suspend.
1349 */
1350 if (pdev->current_state == PCI_D0)
1351 pdev->current_state = PCI_UNKNOWN;
1352
1353 /* tell resume that it's waking up from broken suspend */
1354 spin_lock_irqsave(&host->lock, flags);
1355 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1356 spin_unlock_irqrestore(&host->lock, flags);
1357 } else
1358 ata_pci_device_do_suspend(pdev, mesg);
1359
1360 return 0;
1361}
1362
1363static int piix_pci_device_resume(struct pci_dev *pdev)
1364{
1365 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1366 unsigned long flags;
1367 int rc;
1368
1369 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1370 spin_lock_irqsave(&host->lock, flags);
1371 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1372 spin_unlock_irqrestore(&host->lock, flags);
1373
1374 pci_set_power_state(pdev, PCI_D0);
1375 pci_restore_state(pdev);
1376
1377 /* PCI device wasn't disabled during suspend. Use
0b62e13b
TH		 1378 * pci_reenable_device() to avoid affecting the enable
1379 * count.
b8b275ef 1380 */
0b62e13b 1381 rc = pci_reenable_device(pdev);
b8b275ef
TH		 1382 if (rc)
1383 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1384 "device after resume (%d)\n", rc);
1385 } else
1386 rc = ata_pci_device_do_resume(pdev);
1387
1388 if (rc == 0)
1389 ata_host_resume(host);
1390
1391 return rc;
1392}
1393#endif
1394
25f98131
TH		 1395static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1396{
1397 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1398}
1399
1da177e4
LT		 1400#define AHCI_PCI_BAR 5
1401#define AHCI_GLOBAL_CTL 0x04
1402#define AHCI_ENABLE (1 << 31)
1403static int piix_disable_ahci(struct pci_dev *pdev)
1404{
ea6ba10b 1405 void __iomem *mmio;
1da177e4
LT		 1406 u32 tmp;
1407 int rc = 0;
1408
1409 /* BUG: pci_enable_device has not yet been called. This
1410 * works because this device is usually set up by BIOS.
1411 */
1412
374b1873
JG		 1413 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1414 !pci_resource_len(pdev, AHCI_PCI_BAR))
1da177e4 1415 return 0;
7b6dbd68 1416
374b1873 1417 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1da177e4
LT		 1418 if (!mmio)
1419 return -ENOMEM;
7b6dbd68 1420
c47a631f 1421 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1da177e4
LT		 1422 if (tmp & AHCI_ENABLE) {
1423 tmp &= ~AHCI_ENABLE;
c47a631f 1424 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1da177e4 1425
c47a631f 1426 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1da177e4
LT		 1427 if (tmp & AHCI_ENABLE)
1428 rc = -EIO;
1429 }
7b6dbd68 1430
374b1873 1431 pci_iounmap(pdev, mmio);
1da177e4
LT		 1432 return rc;
1433}
1434
c621b140
AC		 1435/**
1436 * piix_check_450nx_errata - Check for problem 450NX setup
c893a3ae 1437 * @ata_dev: the PCI device to check
2e9edbf8 1438 *
c621b140
AC		 1439 * Check for the present of 450NX errata #19 and errata #25. If
1440 * they are found return an error code so we can turn off DMA
1441 */
1442
1443static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1444{
1445 struct pci_dev *pdev = NULL;
1446 u16 cfg;
c621b140 1447 int no_piix_dma = 0;
2e9edbf8 1448
2dcb407e 1449 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
c621b140
AC		 1450 /* Look for 450NX PXB. Check for problem configurations
1451 A PCI quirk checks bit 6 already */
c621b140
AC		 1452 pci_read_config_word(pdev, 0x41, &cfg);
1453 /* Only on the original revision: IDE DMA can hang */
44c10138 1454 if (pdev->revision == 0x00)
c621b140
AC		 1455 no_piix_dma = 1;
1456 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
44c10138 1457 else if (cfg & (1<<14) && pdev->revision < 5)
c621b140
AC		 1458 no_piix_dma = 2;
1459 }
31a34fe7 1460 if (no_piix_dma)
c621b140 1461 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
31a34fe7 1462 if (no_piix_dma == 2)
c621b140
AC		 1463 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1464 return no_piix_dma;
2e9edbf8 1465}
c621b140 1466
8b09f0da 1467static void __devinit piix_init_pcs(struct ata_host *host,
ea35d29e
JG		 1468 const struct piix_map_db *map_db)
1469{
8b09f0da 1470 struct pci_dev *pdev = to_pci_dev(host->dev);
ea35d29e
JG		 1471 u16 pcs, new_pcs;
1472
1473 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1474
1475 new_pcs = pcs | map_db->port_enable;
1476
1477 if (new_pcs != pcs) {
1478 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1479 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1480 msleep(150);
1481 }
1482}
1483
8b09f0da
TH		 1484static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
1485 struct ata_port_info *pinfo,
1486 const struct piix_map_db *map_db)
d33f58b8 1487{
b4482a4b 1488 const int *map;
d33f58b8
TH		 1489 int i, invalid_map = 0;
1490 u8 map_value;
1491
1492 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1493
1494 map = map_db->map[map_value & map_db->mask];
1495
1496 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1497 for (i = 0; i < 4; i++) {
1498 switch (map[i]) {
1499 case RV:
1500 invalid_map = 1;
1501 printk(" XX");
1502 break;
1503
1504 case NA:
1505 printk(" --");
1506 break;
1507
1508 case IDE:
1509 WARN_ON((i & 1) || map[i + 1] != IDE);
669a5db4 1510 pinfo[i / 2] = piix_port_info[ich_pata_100];
d33f58b8
TH		 1511 i++;
1512 printk(" IDE IDE");
1513 break;
1514
1515 default:
1516 printk(" P%d", map[i]);
1517 if (i & 1)
cca3974e 1518 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
d33f58b8
TH		 1519 break;
1520 }
1521 }
1522 printk(" ]\n");
1523
1524 if (invalid_map)
1525 dev_printk(KERN_ERR, &pdev->dev,
1526 "invalid MAP value %u\n", map_value);
1527
8b09f0da 1528 return map;
d33f58b8
TH		 1529}
1530
c7290724
TH		 1531static void __devinit piix_init_sidpr(struct ata_host *host)
1532{
1533 struct pci_dev *pdev = to_pci_dev(host->dev);
1534 struct piix_host_priv *hpriv = host->private_data;
1535 int i;
1536
1537 /* check for availability */
1538 for (i = 0; i < 4; i++)
1539 if (hpriv->map[i] == IDE)
1540 return;
1541
1542 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1543 return;
1544
1545 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1546 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1547 return;
1548
1549 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1550 return;
1551
1552 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1553 host->ports[0]->ops = &piix_sidpr_sata_ops;
1554 host->ports[1]->ops = &piix_sidpr_sata_ops;
1555}
1556
43a98f05
TH		 1557static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
1558{
1855256c 1559 static const struct dmi_system_id sysids[] = {
43a98f05
TH		 1560 {
1561 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1562 * isn't used to boot the system which
1563 * disables the channel.
1564 */
1565 .ident = "M570U",
1566 .matches = {
1567 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1568 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1569 },
1570 },
7d051548
JG		 1571
1572 { } /* terminate list */
43a98f05
TH		 1573 };
1574 u32 iocfg;
1575
1576 if (!dmi_check_system(sysids))
1577 return;
1578
1579 /* The datasheet says that bit 18 is NOOP but certain systems
1580 * seem to use it to disable a channel. Clear the bit on the
1581 * affected systems.
1582 */
1583 pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg);
1584 if (iocfg & (1 << 18)) {
1585 dev_printk(KERN_INFO, &pdev->dev,
1586 "applying IOCFG bit18 quirk\n");
1587 iocfg &= ~(1 << 18);
1588 pci_write_config_dword(pdev, PIIX_IOCFG, iocfg);
1589 }
1590}
1591
1da177e4
LT		 1592/**
1593 * piix_init_one - Register PIIX ATA PCI device with kernel services
1594 * @pdev: PCI device to register
1595 * @ent: Entry in piix_pci_tbl matching with @pdev
1596 *
1597 * Called from kernel PCI layer. We probe for combined mode (sigh),
1598 * and then hand over control to libata, for it to do the rest.
1599 *
1600 * LOCKING:
1601 * Inherited from PCI layer (may sleep).
1602 *
1603 * RETURNS:
1604 * Zero on success, or -ERRNO value.
1605 */
1606
bc5468f5
AB		 1607static int __devinit piix_init_one(struct pci_dev *pdev,
1608 const struct pci_device_id *ent)
1da177e4
LT		 1609{
1610 static int printed_version;
24dc5f33 1611 struct device *dev = &pdev->dev;
d33f58b8 1612 struct ata_port_info port_info[2];
1626aeb8 1613 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
cca3974e 1614 unsigned long port_flags;
8b09f0da
TH		 1615 struct ata_host *host;
1616 struct piix_host_priv *hpriv;
1617 int rc;
1da177e4
LT		 1618
1619 if (!printed_version++)
6248e647
JG		 1620 dev_printk(KERN_DEBUG, &pdev->dev,
1621 "version " DRV_VERSION "\n");
1da177e4
LT		 1622
1623 /* no hotplugging support (FIXME) */
1624 if (!in_module_init)
1625 return -ENODEV;
1626
8b09f0da
TH		 1627 port_info[0] = piix_port_info[ent->driver_data];
1628 port_info[1] = piix_port_info[ent->driver_data];
1629
1630 port_flags = port_info[0].flags;
1631
1632 /* enable device and prepare host */
1633 rc = pcim_enable_device(pdev);
1634 if (rc)
1635 return rc;
1636
1637 /* SATA map init can change port_info, do it before prepping host */
24dc5f33 1638 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
d96715c1
TH		 1639 if (!hpriv)
1640 return -ENOMEM;
1641
8b09f0da
TH		 1642 if (port_flags & ATA_FLAG_SATA)
1643 hpriv->map = piix_init_sata_map(pdev, port_info,
1644 piix_map_db_table[ent->driver_data]);
1da177e4 1645
8b09f0da
TH		 1646 rc = ata_pci_prepare_sff_host(pdev, ppi, &host);
1647 if (rc)
1648 return rc;
1649 host->private_data = hpriv;
ff0fc146 1650
8b09f0da 1651 /* initialize controller */
cca3974e 1652 if (port_flags & PIIX_FLAG_AHCI) {
8a60a071
JG		 1653 u8 tmp;
1654 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1655 if (tmp == PIIX_AHCI_DEVICE) {
018d9827 1656 rc = piix_disable_ahci(pdev);
8a60a071
JG		 1657 if (rc)
1658 return rc;
1659 }
1da177e4
LT		 1660 }
1661
c7290724 1662 if (port_flags & ATA_FLAG_SATA) {
8b09f0da 1663 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
c7290724
TH		 1664 piix_init_sidpr(host);
1665 }
1da177e4 1666
43a98f05
TH		 1667 /* apply IOCFG bit18 quirk */
1668 piix_iocfg_bit18_quirk(pdev);
1669
1da177e4
LT		 1670 /* On ICH5, some BIOSen disable the interrupt using the
1671 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1672 * On ICH6, this bit has the same effect, but only when
1673 * MSI is disabled (and it is disabled, as we don't use
1674 * message-signalled interrupts currently).
1675 */
cca3974e 1676 if (port_flags & PIIX_FLAG_CHECKINTR)
a04ce0ff 1677 pci_intx(pdev, 1);
1da177e4 1678
c621b140
AC		 1679 if (piix_check_450nx_errata(pdev)) {
1680 /* This writes into the master table but it does not
1681 really matter for this errata as we will apply it to
1682 all the PIIX devices on the board */
8b09f0da
TH		 1683 host->ports[0]->mwdma_mask = 0;
1684 host->ports[0]->udma_mask = 0;
1685 host->ports[1]->mwdma_mask = 0;
1686 host->ports[1]->udma_mask = 0;
c621b140 1687 }
8b09f0da
TH		 1688
1689 pci_set_master(pdev);
1690 return ata_pci_activate_sff_host(host, ata_interrupt, &piix_sht);
1da177e4
LT		 1691}
1692
1da177e4
LT		 1693static int __init piix_init(void)
1694{
1695 int rc;
1696
b7887196
PR		 1697 DPRINTK("pci_register_driver\n");
1698 rc = pci_register_driver(&piix_pci_driver);
1da177e4
LT		 1699 if (rc)
1700 return rc;
1701
1702 in_module_init = 0;
1703
1704 DPRINTK("done\n");
1705 return 0;
1706}
1707
1da177e4
LT		 1708static void __exit piix_exit(void)
1709{
1710 pci_unregister_driver(&piix_pci_driver);
1711}
1712
1713module_init(piix_init);
1714module_exit(piix_exit);
Linux 6.x block layer and io_uring tree(s)