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pata_pdc2027x: Use 64-bit timekeeping
[linux-2.6-block.git] / drivers / ata / ahci_xgene.c
CommitLineData
81d01bfa
LH		 1/*
2 * AppliedMicro X-Gene SoC SATA Host Controller Driver
3 *
4 * Copyright (c) 2014, Applied Micro Circuits Corporation
5 * Author: Loc Ho <lho@apm.com>
6 * Tuan Phan <tphan@apm.com>
7 * Suman Tripathi <stripathi@apm.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 * NOTE: PM support is not currently available.
23 *
24 */
25#include <linux/module.h>
26#include <linux/platform_device.h>
27#include <linux/ahci_platform.h>
28#include <linux/of_address.h>
29#include <linux/of_irq.h>
30#include <linux/phy/phy.h>
31#include "ahci.h"
32
33/* Max # of disk per a controller */
34#define MAX_AHCI_CHN_PERCTR 2
35
36/* MUX CSR */
37#define SATA_ENET_CONFIG_REG 0x00000000
38#define CFG_SATA_ENET_SELECT_MASK 0x00000001
39
40/* SATA core host controller CSR */
41#define SLVRDERRATTRIBUTES 0x00000000
42#define SLVWRERRATTRIBUTES 0x00000004
43#define MSTRDERRATTRIBUTES 0x00000008
44#define MSTWRERRATTRIBUTES 0x0000000c
45#define BUSCTLREG 0x00000014
46#define IOFMSTRWAUX 0x00000018
47#define INTSTATUSMASK 0x0000002c
48#define ERRINTSTATUS 0x00000030
49#define ERRINTSTATUSMASK 0x00000034
50
51/* SATA host AHCI CSR */
52#define PORTCFG 0x000000a4
53#define PORTADDR_SET(dst, src) \
54 (((dst) & ~0x0000003f) | (((u32)(src)) & 0x0000003f))
55#define PORTPHY1CFG 0x000000a8
56#define PORTPHY1CFG_FRCPHYRDY_SET(dst, src) \
57 (((dst) & ~0x00100000) | (((u32)(src) << 0x14) & 0x00100000))
58#define PORTPHY2CFG 0x000000ac
59#define PORTPHY3CFG 0x000000b0
60#define PORTPHY4CFG 0x000000b4
61#define PORTPHY5CFG 0x000000b8
62#define SCTL0 0x0000012C
63#define PORTPHY5CFG_RTCHG_SET(dst, src) \
64 (((dst) & ~0xfff00000) | (((u32)(src) << 0x14) & 0xfff00000))
65#define PORTAXICFG_EN_CONTEXT_SET(dst, src) \
66 (((dst) & ~0x01000000) | (((u32)(src) << 0x18) & 0x01000000))
67#define PORTAXICFG 0x000000bc
68#define PORTAXICFG_OUTTRANS_SET(dst, src) \
69 (((dst) & ~0x00f00000) | (((u32)(src) << 0x14) & 0x00f00000))
aeae4dca
ST		 70#define PORTRANSCFG 0x000000c8
71#define PORTRANSCFG_RXWM_SET(dst, src) \
72 (((dst) & ~0x0000007f) | (((u32)(src)) & 0x0000007f))
81d01bfa
LH		 73
74/* SATA host controller AXI CSR */
75#define INT_SLV_TMOMASK 0x00000010
76
77/* SATA diagnostic CSR */
78#define CFG_MEM_RAM_SHUTDOWN 0x00000070
79#define BLOCK_MEM_RDY 0x00000074
80
0babe614
ST		 81/* Max retry for link down */
82#define MAX_LINK_DOWN_RETRY 3
83
81d01bfa
LH		 84struct xgene_ahci_context {
85 struct ahci_host_priv *hpriv;
86 struct device *dev;
2a0bdff6 87 u8 last_cmd[MAX_AHCI_CHN_PERCTR]; /* tracking the last command issued*/
a3a84bc7 88 u32 class[MAX_AHCI_CHN_PERCTR]; /* tracking the class of device */
81d01bfa
LH		 89 void __iomem *csr_core; /* Core CSR address of IP */
90 void __iomem *csr_diag; /* Diag CSR address of IP */
91 void __iomem *csr_axi; /* AXI CSR address of IP */
92 void __iomem *csr_mux; /* MUX CSR address of IP */
93};
94
95static int xgene_ahci_init_memram(struct xgene_ahci_context *ctx)
96{
97 dev_dbg(ctx->dev, "Release memory from shutdown\n");
98 writel(0x0, ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN);
99 readl(ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */
100 msleep(1); /* reset may take up to 1ms */
101 if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) {
102 dev_err(ctx->dev, "failed to release memory from shutdown\n");
103 return -ENODEV;
104 }
105 return 0;
106}
107
1540035d
ST		 108/**
109 * xgene_ahci_poll_reg_val- Poll a register on a specific value.
110 * @ap : ATA port of interest.
111 * @reg : Register of interest.
112 * @val : Value to be attained.
113 * @interval : waiting interval for polling.
114 * @timeout : timeout for achieving the value.
115 */
116static int xgene_ahci_poll_reg_val(struct ata_port *ap,
117 void __iomem *reg, unsigned
118 int val, unsigned long interval,
119 unsigned long timeout)
120{
121 unsigned long deadline;
122 unsigned int tmp;
123
124 tmp = ioread32(reg);
125 deadline = ata_deadline(jiffies, timeout);
126
127 while (tmp != val && time_before(jiffies, deadline)) {
128 ata_msleep(ap, interval);
129 tmp = ioread32(reg);
130 }
131
132 return tmp;
133}
134
2a0bdff6
ST		 135/**
136 * xgene_ahci_restart_engine - Restart the dma engine.
137 * @ap : ATA port of interest
138 *
1540035d
ST		 139 * Waits for completion of multiple commands and restarts
140 * the DMA engine inside the controller.
2a0bdff6
ST		 141 */
142static int xgene_ahci_restart_engine(struct ata_port *ap)
143{
144 struct ahci_host_priv *hpriv = ap->host->private_data;
1540035d
ST		 145 struct ahci_port_priv *pp = ap->private_data;
146 void __iomem *port_mmio = ahci_port_base(ap);
147 u32 fbs;
148
149 /*
150 * In case of PMP multiple IDENTIFY DEVICE commands can be
151 * issued inside PxCI. So need to poll PxCI for the
152 * completion of outstanding IDENTIFY DEVICE commands before
153 * we restart the DMA engine.
154 */
155 if (xgene_ahci_poll_reg_val(ap, port_mmio +
156 PORT_CMD_ISSUE, 0x0, 1, 100))
157 return -EBUSY;
2a0bdff6
ST		 158
159 ahci_stop_engine(ap);
160 ahci_start_fis_rx(ap);
1540035d
ST		 161
162 /*
163 * Enable the PxFBS.FBS_EN bit as it
164 * gets cleared due to stopping the engine.
165 */
166 if (pp->fbs_supported) {
167 fbs = readl(port_mmio + PORT_FBS);
168 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
169 fbs = readl(port_mmio + PORT_FBS);
170 }
171
2a0bdff6
ST		 172 hpriv->start_engine(ap);
173
174 return 0;
175}
176
177/**
178 * xgene_ahci_qc_issue - Issue commands to the device
179 * @qc: Command to issue
180 *
a3a84bc7
ST		 181 * Due to Hardware errata for IDENTIFY DEVICE command, the controller cannot
182 * clear the BSY bit after receiving the PIO setup FIS. This results in the dma
183 * state machine goes into the CMFatalErrorUpdate state and locks up. By
184 * restarting the dma engine, it removes the controller out of lock up state.
185 *
186 * Due to H/W errata, the controller is unable to save the PMP
187 * field fetched from command header before sending the H2D FIS.
188 * When the device returns the PMP port field in the D2H FIS, there is
189 * a mismatch and results in command completion failure. The
190 * workaround is to write the pmp value to PxFBS.DEV field before issuing
191 * any command to PMP.
2a0bdff6
ST		 192 */
193static unsigned int xgene_ahci_qc_issue(struct ata_queued_cmd *qc)
194{
195 struct ata_port *ap = qc->ap;
196 struct ahci_host_priv *hpriv = ap->host->private_data;
197 struct xgene_ahci_context *ctx = hpriv->plat_data;
198 int rc = 0;
a3a84bc7
ST		 199 u32 port_fbs;
200 void *port_mmio = ahci_port_base(ap);
201
202 /*
203 * Write the pmp value to PxFBS.DEV
204 * for case of Port Mulitplier.
205 */
206 if (ctx->class[ap->port_no] == ATA_DEV_PMP) {
207 port_fbs = readl(port_mmio + PORT_FBS);
208 port_fbs &= ~PORT_FBS_DEV_MASK;
209 port_fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
210 writel(port_fbs, port_mmio + PORT_FBS);
211 }
2a0bdff6 212
1102407b
ST		 213 if (unlikely((ctx->last_cmd[ap->port_no] == ATA_CMD_ID_ATA) ||
214 (ctx->last_cmd[ap->port_no] == ATA_CMD_PACKET)))
2a0bdff6
ST		 215 xgene_ahci_restart_engine(ap);
216
217 rc = ahci_qc_issue(qc);
218
219 /* Save the last command issued */
220 ctx->last_cmd[ap->port_no] = qc->tf.command;
221
222 return rc;
223}
224
0bed13be
ST		 225static bool xgene_ahci_is_memram_inited(struct xgene_ahci_context *ctx)
226{
227 void __iomem *diagcsr = ctx->csr_diag;
228
229 return (readl(diagcsr + CFG_MEM_RAM_SHUTDOWN) == 0 &&
230 readl(diagcsr + BLOCK_MEM_RDY) == 0xFFFFFFFF);
231}
232
81d01bfa
LH		 233/**
234 * xgene_ahci_read_id - Read ID data from the specified device
235 * @dev: device
236 * @tf: proposed taskfile
237 * @id: data buffer
238 *
239 * This custom read ID function is required due to the fact that the HW
2a0bdff6 240 * does not support DEVSLP.
81d01bfa
LH		 241 */
242static unsigned int xgene_ahci_read_id(struct ata_device *dev,
243 struct ata_taskfile *tf, u16 *id)
244{
245 u32 err_mask;
81d01bfa
LH		 246
247 err_mask = ata_do_dev_read_id(dev, tf, id);
248 if (err_mask)
249 return err_mask;
250
251 /*
252 * Mask reserved area. Word78 spec of Link Power Management
253 * bit15-8: reserved
254 * bit7: NCQ autosence
255 * bit6: Software settings preservation supported
256 * bit5: reserved
257 * bit4: In-order sata delivery supported
258 * bit3: DIPM requests supported
259 * bit2: DMA Setup FIS Auto-Activate optimization supported
260 * bit1: DMA Setup FIX non-Zero buffer offsets supported
261 * bit0: Reserved
262 *
263 * Clear reserved bit 8 (DEVSLP bit) as we don't support DEVSLP
264 */
5c0b8e0d 265 id[ATA_ID_FEATURE_SUPP] &= cpu_to_le16(~(1 << 8));
81d01bfa 266
81d01bfa
LH		 267 return 0;
268}
269
270static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel)
271{
272 void __iomem *mmio = ctx->hpriv->mmio;
273 u32 val;
274
275 dev_dbg(ctx->dev, "port configure mmio 0x%p channel %d\n",
276 mmio, channel);
277 val = readl(mmio + PORTCFG);
278 val = PORTADDR_SET(val, channel == 0 ? 2 : 3);
279 writel(val, mmio + PORTCFG);
280 readl(mmio + PORTCFG); /* Force a barrier */
281 /* Disable fix rate */
282 writel(0x0001fffe, mmio + PORTPHY1CFG);
283 readl(mmio + PORTPHY1CFG); /* Force a barrier */
0185b1b7 284 writel(0x28183219, mmio + PORTPHY2CFG);
81d01bfa 285 readl(mmio + PORTPHY2CFG); /* Force a barrier */
0185b1b7 286 writel(0x13081008, mmio + PORTPHY3CFG);
81d01bfa 287 readl(mmio + PORTPHY3CFG); /* Force a barrier */
0185b1b7 288 writel(0x00480815, mmio + PORTPHY4CFG);
81d01bfa
LH		 289 readl(mmio + PORTPHY4CFG); /* Force a barrier */
290 /* Set window negotiation */
291 val = readl(mmio + PORTPHY5CFG);
292 val = PORTPHY5CFG_RTCHG_SET(val, 0x300);
293 writel(val, mmio + PORTPHY5CFG);
294 readl(mmio + PORTPHY5CFG); /* Force a barrier */
295 val = readl(mmio + PORTAXICFG);
296 val = PORTAXICFG_EN_CONTEXT_SET(val, 0x1); /* Enable context mgmt */
297 val = PORTAXICFG_OUTTRANS_SET(val, 0xe); /* Set outstanding */
298 writel(val, mmio + PORTAXICFG);
299 readl(mmio + PORTAXICFG); /* Force a barrier */
aeae4dca
ST		 300 /* Set the watermark threshold of the receive FIFO */
301 val = readl(mmio + PORTRANSCFG);
302 val = PORTRANSCFG_RXWM_SET(val, 0x30);
303 writel(val, mmio + PORTRANSCFG);
81d01bfa
LH		 304}
305
306/**
307 * xgene_ahci_do_hardreset - Issue the actual COMRESET
308 * @link: link to reset
309 * @deadline: deadline jiffies for the operation
310 * @online: Return value to indicate if device online
311 *
312 * Due to the limitation of the hardware PHY, a difference set of setting is
313 * required for each supported disk speed - Gen3 (6.0Gbps), Gen2 (3.0Gbps),
314 * and Gen1 (1.5Gbps). Otherwise during long IO stress test, the PHY will
315 * report disparity error and etc. In addition, during COMRESET, there can
316 * be error reported in the register PORT_SCR_ERR. For SERR_DISPARITY and
0babe614
ST		 317 * SERR_10B_8B_ERR, the PHY receiver line must be reseted. Also during long
318 * reboot cycle regression, sometimes the PHY reports link down even if the
319 * device is present because of speed negotiation failure. so need to retry
320 * the COMRESET to get the link up. The following algorithm is followed to
321 * proper configure the hardware PHY during COMRESET:
81d01bfa
LH		 322 *
323 * Alg Part 1:
324 * 1. Start the PHY at Gen3 speed (default setting)
325 * 2. Issue the COMRESET
326 * 3. If no link, go to Alg Part 3
327 * 4. If link up, determine if the negotiated speed matches the PHY
328 * configured speed
329 * 5. If they matched, go to Alg Part 2
330 * 6. If they do not matched and first time, configure the PHY for the linked
331 * up disk speed and repeat step 2
332 * 7. Go to Alg Part 2
333 *
334 * Alg Part 2:
335 * 1. On link up, if there are any SERR_DISPARITY and SERR_10B_8B_ERR error
336 * reported in the register PORT_SCR_ERR, then reset the PHY receiver line
0babe614 337 * 2. Go to Alg Part 4
81d01bfa
LH		 338 *
339 * Alg Part 3:
0babe614
ST		 340 * 1. Check the PORT_SCR_STAT to see whether device presence detected but PHY
341 * communication establishment failed and maximum link down attempts are
342 * less than Max attempts 3 then goto Alg Part 1.
343 * 2. Go to Alg Part 4.
344 *
345 * Alg Part 4:
81d01bfa
LH		 346 * 1. Clear any pending from register PORT_SCR_ERR.
347 *
348 * NOTE: For the initial version, we will NOT support Gen1/Gen2. In addition
349 * and until the underlying PHY supports an method to reset the receiver
350 * line, on detection of SERR_DISPARITY or SERR_10B_8B_ERR errors,
351 * an warning message will be printed.
352 */
353static int xgene_ahci_do_hardreset(struct ata_link *link,
354 unsigned long deadline, bool *online)
355{
356 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
357 struct ata_port *ap = link->ap;
358 struct ahci_host_priv *hpriv = ap->host->private_data;
359 struct xgene_ahci_context *ctx = hpriv->plat_data;
360 struct ahci_port_priv *pp = ap->private_data;
361 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
362 void __iomem *port_mmio = ahci_port_base(ap);
363 struct ata_taskfile tf;
0babe614 364 int link_down_retry = 0;
81d01bfa 365 int rc;
0babe614 366 u32 val, sstatus;
81d01bfa 367
0babe614
ST		 368 do {
369 /* clear D2H reception area to properly wait for D2H FIS */
370 ata_tf_init(link->device, &tf);
371 tf.command = ATA_BUSY;
372 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
373 rc = sata_link_hardreset(link, timing, deadline, online,
81d01bfa 374 ahci_check_ready);
0babe614
ST		 375 if (*online) {
376 val = readl(port_mmio + PORT_SCR_ERR);
377 if (val & (SERR_DISPARITY | SERR_10B_8B_ERR))
378 dev_warn(ctx->dev, "link has error\n");
379 break;
380 }
81d01bfa 381
0babe614
ST		 382 sata_scr_read(link, SCR_STATUS, &sstatus);
383 } while (link_down_retry++ < MAX_LINK_DOWN_RETRY &&
384 (sstatus & 0xff) == 0x1);
81d01bfa
LH		 385
386 /* clear all errors if any pending */
387 val = readl(port_mmio + PORT_SCR_ERR);
388 writel(val, port_mmio + PORT_SCR_ERR);
389
390 return rc;
391}
392
393static int xgene_ahci_hardreset(struct ata_link *link, unsigned int *class,
394 unsigned long deadline)
395{
396 struct ata_port *ap = link->ap;
397 struct ahci_host_priv *hpriv = ap->host->private_data;
398 void __iomem *port_mmio = ahci_port_base(ap);
399 bool online;
400 int rc;
401 u32 portcmd_saved;
402 u32 portclb_saved;
403 u32 portclbhi_saved;
404 u32 portrxfis_saved;
405 u32 portrxfishi_saved;
406
407 /* As hardreset resets these CSR, save it to restore later */
408 portcmd_saved = readl(port_mmio + PORT_CMD);
409 portclb_saved = readl(port_mmio + PORT_LST_ADDR);
410 portclbhi_saved = readl(port_mmio + PORT_LST_ADDR_HI);
411 portrxfis_saved = readl(port_mmio + PORT_FIS_ADDR);
412 portrxfishi_saved = readl(port_mmio + PORT_FIS_ADDR_HI);
413
414 ahci_stop_engine(ap);
415
416 rc = xgene_ahci_do_hardreset(link, deadline, &online);
417
418 /* As controller hardreset clears them, restore them */
419 writel(portcmd_saved, port_mmio + PORT_CMD);
420 writel(portclb_saved, port_mmio + PORT_LST_ADDR);
421 writel(portclbhi_saved, port_mmio + PORT_LST_ADDR_HI);
422 writel(portrxfis_saved, port_mmio + PORT_FIS_ADDR);
423 writel(portrxfishi_saved, port_mmio + PORT_FIS_ADDR_HI);
424
425 hpriv->start_engine(ap);
426
427 if (online)
428 *class = ahci_dev_classify(ap);
429
430 return rc;
431}
432
433static void xgene_ahci_host_stop(struct ata_host *host)
434{
435 struct ahci_host_priv *hpriv = host->private_data;
436
437 ahci_platform_disable_resources(hpriv);
438}
439
a3a84bc7
ST		 440/**
441 * xgene_ahci_pmp_softreset - Issue the softreset to the drives connected
442 * to Port Multiplier.
443 * @link: link to reset
444 * @class: Return value to indicate class of device
445 * @deadline: deadline jiffies for the operation
446 *
447 * Due to H/W errata, the controller is unable to save the PMP
448 * field fetched from command header before sending the H2D FIS.
449 * When the device returns the PMP port field in the D2H FIS, there is
450 * a mismatch and results in command completion failure. The workaround
451 * is to write the pmp value to PxFBS.DEV field before issuing any command
452 * to PMP.
453 */
454static int xgene_ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
455 unsigned long deadline)
456{
457 int pmp = sata_srst_pmp(link);
458 struct ata_port *ap = link->ap;
459 u32 rc;
460 void *port_mmio = ahci_port_base(ap);
461 u32 port_fbs;
462
463 /*
464 * Set PxFBS.DEV field with pmp
465 * value.
466 */
467 port_fbs = readl(port_mmio + PORT_FBS);
468 port_fbs &= ~PORT_FBS_DEV_MASK;
469 port_fbs |= pmp << PORT_FBS_DEV_OFFSET;
470 writel(port_fbs, port_mmio + PORT_FBS);
471
472 rc = ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
473
474 return rc;
475}
476
477/**
478 * xgene_ahci_softreset - Issue the softreset to the drive.
479 * @link: link to reset
480 * @class: Return value to indicate class of device
481 * @deadline: deadline jiffies for the operation
482 *
483 * Due to H/W errata, the controller is unable to save the PMP
484 * field fetched from command header before sending the H2D FIS.
485 * When the device returns the PMP port field in the D2H FIS, there is
486 * a mismatch and results in command completion failure. The workaround
487 * is to write the pmp value to PxFBS.DEV field before issuing any command
488 * to PMP. Here is the algorithm to detect PMP :
489 *
490 * 1. Save the PxFBS value
491 * 2. Program PxFBS.DEV with pmp value send by framework. Framework sends
492 * 0xF for both PMP/NON-PMP initially
493 * 3. Issue softreset
494 * 4. If signature class is PMP goto 6
495 * 5. restore the original PxFBS and goto 3
496 * 6. return
497 */
498static int xgene_ahci_softreset(struct ata_link *link, unsigned int *class,
499 unsigned long deadline)
500{
501 int pmp = sata_srst_pmp(link);
502 struct ata_port *ap = link->ap;
503 struct ahci_host_priv *hpriv = ap->host->private_data;
504 struct xgene_ahci_context *ctx = hpriv->plat_data;
505 void *port_mmio = ahci_port_base(ap);
506 u32 port_fbs;
507 u32 port_fbs_save;
508 u32 retry = 1;
509 u32 rc;
510
511 port_fbs_save = readl(port_mmio + PORT_FBS);
512
513 /*
514 * Set PxFBS.DEV field with pmp
515 * value.
516 */
517 port_fbs = readl(port_mmio + PORT_FBS);
518 port_fbs &= ~PORT_FBS_DEV_MASK;
519 port_fbs |= pmp << PORT_FBS_DEV_OFFSET;
520 writel(port_fbs, port_mmio + PORT_FBS);
521
522softreset_retry:
523 rc = ahci_do_softreset(link, class, pmp,
524 deadline, ahci_check_ready);
525
526 ctx->class[ap->port_no] = *class;
527 if (*class != ATA_DEV_PMP) {
528 /*
529 * Retry for normal drives without
530 * setting PxFBS.DEV field with pmp value.
531 */
532 if (retry--) {
533 writel(port_fbs_save, port_mmio + PORT_FBS);
534 goto softreset_retry;
535 }
536 }
537
538 return rc;
539}
540
81d01bfa
LH		 541static struct ata_port_operations xgene_ahci_ops = {
542 .inherits = &ahci_ops,
543 .host_stop = xgene_ahci_host_stop,
544 .hardreset = xgene_ahci_hardreset,
545 .read_id = xgene_ahci_read_id,
2a0bdff6 546 .qc_issue = xgene_ahci_qc_issue,
a3a84bc7
ST		 547 .softreset = xgene_ahci_softreset,
548 .pmp_softreset = xgene_ahci_pmp_softreset
81d01bfa
LH		 549};
550
551static const struct ata_port_info xgene_ahci_port_info = {
1540035d 552 .flags = AHCI_FLAG_COMMON | ATA_FLAG_PMP,
81d01bfa
LH		 553 .pio_mask = ATA_PIO4,
554 .udma_mask = ATA_UDMA6,
555 .port_ops = &xgene_ahci_ops,
556};
557
558static int xgene_ahci_hw_init(struct ahci_host_priv *hpriv)
559{
560 struct xgene_ahci_context *ctx = hpriv->plat_data;
561 int i;
562 int rc;
563 u32 val;
564
565 /* Remove IP RAM out of shutdown */
566 rc = xgene_ahci_init_memram(ctx);
567 if (rc)
568 return rc;
569
570 for (i = 0; i < MAX_AHCI_CHN_PERCTR; i++)
571 xgene_ahci_set_phy_cfg(ctx, i);
572
573 /* AXI disable Mask */
574 writel(0xffffffff, hpriv->mmio + HOST_IRQ_STAT);
575 readl(hpriv->mmio + HOST_IRQ_STAT); /* Force a barrier */
576 writel(0, ctx->csr_core + INTSTATUSMASK);
6a96918a 577 val = readl(ctx->csr_core + INTSTATUSMASK); /* Force a barrier */
81d01bfa
LH		 578 dev_dbg(ctx->dev, "top level interrupt mask 0x%X value 0x%08X\n",
579 INTSTATUSMASK, val);
580
581 writel(0x0, ctx->csr_core + ERRINTSTATUSMASK);
582 readl(ctx->csr_core + ERRINTSTATUSMASK); /* Force a barrier */
583 writel(0x0, ctx->csr_axi + INT_SLV_TMOMASK);
584 readl(ctx->csr_axi + INT_SLV_TMOMASK);
585
586 /* Enable AXI Interrupt */
587 writel(0xffffffff, ctx->csr_core + SLVRDERRATTRIBUTES);
588 writel(0xffffffff, ctx->csr_core + SLVWRERRATTRIBUTES);
589 writel(0xffffffff, ctx->csr_core + MSTRDERRATTRIBUTES);
590 writel(0xffffffff, ctx->csr_core + MSTWRERRATTRIBUTES);
591
592 /* Enable coherency */
593 val = readl(ctx->csr_core + BUSCTLREG);
594 val &= ~0x00000002; /* Enable write coherency */
595 val &= ~0x00000001; /* Enable read coherency */
596 writel(val, ctx->csr_core + BUSCTLREG);
597
598 val = readl(ctx->csr_core + IOFMSTRWAUX);
599 val |= (1 << 3); /* Enable read coherency */
600 val |= (1 << 9); /* Enable write coherency */
601 writel(val, ctx->csr_core + IOFMSTRWAUX);
602 val = readl(ctx->csr_core + IOFMSTRWAUX);
603 dev_dbg(ctx->dev, "coherency 0x%X value 0x%08X\n",
604 IOFMSTRWAUX, val);
605
606 return rc;
607}
608
609static int xgene_ahci_mux_select(struct xgene_ahci_context *ctx)
610{
611 u32 val;
612
613 /* Check for optional MUX resource */
a77b6ee9 614 if (!ctx->csr_mux)
81d01bfa
LH		 615 return 0;
616
617 val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);
618 val &= ~CFG_SATA_ENET_SELECT_MASK;
619 writel(val, ctx->csr_mux + SATA_ENET_CONFIG_REG);
620 val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);
621 return val & CFG_SATA_ENET_SELECT_MASK ? -1 : 0;
622}
623
624static int xgene_ahci_probe(struct platform_device *pdev)
625{
626 struct device *dev = &pdev->dev;
627 struct ahci_host_priv *hpriv;
628 struct xgene_ahci_context *ctx;
629 struct resource *res;
630 int rc;
631
632 hpriv = ahci_platform_get_resources(pdev);
633 if (IS_ERR(hpriv))
634 return PTR_ERR(hpriv);
635
636 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
637 if (!ctx)
638 return -ENOMEM;
639
640 hpriv->plat_data = ctx;
641 ctx->hpriv = hpriv;
642 ctx->dev = dev;
643
644 /* Retrieve the IP core resource */
645 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
646 ctx->csr_core = devm_ioremap_resource(dev, res);
647 if (IS_ERR(ctx->csr_core))
648 return PTR_ERR(ctx->csr_core);
649
650 /* Retrieve the IP diagnostic resource */
651 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
652 ctx->csr_diag = devm_ioremap_resource(dev, res);
653 if (IS_ERR(ctx->csr_diag))
654 return PTR_ERR(ctx->csr_diag);
655
656 /* Retrieve the IP AXI resource */
657 res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
658 ctx->csr_axi = devm_ioremap_resource(dev, res);
659 if (IS_ERR(ctx->csr_axi))
660 return PTR_ERR(ctx->csr_axi);
661
662 /* Retrieve the optional IP mux resource */
663 res = platform_get_resource(pdev, IORESOURCE_MEM, 4);
a77b6ee9
ST		 664 if (res) {
665 void __iomem *csr = devm_ioremap_resource(dev, res);
666 if (IS_ERR(csr))
667 return PTR_ERR(csr);
668
669 ctx->csr_mux = csr;
670 }
81d01bfa
LH		 671
672 dev_dbg(dev, "VAddr 0x%p Mmio VAddr 0x%p\n", ctx->csr_core,
673 hpriv->mmio);
674
675 /* Select ATA */
676 if ((rc = xgene_ahci_mux_select(ctx))) {
677 dev_err(dev, "SATA mux selection failed error %d\n", rc);
678 return -ENODEV;
679 }
680
0bed13be
ST		 681 if (xgene_ahci_is_memram_inited(ctx)) {
682 dev_info(dev, "skip clock and PHY initialization\n");
683 goto skip_clk_phy;
684 }
685
81d01bfa
LH		 686 /* Due to errata, HW requires full toggle transition */
687 rc = ahci_platform_enable_clks(hpriv);
688 if (rc)
689 goto disable_resources;
690 ahci_platform_disable_clks(hpriv);
691
692 rc = ahci_platform_enable_resources(hpriv);
693 if (rc)
694 goto disable_resources;
695
696 /* Configure the host controller */
697 xgene_ahci_hw_init(hpriv);
0bed13be 698skip_clk_phy:
72f79f9e 699 hpriv->flags = AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_NCQ;
f9f36917 700
725c7b57 701 rc = ahci_platform_init_host(pdev, hpriv, &xgene_ahci_port_info);
81d01bfa
LH		 702 if (rc)
703 goto disable_resources;
704
705 dev_dbg(dev, "X-Gene SATA host controller initialized\n");
706 return 0;
707
708disable_resources:
709 ahci_platform_disable_resources(hpriv);
710 return rc;
711}
712
713static const struct of_device_id xgene_ahci_of_match[] = {
714 {.compatible = "apm,xgene-ahci"},
715 {},
716};
717MODULE_DEVICE_TABLE(of, xgene_ahci_of_match);
718
719static struct platform_driver xgene_ahci_driver = {
720 .probe = xgene_ahci_probe,
721 .remove = ata_platform_remove_one,
722 .driver = {
723 .name = "xgene-ahci",
81d01bfa
LH		 724 .of_match_table = xgene_ahci_of_match,
725 },
726};
727
728module_platform_driver(xgene_ahci_driver);
729
730MODULE_DESCRIPTION("APM X-Gene AHCI SATA driver");
731MODULE_AUTHOR("Loc Ho <lho@apm.com>");
732MODULE_LICENSE("GPL");
733MODULE_VERSION("0.4");
Linux 6.x block layer and io_uring tree(s)