Commit | Line | Data |
---|---|---|
81d01bfa LH |
1 | /* |
2 | * AppliedMicro X-Gene SoC SATA Host Controller Driver | |
3 | * | |
4 | * Copyright (c) 2014, Applied Micro Circuits Corporation | |
5 | * Author: Loc Ho <lho@apm.com> | |
6 | * Tuan Phan <tphan@apm.com> | |
7 | * Suman Tripathi <stripathi@apm.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | * | |
22 | * NOTE: PM support is not currently available. | |
23 | * | |
24 | */ | |
25 | #include <linux/module.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/ahci_platform.h> | |
28 | #include <linux/of_address.h> | |
29 | #include <linux/of_irq.h> | |
30 | #include <linux/phy/phy.h> | |
31 | #include "ahci.h" | |
32 | ||
33 | /* Max # of disk per a controller */ | |
34 | #define MAX_AHCI_CHN_PERCTR 2 | |
35 | ||
36 | /* MUX CSR */ | |
37 | #define SATA_ENET_CONFIG_REG 0x00000000 | |
38 | #define CFG_SATA_ENET_SELECT_MASK 0x00000001 | |
39 | ||
40 | /* SATA core host controller CSR */ | |
41 | #define SLVRDERRATTRIBUTES 0x00000000 | |
42 | #define SLVWRERRATTRIBUTES 0x00000004 | |
43 | #define MSTRDERRATTRIBUTES 0x00000008 | |
44 | #define MSTWRERRATTRIBUTES 0x0000000c | |
45 | #define BUSCTLREG 0x00000014 | |
46 | #define IOFMSTRWAUX 0x00000018 | |
47 | #define INTSTATUSMASK 0x0000002c | |
48 | #define ERRINTSTATUS 0x00000030 | |
49 | #define ERRINTSTATUSMASK 0x00000034 | |
50 | ||
51 | /* SATA host AHCI CSR */ | |
52 | #define PORTCFG 0x000000a4 | |
53 | #define PORTADDR_SET(dst, src) \ | |
54 | (((dst) & ~0x0000003f) | (((u32)(src)) & 0x0000003f)) | |
55 | #define PORTPHY1CFG 0x000000a8 | |
56 | #define PORTPHY1CFG_FRCPHYRDY_SET(dst, src) \ | |
57 | (((dst) & ~0x00100000) | (((u32)(src) << 0x14) & 0x00100000)) | |
58 | #define PORTPHY2CFG 0x000000ac | |
59 | #define PORTPHY3CFG 0x000000b0 | |
60 | #define PORTPHY4CFG 0x000000b4 | |
61 | #define PORTPHY5CFG 0x000000b8 | |
62 | #define SCTL0 0x0000012C | |
63 | #define PORTPHY5CFG_RTCHG_SET(dst, src) \ | |
64 | (((dst) & ~0xfff00000) | (((u32)(src) << 0x14) & 0xfff00000)) | |
65 | #define PORTAXICFG_EN_CONTEXT_SET(dst, src) \ | |
66 | (((dst) & ~0x01000000) | (((u32)(src) << 0x18) & 0x01000000)) | |
67 | #define PORTAXICFG 0x000000bc | |
68 | #define PORTAXICFG_OUTTRANS_SET(dst, src) \ | |
69 | (((dst) & ~0x00f00000) | (((u32)(src) << 0x14) & 0x00f00000)) | |
70 | ||
71 | /* SATA host controller AXI CSR */ | |
72 | #define INT_SLV_TMOMASK 0x00000010 | |
73 | ||
74 | /* SATA diagnostic CSR */ | |
75 | #define CFG_MEM_RAM_SHUTDOWN 0x00000070 | |
76 | #define BLOCK_MEM_RDY 0x00000074 | |
77 | ||
78 | struct xgene_ahci_context { | |
79 | struct ahci_host_priv *hpriv; | |
80 | struct device *dev; | |
81 | void __iomem *csr_core; /* Core CSR address of IP */ | |
82 | void __iomem *csr_diag; /* Diag CSR address of IP */ | |
83 | void __iomem *csr_axi; /* AXI CSR address of IP */ | |
84 | void __iomem *csr_mux; /* MUX CSR address of IP */ | |
85 | }; | |
86 | ||
87 | static int xgene_ahci_init_memram(struct xgene_ahci_context *ctx) | |
88 | { | |
89 | dev_dbg(ctx->dev, "Release memory from shutdown\n"); | |
90 | writel(0x0, ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); | |
91 | readl(ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */ | |
92 | msleep(1); /* reset may take up to 1ms */ | |
93 | if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) { | |
94 | dev_err(ctx->dev, "failed to release memory from shutdown\n"); | |
95 | return -ENODEV; | |
96 | } | |
97 | return 0; | |
98 | } | |
99 | ||
100 | /** | |
101 | * xgene_ahci_read_id - Read ID data from the specified device | |
102 | * @dev: device | |
103 | * @tf: proposed taskfile | |
104 | * @id: data buffer | |
105 | * | |
106 | * This custom read ID function is required due to the fact that the HW | |
107 | * does not support DEVSLP and the controller state machine may get stuck | |
108 | * after processing the ID query command. | |
109 | */ | |
110 | static unsigned int xgene_ahci_read_id(struct ata_device *dev, | |
111 | struct ata_taskfile *tf, u16 *id) | |
112 | { | |
113 | u32 err_mask; | |
114 | void __iomem *port_mmio = ahci_port_base(dev->link->ap); | |
115 | ||
116 | err_mask = ata_do_dev_read_id(dev, tf, id); | |
117 | if (err_mask) | |
118 | return err_mask; | |
119 | ||
120 | /* | |
121 | * Mask reserved area. Word78 spec of Link Power Management | |
122 | * bit15-8: reserved | |
123 | * bit7: NCQ autosence | |
124 | * bit6: Software settings preservation supported | |
125 | * bit5: reserved | |
126 | * bit4: In-order sata delivery supported | |
127 | * bit3: DIPM requests supported | |
128 | * bit2: DMA Setup FIS Auto-Activate optimization supported | |
129 | * bit1: DMA Setup FIX non-Zero buffer offsets supported | |
130 | * bit0: Reserved | |
131 | * | |
132 | * Clear reserved bit 8 (DEVSLP bit) as we don't support DEVSLP | |
133 | */ | |
134 | id[ATA_ID_FEATURE_SUPP] &= ~(1 << 8); | |
135 | ||
136 | /* | |
137 | * Due to HW errata, restart the port if no other command active. | |
138 | * Otherwise the controller may get stuck. | |
139 | */ | |
140 | if (!readl(port_mmio + PORT_CMD_ISSUE)) { | |
141 | writel(PORT_CMD_FIS_RX, port_mmio + PORT_CMD); | |
142 | readl(port_mmio + PORT_CMD); /* Force a barrier */ | |
143 | writel(PORT_CMD_FIS_RX | PORT_CMD_START, port_mmio + PORT_CMD); | |
144 | readl(port_mmio + PORT_CMD); /* Force a barrier */ | |
145 | } | |
146 | return 0; | |
147 | } | |
148 | ||
149 | static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel) | |
150 | { | |
151 | void __iomem *mmio = ctx->hpriv->mmio; | |
152 | u32 val; | |
153 | ||
154 | dev_dbg(ctx->dev, "port configure mmio 0x%p channel %d\n", | |
155 | mmio, channel); | |
156 | val = readl(mmio + PORTCFG); | |
157 | val = PORTADDR_SET(val, channel == 0 ? 2 : 3); | |
158 | writel(val, mmio + PORTCFG); | |
159 | readl(mmio + PORTCFG); /* Force a barrier */ | |
160 | /* Disable fix rate */ | |
161 | writel(0x0001fffe, mmio + PORTPHY1CFG); | |
162 | readl(mmio + PORTPHY1CFG); /* Force a barrier */ | |
163 | writel(0x5018461c, mmio + PORTPHY2CFG); | |
164 | readl(mmio + PORTPHY2CFG); /* Force a barrier */ | |
165 | writel(0x1c081907, mmio + PORTPHY3CFG); | |
166 | readl(mmio + PORTPHY3CFG); /* Force a barrier */ | |
167 | writel(0x1c080815, mmio + PORTPHY4CFG); | |
168 | readl(mmio + PORTPHY4CFG); /* Force a barrier */ | |
169 | /* Set window negotiation */ | |
170 | val = readl(mmio + PORTPHY5CFG); | |
171 | val = PORTPHY5CFG_RTCHG_SET(val, 0x300); | |
172 | writel(val, mmio + PORTPHY5CFG); | |
173 | readl(mmio + PORTPHY5CFG); /* Force a barrier */ | |
174 | val = readl(mmio + PORTAXICFG); | |
175 | val = PORTAXICFG_EN_CONTEXT_SET(val, 0x1); /* Enable context mgmt */ | |
176 | val = PORTAXICFG_OUTTRANS_SET(val, 0xe); /* Set outstanding */ | |
177 | writel(val, mmio + PORTAXICFG); | |
178 | readl(mmio + PORTAXICFG); /* Force a barrier */ | |
179 | } | |
180 | ||
181 | /** | |
182 | * xgene_ahci_do_hardreset - Issue the actual COMRESET | |
183 | * @link: link to reset | |
184 | * @deadline: deadline jiffies for the operation | |
185 | * @online: Return value to indicate if device online | |
186 | * | |
187 | * Due to the limitation of the hardware PHY, a difference set of setting is | |
188 | * required for each supported disk speed - Gen3 (6.0Gbps), Gen2 (3.0Gbps), | |
189 | * and Gen1 (1.5Gbps). Otherwise during long IO stress test, the PHY will | |
190 | * report disparity error and etc. In addition, during COMRESET, there can | |
191 | * be error reported in the register PORT_SCR_ERR. For SERR_DISPARITY and | |
192 | * SERR_10B_8B_ERR, the PHY receiver line must be reseted. The following | |
193 | * algorithm is followed to proper configure the hardware PHY during COMRESET: | |
194 | * | |
195 | * Alg Part 1: | |
196 | * 1. Start the PHY at Gen3 speed (default setting) | |
197 | * 2. Issue the COMRESET | |
198 | * 3. If no link, go to Alg Part 3 | |
199 | * 4. If link up, determine if the negotiated speed matches the PHY | |
200 | * configured speed | |
201 | * 5. If they matched, go to Alg Part 2 | |
202 | * 6. If they do not matched and first time, configure the PHY for the linked | |
203 | * up disk speed and repeat step 2 | |
204 | * 7. Go to Alg Part 2 | |
205 | * | |
206 | * Alg Part 2: | |
207 | * 1. On link up, if there are any SERR_DISPARITY and SERR_10B_8B_ERR error | |
208 | * reported in the register PORT_SCR_ERR, then reset the PHY receiver line | |
209 | * 2. Go to Alg Part 3 | |
210 | * | |
211 | * Alg Part 3: | |
212 | * 1. Clear any pending from register PORT_SCR_ERR. | |
213 | * | |
214 | * NOTE: For the initial version, we will NOT support Gen1/Gen2. In addition | |
215 | * and until the underlying PHY supports an method to reset the receiver | |
216 | * line, on detection of SERR_DISPARITY or SERR_10B_8B_ERR errors, | |
217 | * an warning message will be printed. | |
218 | */ | |
219 | static int xgene_ahci_do_hardreset(struct ata_link *link, | |
220 | unsigned long deadline, bool *online) | |
221 | { | |
222 | const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); | |
223 | struct ata_port *ap = link->ap; | |
224 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
225 | struct xgene_ahci_context *ctx = hpriv->plat_data; | |
226 | struct ahci_port_priv *pp = ap->private_data; | |
227 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
228 | void __iomem *port_mmio = ahci_port_base(ap); | |
229 | struct ata_taskfile tf; | |
230 | int rc; | |
231 | u32 val; | |
232 | ||
233 | /* clear D2H reception area to properly wait for D2H FIS */ | |
234 | ata_tf_init(link->device, &tf); | |
235 | tf.command = ATA_BUSY; | |
236 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); | |
237 | rc = sata_link_hardreset(link, timing, deadline, online, | |
238 | ahci_check_ready); | |
239 | ||
240 | val = readl(port_mmio + PORT_SCR_ERR); | |
241 | if (val & (SERR_DISPARITY | SERR_10B_8B_ERR)) | |
242 | dev_warn(ctx->dev, "link has error\n"); | |
243 | ||
244 | /* clear all errors if any pending */ | |
245 | val = readl(port_mmio + PORT_SCR_ERR); | |
246 | writel(val, port_mmio + PORT_SCR_ERR); | |
247 | ||
248 | return rc; | |
249 | } | |
250 | ||
251 | static int xgene_ahci_hardreset(struct ata_link *link, unsigned int *class, | |
252 | unsigned long deadline) | |
253 | { | |
254 | struct ata_port *ap = link->ap; | |
255 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
256 | void __iomem *port_mmio = ahci_port_base(ap); | |
257 | bool online; | |
258 | int rc; | |
259 | u32 portcmd_saved; | |
260 | u32 portclb_saved; | |
261 | u32 portclbhi_saved; | |
262 | u32 portrxfis_saved; | |
263 | u32 portrxfishi_saved; | |
264 | ||
265 | /* As hardreset resets these CSR, save it to restore later */ | |
266 | portcmd_saved = readl(port_mmio + PORT_CMD); | |
267 | portclb_saved = readl(port_mmio + PORT_LST_ADDR); | |
268 | portclbhi_saved = readl(port_mmio + PORT_LST_ADDR_HI); | |
269 | portrxfis_saved = readl(port_mmio + PORT_FIS_ADDR); | |
270 | portrxfishi_saved = readl(port_mmio + PORT_FIS_ADDR_HI); | |
271 | ||
272 | ahci_stop_engine(ap); | |
273 | ||
274 | rc = xgene_ahci_do_hardreset(link, deadline, &online); | |
275 | ||
276 | /* As controller hardreset clears them, restore them */ | |
277 | writel(portcmd_saved, port_mmio + PORT_CMD); | |
278 | writel(portclb_saved, port_mmio + PORT_LST_ADDR); | |
279 | writel(portclbhi_saved, port_mmio + PORT_LST_ADDR_HI); | |
280 | writel(portrxfis_saved, port_mmio + PORT_FIS_ADDR); | |
281 | writel(portrxfishi_saved, port_mmio + PORT_FIS_ADDR_HI); | |
282 | ||
283 | hpriv->start_engine(ap); | |
284 | ||
285 | if (online) | |
286 | *class = ahci_dev_classify(ap); | |
287 | ||
288 | return rc; | |
289 | } | |
290 | ||
291 | static void xgene_ahci_host_stop(struct ata_host *host) | |
292 | { | |
293 | struct ahci_host_priv *hpriv = host->private_data; | |
294 | ||
295 | ahci_platform_disable_resources(hpriv); | |
296 | } | |
297 | ||
298 | static struct ata_port_operations xgene_ahci_ops = { | |
299 | .inherits = &ahci_ops, | |
300 | .host_stop = xgene_ahci_host_stop, | |
301 | .hardreset = xgene_ahci_hardreset, | |
302 | .read_id = xgene_ahci_read_id, | |
303 | }; | |
304 | ||
305 | static const struct ata_port_info xgene_ahci_port_info = { | |
306 | AHCI_HFLAGS(AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ), | |
307 | .flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ, | |
308 | .pio_mask = ATA_PIO4, | |
309 | .udma_mask = ATA_UDMA6, | |
310 | .port_ops = &xgene_ahci_ops, | |
311 | }; | |
312 | ||
313 | static int xgene_ahci_hw_init(struct ahci_host_priv *hpriv) | |
314 | { | |
315 | struct xgene_ahci_context *ctx = hpriv->plat_data; | |
316 | int i; | |
317 | int rc; | |
318 | u32 val; | |
319 | ||
320 | /* Remove IP RAM out of shutdown */ | |
321 | rc = xgene_ahci_init_memram(ctx); | |
322 | if (rc) | |
323 | return rc; | |
324 | ||
325 | for (i = 0; i < MAX_AHCI_CHN_PERCTR; i++) | |
326 | xgene_ahci_set_phy_cfg(ctx, i); | |
327 | ||
328 | /* AXI disable Mask */ | |
329 | writel(0xffffffff, hpriv->mmio + HOST_IRQ_STAT); | |
330 | readl(hpriv->mmio + HOST_IRQ_STAT); /* Force a barrier */ | |
331 | writel(0, ctx->csr_core + INTSTATUSMASK); | |
6a96918a | 332 | val = readl(ctx->csr_core + INTSTATUSMASK); /* Force a barrier */ |
81d01bfa LH |
333 | dev_dbg(ctx->dev, "top level interrupt mask 0x%X value 0x%08X\n", |
334 | INTSTATUSMASK, val); | |
335 | ||
336 | writel(0x0, ctx->csr_core + ERRINTSTATUSMASK); | |
337 | readl(ctx->csr_core + ERRINTSTATUSMASK); /* Force a barrier */ | |
338 | writel(0x0, ctx->csr_axi + INT_SLV_TMOMASK); | |
339 | readl(ctx->csr_axi + INT_SLV_TMOMASK); | |
340 | ||
341 | /* Enable AXI Interrupt */ | |
342 | writel(0xffffffff, ctx->csr_core + SLVRDERRATTRIBUTES); | |
343 | writel(0xffffffff, ctx->csr_core + SLVWRERRATTRIBUTES); | |
344 | writel(0xffffffff, ctx->csr_core + MSTRDERRATTRIBUTES); | |
345 | writel(0xffffffff, ctx->csr_core + MSTWRERRATTRIBUTES); | |
346 | ||
347 | /* Enable coherency */ | |
348 | val = readl(ctx->csr_core + BUSCTLREG); | |
349 | val &= ~0x00000002; /* Enable write coherency */ | |
350 | val &= ~0x00000001; /* Enable read coherency */ | |
351 | writel(val, ctx->csr_core + BUSCTLREG); | |
352 | ||
353 | val = readl(ctx->csr_core + IOFMSTRWAUX); | |
354 | val |= (1 << 3); /* Enable read coherency */ | |
355 | val |= (1 << 9); /* Enable write coherency */ | |
356 | writel(val, ctx->csr_core + IOFMSTRWAUX); | |
357 | val = readl(ctx->csr_core + IOFMSTRWAUX); | |
358 | dev_dbg(ctx->dev, "coherency 0x%X value 0x%08X\n", | |
359 | IOFMSTRWAUX, val); | |
360 | ||
361 | return rc; | |
362 | } | |
363 | ||
364 | static int xgene_ahci_mux_select(struct xgene_ahci_context *ctx) | |
365 | { | |
366 | u32 val; | |
367 | ||
368 | /* Check for optional MUX resource */ | |
369 | if (IS_ERR(ctx->csr_mux)) | |
370 | return 0; | |
371 | ||
372 | val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG); | |
373 | val &= ~CFG_SATA_ENET_SELECT_MASK; | |
374 | writel(val, ctx->csr_mux + SATA_ENET_CONFIG_REG); | |
375 | val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG); | |
376 | return val & CFG_SATA_ENET_SELECT_MASK ? -1 : 0; | |
377 | } | |
378 | ||
379 | static int xgene_ahci_probe(struct platform_device *pdev) | |
380 | { | |
381 | struct device *dev = &pdev->dev; | |
382 | struct ahci_host_priv *hpriv; | |
383 | struct xgene_ahci_context *ctx; | |
384 | struct resource *res; | |
385 | int rc; | |
386 | ||
387 | hpriv = ahci_platform_get_resources(pdev); | |
388 | if (IS_ERR(hpriv)) | |
389 | return PTR_ERR(hpriv); | |
390 | ||
391 | ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); | |
392 | if (!ctx) | |
393 | return -ENOMEM; | |
394 | ||
395 | hpriv->plat_data = ctx; | |
396 | ctx->hpriv = hpriv; | |
397 | ctx->dev = dev; | |
398 | ||
399 | /* Retrieve the IP core resource */ | |
400 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
401 | ctx->csr_core = devm_ioremap_resource(dev, res); | |
402 | if (IS_ERR(ctx->csr_core)) | |
403 | return PTR_ERR(ctx->csr_core); | |
404 | ||
405 | /* Retrieve the IP diagnostic resource */ | |
406 | res = platform_get_resource(pdev, IORESOURCE_MEM, 2); | |
407 | ctx->csr_diag = devm_ioremap_resource(dev, res); | |
408 | if (IS_ERR(ctx->csr_diag)) | |
409 | return PTR_ERR(ctx->csr_diag); | |
410 | ||
411 | /* Retrieve the IP AXI resource */ | |
412 | res = platform_get_resource(pdev, IORESOURCE_MEM, 3); | |
413 | ctx->csr_axi = devm_ioremap_resource(dev, res); | |
414 | if (IS_ERR(ctx->csr_axi)) | |
415 | return PTR_ERR(ctx->csr_axi); | |
416 | ||
417 | /* Retrieve the optional IP mux resource */ | |
418 | res = platform_get_resource(pdev, IORESOURCE_MEM, 4); | |
419 | ctx->csr_mux = devm_ioremap_resource(dev, res); | |
420 | ||
421 | dev_dbg(dev, "VAddr 0x%p Mmio VAddr 0x%p\n", ctx->csr_core, | |
422 | hpriv->mmio); | |
423 | ||
424 | /* Select ATA */ | |
425 | if ((rc = xgene_ahci_mux_select(ctx))) { | |
426 | dev_err(dev, "SATA mux selection failed error %d\n", rc); | |
427 | return -ENODEV; | |
428 | } | |
429 | ||
430 | /* Due to errata, HW requires full toggle transition */ | |
431 | rc = ahci_platform_enable_clks(hpriv); | |
432 | if (rc) | |
433 | goto disable_resources; | |
434 | ahci_platform_disable_clks(hpriv); | |
435 | ||
436 | rc = ahci_platform_enable_resources(hpriv); | |
437 | if (rc) | |
438 | goto disable_resources; | |
439 | ||
440 | /* Configure the host controller */ | |
441 | xgene_ahci_hw_init(hpriv); | |
442 | ||
443 | /* | |
444 | * Setup DMA mask. This is preliminary until the DMA range is sorted | |
445 | * out. | |
446 | */ | |
447 | rc = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); | |
448 | if (rc) { | |
449 | dev_err(dev, "Unable to set dma mask\n"); | |
450 | goto disable_resources; | |
451 | } | |
452 | ||
453 | rc = ahci_platform_init_host(pdev, hpriv, &xgene_ahci_port_info, 0, 0); | |
454 | if (rc) | |
455 | goto disable_resources; | |
456 | ||
457 | dev_dbg(dev, "X-Gene SATA host controller initialized\n"); | |
458 | return 0; | |
459 | ||
460 | disable_resources: | |
461 | ahci_platform_disable_resources(hpriv); | |
462 | return rc; | |
463 | } | |
464 | ||
465 | static const struct of_device_id xgene_ahci_of_match[] = { | |
466 | {.compatible = "apm,xgene-ahci"}, | |
467 | {}, | |
468 | }; | |
469 | MODULE_DEVICE_TABLE(of, xgene_ahci_of_match); | |
470 | ||
471 | static struct platform_driver xgene_ahci_driver = { | |
472 | .probe = xgene_ahci_probe, | |
473 | .remove = ata_platform_remove_one, | |
474 | .driver = { | |
475 | .name = "xgene-ahci", | |
476 | .owner = THIS_MODULE, | |
477 | .of_match_table = xgene_ahci_of_match, | |
478 | }, | |
479 | }; | |
480 | ||
481 | module_platform_driver(xgene_ahci_driver); | |
482 | ||
483 | MODULE_DESCRIPTION("APM X-Gene AHCI SATA driver"); | |
484 | MODULE_AUTHOR("Loc Ho <lho@apm.com>"); | |
485 | MODULE_LICENSE("GPL"); | |
486 | MODULE_VERSION("0.4"); |