[linux-2.6-block.git] / drivers / ata / ahci_qoriq.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Freescale QorIQ AHCI SATA platform driver
 *
 * Copyright 2015 Freescale, Inc.
 *   Tang Yuantian <Yuantian.Tang@freescale.com>
 */

#include <linux/acpi.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/ahci_platform.h>
#include <linux/device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/libata.h>
#include "ahci.h"

#define DRV_NAME "ahci-qoriq"

/* port register definition */
#define PORT_PHY1	0xA8
#define PORT_PHY2	0xAC
#define PORT_PHY3	0xB0
#define PORT_PHY4	0xB4
#define PORT_PHY5	0xB8
#define PORT_AXICC	0xBC
#define PORT_TRANS	0xC8

/* port register default value */
#define AHCI_PORT_PHY_1_CFG	0xa003fffe
#define AHCI_PORT_PHY2_CFG	0x28184d1f
#define AHCI_PORT_PHY3_CFG	0x0e081509
#define AHCI_PORT_TRANS_CFG	0x08000029
#define AHCI_PORT_AXICC_CFG	0x3fffffff

/* for ls1021a */
#define LS1021A_PORT_PHY2	0x28183414
#define LS1021A_PORT_PHY3	0x0e080e06
#define LS1021A_PORT_PHY4	0x064a080b
#define LS1021A_PORT_PHY5	0x2aa86470
#define LS1021A_AXICC_ADDR	0xC0

#define SATA_ECC_DISABLE	0x00020000
#define ECC_DIS_ARMV8_CH2	0x80000000
#define ECC_DIS_LS1088A		0x40000000

enum ahci_qoriq_type {
	AHCI_LS1021A,
	AHCI_LS1028A,
	AHCI_LS1043A,
	AHCI_LS2080A,
	AHCI_LS1046A,
	AHCI_LS1088A,
	AHCI_LS2088A,
	AHCI_LX2160A,
};

struct ahci_qoriq_priv {
	struct ccsr_ahci *reg_base;
	enum ahci_qoriq_type type;
	void __iomem *ecc_addr;
	bool is_dmacoherent;
};

static bool ecc_initialized;

static const struct of_device_id ahci_qoriq_of_match[] = {
	{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
	{ .compatible = "fsl,ls1028a-ahci", .data = (void *)AHCI_LS1028A},
	{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
	{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
	{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
	{ .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
	{ .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
	{ .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);

static const struct acpi_device_id ahci_qoriq_acpi_match[] = {
	{"NXP0004", .driver_data = (kernel_ulong_t)AHCI_LX2160A},
	{ }
};
MODULE_DEVICE_TABLE(acpi, ahci_qoriq_acpi_match);

static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
			  unsigned long deadline)
{
	const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
	void __iomem *port_mmio = ahci_port_base(link->ap);
	u32 px_cmd, px_is, px_val;
	struct ata_port *ap = link->ap;
	struct ahci_port_priv *pp = ap->private_data;
	struct ahci_host_priv *hpriv = ap->host->private_data;
	struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	struct ata_taskfile tf;
	bool online;
	int rc;
	bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);

	hpriv->stop_engine(ap);

	/*
	 * There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
	 * A-009042: The device detection initialization sequence
	 * mistakenly resets some registers.
	 *
	 * Workaround for this is:
	 * The software should read and store PxCMD and PxIS values
	 * before issuing the device detection initialization sequence.
	 * After the sequence is complete, software should restore the
	 * PxCMD and PxIS with the stored values.
	 */
	if (ls1021a_workaround) {
		px_cmd = readl(port_mmio + PORT_CMD);
		px_is = readl(port_mmio + PORT_IRQ_STAT);
	}

	/* clear D2H reception area to properly wait for D2H FIS */
	ata_tf_init(link->device, &tf);
	tf.status = ATA_BUSY;
	ata_tf_to_fis(&tf, 0, 0, d2h_fis);

	rc = sata_link_hardreset(link, timing, deadline, &online,
				 ahci_check_ready);

	/* restore the PxCMD and PxIS on ls1021 */
	if (ls1021a_workaround) {
		px_val = readl(port_mmio + PORT_CMD);
		if (px_val != px_cmd)
			writel(px_cmd, port_mmio + PORT_CMD);

		px_val = readl(port_mmio + PORT_IRQ_STAT);
		if (px_val != px_is)
			writel(px_is, port_mmio + PORT_IRQ_STAT);
	}

	hpriv->start_engine(ap);

	if (online)
		*class = ahci_dev_classify(ap);
	return rc;
}

static struct ata_port_operations ahci_qoriq_ops = {
	.inherits	= &ahci_ops,
	.hardreset	= ahci_qoriq_hardreset,
};

static const struct ata_port_info ahci_qoriq_port_info = {
	.flags		= AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
	.pio_mask	= ATA_PIO4,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &ahci_qoriq_ops,
};

static const struct scsi_host_template ahci_qoriq_sht = {
	AHCI_SHT(DRV_NAME),
};

static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
{
	struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
	void __iomem *reg_base = hpriv->mmio;

	switch (qpriv->type) {
	case AHCI_LS1021A:
		if (!(qpriv->ecc_addr || ecc_initialized))
			return -EINVAL;
		else if (qpriv->ecc_addr && !ecc_initialized)
			writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
		writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
		writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
		writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG,
					reg_base + LS1021A_AXICC_ADDR);
		break;

	case AHCI_LS1043A:
		if (!(qpriv->ecc_addr || ecc_initialized))
			return -EINVAL;
		else if (qpriv->ecc_addr && !ecc_initialized)
			writel(readl(qpriv->ecc_addr) |
			       ECC_DIS_ARMV8_CH2,
			       qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS2080A:
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS1046A:
		if (!(qpriv->ecc_addr || ecc_initialized))
			return -EINVAL;
		else if (qpriv->ecc_addr && !ecc_initialized)
			writel(readl(qpriv->ecc_addr) |
			       ECC_DIS_ARMV8_CH2,
			       qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS1028A:
	case AHCI_LS1088A:
	case AHCI_LX2160A:
		if (!(qpriv->ecc_addr || ecc_initialized))
			return -EINVAL;
		else if (qpriv->ecc_addr && !ecc_initialized)
			writel(readl(qpriv->ecc_addr) |
			       ECC_DIS_LS1088A,
			       qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS2088A:
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;
	}

	ecc_initialized = true;
	return 0;
}

static int ahci_qoriq_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	const struct acpi_device_id *acpi_id;
	struct device *dev = &pdev->dev;
	struct ahci_host_priv *hpriv;
	struct ahci_qoriq_priv *qoriq_priv;
	const struct of_device_id *of_id;
	struct resource *res;
	int rc;

	hpriv = ahci_platform_get_resources(pdev, 0);
	if (IS_ERR(hpriv))
		return PTR_ERR(hpriv);

	of_id = of_match_node(ahci_qoriq_of_match, np);
	acpi_id = acpi_match_device(ahci_qoriq_acpi_match, &pdev->dev);
	if (!(of_id || acpi_id))
		return -ENODEV;

	qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
	if (!qoriq_priv)
		return -ENOMEM;

	if (of_id)
		qoriq_priv->type = (unsigned long)of_id->data;
	else
		qoriq_priv->type = (enum ahci_qoriq_type)acpi_id->driver_data;

	if (unlikely(!ecc_initialized)) {
		res = platform_get_resource_byname(pdev,
						   IORESOURCE_MEM,
						   "sata-ecc");
		if (res) {
			qoriq_priv->ecc_addr =
				devm_ioremap_resource(dev, res);
			if (IS_ERR(qoriq_priv->ecc_addr))
				return PTR_ERR(qoriq_priv->ecc_addr);
		}
	}

	if (device_get_dma_attr(&pdev->dev) == DEV_DMA_COHERENT)
		qoriq_priv->is_dmacoherent = true;

	rc = ahci_platform_enable_resources(hpriv);
	if (rc)
		return rc;

	hpriv->plat_data = qoriq_priv;
	rc = ahci_qoriq_phy_init(hpriv);
	if (rc)
		goto disable_resources;

	rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
				     &ahci_qoriq_sht);
	if (rc)
		goto disable_resources;

	return 0;

disable_resources:
	ahci_platform_disable_resources(hpriv);

	return rc;
}

#ifdef CONFIG_PM_SLEEP
static int ahci_qoriq_resume(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	int rc;

	rc = ahci_platform_enable_resources(hpriv);
	if (rc)
		return rc;

	rc = ahci_qoriq_phy_init(hpriv);
	if (rc)
		goto disable_resources;

	rc = ahci_platform_resume_host(dev);
	if (rc)
		goto disable_resources;

	/* We resumed so update PM runtime state */
	pm_runtime_disable(dev);
	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);

	return 0;

disable_resources:
	ahci_platform_disable_resources(hpriv);

	return rc;
}
#endif

static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
			 ahci_qoriq_resume);

static struct platform_driver ahci_qoriq_driver = {
	.probe = ahci_qoriq_probe,
	.remove_new = ata_platform_remove_one,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = ahci_qoriq_of_match,
		.acpi_match_table = ahci_qoriq_acpi_match,
		.pm = &ahci_qoriq_pm_ops,
	},
};
module_platform_driver(ahci_qoriq_driver);

MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
8d7c56d0	1	// SPDX-License-Identifier: GPL-2.0-or-later
ecfb4598 TY	2	/*
	3	* Freescale QorIQ AHCI SATA platform driver
	4	*
	5	* Copyright 2015 Freescale, Inc.
	6	* Tang Yuantian <Yuantian.Tang@freescale.com>
ecfb4598 TY	7	*/
ecfb4598 TY	8
564a7eed	9	#include <linux/acpi.h>
ecfb4598 TY	10	#include <linux/kernel.h>
	11	#include <linux/module.h>
	12	#include <linux/pm.h>
	13	#include <linux/ahci_platform.h>
	14	#include <linux/device.h>
ecfb4598	15	#include <linux/of.h>
ecfb4598 TY	16	#include <linux/platform_device.h>
	17	#include <linux/libata.h>
	18	#include "ahci.h"
	19
	20	#define DRV_NAME "ahci-qoriq"
	21
	22	/* port register definition */
	23	#define PORT_PHY1 0xA8
	24	#define PORT_PHY2 0xAC
	25	#define PORT_PHY3 0xB0
	26	#define PORT_PHY4 0xB4
	27	#define PORT_PHY5 0xB8
16af080e	28	#define PORT_AXICC 0xBC
ecfb4598 TY	29	#define PORT_TRANS 0xC8
	30
	31	/* port register default value */
	32	#define AHCI_PORT_PHY_1_CFG 0xa003fffe
ce179cbd YT	33	#define AHCI_PORT_PHY2_CFG 0x28184d1f
ce179cbd YT	34	#define AHCI_PORT_PHY3_CFG 0x0e081509
e3a6dadc	35	#define AHCI_PORT_TRANS_CFG 0x08000029
16af080e	36	#define AHCI_PORT_AXICC_CFG 0x3fffffff
dfcdc5fe TY	37
	38	/* for ls1021a */
	39	#define LS1021A_PORT_PHY2 0x28183414
	40	#define LS1021A_PORT_PHY3 0x0e080e06
	41	#define LS1021A_PORT_PHY4 0x064a080b
	42	#define LS1021A_PORT_PHY5 0x2aa86470
16af080e	43	#define LS1021A_AXICC_ADDR 0xC0
ecfb4598 TY	44
ecfb4598 TY	45	#define SATA_ECC_DISABLE 0x00020000
01f2901a	46	#define ECC_DIS_ARMV8_CH2 0x80000000
0cee73f7	47	#define ECC_DIS_LS1088A 0x40000000
ecfb4598 TY	48
	49	enum ahci_qoriq_type {
	50	AHCI_LS1021A,
a1d78317	51	AHCI_LS1028A,
ecfb4598	52	AHCI_LS1043A,
d19f9aaf	53	AHCI_LS2080A,
2facc6da	54	AHCI_LS1046A,
0cee73f7	55	AHCI_LS1088A,
ce8f4537	56	AHCI_LS2088A,
2be8481a	57	AHCI_LX2160A,
ecfb4598 TY	58	};
	59
	60	struct ahci_qoriq_priv {
	61	struct ccsr_ahci *reg_base;
	62	enum ahci_qoriq_type type;
	63	void __iomem *ecc_addr;
386dc3b8	64	bool is_dmacoherent;
ecfb4598 TY	65	};
ecfb4598 TY	66
2be8481a PM	67	static bool ecc_initialized;
2be8481a PM	68
ecfb4598 TY	69	static const struct of_device_id ahci_qoriq_of_match[] = {
ecfb4598 TY	70	{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
a1d78317	71	{ .compatible = "fsl,ls1028a-ahci", .data = (void *)AHCI_LS1028A},
ecfb4598	72	{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
d19f9aaf	73	{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
2facc6da	74	{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
0cee73f7	75	{ .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
ce8f4537	76	{ .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
2be8481a	77	{ .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
5e776d7b	78	{ /* sentinel */ }
ecfb4598 TY	79	};
	80	MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
	81
564a7eed YT	82	static const struct acpi_device_id ahci_qoriq_acpi_match[] = {
	83	{"NXP0004", .driver_data = (kernel_ulong_t)AHCI_LX2160A},
	84	{ }
	85	};
	86	MODULE_DEVICE_TABLE(acpi, ahci_qoriq_acpi_match);
	87
ecfb4598 TY	88	static int ahci_qoriq_hardreset(struct ata_link link, unsigned int class,
	89	unsigned long deadline)
	90	{
d14d41cc	91	const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
ecfb4598 TY	92	void __iomem *port_mmio = ahci_port_base(link->ap);
	93	u32 px_cmd, px_is, px_val;
	94	struct ata_port *ap = link->ap;
	95	struct ahci_port_priv *pp = ap->private_data;
	96	struct ahci_host_priv *hpriv = ap->host->private_data;
	97	struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
	98	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	99	struct ata_taskfile tf;
	100	bool online;
	101	int rc;
eb351031	102	bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);
ecfb4598	103
fa89f53b	104	hpriv->stop_engine(ap);
ecfb4598 TY	105
	106	/*
	107	* There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
	108	* A-009042: The device detection initialization sequence
	109	* mistakenly resets some registers.
	110	*
	111	* Workaround for this is:
	112	* The software should read and store PxCMD and PxIS values
	113	* before issuing the device detection initialization sequence.
	114	* After the sequence is complete, software should restore the
	115	* PxCMD and PxIS with the stored values.
	116	*/
eb351031	117	if (ls1021a_workaround) {
ecfb4598 TY	118	px_cmd = readl(port_mmio + PORT_CMD);
	119	px_is = readl(port_mmio + PORT_IRQ_STAT);
	120	}
	121
	122	/* clear D2H reception area to properly wait for D2H FIS */
	123	ata_tf_init(link->device, &tf);
efcef265	124	tf.status = ATA_BUSY;
ecfb4598 TY	125	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
	126
	127	rc = sata_link_hardreset(link, timing, deadline, &online,
	128	ahci_check_ready);
	129
	130	/* restore the PxCMD and PxIS on ls1021 */
eb351031	131	if (ls1021a_workaround) {
ecfb4598 TY	132	px_val = readl(port_mmio + PORT_CMD);
	133	if (px_val != px_cmd)
	134	writel(px_cmd, port_mmio + PORT_CMD);
	135
	136	px_val = readl(port_mmio + PORT_IRQ_STAT);
	137	if (px_val != px_is)
	138	writel(px_is, port_mmio + PORT_IRQ_STAT);
	139	}
	140
	141	hpriv->start_engine(ap);
	142
	143	if (online)
	144	*class = ahci_dev_classify(ap);
ecfb4598 TY	145	return rc;
	146	}
	147
	148	static struct ata_port_operations ahci_qoriq_ops = {
	149	.inherits = &ahci_ops,
	150	.hardreset = ahci_qoriq_hardreset,
	151	};
	152
1ce788d2	153	static const struct ata_port_info ahci_qoriq_port_info = {
ecfb4598 TY	154	.flags = AHCI_FLAG_COMMON \| ATA_FLAG_NCQ,
	155	.pio_mask = ATA_PIO4,
	156	.udma_mask = ATA_UDMA6,
	157	.port_ops = &ahci_qoriq_ops,
	158	};
	159
25df73d9	160	static const struct scsi_host_template ahci_qoriq_sht = {
ecfb4598 TY	161	AHCI_SHT(DRV_NAME),
	162	};
	163
	164	static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
	165	{
	166	struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
	167	void __iomem *reg_base = hpriv->mmio;
	168
	169	switch (qpriv->type) {
	170	case AHCI_LS1021A:
2be8481a	171	if (!(qpriv->ecc_addr \|\| ecc_initialized))
01f2901a	172	return -EINVAL;
2be8481a PM	173	else if (qpriv->ecc_addr && !ecc_initialized)
2be8481a PM	174	writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
ecfb4598	175	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
dfcdc5fe TY	176	writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
	177	writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
	178	writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
	179	writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
ecfb4598	180	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	181	if (qpriv->is_dmacoherent)
	182	writel(AHCI_PORT_AXICC_CFG,
	183	reg_base + LS1021A_AXICC_ADDR);
ecfb4598 TY	184	break;
	185
	186	case AHCI_LS1043A:
2be8481a	187	if (!(qpriv->ecc_addr \|\| ecc_initialized))
01f2901a	188	return -EINVAL;
2be8481a PM	189	else if (qpriv->ecc_addr && !ecc_initialized)
	190	writel(readl(qpriv->ecc_addr) \|
	191	ECC_DIS_ARMV8_CH2,
	192	qpriv->ecc_addr);
ef0cc7fe	193	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	194	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	195	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
ef0cc7fe	196	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	197	if (qpriv->is_dmacoherent)
386dc3b8 TY	198	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
ef0cc7fe TY	199	break;
ef0cc7fe TY	200
d19f9aaf	201	case AHCI_LS2080A:
ecfb4598	202	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	203	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	204	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
e3a6dadc	205	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	206	if (qpriv->is_dmacoherent)
386dc3b8 TY	207	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
ecfb4598	208	break;
2facc6da TY	209
2facc6da TY	210	case AHCI_LS1046A:
2be8481a	211	if (!(qpriv->ecc_addr \|\| ecc_initialized))
01f2901a	212	return -EINVAL;
2be8481a PM	213	else if (qpriv->ecc_addr && !ecc_initialized)
	214	writel(readl(qpriv->ecc_addr) \|
	215	ECC_DIS_ARMV8_CH2,
	216	qpriv->ecc_addr);
2facc6da	217	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	218	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	219	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
2facc6da	220	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	221	if (qpriv->is_dmacoherent)
386dc3b8 TY	222	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
2facc6da	223	break;
ce8f4537	224
a1d78317	225	case AHCI_LS1028A:
0cee73f7	226	case AHCI_LS1088A:
2be8481a PM	227	case AHCI_LX2160A:
2be8481a PM	228	if (!(qpriv->ecc_addr \|\| ecc_initialized))
0cee73f7	229	return -EINVAL;
2be8481a PM	230	else if (qpriv->ecc_addr && !ecc_initialized)
	231	writel(readl(qpriv->ecc_addr) \|
	232	ECC_DIS_LS1088A,
	233	qpriv->ecc_addr);
0cee73f7	234	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	235	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	236	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
0cee73f7 YT	237	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
	238	if (qpriv->is_dmacoherent)
	239	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
	240	break;
	241
ce8f4537 TY	242	case AHCI_LS2088A:
ce8f4537 TY	243	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	244	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	245	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
ce8f4537 TY	246	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
	247	if (qpriv->is_dmacoherent)
	248	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
	249	break;
ecfb4598 TY	250	}
ecfb4598 TY	251
2be8481a	252	ecc_initialized = true;
ecfb4598 TY	253	return 0;
	254	}
	255
	256	static int ahci_qoriq_probe(struct platform_device *pdev)
	257	{
	258	struct device_node *np = pdev->dev.of_node;
564a7eed	259	const struct acpi_device_id *acpi_id;
ecfb4598 TY	260	struct device *dev = &pdev->dev;
	261	struct ahci_host_priv *hpriv;
	262	struct ahci_qoriq_priv *qoriq_priv;
	263	const struct of_device_id *of_id;
	264	struct resource *res;
	265	int rc;
	266
16af2d65	267	hpriv = ahci_platform_get_resources(pdev, 0);
ecfb4598 TY	268	if (IS_ERR(hpriv))
	269	return PTR_ERR(hpriv);
	270
	271	of_id = of_match_node(ahci_qoriq_of_match, np);
564a7eed YT	272	acpi_id = acpi_match_device(ahci_qoriq_acpi_match, &pdev->dev);
564a7eed YT	273	if (!(of_id \|\| acpi_id))
ecfb4598 TY	274	return -ENODEV;
	275
	276	qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
	277	if (!qoriq_priv)
	278	return -ENOMEM;
	279
564a7eed	280	if (of_id)
2ce3a0bf	281	qoriq_priv->type = (unsigned long)of_id->data;
564a7eed YT	282	else
564a7eed YT	283	qoriq_priv->type = (enum ahci_qoriq_type)acpi_id->driver_data;
ecfb4598	284
2be8481a PM	285	if (unlikely(!ecc_initialized)) {
	286	res = platform_get_resource_byname(pdev,
	287	IORESOURCE_MEM,
	288	"sata-ecc");
	289	if (res) {
	290	qoriq_priv->ecc_addr =
	291	devm_ioremap_resource(dev, res);
	292	if (IS_ERR(qoriq_priv->ecc_addr))
	293	return PTR_ERR(qoriq_priv->ecc_addr);
	294	}
ecfb4598	295	}
2be8481a	296
564a7eed YT	297	if (device_get_dma_attr(&pdev->dev) == DEV_DMA_COHERENT)
564a7eed YT	298	qoriq_priv->is_dmacoherent = true;
ecfb4598 TY	299
	300	rc = ahci_platform_enable_resources(hpriv);
	301	if (rc)
	302	return rc;
	303
	304	hpriv->plat_data = qoriq_priv;
	305	rc = ahci_qoriq_phy_init(hpriv);
	306	if (rc)
	307	goto disable_resources;
	308
	309	rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
	310	&ahci_qoriq_sht);
	311	if (rc)
	312	goto disable_resources;
	313
	314	return 0;
	315
	316	disable_resources:
	317	ahci_platform_disable_resources(hpriv);
	318
	319	return rc;
	320	}
	321
	322	#ifdef CONFIG_PM_SLEEP
	323	static int ahci_qoriq_resume(struct device *dev)
	324	{
	325	struct ata_host *host = dev_get_drvdata(dev);
	326	struct ahci_host_priv *hpriv = host->private_data;
	327	int rc;
	328
	329	rc = ahci_platform_enable_resources(hpriv);
	330	if (rc)
	331	return rc;
	332
	333	rc = ahci_qoriq_phy_init(hpriv);
	334	if (rc)
	335	goto disable_resources;
	336
	337	rc = ahci_platform_resume_host(dev);
	338	if (rc)
	339	goto disable_resources;
	340
	341	/* We resumed so update PM runtime state */
	342	pm_runtime_disable(dev);
	343	pm_runtime_set_active(dev);
	344	pm_runtime_enable(dev);
	345
	346	return 0;
	347
	348	disable_resources:
	349	ahci_platform_disable_resources(hpriv);
	350
	351	return rc;
	352	}
	353	#endif
	354
	355	static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
	356	ahci_qoriq_resume);
	357
	358	static struct platform_driver ahci_qoriq_driver = {
	359	.probe = ahci_qoriq_probe,
a7eb54d4	360	.remove_new = ata_platform_remove_one,
ecfb4598 TY	361	.driver = {
	362	.name = DRV_NAME,
	363	.of_match_table = ahci_qoriq_of_match,
564a7eed	364	.acpi_match_table = ahci_qoriq_acpi_match,
ecfb4598 TY	365	.pm = &ahci_qoriq_pm_ops,
	366	},
	367	};
	368	module_platform_driver(ahci_qoriq_driver);
	369
	370	MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
	371	MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
	372	MODULE_LICENSE("GPL");