[linux-block.git] / drivers / ata / ahci_qoriq.c

/*
 * Freescale QorIQ AHCI SATA platform driver
 *
 * Copyright 2015 Freescale, Inc.
 *   Tang Yuantian <Yuantian.Tang@freescale.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/ahci_platform.h>
#include <linux/device.h>
#include <linux/of_address.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/libata.h>
#include "ahci.h"

#define DRV_NAME "ahci-qoriq"

/* port register definition */
#define PORT_PHY1	0xA8
#define PORT_PHY2	0xAC
#define PORT_PHY3	0xB0
#define PORT_PHY4	0xB4
#define PORT_PHY5	0xB8
#define PORT_TRANS	0xC8

/* port register default value */
#define AHCI_PORT_PHY_1_CFG	0xa003fffe
#define AHCI_PORT_PHY_2_CFG	0x28183411
#define AHCI_PORT_PHY_3_CFG	0x0e081004
#define AHCI_PORT_PHY_4_CFG	0x00480811
#define AHCI_PORT_PHY_5_CFG	0x192c96a4
#define AHCI_PORT_TRANS_CFG	0x08000025
#define LS1043A_PORT_PHY2	0x28184d1f
#define LS1043A_PORT_PHY3	0x0e081509

#define SATA_ECC_DISABLE	0x00020000

enum ahci_qoriq_type {
	AHCI_LS1021A,
	AHCI_LS1043A,
	AHCI_LS2080A,
};

struct ahci_qoriq_priv {
	struct ccsr_ahci *reg_base;
	enum ahci_qoriq_type type;
	void __iomem *ecc_addr;
};

static const struct of_device_id ahci_qoriq_of_match[] = {
	{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
	{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
	{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
	{},
};
MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);

static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
			  unsigned long deadline)
{
	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
	void __iomem *port_mmio = ahci_port_base(link->ap);
	u32 px_cmd, px_is, px_val;
	struct ata_port *ap = link->ap;
	struct ahci_port_priv *pp = ap->private_data;
	struct ahci_host_priv *hpriv = ap->host->private_data;
	struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	struct ata_taskfile tf;
	bool online;
	int rc;
	bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);

	DPRINTK("ENTER\n");

	ahci_stop_engine(ap);

	/*
	 * There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
	 * A-009042: The device detection initialization sequence
	 * mistakenly resets some registers.
	 *
	 * Workaround for this is:
	 * The software should read and store PxCMD and PxIS values
	 * before issuing the device detection initialization sequence.
	 * After the sequence is complete, software should restore the
	 * PxCMD and PxIS with the stored values.
	 */
	if (ls1021a_workaround) {
		px_cmd = readl(port_mmio + PORT_CMD);
		px_is = readl(port_mmio + PORT_IRQ_STAT);
	}

	/* clear D2H reception area to properly wait for D2H FIS */
	ata_tf_init(link->device, &tf);
	tf.command = ATA_BUSY;
	ata_tf_to_fis(&tf, 0, 0, d2h_fis);

	rc = sata_link_hardreset(link, timing, deadline, &online,
				 ahci_check_ready);

	/* restore the PxCMD and PxIS on ls1021 */
	if (ls1021a_workaround) {
		px_val = readl(port_mmio + PORT_CMD);
		if (px_val != px_cmd)
			writel(px_cmd, port_mmio + PORT_CMD);

		px_val = readl(port_mmio + PORT_IRQ_STAT);
		if (px_val != px_is)
			writel(px_is, port_mmio + PORT_IRQ_STAT);
	}

	hpriv->start_engine(ap);

	if (online)
		*class = ahci_dev_classify(ap);

	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
	return rc;
}

static struct ata_port_operations ahci_qoriq_ops = {
	.inherits	= &ahci_ops,
	.hardreset	= ahci_qoriq_hardreset,
};

static struct ata_port_info ahci_qoriq_port_info = {
	.flags		= AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
	.pio_mask	= ATA_PIO4,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &ahci_qoriq_ops,
};

static struct scsi_host_template ahci_qoriq_sht = {
	AHCI_SHT(DRV_NAME),
};

static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
{
	struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
	void __iomem *reg_base = hpriv->mmio;

	switch (qpriv->type) {
	case AHCI_LS1021A:
		writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY_2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY_3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_PHY_4_CFG, reg_base + PORT_PHY4);
		writel(AHCI_PORT_PHY_5_CFG, reg_base + PORT_PHY5);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		break;

	case AHCI_LS1043A:
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(LS1043A_PORT_PHY2, reg_base + PORT_PHY2);
		writel(LS1043A_PORT_PHY3, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		break;

	case AHCI_LS2080A:
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		break;
	}

	return 0;
}

static int ahci_qoriq_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct device *dev = &pdev->dev;
	struct ahci_host_priv *hpriv;
	struct ahci_qoriq_priv *qoriq_priv;
	const struct of_device_id *of_id;
	struct resource *res;
	int rc;

	hpriv = ahci_platform_get_resources(pdev);
	if (IS_ERR(hpriv))
		return PTR_ERR(hpriv);

	of_id = of_match_node(ahci_qoriq_of_match, np);
	if (!of_id)
		return -ENODEV;

	qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
	if (!qoriq_priv)
		return -ENOMEM;

	qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;

	if (qoriq_priv->type == AHCI_LS1021A) {
		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
				"sata-ecc");
		qoriq_priv->ecc_addr = devm_ioremap_resource(dev, res);
		if (IS_ERR(qoriq_priv->ecc_addr))
			return PTR_ERR(qoriq_priv->ecc_addr);
	}

	rc = ahci_platform_enable_resources(hpriv);
	if (rc)
		return rc;

	hpriv->plat_data = qoriq_priv;
	rc = ahci_qoriq_phy_init(hpriv);
	if (rc)
		goto disable_resources;

	/* Workaround for ls2080a */
	if (qoriq_priv->type == AHCI_LS2080A) {
		hpriv->flags |= AHCI_HFLAG_NO_NCQ;
		ahci_qoriq_port_info.flags &= ~ATA_FLAG_NCQ;
	}

	rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
				     &ahci_qoriq_sht);
	if (rc)
		goto disable_resources;

	return 0;

disable_resources:
	ahci_platform_disable_resources(hpriv);

	return rc;
}

#ifdef CONFIG_PM_SLEEP
static int ahci_qoriq_resume(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	int rc;

	rc = ahci_platform_enable_resources(hpriv);
	if (rc)
		return rc;

	rc = ahci_qoriq_phy_init(hpriv);
	if (rc)
		goto disable_resources;

	rc = ahci_platform_resume_host(dev);
	if (rc)
		goto disable_resources;

	/* We resumed so update PM runtime state */
	pm_runtime_disable(dev);
	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);

	return 0;

disable_resources:
	ahci_platform_disable_resources(hpriv);

	return rc;
}
#endif

static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
			 ahci_qoriq_resume);

static struct platform_driver ahci_qoriq_driver = {
	.probe = ahci_qoriq_probe,
	.remove = ata_platform_remove_one,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = ahci_qoriq_of_match,
		.pm = &ahci_qoriq_pm_ops,
	},
};
module_platform_driver(ahci_qoriq_driver);

MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
ecfb4598 TY	1	/*
	2	* Freescale QorIQ AHCI SATA platform driver
	3	*
	4	* Copyright 2015 Freescale, Inc.
	5	* Tang Yuantian <Yuantian.Tang@freescale.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2, or (at your option)
	10	* any later version.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/module.h>
	15	#include <linux/pm.h>
	16	#include <linux/ahci_platform.h>
	17	#include <linux/device.h>
	18	#include <linux/of_address.h>
	19	#include <linux/of.h>
	20	#include <linux/of_device.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/libata.h>
	23	#include "ahci.h"
	24
	25	#define DRV_NAME "ahci-qoriq"
	26
	27	/* port register definition */
	28	#define PORT_PHY1 0xA8
	29	#define PORT_PHY2 0xAC
	30	#define PORT_PHY3 0xB0
	31	#define PORT_PHY4 0xB4
	32	#define PORT_PHY5 0xB8
	33	#define PORT_TRANS 0xC8
	34
	35	/* port register default value */
	36	#define AHCI_PORT_PHY_1_CFG 0xa003fffe
	37	#define AHCI_PORT_PHY_2_CFG 0x28183411
	38	#define AHCI_PORT_PHY_3_CFG 0x0e081004
	39	#define AHCI_PORT_PHY_4_CFG 0x00480811
	40	#define AHCI_PORT_PHY_5_CFG 0x192c96a4
	41	#define AHCI_PORT_TRANS_CFG 0x08000025
ef0cc7fe TY	42	#define LS1043A_PORT_PHY2 0x28184d1f
ef0cc7fe TY	43	#define LS1043A_PORT_PHY3 0x0e081509
ecfb4598 TY	44
	45	#define SATA_ECC_DISABLE 0x00020000
	46
	47	enum ahci_qoriq_type {
	48	AHCI_LS1021A,
	49	AHCI_LS1043A,
d19f9aaf	50	AHCI_LS2080A,
ecfb4598 TY	51	};
	52
	53	struct ahci_qoriq_priv {
	54	struct ccsr_ahci *reg_base;
	55	enum ahci_qoriq_type type;
	56	void __iomem *ecc_addr;
	57	};
	58
	59	static const struct of_device_id ahci_qoriq_of_match[] = {
	60	{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
	61	{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
d19f9aaf	62	{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
ecfb4598 TY	63	{},
	64	};
	65	MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
	66
	67	static int ahci_qoriq_hardreset(struct ata_link link, unsigned int class,
	68	unsigned long deadline)
	69	{
	70	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
	71	void __iomem *port_mmio = ahci_port_base(link->ap);
	72	u32 px_cmd, px_is, px_val;
	73	struct ata_port *ap = link->ap;
	74	struct ahci_port_priv *pp = ap->private_data;
	75	struct ahci_host_priv *hpriv = ap->host->private_data;
	76	struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
	77	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	78	struct ata_taskfile tf;
	79	bool online;
	80	int rc;
eb351031	81	bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);
ecfb4598 TY	82
	83	DPRINTK("ENTER\n");
	84
	85	ahci_stop_engine(ap);
	86
	87	/*
	88	* There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
	89	* A-009042: The device detection initialization sequence
	90	* mistakenly resets some registers.
	91	*
	92	* Workaround for this is:
	93	* The software should read and store PxCMD and PxIS values
	94	* before issuing the device detection initialization sequence.
	95	* After the sequence is complete, software should restore the
	96	* PxCMD and PxIS with the stored values.
	97	*/
eb351031	98	if (ls1021a_workaround) {
ecfb4598 TY	99	px_cmd = readl(port_mmio + PORT_CMD);
	100	px_is = readl(port_mmio + PORT_IRQ_STAT);
	101	}
	102
	103	/* clear D2H reception area to properly wait for D2H FIS */
	104	ata_tf_init(link->device, &tf);
	105	tf.command = ATA_BUSY;
	106	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
	107
	108	rc = sata_link_hardreset(link, timing, deadline, &online,
	109	ahci_check_ready);
	110
	111	/* restore the PxCMD and PxIS on ls1021 */
eb351031	112	if (ls1021a_workaround) {
ecfb4598 TY	113	px_val = readl(port_mmio + PORT_CMD);
	114	if (px_val != px_cmd)
	115	writel(px_cmd, port_mmio + PORT_CMD);
	116
	117	px_val = readl(port_mmio + PORT_IRQ_STAT);
	118	if (px_val != px_is)
	119	writel(px_is, port_mmio + PORT_IRQ_STAT);
	120	}
	121
	122	hpriv->start_engine(ap);
	123
	124	if (online)
	125	*class = ahci_dev_classify(ap);
	126
	127	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
	128	return rc;
	129	}
	130
	131	static struct ata_port_operations ahci_qoriq_ops = {
	132	.inherits = &ahci_ops,
	133	.hardreset = ahci_qoriq_hardreset,
	134	};
	135
64084729	136	static struct ata_port_info ahci_qoriq_port_info = {
ecfb4598 TY	137	.flags = AHCI_FLAG_COMMON \| ATA_FLAG_NCQ,
	138	.pio_mask = ATA_PIO4,
	139	.udma_mask = ATA_UDMA6,
	140	.port_ops = &ahci_qoriq_ops,
	141	};
	142
	143	static struct scsi_host_template ahci_qoriq_sht = {
	144	AHCI_SHT(DRV_NAME),
	145	};
	146
	147	static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
	148	{
	149	struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
	150	void __iomem *reg_base = hpriv->mmio;
	151
	152	switch (qpriv->type) {
	153	case AHCI_LS1021A:
	154	writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
	155	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
	156	writel(AHCI_PORT_PHY_2_CFG, reg_base + PORT_PHY2);
	157	writel(AHCI_PORT_PHY_3_CFG, reg_base + PORT_PHY3);
	158	writel(AHCI_PORT_PHY_4_CFG, reg_base + PORT_PHY4);
	159	writel(AHCI_PORT_PHY_5_CFG, reg_base + PORT_PHY5);
	160	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
	161	break;
	162
	163	case AHCI_LS1043A:
ef0cc7fe TY	164	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
	165	writel(LS1043A_PORT_PHY2, reg_base + PORT_PHY2);
	166	writel(LS1043A_PORT_PHY3, reg_base + PORT_PHY3);
	167	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
	168	break;
	169
d19f9aaf	170	case AHCI_LS2080A:
ecfb4598 TY	171	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
	172	break;
	173	}
	174
	175	return 0;
	176	}
	177
	178	static int ahci_qoriq_probe(struct platform_device *pdev)
	179	{
	180	struct device_node *np = pdev->dev.of_node;
	181	struct device *dev = &pdev->dev;
	182	struct ahci_host_priv *hpriv;
	183	struct ahci_qoriq_priv *qoriq_priv;
	184	const struct of_device_id *of_id;
	185	struct resource *res;
	186	int rc;
	187
	188	hpriv = ahci_platform_get_resources(pdev);
	189	if (IS_ERR(hpriv))
	190	return PTR_ERR(hpriv);
	191
	192	of_id = of_match_node(ahci_qoriq_of_match, np);
	193	if (!of_id)
	194	return -ENODEV;
	195
	196	qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
	197	if (!qoriq_priv)
	198	return -ENOMEM;
	199
	200	qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
	201
	202	if (qoriq_priv->type == AHCI_LS1021A) {
	203	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
	204	"sata-ecc");
	205	qoriq_priv->ecc_addr = devm_ioremap_resource(dev, res);
	206	if (IS_ERR(qoriq_priv->ecc_addr))
	207	return PTR_ERR(qoriq_priv->ecc_addr);
	208	}
	209
	210	rc = ahci_platform_enable_resources(hpriv);
	211	if (rc)
	212	return rc;
	213
	214	hpriv->plat_data = qoriq_priv;
	215	rc = ahci_qoriq_phy_init(hpriv);
	216	if (rc)
	217	goto disable_resources;
	218
64084729 TY	219	/* Workaround for ls2080a */
	220	if (qoriq_priv->type == AHCI_LS2080A) {
	221	hpriv->flags \|= AHCI_HFLAG_NO_NCQ;
	222	ahci_qoriq_port_info.flags &= ~ATA_FLAG_NCQ;
	223	}
	224
ecfb4598 TY	225	rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
	226	&ahci_qoriq_sht);
	227	if (rc)
	228	goto disable_resources;
	229
	230	return 0;
	231
	232	disable_resources:
	233	ahci_platform_disable_resources(hpriv);
	234
	235	return rc;
	236	}
	237
	238	#ifdef CONFIG_PM_SLEEP
	239	static int ahci_qoriq_resume(struct device *dev)
	240	{
	241	struct ata_host *host = dev_get_drvdata(dev);
	242	struct ahci_host_priv *hpriv = host->private_data;
	243	int rc;
	244
	245	rc = ahci_platform_enable_resources(hpriv);
	246	if (rc)
	247	return rc;
	248
	249	rc = ahci_qoriq_phy_init(hpriv);
	250	if (rc)
	251	goto disable_resources;
	252
	253	rc = ahci_platform_resume_host(dev);
	254	if (rc)
	255	goto disable_resources;
	256
	257	/* We resumed so update PM runtime state */
	258	pm_runtime_disable(dev);
	259	pm_runtime_set_active(dev);
	260	pm_runtime_enable(dev);
	261
	262	return 0;
	263
	264	disable_resources:
	265	ahci_platform_disable_resources(hpriv);
	266
	267	return rc;
	268	}
	269	#endif
	270
	271	static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
	272	ahci_qoriq_resume);
	273
	274	static struct platform_driver ahci_qoriq_driver = {
	275	.probe = ahci_qoriq_probe,
	276	.remove = ata_platform_remove_one,
	277	.driver = {
	278	.name = DRV_NAME,
	279	.of_match_table = ahci_qoriq_of_match,
	280	.pm = &ahci_qoriq_pm_ops,
	281	},
	282	};
	283	module_platform_driver(ahci_qoriq_driver);
	284
	285	MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
	286	MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
	287	MODULE_LICENSE("GPL");