[linux-block.git] / drivers / ata / ahci_qoriq.c

/*
 * Freescale QorIQ AHCI SATA platform driver
 *
 * Copyright 2015 Freescale, Inc.
 *   Tang Yuantian <Yuantian.Tang@freescale.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/ahci_platform.h>
#include <linux/device.h>
#include <linux/of_address.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/libata.h>
#include "ahci.h"

#define DRV_NAME "ahci-qoriq"

/* port register definition */
#define PORT_PHY1	0xA8
#define PORT_PHY2	0xAC
#define PORT_PHY3	0xB0
#define PORT_PHY4	0xB4
#define PORT_PHY5	0xB8
#define PORT_AXICC	0xBC
#define PORT_TRANS	0xC8

/* port register default value */
#define AHCI_PORT_PHY_1_CFG	0xa003fffe
#define AHCI_PORT_PHY2_CFG	0x28184d1f
#define AHCI_PORT_PHY3_CFG	0x0e081509
#define AHCI_PORT_TRANS_CFG	0x08000029
#define AHCI_PORT_AXICC_CFG	0x3fffffff

/* for ls1021a */
#define LS1021A_PORT_PHY2	0x28183414
#define LS1021A_PORT_PHY3	0x0e080e06
#define LS1021A_PORT_PHY4	0x064a080b
#define LS1021A_PORT_PHY5	0x2aa86470
#define LS1021A_AXICC_ADDR	0xC0

#define SATA_ECC_DISABLE	0x00020000
#define ECC_DIS_ARMV8_CH2	0x80000000
#define ECC_DIS_LS1088A		0x40000000

enum ahci_qoriq_type {
	AHCI_LS1021A,
	AHCI_LS1028A,
	AHCI_LS1043A,
	AHCI_LS2080A,
	AHCI_LS1046A,
	AHCI_LS1088A,
	AHCI_LS2088A,
	AHCI_LX2160A,
};

struct ahci_qoriq_priv {
	struct ccsr_ahci *reg_base;
	enum ahci_qoriq_type type;
	void __iomem *ecc_addr;
	bool is_dmacoherent;
};

static bool ecc_initialized;

static const struct of_device_id ahci_qoriq_of_match[] = {
	{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
	{ .compatible = "fsl,ls1028a-ahci", .data = (void *)AHCI_LS1028A},
	{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
	{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
	{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
	{ .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
	{ .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
	{ .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
	{},
};
MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);

static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
			  unsigned long deadline)
{
	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
	void __iomem *port_mmio = ahci_port_base(link->ap);
	u32 px_cmd, px_is, px_val;
	struct ata_port *ap = link->ap;
	struct ahci_port_priv *pp = ap->private_data;
	struct ahci_host_priv *hpriv = ap->host->private_data;
	struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	struct ata_taskfile tf;
	bool online;
	int rc;
	bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);

	DPRINTK("ENTER\n");

	hpriv->stop_engine(ap);

	/*
	 * There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
	 * A-009042: The device detection initialization sequence
	 * mistakenly resets some registers.
	 *
	 * Workaround for this is:
	 * The software should read and store PxCMD and PxIS values
	 * before issuing the device detection initialization sequence.
	 * After the sequence is complete, software should restore the
	 * PxCMD and PxIS with the stored values.
	 */
	if (ls1021a_workaround) {
		px_cmd = readl(port_mmio + PORT_CMD);
		px_is = readl(port_mmio + PORT_IRQ_STAT);
	}

	/* clear D2H reception area to properly wait for D2H FIS */
	ata_tf_init(link->device, &tf);
	tf.command = ATA_BUSY;
	ata_tf_to_fis(&tf, 0, 0, d2h_fis);

	rc = sata_link_hardreset(link, timing, deadline, &online,
				 ahci_check_ready);

	/* restore the PxCMD and PxIS on ls1021 */
	if (ls1021a_workaround) {
		px_val = readl(port_mmio + PORT_CMD);
		if (px_val != px_cmd)
			writel(px_cmd, port_mmio + PORT_CMD);

		px_val = readl(port_mmio + PORT_IRQ_STAT);
		if (px_val != px_is)
			writel(px_is, port_mmio + PORT_IRQ_STAT);
	}

	hpriv->start_engine(ap);

	if (online)
		*class = ahci_dev_classify(ap);

	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
	return rc;
}

static struct ata_port_operations ahci_qoriq_ops = {
	.inherits	= &ahci_ops,
	.hardreset	= ahci_qoriq_hardreset,
};

static const struct ata_port_info ahci_qoriq_port_info = {
	.flags		= AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
	.pio_mask	= ATA_PIO4,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &ahci_qoriq_ops,
};

static struct scsi_host_template ahci_qoriq_sht = {
	AHCI_SHT(DRV_NAME),
};

static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
{
	struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
	void __iomem *reg_base = hpriv->mmio;

	switch (qpriv->type) {
	case AHCI_LS1021A:
		if (!(qpriv->ecc_addr || ecc_initialized))
			return -EINVAL;
		else if (qpriv->ecc_addr && !ecc_initialized)
			writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
		writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
		writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
		writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG,
					reg_base + LS1021A_AXICC_ADDR);
		break;

	case AHCI_LS1043A:
		if (!(qpriv->ecc_addr || ecc_initialized))
			return -EINVAL;
		else if (qpriv->ecc_addr && !ecc_initialized)
			writel(readl(qpriv->ecc_addr) |
			       ECC_DIS_ARMV8_CH2,
			       qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS2080A:
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS1046A:
		if (!(qpriv->ecc_addr || ecc_initialized))
			return -EINVAL;
		else if (qpriv->ecc_addr && !ecc_initialized)
			writel(readl(qpriv->ecc_addr) |
			       ECC_DIS_ARMV8_CH2,
			       qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS1028A:
	case AHCI_LS1088A:
	case AHCI_LX2160A:
		if (!(qpriv->ecc_addr || ecc_initialized))
			return -EINVAL;
		else if (qpriv->ecc_addr && !ecc_initialized)
			writel(readl(qpriv->ecc_addr) |
			       ECC_DIS_LS1088A,
			       qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS2088A:
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;
	}

	ecc_initialized = true;
	return 0;
}

static int ahci_qoriq_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct device *dev = &pdev->dev;
	struct ahci_host_priv *hpriv;
	struct ahci_qoriq_priv *qoriq_priv;
	const struct of_device_id *of_id;
	struct resource *res;
	int rc;

	hpriv = ahci_platform_get_resources(pdev, 0);
	if (IS_ERR(hpriv))
		return PTR_ERR(hpriv);

	of_id = of_match_node(ahci_qoriq_of_match, np);
	if (!of_id)
		return -ENODEV;

	qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
	if (!qoriq_priv)
		return -ENOMEM;

	qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;

	if (unlikely(!ecc_initialized)) {
		res = platform_get_resource_byname(pdev,
						   IORESOURCE_MEM,
						   "sata-ecc");
		if (res) {
			qoriq_priv->ecc_addr =
				devm_ioremap_resource(dev, res);
			if (IS_ERR(qoriq_priv->ecc_addr))
				return PTR_ERR(qoriq_priv->ecc_addr);
		}
	}

	qoriq_priv->is_dmacoherent = of_dma_is_coherent(np);

	rc = ahci_platform_enable_resources(hpriv);
	if (rc)
		return rc;

	hpriv->plat_data = qoriq_priv;
	rc = ahci_qoriq_phy_init(hpriv);
	if (rc)
		goto disable_resources;

	rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
				     &ahci_qoriq_sht);
	if (rc)
		goto disable_resources;

	return 0;

disable_resources:
	ahci_platform_disable_resources(hpriv);

	return rc;
}

#ifdef CONFIG_PM_SLEEP
static int ahci_qoriq_resume(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	int rc;

	rc = ahci_platform_enable_resources(hpriv);
	if (rc)
		return rc;

	rc = ahci_qoriq_phy_init(hpriv);
	if (rc)
		goto disable_resources;

	rc = ahci_platform_resume_host(dev);
	if (rc)
		goto disable_resources;

	/* We resumed so update PM runtime state */
	pm_runtime_disable(dev);
	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);

	return 0;

disable_resources:
	ahci_platform_disable_resources(hpriv);

	return rc;
}
#endif

static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
			 ahci_qoriq_resume);

static struct platform_driver ahci_qoriq_driver = {
	.probe = ahci_qoriq_probe,
	.remove = ata_platform_remove_one,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = ahci_qoriq_of_match,
		.pm = &ahci_qoriq_pm_ops,
	},
};
module_platform_driver(ahci_qoriq_driver);

MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
ecfb4598 TY	1	/*
	2	* Freescale QorIQ AHCI SATA platform driver
	3	*
	4	* Copyright 2015 Freescale, Inc.
	5	* Tang Yuantian <Yuantian.Tang@freescale.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2, or (at your option)
	10	* any later version.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/module.h>
	15	#include <linux/pm.h>
	16	#include <linux/ahci_platform.h>
	17	#include <linux/device.h>
	18	#include <linux/of_address.h>
	19	#include <linux/of.h>
	20	#include <linux/of_device.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/libata.h>
	23	#include "ahci.h"
	24
	25	#define DRV_NAME "ahci-qoriq"
	26
	27	/* port register definition */
	28	#define PORT_PHY1 0xA8
	29	#define PORT_PHY2 0xAC
	30	#define PORT_PHY3 0xB0
	31	#define PORT_PHY4 0xB4
	32	#define PORT_PHY5 0xB8
16af080e	33	#define PORT_AXICC 0xBC
ecfb4598 TY	34	#define PORT_TRANS 0xC8
	35
	36	/* port register default value */
	37	#define AHCI_PORT_PHY_1_CFG 0xa003fffe
ce179cbd YT	38	#define AHCI_PORT_PHY2_CFG 0x28184d1f
ce179cbd YT	39	#define AHCI_PORT_PHY3_CFG 0x0e081509
e3a6dadc	40	#define AHCI_PORT_TRANS_CFG 0x08000029
16af080e	41	#define AHCI_PORT_AXICC_CFG 0x3fffffff
dfcdc5fe TY	42
	43	/* for ls1021a */
	44	#define LS1021A_PORT_PHY2 0x28183414
	45	#define LS1021A_PORT_PHY3 0x0e080e06
	46	#define LS1021A_PORT_PHY4 0x064a080b
	47	#define LS1021A_PORT_PHY5 0x2aa86470
16af080e	48	#define LS1021A_AXICC_ADDR 0xC0
ecfb4598 TY	49
ecfb4598 TY	50	#define SATA_ECC_DISABLE 0x00020000
01f2901a	51	#define ECC_DIS_ARMV8_CH2 0x80000000
0cee73f7	52	#define ECC_DIS_LS1088A 0x40000000
ecfb4598 TY	53
	54	enum ahci_qoriq_type {
	55	AHCI_LS1021A,
a1d78317	56	AHCI_LS1028A,
ecfb4598	57	AHCI_LS1043A,
d19f9aaf	58	AHCI_LS2080A,
2facc6da	59	AHCI_LS1046A,
0cee73f7	60	AHCI_LS1088A,
ce8f4537	61	AHCI_LS2088A,
2be8481a	62	AHCI_LX2160A,
ecfb4598 TY	63	};
	64
	65	struct ahci_qoriq_priv {
	66	struct ccsr_ahci *reg_base;
	67	enum ahci_qoriq_type type;
	68	void __iomem *ecc_addr;
386dc3b8	69	bool is_dmacoherent;
ecfb4598 TY	70	};
ecfb4598 TY	71
2be8481a PM	72	static bool ecc_initialized;
2be8481a PM	73
ecfb4598 TY	74	static const struct of_device_id ahci_qoriq_of_match[] = {
ecfb4598 TY	75	{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
a1d78317	76	{ .compatible = "fsl,ls1028a-ahci", .data = (void *)AHCI_LS1028A},
ecfb4598	77	{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
d19f9aaf	78	{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
2facc6da	79	{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
0cee73f7	80	{ .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
ce8f4537	81	{ .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
2be8481a	82	{ .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
ecfb4598 TY	83	{},
	84	};
	85	MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
	86
	87	static int ahci_qoriq_hardreset(struct ata_link link, unsigned int class,
	88	unsigned long deadline)
	89	{
	90	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
	91	void __iomem *port_mmio = ahci_port_base(link->ap);
	92	u32 px_cmd, px_is, px_val;
	93	struct ata_port *ap = link->ap;
	94	struct ahci_port_priv *pp = ap->private_data;
	95	struct ahci_host_priv *hpriv = ap->host->private_data;
	96	struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
	97	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	98	struct ata_taskfile tf;
	99	bool online;
	100	int rc;
eb351031	101	bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);
ecfb4598 TY	102
	103	DPRINTK("ENTER\n");
	104
fa89f53b	105	hpriv->stop_engine(ap);
ecfb4598 TY	106
	107	/*
	108	* There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
	109	* A-009042: The device detection initialization sequence
	110	* mistakenly resets some registers.
	111	*
	112	* Workaround for this is:
	113	* The software should read and store PxCMD and PxIS values
	114	* before issuing the device detection initialization sequence.
	115	* After the sequence is complete, software should restore the
	116	* PxCMD and PxIS with the stored values.
	117	*/
eb351031	118	if (ls1021a_workaround) {
ecfb4598 TY	119	px_cmd = readl(port_mmio + PORT_CMD);
	120	px_is = readl(port_mmio + PORT_IRQ_STAT);
	121	}
	122
	123	/* clear D2H reception area to properly wait for D2H FIS */
	124	ata_tf_init(link->device, &tf);
	125	tf.command = ATA_BUSY;
	126	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
	127
	128	rc = sata_link_hardreset(link, timing, deadline, &online,
	129	ahci_check_ready);
	130
	131	/* restore the PxCMD and PxIS on ls1021 */
eb351031	132	if (ls1021a_workaround) {
ecfb4598 TY	133	px_val = readl(port_mmio + PORT_CMD);
	134	if (px_val != px_cmd)
	135	writel(px_cmd, port_mmio + PORT_CMD);
	136
	137	px_val = readl(port_mmio + PORT_IRQ_STAT);
	138	if (px_val != px_is)
	139	writel(px_is, port_mmio + PORT_IRQ_STAT);
	140	}
	141
	142	hpriv->start_engine(ap);
	143
	144	if (online)
	145	*class = ahci_dev_classify(ap);
	146
	147	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
	148	return rc;
	149	}
	150
	151	static struct ata_port_operations ahci_qoriq_ops = {
	152	.inherits = &ahci_ops,
	153	.hardreset = ahci_qoriq_hardreset,
	154	};
	155
1ce788d2	156	static const struct ata_port_info ahci_qoriq_port_info = {
ecfb4598 TY	157	.flags = AHCI_FLAG_COMMON \| ATA_FLAG_NCQ,
	158	.pio_mask = ATA_PIO4,
	159	.udma_mask = ATA_UDMA6,
	160	.port_ops = &ahci_qoriq_ops,
	161	};
	162
	163	static struct scsi_host_template ahci_qoriq_sht = {
	164	AHCI_SHT(DRV_NAME),
	165	};
	166
	167	static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
	168	{
	169	struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
	170	void __iomem *reg_base = hpriv->mmio;
	171
	172	switch (qpriv->type) {
	173	case AHCI_LS1021A:
2be8481a	174	if (!(qpriv->ecc_addr \|\| ecc_initialized))
01f2901a	175	return -EINVAL;
2be8481a PM	176	else if (qpriv->ecc_addr && !ecc_initialized)
2be8481a PM	177	writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
ecfb4598	178	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
dfcdc5fe TY	179	writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
	180	writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
	181	writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
	182	writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
ecfb4598	183	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	184	if (qpriv->is_dmacoherent)
	185	writel(AHCI_PORT_AXICC_CFG,
	186	reg_base + LS1021A_AXICC_ADDR);
ecfb4598 TY	187	break;
	188
	189	case AHCI_LS1043A:
2be8481a	190	if (!(qpriv->ecc_addr \|\| ecc_initialized))
01f2901a	191	return -EINVAL;
2be8481a PM	192	else if (qpriv->ecc_addr && !ecc_initialized)
	193	writel(readl(qpriv->ecc_addr) \|
	194	ECC_DIS_ARMV8_CH2,
	195	qpriv->ecc_addr);
ef0cc7fe	196	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	197	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	198	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
ef0cc7fe	199	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	200	if (qpriv->is_dmacoherent)
386dc3b8 TY	201	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
ef0cc7fe TY	202	break;
ef0cc7fe TY	203
d19f9aaf	204	case AHCI_LS2080A:
ecfb4598	205	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	206	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	207	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
e3a6dadc	208	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	209	if (qpriv->is_dmacoherent)
386dc3b8 TY	210	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
ecfb4598	211	break;
2facc6da TY	212
2facc6da TY	213	case AHCI_LS1046A:
2be8481a	214	if (!(qpriv->ecc_addr \|\| ecc_initialized))
01f2901a	215	return -EINVAL;
2be8481a PM	216	else if (qpriv->ecc_addr && !ecc_initialized)
	217	writel(readl(qpriv->ecc_addr) \|
	218	ECC_DIS_ARMV8_CH2,
	219	qpriv->ecc_addr);
2facc6da	220	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	221	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	222	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
2facc6da	223	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	224	if (qpriv->is_dmacoherent)
386dc3b8 TY	225	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
2facc6da	226	break;
ce8f4537	227
a1d78317	228	case AHCI_LS1028A:
0cee73f7	229	case AHCI_LS1088A:
2be8481a PM	230	case AHCI_LX2160A:
2be8481a PM	231	if (!(qpriv->ecc_addr \|\| ecc_initialized))
0cee73f7	232	return -EINVAL;
2be8481a PM	233	else if (qpriv->ecc_addr && !ecc_initialized)
	234	writel(readl(qpriv->ecc_addr) \|
	235	ECC_DIS_LS1088A,
	236	qpriv->ecc_addr);
0cee73f7	237	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	238	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	239	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
0cee73f7 YT	240	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
	241	if (qpriv->is_dmacoherent)
	242	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
	243	break;
	244
ce8f4537 TY	245	case AHCI_LS2088A:
ce8f4537 TY	246	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	247	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	248	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
ce8f4537 TY	249	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
	250	if (qpriv->is_dmacoherent)
	251	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
	252	break;
ecfb4598 TY	253	}
ecfb4598 TY	254
2be8481a	255	ecc_initialized = true;
ecfb4598 TY	256	return 0;
	257	}
	258
	259	static int ahci_qoriq_probe(struct platform_device *pdev)
	260	{
	261	struct device_node *np = pdev->dev.of_node;
	262	struct device *dev = &pdev->dev;
	263	struct ahci_host_priv *hpriv;
	264	struct ahci_qoriq_priv *qoriq_priv;
	265	const struct of_device_id *of_id;
	266	struct resource *res;
	267	int rc;
	268
16af2d65	269	hpriv = ahci_platform_get_resources(pdev, 0);
ecfb4598 TY	270	if (IS_ERR(hpriv))
	271	return PTR_ERR(hpriv);
	272
	273	of_id = of_match_node(ahci_qoriq_of_match, np);
	274	if (!of_id)
	275	return -ENODEV;
	276
	277	qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
	278	if (!qoriq_priv)
	279	return -ENOMEM;
	280
	281	qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
	282
2be8481a PM	283	if (unlikely(!ecc_initialized)) {
	284	res = platform_get_resource_byname(pdev,
	285	IORESOURCE_MEM,
	286	"sata-ecc");
	287	if (res) {
	288	qoriq_priv->ecc_addr =
	289	devm_ioremap_resource(dev, res);
	290	if (IS_ERR(qoriq_priv->ecc_addr))
	291	return PTR_ERR(qoriq_priv->ecc_addr);
	292	}
ecfb4598	293	}
2be8481a	294
386dc3b8	295	qoriq_priv->is_dmacoherent = of_dma_is_coherent(np);
ecfb4598 TY	296
	297	rc = ahci_platform_enable_resources(hpriv);
	298	if (rc)
	299	return rc;
	300
	301	hpriv->plat_data = qoriq_priv;
	302	rc = ahci_qoriq_phy_init(hpriv);
	303	if (rc)
	304	goto disable_resources;
	305
	306	rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
	307	&ahci_qoriq_sht);
	308	if (rc)
	309	goto disable_resources;
	310
	311	return 0;
	312
	313	disable_resources:
	314	ahci_platform_disable_resources(hpriv);
	315
	316	return rc;
	317	}
	318
	319	#ifdef CONFIG_PM_SLEEP
	320	static int ahci_qoriq_resume(struct device *dev)
	321	{
	322	struct ata_host *host = dev_get_drvdata(dev);
	323	struct ahci_host_priv *hpriv = host->private_data;
	324	int rc;
	325
	326	rc = ahci_platform_enable_resources(hpriv);
	327	if (rc)
	328	return rc;
	329
	330	rc = ahci_qoriq_phy_init(hpriv);
	331	if (rc)
	332	goto disable_resources;
	333
	334	rc = ahci_platform_resume_host(dev);
	335	if (rc)
	336	goto disable_resources;
	337
	338	/* We resumed so update PM runtime state */
	339	pm_runtime_disable(dev);
	340	pm_runtime_set_active(dev);
	341	pm_runtime_enable(dev);
	342
	343	return 0;
	344
	345	disable_resources:
	346	ahci_platform_disable_resources(hpriv);
	347
	348	return rc;
	349	}
	350	#endif
	351
	352	static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
	353	ahci_qoriq_resume);
	354
	355	static struct platform_driver ahci_qoriq_driver = {
	356	.probe = ahci_qoriq_probe,
	357	.remove = ata_platform_remove_one,
	358	.driver = {
	359	.name = DRV_NAME,
360	.of_match_table = ahci_qoriq_of_match,
361	.pm = &ahci_qoriq_pm_ops,
362	},
363	};
364	module_platform_driver(ahci_qoriq_driver);
365
366	MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
367	MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
368	MODULE_LICENSE("GPL");