[linux-2.6-block.git] / drivers / ata / ahci_qoriq.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Freescale QorIQ AHCI SATA platform driver
 *
 * Copyright 2015 Freescale, Inc.
 *   Tang Yuantian <Yuantian.Tang@freescale.com>
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/ahci_platform.h>
#include <linux/device.h>
#include <linux/of_address.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/libata.h>
#include "ahci.h"

#define DRV_NAME "ahci-qoriq"

/* port register definition */
#define PORT_PHY1	0xA8
#define PORT_PHY2	0xAC
#define PORT_PHY3	0xB0
#define PORT_PHY4	0xB4
#define PORT_PHY5	0xB8
#define PORT_AXICC	0xBC
#define PORT_TRANS	0xC8

/* port register default value */
#define AHCI_PORT_PHY_1_CFG	0xa003fffe
#define AHCI_PORT_PHY2_CFG	0x28184d1f
#define AHCI_PORT_PHY3_CFG	0x0e081509
#define AHCI_PORT_TRANS_CFG	0x08000029
#define AHCI_PORT_AXICC_CFG	0x3fffffff

/* for ls1021a */
#define LS1021A_PORT_PHY2	0x28183414
#define LS1021A_PORT_PHY3	0x0e080e06
#define LS1021A_PORT_PHY4	0x064a080b
#define LS1021A_PORT_PHY5	0x2aa86470
#define LS1021A_AXICC_ADDR	0xC0

#define SATA_ECC_DISABLE	0x00020000
#define ECC_DIS_ARMV8_CH2	0x80000000
#define ECC_DIS_LS1088A		0x40000000

enum ahci_qoriq_type {
	AHCI_LS1021A,
	AHCI_LS1028A,
	AHCI_LS1043A,
	AHCI_LS2080A,
	AHCI_LS1046A,
	AHCI_LS1088A,
	AHCI_LS2088A,
	AHCI_LX2160A,
};

struct ahci_qoriq_priv {
	struct ccsr_ahci *reg_base;
	enum ahci_qoriq_type type;
	void __iomem *ecc_addr;
	bool is_dmacoherent;
};

static bool ecc_initialized;

static const struct of_device_id ahci_qoriq_of_match[] = {
	{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
	{ .compatible = "fsl,ls1028a-ahci", .data = (void *)AHCI_LS1028A},
	{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
	{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
	{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
	{ .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
	{ .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
	{ .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
	{},
};
MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);

static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
			  unsigned long deadline)
{
	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
	void __iomem *port_mmio = ahci_port_base(link->ap);
	u32 px_cmd, px_is, px_val;
	struct ata_port *ap = link->ap;
	struct ahci_port_priv *pp = ap->private_data;
	struct ahci_host_priv *hpriv = ap->host->private_data;
	struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	struct ata_taskfile tf;
	bool online;
	int rc;
	bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);

	DPRINTK("ENTER\n");

	hpriv->stop_engine(ap);

	/*
	 * There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
	 * A-009042: The device detection initialization sequence
	 * mistakenly resets some registers.
	 *
	 * Workaround for this is:
	 * The software should read and store PxCMD and PxIS values
	 * before issuing the device detection initialization sequence.
	 * After the sequence is complete, software should restore the
	 * PxCMD and PxIS with the stored values.
	 */
	if (ls1021a_workaround) {
		px_cmd = readl(port_mmio + PORT_CMD);
		px_is = readl(port_mmio + PORT_IRQ_STAT);
	}

	/* clear D2H reception area to properly wait for D2H FIS */
	ata_tf_init(link->device, &tf);
	tf.command = ATA_BUSY;
	ata_tf_to_fis(&tf, 0, 0, d2h_fis);

	rc = sata_link_hardreset(link, timing, deadline, &online,
				 ahci_check_ready);

	/* restore the PxCMD and PxIS on ls1021 */
	if (ls1021a_workaround) {
		px_val = readl(port_mmio + PORT_CMD);
		if (px_val != px_cmd)
			writel(px_cmd, port_mmio + PORT_CMD);

		px_val = readl(port_mmio + PORT_IRQ_STAT);
		if (px_val != px_is)
			writel(px_is, port_mmio + PORT_IRQ_STAT);
	}

	hpriv->start_engine(ap);

	if (online)
		*class = ahci_dev_classify(ap);

	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
	return rc;
}

static struct ata_port_operations ahci_qoriq_ops = {
	.inherits	= &ahci_ops,
	.hardreset	= ahci_qoriq_hardreset,
};

static const struct ata_port_info ahci_qoriq_port_info = {
	.flags		= AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
	.pio_mask	= ATA_PIO4,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &ahci_qoriq_ops,
};

static struct scsi_host_template ahci_qoriq_sht = {
	AHCI_SHT(DRV_NAME),
};

static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
{
	struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
	void __iomem *reg_base = hpriv->mmio;

	switch (qpriv->type) {
	case AHCI_LS1021A:
		if (!(qpriv->ecc_addr || ecc_initialized))
			return -EINVAL;
		else if (qpriv->ecc_addr && !ecc_initialized)
			writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
		writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
		writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
		writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG,
					reg_base + LS1021A_AXICC_ADDR);
		break;

	case AHCI_LS1043A:
		if (!(qpriv->ecc_addr || ecc_initialized))
			return -EINVAL;
		else if (qpriv->ecc_addr && !ecc_initialized)
			writel(readl(qpriv->ecc_addr) |
			       ECC_DIS_ARMV8_CH2,
			       qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS2080A:
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS1046A:
		if (!(qpriv->ecc_addr || ecc_initialized))
			return -EINVAL;
		else if (qpriv->ecc_addr && !ecc_initialized)
			writel(readl(qpriv->ecc_addr) |
			       ECC_DIS_ARMV8_CH2,
			       qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS1028A:
	case AHCI_LS1088A:
	case AHCI_LX2160A:
		if (!(qpriv->ecc_addr || ecc_initialized))
			return -EINVAL;
		else if (qpriv->ecc_addr && !ecc_initialized)
			writel(readl(qpriv->ecc_addr) |
			       ECC_DIS_LS1088A,
			       qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS2088A:
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;
	}

	ecc_initialized = true;
	return 0;
}

static int ahci_qoriq_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct device *dev = &pdev->dev;
	struct ahci_host_priv *hpriv;
	struct ahci_qoriq_priv *qoriq_priv;
	const struct of_device_id *of_id;
	struct resource *res;
	int rc;

	hpriv = ahci_platform_get_resources(pdev, 0);
	if (IS_ERR(hpriv))
		return PTR_ERR(hpriv);

	of_id = of_match_node(ahci_qoriq_of_match, np);
	if (!of_id)
		return -ENODEV;

	qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
	if (!qoriq_priv)
		return -ENOMEM;

	qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;

	if (unlikely(!ecc_initialized)) {
		res = platform_get_resource_byname(pdev,
						   IORESOURCE_MEM,
						   "sata-ecc");
		if (res) {
			qoriq_priv->ecc_addr =
				devm_ioremap_resource(dev, res);
			if (IS_ERR(qoriq_priv->ecc_addr))
				return PTR_ERR(qoriq_priv->ecc_addr);
		}
	}

	qoriq_priv->is_dmacoherent = of_dma_is_coherent(np);

	rc = ahci_platform_enable_resources(hpriv);
	if (rc)
		return rc;

	hpriv->plat_data = qoriq_priv;
	rc = ahci_qoriq_phy_init(hpriv);
	if (rc)
		goto disable_resources;

	rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
				     &ahci_qoriq_sht);
	if (rc)
		goto disable_resources;

	return 0;

disable_resources:
	ahci_platform_disable_resources(hpriv);

	return rc;
}

#ifdef CONFIG_PM_SLEEP
static int ahci_qoriq_resume(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	int rc;

	rc = ahci_platform_enable_resources(hpriv);
	if (rc)
		return rc;

	rc = ahci_qoriq_phy_init(hpriv);
	if (rc)
		goto disable_resources;

	rc = ahci_platform_resume_host(dev);
	if (rc)
		goto disable_resources;

	/* We resumed so update PM runtime state */
	pm_runtime_disable(dev);
	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);

	return 0;

disable_resources:
	ahci_platform_disable_resources(hpriv);

	return rc;
}
#endif

static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
			 ahci_qoriq_resume);

static struct platform_driver ahci_qoriq_driver = {
	.probe = ahci_qoriq_probe,
	.remove = ata_platform_remove_one,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = ahci_qoriq_of_match,
		.pm = &ahci_qoriq_pm_ops,
	},
};
module_platform_driver(ahci_qoriq_driver);

MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
8d7c56d0	1	// SPDX-License-Identifier: GPL-2.0-or-later
ecfb4598 TY	2	/*
	3	* Freescale QorIQ AHCI SATA platform driver
	4	*
	5	* Copyright 2015 Freescale, Inc.
	6	* Tang Yuantian <Yuantian.Tang@freescale.com>
ecfb4598 TY	7	*/
	8
	9	#include <linux/kernel.h>
	10	#include <linux/module.h>
	11	#include <linux/pm.h>
	12	#include <linux/ahci_platform.h>
	13	#include <linux/device.h>
	14	#include <linux/of_address.h>
	15	#include <linux/of.h>
	16	#include <linux/of_device.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/libata.h>
	19	#include "ahci.h"
	20
	21	#define DRV_NAME "ahci-qoriq"
	22
	23	/* port register definition */
	24	#define PORT_PHY1 0xA8
	25	#define PORT_PHY2 0xAC
	26	#define PORT_PHY3 0xB0
	27	#define PORT_PHY4 0xB4
	28	#define PORT_PHY5 0xB8
16af080e	29	#define PORT_AXICC 0xBC
ecfb4598 TY	30	#define PORT_TRANS 0xC8
	31
	32	/* port register default value */
	33	#define AHCI_PORT_PHY_1_CFG 0xa003fffe
ce179cbd YT	34	#define AHCI_PORT_PHY2_CFG 0x28184d1f
ce179cbd YT	35	#define AHCI_PORT_PHY3_CFG 0x0e081509
e3a6dadc	36	#define AHCI_PORT_TRANS_CFG 0x08000029
16af080e	37	#define AHCI_PORT_AXICC_CFG 0x3fffffff
dfcdc5fe TY	38
	39	/* for ls1021a */
	40	#define LS1021A_PORT_PHY2 0x28183414
	41	#define LS1021A_PORT_PHY3 0x0e080e06
	42	#define LS1021A_PORT_PHY4 0x064a080b
	43	#define LS1021A_PORT_PHY5 0x2aa86470
16af080e	44	#define LS1021A_AXICC_ADDR 0xC0
ecfb4598 TY	45
ecfb4598 TY	46	#define SATA_ECC_DISABLE 0x00020000
01f2901a	47	#define ECC_DIS_ARMV8_CH2 0x80000000
0cee73f7	48	#define ECC_DIS_LS1088A 0x40000000
ecfb4598 TY	49
	50	enum ahci_qoriq_type {
	51	AHCI_LS1021A,
a1d78317	52	AHCI_LS1028A,
ecfb4598	53	AHCI_LS1043A,
d19f9aaf	54	AHCI_LS2080A,
2facc6da	55	AHCI_LS1046A,
0cee73f7	56	AHCI_LS1088A,
ce8f4537	57	AHCI_LS2088A,
2be8481a	58	AHCI_LX2160A,
ecfb4598 TY	59	};
	60
	61	struct ahci_qoriq_priv {
	62	struct ccsr_ahci *reg_base;
	63	enum ahci_qoriq_type type;
	64	void __iomem *ecc_addr;
386dc3b8	65	bool is_dmacoherent;
ecfb4598 TY	66	};
ecfb4598 TY	67
2be8481a PM	68	static bool ecc_initialized;
2be8481a PM	69
ecfb4598 TY	70	static const struct of_device_id ahci_qoriq_of_match[] = {
ecfb4598 TY	71	{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
a1d78317	72	{ .compatible = "fsl,ls1028a-ahci", .data = (void *)AHCI_LS1028A},
ecfb4598	73	{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
d19f9aaf	74	{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
2facc6da	75	{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
0cee73f7	76	{ .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
ce8f4537	77	{ .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
2be8481a	78	{ .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
ecfb4598 TY	79	{},
	80	};
	81	MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
	82
	83	static int ahci_qoriq_hardreset(struct ata_link link, unsigned int class,
	84	unsigned long deadline)
	85	{
	86	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
	87	void __iomem *port_mmio = ahci_port_base(link->ap);
	88	u32 px_cmd, px_is, px_val;
	89	struct ata_port *ap = link->ap;
	90	struct ahci_port_priv *pp = ap->private_data;
	91	struct ahci_host_priv *hpriv = ap->host->private_data;
	92	struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
	93	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	94	struct ata_taskfile tf;
	95	bool online;
	96	int rc;
eb351031	97	bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);
ecfb4598 TY	98
	99	DPRINTK("ENTER\n");
	100
fa89f53b	101	hpriv->stop_engine(ap);
ecfb4598 TY	102
	103	/*
	104	* There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
	105	* A-009042: The device detection initialization sequence
	106	* mistakenly resets some registers.
	107	*
	108	* Workaround for this is:
	109	* The software should read and store PxCMD and PxIS values
	110	* before issuing the device detection initialization sequence.
	111	* After the sequence is complete, software should restore the
	112	* PxCMD and PxIS with the stored values.
	113	*/
eb351031	114	if (ls1021a_workaround) {
ecfb4598 TY	115	px_cmd = readl(port_mmio + PORT_CMD);
	116	px_is = readl(port_mmio + PORT_IRQ_STAT);
	117	}
	118
	119	/* clear D2H reception area to properly wait for D2H FIS */
	120	ata_tf_init(link->device, &tf);
	121	tf.command = ATA_BUSY;
	122	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
	123
	124	rc = sata_link_hardreset(link, timing, deadline, &online,
	125	ahci_check_ready);
	126
	127	/* restore the PxCMD and PxIS on ls1021 */
eb351031	128	if (ls1021a_workaround) {
ecfb4598 TY	129	px_val = readl(port_mmio + PORT_CMD);
	130	if (px_val != px_cmd)
	131	writel(px_cmd, port_mmio + PORT_CMD);
	132
	133	px_val = readl(port_mmio + PORT_IRQ_STAT);
	134	if (px_val != px_is)
	135	writel(px_is, port_mmio + PORT_IRQ_STAT);
	136	}
	137
	138	hpriv->start_engine(ap);
	139
	140	if (online)
	141	*class = ahci_dev_classify(ap);
	142
	143	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
	144	return rc;
	145	}
	146
	147	static struct ata_port_operations ahci_qoriq_ops = {
	148	.inherits = &ahci_ops,
	149	.hardreset = ahci_qoriq_hardreset,
	150	};
	151
1ce788d2	152	static const struct ata_port_info ahci_qoriq_port_info = {
ecfb4598 TY	153	.flags = AHCI_FLAG_COMMON \| ATA_FLAG_NCQ,
	154	.pio_mask = ATA_PIO4,
	155	.udma_mask = ATA_UDMA6,
	156	.port_ops = &ahci_qoriq_ops,
	157	};
	158
	159	static struct scsi_host_template ahci_qoriq_sht = {
	160	AHCI_SHT(DRV_NAME),
	161	};
	162
	163	static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
	164	{
	165	struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
	166	void __iomem *reg_base = hpriv->mmio;
	167
	168	switch (qpriv->type) {
	169	case AHCI_LS1021A:
2be8481a	170	if (!(qpriv->ecc_addr \|\| ecc_initialized))
01f2901a	171	return -EINVAL;
2be8481a PM	172	else if (qpriv->ecc_addr && !ecc_initialized)
2be8481a PM	173	writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
ecfb4598	174	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
dfcdc5fe TY	175	writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
	176	writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
	177	writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
	178	writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
ecfb4598	179	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	180	if (qpriv->is_dmacoherent)
	181	writel(AHCI_PORT_AXICC_CFG,
	182	reg_base + LS1021A_AXICC_ADDR);
ecfb4598 TY	183	break;
	184
	185	case AHCI_LS1043A:
2be8481a	186	if (!(qpriv->ecc_addr \|\| ecc_initialized))
01f2901a	187	return -EINVAL;
2be8481a PM	188	else if (qpriv->ecc_addr && !ecc_initialized)
	189	writel(readl(qpriv->ecc_addr) \|
	190	ECC_DIS_ARMV8_CH2,
	191	qpriv->ecc_addr);
ef0cc7fe	192	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	193	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	194	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
ef0cc7fe	195	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	196	if (qpriv->is_dmacoherent)
386dc3b8 TY	197	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
ef0cc7fe TY	198	break;
ef0cc7fe TY	199
d19f9aaf	200	case AHCI_LS2080A:
ecfb4598	201	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	202	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	203	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
e3a6dadc	204	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	205	if (qpriv->is_dmacoherent)
386dc3b8 TY	206	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
ecfb4598	207	break;
2facc6da TY	208
2facc6da TY	209	case AHCI_LS1046A:
2be8481a	210	if (!(qpriv->ecc_addr \|\| ecc_initialized))
01f2901a	211	return -EINVAL;
2be8481a PM	212	else if (qpriv->ecc_addr && !ecc_initialized)
	213	writel(readl(qpriv->ecc_addr) \|
	214	ECC_DIS_ARMV8_CH2,
	215	qpriv->ecc_addr);
2facc6da	216	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	217	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	218	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
2facc6da	219	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	220	if (qpriv->is_dmacoherent)
386dc3b8 TY	221	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
2facc6da	222	break;
ce8f4537	223
a1d78317	224	case AHCI_LS1028A:
0cee73f7	225	case AHCI_LS1088A:
2be8481a PM	226	case AHCI_LX2160A:
2be8481a PM	227	if (!(qpriv->ecc_addr \|\| ecc_initialized))
0cee73f7	228	return -EINVAL;
2be8481a PM	229	else if (qpriv->ecc_addr && !ecc_initialized)
	230	writel(readl(qpriv->ecc_addr) \|
	231	ECC_DIS_LS1088A,
	232	qpriv->ecc_addr);
0cee73f7	233	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	234	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	235	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
0cee73f7 YT	236	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
	237	if (qpriv->is_dmacoherent)
	238	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
	239	break;
	240
ce8f4537 TY	241	case AHCI_LS2088A:
ce8f4537 TY	242	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	243	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	244	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
ce8f4537 TY	245	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
	246	if (qpriv->is_dmacoherent)
	247	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
	248	break;
ecfb4598 TY	249	}
ecfb4598 TY	250
2be8481a	251	ecc_initialized = true;
ecfb4598 TY	252	return 0;
	253	}
	254
	255	static int ahci_qoriq_probe(struct platform_device *pdev)
	256	{
	257	struct device_node *np = pdev->dev.of_node;
	258	struct device *dev = &pdev->dev;
	259	struct ahci_host_priv *hpriv;
	260	struct ahci_qoriq_priv *qoriq_priv;
	261	const struct of_device_id *of_id;
	262	struct resource *res;
	263	int rc;
	264
16af2d65	265	hpriv = ahci_platform_get_resources(pdev, 0);
ecfb4598 TY	266	if (IS_ERR(hpriv))
	267	return PTR_ERR(hpriv);
	268
	269	of_id = of_match_node(ahci_qoriq_of_match, np);
	270	if (!of_id)
	271	return -ENODEV;
	272
	273	qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
	274	if (!qoriq_priv)
	275	return -ENOMEM;
	276
	277	qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
	278
2be8481a PM	279	if (unlikely(!ecc_initialized)) {
	280	res = platform_get_resource_byname(pdev,
	281	IORESOURCE_MEM,
	282	"sata-ecc");
	283	if (res) {
	284	qoriq_priv->ecc_addr =
	285	devm_ioremap_resource(dev, res);
	286	if (IS_ERR(qoriq_priv->ecc_addr))
	287	return PTR_ERR(qoriq_priv->ecc_addr);
	288	}
ecfb4598	289	}
2be8481a	290
386dc3b8	291	qoriq_priv->is_dmacoherent = of_dma_is_coherent(np);
ecfb4598 TY	292
	293	rc = ahci_platform_enable_resources(hpriv);
	294	if (rc)
	295	return rc;
	296
	297	hpriv->plat_data = qoriq_priv;
	298	rc = ahci_qoriq_phy_init(hpriv);
	299	if (rc)
	300	goto disable_resources;
	301
	302	rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
	303	&ahci_qoriq_sht);
	304	if (rc)
	305	goto disable_resources;
	306
	307	return 0;
	308
	309	disable_resources:
	310	ahci_platform_disable_resources(hpriv);
	311
	312	return rc;
	313	}
	314
	315	#ifdef CONFIG_PM_SLEEP
	316	static int ahci_qoriq_resume(struct device *dev)
	317	{
	318	struct ata_host *host = dev_get_drvdata(dev);
	319	struct ahci_host_priv *hpriv = host->private_data;
	320	int rc;
	321
	322	rc = ahci_platform_enable_resources(hpriv);
	323	if (rc)
	324	return rc;
	325
	326	rc = ahci_qoriq_phy_init(hpriv);
	327	if (rc)
	328	goto disable_resources;
	329
	330	rc = ahci_platform_resume_host(dev);
	331	if (rc)
	332	goto disable_resources;
	333
	334	/* We resumed so update PM runtime state */
	335	pm_runtime_disable(dev);
	336	pm_runtime_set_active(dev);
	337	pm_runtime_enable(dev);
	338
	339	return 0;
	340
	341	disable_resources:
	342	ahci_platform_disable_resources(hpriv);
	343
	344	return rc;
	345	}
	346	#endif
	347
	348	static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
	349	ahci_qoriq_resume);
	350
	351	static struct platform_driver ahci_qoriq_driver = {
	352	.probe = ahci_qoriq_probe,
	353	.remove = ata_platform_remove_one,
	354	.driver = {
	355	.name = DRV_NAME,
356	.of_match_table = ahci_qoriq_of_match,
357	.pm = &ahci_qoriq_pm_ops,
358	},
359	};
360	module_platform_driver(ahci_qoriq_driver);
361
362	MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
363	MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
364	MODULE_LICENSE("GPL");