[linux-2.6-block.git] / drivers / ata / ahci_qoriq.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Freescale QorIQ AHCI SATA platform driver
 *
 * Copyright 2015 Freescale, Inc.
 *   Tang Yuantian <Yuantian.Tang@freescale.com>
 */

#include <linux/acpi.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/ahci_platform.h>
#include <linux/device.h>
#include <linux/of_address.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/libata.h>
#include "ahci.h"

#define DRV_NAME "ahci-qoriq"

/* port register definition */
#define PORT_PHY1	0xA8
#define PORT_PHY2	0xAC
#define PORT_PHY3	0xB0
#define PORT_PHY4	0xB4
#define PORT_PHY5	0xB8
#define PORT_AXICC	0xBC
#define PORT_TRANS	0xC8

/* port register default value */
#define AHCI_PORT_PHY_1_CFG	0xa003fffe
#define AHCI_PORT_PHY2_CFG	0x28184d1f
#define AHCI_PORT_PHY3_CFG	0x0e081509
#define AHCI_PORT_TRANS_CFG	0x08000029
#define AHCI_PORT_AXICC_CFG	0x3fffffff

/* for ls1021a */
#define LS1021A_PORT_PHY2	0x28183414
#define LS1021A_PORT_PHY3	0x0e080e06
#define LS1021A_PORT_PHY4	0x064a080b
#define LS1021A_PORT_PHY5	0x2aa86470
#define LS1021A_AXICC_ADDR	0xC0

#define SATA_ECC_DISABLE	0x00020000
#define ECC_DIS_ARMV8_CH2	0x80000000
#define ECC_DIS_LS1088A		0x40000000

enum ahci_qoriq_type {
	AHCI_LS1021A,
	AHCI_LS1028A,
	AHCI_LS1043A,
	AHCI_LS2080A,
	AHCI_LS1046A,
	AHCI_LS1088A,
	AHCI_LS2088A,
	AHCI_LX2160A,
};

struct ahci_qoriq_priv {
	struct ccsr_ahci *reg_base;
	enum ahci_qoriq_type type;
	void __iomem *ecc_addr;
	bool is_dmacoherent;
};

static bool ecc_initialized;

static const struct of_device_id ahci_qoriq_of_match[] = {
	{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
	{ .compatible = "fsl,ls1028a-ahci", .data = (void *)AHCI_LS1028A},
	{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
	{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
	{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
	{ .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
	{ .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
	{ .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
	{},
};
MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);

static const struct acpi_device_id ahci_qoriq_acpi_match[] = {
	{"NXP0004", .driver_data = (kernel_ulong_t)AHCI_LX2160A},
	{ }
};
MODULE_DEVICE_TABLE(acpi, ahci_qoriq_acpi_match);

static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
			  unsigned long deadline)
{
	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
	void __iomem *port_mmio = ahci_port_base(link->ap);
	u32 px_cmd, px_is, px_val;
	struct ata_port *ap = link->ap;
	struct ahci_port_priv *pp = ap->private_data;
	struct ahci_host_priv *hpriv = ap->host->private_data;
	struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	struct ata_taskfile tf;
	bool online;
	int rc;
	bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);

	DPRINTK("ENTER\n");

	hpriv->stop_engine(ap);

	/*
	 * There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
	 * A-009042: The device detection initialization sequence
	 * mistakenly resets some registers.
	 *
	 * Workaround for this is:
	 * The software should read and store PxCMD and PxIS values
	 * before issuing the device detection initialization sequence.
	 * After the sequence is complete, software should restore the
	 * PxCMD and PxIS with the stored values.
	 */
	if (ls1021a_workaround) {
		px_cmd = readl(port_mmio + PORT_CMD);
		px_is = readl(port_mmio + PORT_IRQ_STAT);
	}

	/* clear D2H reception area to properly wait for D2H FIS */
	ata_tf_init(link->device, &tf);
	tf.command = ATA_BUSY;
	ata_tf_to_fis(&tf, 0, 0, d2h_fis);

	rc = sata_link_hardreset(link, timing, deadline, &online,
				 ahci_check_ready);

	/* restore the PxCMD and PxIS on ls1021 */
	if (ls1021a_workaround) {
		px_val = readl(port_mmio + PORT_CMD);
		if (px_val != px_cmd)
			writel(px_cmd, port_mmio + PORT_CMD);

		px_val = readl(port_mmio + PORT_IRQ_STAT);
		if (px_val != px_is)
			writel(px_is, port_mmio + PORT_IRQ_STAT);
	}

	hpriv->start_engine(ap);

	if (online)
		*class = ahci_dev_classify(ap);

	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
	return rc;
}

static struct ata_port_operations ahci_qoriq_ops = {
	.inherits	= &ahci_ops,
	.hardreset	= ahci_qoriq_hardreset,
};

static const struct ata_port_info ahci_qoriq_port_info = {
	.flags		= AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
	.pio_mask	= ATA_PIO4,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &ahci_qoriq_ops,
};

static struct scsi_host_template ahci_qoriq_sht = {
	AHCI_SHT(DRV_NAME),
};

static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
{
	struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
	void __iomem *reg_base = hpriv->mmio;

	switch (qpriv->type) {
	case AHCI_LS1021A:
		if (!(qpriv->ecc_addr || ecc_initialized))
			return -EINVAL;
		else if (qpriv->ecc_addr && !ecc_initialized)
			writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
		writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
		writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
		writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG,
					reg_base + LS1021A_AXICC_ADDR);
		break;

	case AHCI_LS1043A:
		if (!(qpriv->ecc_addr || ecc_initialized))
			return -EINVAL;
		else if (qpriv->ecc_addr && !ecc_initialized)
			writel(readl(qpriv->ecc_addr) |
			       ECC_DIS_ARMV8_CH2,
			       qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS2080A:
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS1046A:
		if (!(qpriv->ecc_addr || ecc_initialized))
			return -EINVAL;
		else if (qpriv->ecc_addr && !ecc_initialized)
			writel(readl(qpriv->ecc_addr) |
			       ECC_DIS_ARMV8_CH2,
			       qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS1028A:
	case AHCI_LS1088A:
	case AHCI_LX2160A:
		if (!(qpriv->ecc_addr || ecc_initialized))
			return -EINVAL;
		else if (qpriv->ecc_addr && !ecc_initialized)
			writel(readl(qpriv->ecc_addr) |
			       ECC_DIS_LS1088A,
			       qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS2088A:
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;
	}

	ecc_initialized = true;
	return 0;
}

static int ahci_qoriq_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	const struct acpi_device_id *acpi_id;
	struct device *dev = &pdev->dev;
	struct ahci_host_priv *hpriv;
	struct ahci_qoriq_priv *qoriq_priv;
	const struct of_device_id *of_id;
	struct resource *res;
	int rc;

	hpriv = ahci_platform_get_resources(pdev, 0);
	if (IS_ERR(hpriv))
		return PTR_ERR(hpriv);

	of_id = of_match_node(ahci_qoriq_of_match, np);
	acpi_id = acpi_match_device(ahci_qoriq_acpi_match, &pdev->dev);
	if (!(of_id || acpi_id))
		return -ENODEV;

	qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
	if (!qoriq_priv)
		return -ENOMEM;

	if (of_id)
		qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
	else
		qoriq_priv->type = (enum ahci_qoriq_type)acpi_id->driver_data;

	if (unlikely(!ecc_initialized)) {
		res = platform_get_resource_byname(pdev,
						   IORESOURCE_MEM,
						   "sata-ecc");
		if (res) {
			qoriq_priv->ecc_addr =
				devm_ioremap_resource(dev, res);
			if (IS_ERR(qoriq_priv->ecc_addr))
				return PTR_ERR(qoriq_priv->ecc_addr);
		}
	}

	if (device_get_dma_attr(&pdev->dev) == DEV_DMA_COHERENT)
		qoriq_priv->is_dmacoherent = true;

	rc = ahci_platform_enable_resources(hpriv);
	if (rc)
		return rc;

	hpriv->plat_data = qoriq_priv;
	rc = ahci_qoriq_phy_init(hpriv);
	if (rc)
		goto disable_resources;

	rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
				     &ahci_qoriq_sht);
	if (rc)
		goto disable_resources;

	return 0;

disable_resources:
	ahci_platform_disable_resources(hpriv);

	return rc;
}

#ifdef CONFIG_PM_SLEEP
static int ahci_qoriq_resume(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	int rc;

	rc = ahci_platform_enable_resources(hpriv);
	if (rc)
		return rc;

	rc = ahci_qoriq_phy_init(hpriv);
	if (rc)
		goto disable_resources;

	rc = ahci_platform_resume_host(dev);
	if (rc)
		goto disable_resources;

	/* We resumed so update PM runtime state */
	pm_runtime_disable(dev);
	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);

	return 0;

disable_resources:
	ahci_platform_disable_resources(hpriv);

	return rc;
}
#endif

static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
			 ahci_qoriq_resume);

static struct platform_driver ahci_qoriq_driver = {
	.probe = ahci_qoriq_probe,
	.remove = ata_platform_remove_one,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = ahci_qoriq_of_match,
		.acpi_match_table = ahci_qoriq_acpi_match,
		.pm = &ahci_qoriq_pm_ops,
	},
};
module_platform_driver(ahci_qoriq_driver);

MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
8d7c56d0	1	// SPDX-License-Identifier: GPL-2.0-or-later
ecfb4598 TY	2	/*
	3	* Freescale QorIQ AHCI SATA platform driver
	4	*
	5	* Copyright 2015 Freescale, Inc.
	6	* Tang Yuantian <Yuantian.Tang@freescale.com>
ecfb4598 TY	7	*/
ecfb4598 TY	8
564a7eed	9	#include <linux/acpi.h>
ecfb4598 TY	10	#include <linux/kernel.h>
	11	#include <linux/module.h>
	12	#include <linux/pm.h>
	13	#include <linux/ahci_platform.h>
	14	#include <linux/device.h>
	15	#include <linux/of_address.h>
	16	#include <linux/of.h>
	17	#include <linux/of_device.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/libata.h>
	20	#include "ahci.h"
	21
	22	#define DRV_NAME "ahci-qoriq"
	23
	24	/* port register definition */
	25	#define PORT_PHY1 0xA8
	26	#define PORT_PHY2 0xAC
	27	#define PORT_PHY3 0xB0
	28	#define PORT_PHY4 0xB4
	29	#define PORT_PHY5 0xB8
16af080e	30	#define PORT_AXICC 0xBC
ecfb4598 TY	31	#define PORT_TRANS 0xC8
	32
	33	/* port register default value */
	34	#define AHCI_PORT_PHY_1_CFG 0xa003fffe
ce179cbd YT	35	#define AHCI_PORT_PHY2_CFG 0x28184d1f
ce179cbd YT	36	#define AHCI_PORT_PHY3_CFG 0x0e081509
e3a6dadc	37	#define AHCI_PORT_TRANS_CFG 0x08000029
16af080e	38	#define AHCI_PORT_AXICC_CFG 0x3fffffff
dfcdc5fe TY	39
	40	/* for ls1021a */
	41	#define LS1021A_PORT_PHY2 0x28183414
	42	#define LS1021A_PORT_PHY3 0x0e080e06
	43	#define LS1021A_PORT_PHY4 0x064a080b
	44	#define LS1021A_PORT_PHY5 0x2aa86470
16af080e	45	#define LS1021A_AXICC_ADDR 0xC0
ecfb4598 TY	46
ecfb4598 TY	47	#define SATA_ECC_DISABLE 0x00020000
01f2901a	48	#define ECC_DIS_ARMV8_CH2 0x80000000
0cee73f7	49	#define ECC_DIS_LS1088A 0x40000000
ecfb4598 TY	50
	51	enum ahci_qoriq_type {
	52	AHCI_LS1021A,
a1d78317	53	AHCI_LS1028A,
ecfb4598	54	AHCI_LS1043A,
d19f9aaf	55	AHCI_LS2080A,
2facc6da	56	AHCI_LS1046A,
0cee73f7	57	AHCI_LS1088A,
ce8f4537	58	AHCI_LS2088A,
2be8481a	59	AHCI_LX2160A,
ecfb4598 TY	60	};
	61
	62	struct ahci_qoriq_priv {
	63	struct ccsr_ahci *reg_base;
	64	enum ahci_qoriq_type type;
	65	void __iomem *ecc_addr;
386dc3b8	66	bool is_dmacoherent;
ecfb4598 TY	67	};
ecfb4598 TY	68
2be8481a PM	69	static bool ecc_initialized;
2be8481a PM	70
ecfb4598 TY	71	static const struct of_device_id ahci_qoriq_of_match[] = {
ecfb4598 TY	72	{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
a1d78317	73	{ .compatible = "fsl,ls1028a-ahci", .data = (void *)AHCI_LS1028A},
ecfb4598	74	{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
d19f9aaf	75	{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
2facc6da	76	{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
0cee73f7	77	{ .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
ce8f4537	78	{ .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
2be8481a	79	{ .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
ecfb4598 TY	80	{},
	81	};
	82	MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
	83
564a7eed YT	84	static const struct acpi_device_id ahci_qoriq_acpi_match[] = {
	85	{"NXP0004", .driver_data = (kernel_ulong_t)AHCI_LX2160A},
	86	{ }
	87	};
	88	MODULE_DEVICE_TABLE(acpi, ahci_qoriq_acpi_match);
	89
ecfb4598 TY	90	static int ahci_qoriq_hardreset(struct ata_link link, unsigned int class,
	91	unsigned long deadline)
	92	{
	93	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
	94	void __iomem *port_mmio = ahci_port_base(link->ap);
	95	u32 px_cmd, px_is, px_val;
	96	struct ata_port *ap = link->ap;
	97	struct ahci_port_priv *pp = ap->private_data;
	98	struct ahci_host_priv *hpriv = ap->host->private_data;
	99	struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
	100	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	101	struct ata_taskfile tf;
	102	bool online;
	103	int rc;
eb351031	104	bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);
ecfb4598 TY	105
	106	DPRINTK("ENTER\n");
	107
fa89f53b	108	hpriv->stop_engine(ap);
ecfb4598 TY	109
	110	/*
	111	* There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
	112	* A-009042: The device detection initialization sequence
	113	* mistakenly resets some registers.
	114	*
	115	* Workaround for this is:
	116	* The software should read and store PxCMD and PxIS values
	117	* before issuing the device detection initialization sequence.
	118	* After the sequence is complete, software should restore the
	119	* PxCMD and PxIS with the stored values.
	120	*/
eb351031	121	if (ls1021a_workaround) {
ecfb4598 TY	122	px_cmd = readl(port_mmio + PORT_CMD);
	123	px_is = readl(port_mmio + PORT_IRQ_STAT);
	124	}
	125
	126	/* clear D2H reception area to properly wait for D2H FIS */
	127	ata_tf_init(link->device, &tf);
	128	tf.command = ATA_BUSY;
	129	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
	130
	131	rc = sata_link_hardreset(link, timing, deadline, &online,
	132	ahci_check_ready);
	133
	134	/* restore the PxCMD and PxIS on ls1021 */
eb351031	135	if (ls1021a_workaround) {
ecfb4598 TY	136	px_val = readl(port_mmio + PORT_CMD);
	137	if (px_val != px_cmd)
	138	writel(px_cmd, port_mmio + PORT_CMD);
	139
	140	px_val = readl(port_mmio + PORT_IRQ_STAT);
	141	if (px_val != px_is)
	142	writel(px_is, port_mmio + PORT_IRQ_STAT);
	143	}
	144
	145	hpriv->start_engine(ap);
	146
	147	if (online)
	148	*class = ahci_dev_classify(ap);
	149
	150	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
	151	return rc;
	152	}
	153
	154	static struct ata_port_operations ahci_qoriq_ops = {
	155	.inherits = &ahci_ops,
	156	.hardreset = ahci_qoriq_hardreset,
	157	};
	158
1ce788d2	159	static const struct ata_port_info ahci_qoriq_port_info = {
ecfb4598 TY	160	.flags = AHCI_FLAG_COMMON \| ATA_FLAG_NCQ,
	161	.pio_mask = ATA_PIO4,
	162	.udma_mask = ATA_UDMA6,
	163	.port_ops = &ahci_qoriq_ops,
	164	};
	165
	166	static struct scsi_host_template ahci_qoriq_sht = {
	167	AHCI_SHT(DRV_NAME),
	168	};
	169
	170	static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
	171	{
	172	struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
	173	void __iomem *reg_base = hpriv->mmio;
	174
	175	switch (qpriv->type) {
	176	case AHCI_LS1021A:
2be8481a	177	if (!(qpriv->ecc_addr \|\| ecc_initialized))
01f2901a	178	return -EINVAL;
2be8481a PM	179	else if (qpriv->ecc_addr && !ecc_initialized)
2be8481a PM	180	writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
ecfb4598	181	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
dfcdc5fe TY	182	writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
	183	writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
	184	writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
	185	writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
ecfb4598	186	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	187	if (qpriv->is_dmacoherent)
	188	writel(AHCI_PORT_AXICC_CFG,
	189	reg_base + LS1021A_AXICC_ADDR);
ecfb4598 TY	190	break;
	191
	192	case AHCI_LS1043A:
2be8481a	193	if (!(qpriv->ecc_addr \|\| ecc_initialized))
01f2901a	194	return -EINVAL;
2be8481a PM	195	else if (qpriv->ecc_addr && !ecc_initialized)
	196	writel(readl(qpriv->ecc_addr) \|
	197	ECC_DIS_ARMV8_CH2,
	198	qpriv->ecc_addr);
ef0cc7fe	199	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	200	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	201	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
ef0cc7fe	202	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	203	if (qpriv->is_dmacoherent)
386dc3b8 TY	204	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
ef0cc7fe TY	205	break;
ef0cc7fe TY	206
d19f9aaf	207	case AHCI_LS2080A:
ecfb4598	208	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	209	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	210	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
e3a6dadc	211	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	212	if (qpriv->is_dmacoherent)
386dc3b8 TY	213	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
ecfb4598	214	break;
2facc6da TY	215
2facc6da TY	216	case AHCI_LS1046A:
2be8481a	217	if (!(qpriv->ecc_addr \|\| ecc_initialized))
01f2901a	218	return -EINVAL;
2be8481a PM	219	else if (qpriv->ecc_addr && !ecc_initialized)
	220	writel(readl(qpriv->ecc_addr) \|
	221	ECC_DIS_ARMV8_CH2,
	222	qpriv->ecc_addr);
2facc6da	223	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	224	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	225	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
2facc6da	226	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	227	if (qpriv->is_dmacoherent)
386dc3b8 TY	228	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
2facc6da	229	break;
ce8f4537	230
a1d78317	231	case AHCI_LS1028A:
0cee73f7	232	case AHCI_LS1088A:
2be8481a PM	233	case AHCI_LX2160A:
2be8481a PM	234	if (!(qpriv->ecc_addr \|\| ecc_initialized))
0cee73f7	235	return -EINVAL;
2be8481a PM	236	else if (qpriv->ecc_addr && !ecc_initialized)
	237	writel(readl(qpriv->ecc_addr) \|
	238	ECC_DIS_LS1088A,
	239	qpriv->ecc_addr);
0cee73f7	240	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	241	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	242	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
0cee73f7 YT	243	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
	244	if (qpriv->is_dmacoherent)
	245	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
	246	break;
	247
ce8f4537 TY	248	case AHCI_LS2088A:
ce8f4537 TY	249	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	250	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	251	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
ce8f4537 TY	252	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
	253	if (qpriv->is_dmacoherent)
	254	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
	255	break;
ecfb4598 TY	256	}
ecfb4598 TY	257
2be8481a	258	ecc_initialized = true;
ecfb4598 TY	259	return 0;
	260	}
	261
	262	static int ahci_qoriq_probe(struct platform_device *pdev)
	263	{
	264	struct device_node *np = pdev->dev.of_node;
564a7eed	265	const struct acpi_device_id *acpi_id;
ecfb4598 TY	266	struct device *dev = &pdev->dev;
	267	struct ahci_host_priv *hpriv;
	268	struct ahci_qoriq_priv *qoriq_priv;
	269	const struct of_device_id *of_id;
	270	struct resource *res;
	271	int rc;
	272
16af2d65	273	hpriv = ahci_platform_get_resources(pdev, 0);
ecfb4598 TY	274	if (IS_ERR(hpriv))
	275	return PTR_ERR(hpriv);
	276
	277	of_id = of_match_node(ahci_qoriq_of_match, np);
564a7eed YT	278	acpi_id = acpi_match_device(ahci_qoriq_acpi_match, &pdev->dev);
564a7eed YT	279	if (!(of_id \|\| acpi_id))
ecfb4598 TY	280	return -ENODEV;
	281
	282	qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
	283	if (!qoriq_priv)
	284	return -ENOMEM;
	285
564a7eed YT	286	if (of_id)
	287	qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
	288	else
	289	qoriq_priv->type = (enum ahci_qoriq_type)acpi_id->driver_data;
ecfb4598	290
2be8481a PM	291	if (unlikely(!ecc_initialized)) {
	292	res = platform_get_resource_byname(pdev,
	293	IORESOURCE_MEM,
	294	"sata-ecc");
	295	if (res) {
	296	qoriq_priv->ecc_addr =
	297	devm_ioremap_resource(dev, res);
	298	if (IS_ERR(qoriq_priv->ecc_addr))
	299	return PTR_ERR(qoriq_priv->ecc_addr);
	300	}
ecfb4598	301	}
2be8481a	302
564a7eed YT	303	if (device_get_dma_attr(&pdev->dev) == DEV_DMA_COHERENT)
564a7eed YT	304	qoriq_priv->is_dmacoherent = true;
ecfb4598 TY	305
	306	rc = ahci_platform_enable_resources(hpriv);
	307	if (rc)
	308	return rc;
	309
	310	hpriv->plat_data = qoriq_priv;
	311	rc = ahci_qoriq_phy_init(hpriv);
	312	if (rc)
	313	goto disable_resources;
	314
	315	rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
	316	&ahci_qoriq_sht);
	317	if (rc)
	318	goto disable_resources;
	319
	320	return 0;
	321
	322	disable_resources:
	323	ahci_platform_disable_resources(hpriv);
	324
	325	return rc;
	326	}
	327
	328	#ifdef CONFIG_PM_SLEEP
	329	static int ahci_qoriq_resume(struct device *dev)
	330	{
	331	struct ata_host *host = dev_get_drvdata(dev);
	332	struct ahci_host_priv *hpriv = host->private_data;
	333	int rc;
	334
	335	rc = ahci_platform_enable_resources(hpriv);
	336	if (rc)
	337	return rc;
	338
	339	rc = ahci_qoriq_phy_init(hpriv);
	340	if (rc)
	341	goto disable_resources;
	342
	343	rc = ahci_platform_resume_host(dev);
	344	if (rc)
	345	goto disable_resources;
	346
	347	/* We resumed so update PM runtime state */
	348	pm_runtime_disable(dev);
	349	pm_runtime_set_active(dev);
	350	pm_runtime_enable(dev);
	351
	352	return 0;
	353
	354	disable_resources:
	355	ahci_platform_disable_resources(hpriv);
	356
	357	return rc;
	358	}
	359	#endif
	360
	361	static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
	362	ahci_qoriq_resume);
	363
	364	static struct platform_driver ahci_qoriq_driver = {
	365	.probe = ahci_qoriq_probe,
	366	.remove = ata_platform_remove_one,
	367	.driver = {
	368	.name = DRV_NAME,
369	.of_match_table = ahci_qoriq_of_match,
564a7eed	370	.acpi_match_table = ahci_qoriq_acpi_match,
ecfb4598 TY	371	.pm = &ahci_qoriq_pm_ops,
	372	},
	373	};
	374	module_platform_driver(ahci_qoriq_driver);
	375
	376	MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
	377	MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
	378	MODULE_LICENSE("GPL");