[linux-block.git] / drivers / ata / ahci_qoriq.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Freescale QorIQ AHCI SATA platform driver
 *
 * Copyright 2015 Freescale, Inc.
 *   Tang Yuantian <Yuantian.Tang@freescale.com>
 */

#include <linux/acpi.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/ahci_platform.h>
#include <linux/device.h>
#include <linux/of_address.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/libata.h>
#include "ahci.h"

#define DRV_NAME "ahci-qoriq"

/* port register definition */
#define PORT_PHY1	0xA8
#define PORT_PHY2	0xAC
#define PORT_PHY3	0xB0
#define PORT_PHY4	0xB4
#define PORT_PHY5	0xB8
#define PORT_AXICC	0xBC
#define PORT_TRANS	0xC8

/* port register default value */
#define AHCI_PORT_PHY_1_CFG	0xa003fffe
#define AHCI_PORT_PHY2_CFG	0x28184d1f
#define AHCI_PORT_PHY3_CFG	0x0e081509
#define AHCI_PORT_TRANS_CFG	0x08000029
#define AHCI_PORT_AXICC_CFG	0x3fffffff

/* for ls1021a */
#define LS1021A_PORT_PHY2	0x28183414
#define LS1021A_PORT_PHY3	0x0e080e06
#define LS1021A_PORT_PHY4	0x064a080b
#define LS1021A_PORT_PHY5	0x2aa86470
#define LS1021A_AXICC_ADDR	0xC0

#define SATA_ECC_DISABLE	0x00020000
#define ECC_DIS_ARMV8_CH2	0x80000000
#define ECC_DIS_LS1088A		0x40000000

enum ahci_qoriq_type {
	AHCI_LS1021A,
	AHCI_LS1028A,
	AHCI_LS1043A,
	AHCI_LS2080A,
	AHCI_LS1046A,
	AHCI_LS1088A,
	AHCI_LS2088A,
	AHCI_LX2160A,
};

struct ahci_qoriq_priv {
	struct ccsr_ahci *reg_base;
	enum ahci_qoriq_type type;
	void __iomem *ecc_addr;
	bool is_dmacoherent;
};

static bool ecc_initialized;

static const struct of_device_id ahci_qoriq_of_match[] = {
	{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
	{ .compatible = "fsl,ls1028a-ahci", .data = (void *)AHCI_LS1028A},
	{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
	{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
	{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
	{ .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
	{ .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
	{ .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);

static const struct acpi_device_id ahci_qoriq_acpi_match[] = {
	{"NXP0004", .driver_data = (kernel_ulong_t)AHCI_LX2160A},
	{ }
};
MODULE_DEVICE_TABLE(acpi, ahci_qoriq_acpi_match);

static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
			  unsigned long deadline)
{
	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
	void __iomem *port_mmio = ahci_port_base(link->ap);
	u32 px_cmd, px_is, px_val;
	struct ata_port *ap = link->ap;
	struct ahci_port_priv *pp = ap->private_data;
	struct ahci_host_priv *hpriv = ap->host->private_data;
	struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	struct ata_taskfile tf;
	bool online;
	int rc;
	bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);

	hpriv->stop_engine(ap);

	/*
	 * There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
	 * A-009042: The device detection initialization sequence
	 * mistakenly resets some registers.
	 *
	 * Workaround for this is:
	 * The software should read and store PxCMD and PxIS values
	 * before issuing the device detection initialization sequence.
	 * After the sequence is complete, software should restore the
	 * PxCMD and PxIS with the stored values.
	 */
	if (ls1021a_workaround) {
		px_cmd = readl(port_mmio + PORT_CMD);
		px_is = readl(port_mmio + PORT_IRQ_STAT);
	}

	/* clear D2H reception area to properly wait for D2H FIS */
	ata_tf_init(link->device, &tf);
	tf.status = ATA_BUSY;
	ata_tf_to_fis(&tf, 0, 0, d2h_fis);

	rc = sata_link_hardreset(link, timing, deadline, &online,
				 ahci_check_ready);

	/* restore the PxCMD and PxIS on ls1021 */
	if (ls1021a_workaround) {
		px_val = readl(port_mmio + PORT_CMD);
		if (px_val != px_cmd)
			writel(px_cmd, port_mmio + PORT_CMD);

		px_val = readl(port_mmio + PORT_IRQ_STAT);
		if (px_val != px_is)
			writel(px_is, port_mmio + PORT_IRQ_STAT);
	}

	hpriv->start_engine(ap);

	if (online)
		*class = ahci_dev_classify(ap);
	return rc;
}

static struct ata_port_operations ahci_qoriq_ops = {
	.inherits	= &ahci_ops,
	.hardreset	= ahci_qoriq_hardreset,
};

static const struct ata_port_info ahci_qoriq_port_info = {
	.flags		= AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
	.pio_mask	= ATA_PIO4,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &ahci_qoriq_ops,
};

static const struct scsi_host_template ahci_qoriq_sht = {
	AHCI_SHT(DRV_NAME),
};

static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
{
	struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
	void __iomem *reg_base = hpriv->mmio;

	switch (qpriv->type) {
	case AHCI_LS1021A:
		if (!(qpriv->ecc_addr || ecc_initialized))
			return -EINVAL;
		else if (qpriv->ecc_addr && !ecc_initialized)
			writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
		writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
		writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
		writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG,
					reg_base + LS1021A_AXICC_ADDR);
		break;

	case AHCI_LS1043A:
		if (!(qpriv->ecc_addr || ecc_initialized))
			return -EINVAL;
		else if (qpriv->ecc_addr && !ecc_initialized)
			writel(readl(qpriv->ecc_addr) |
			       ECC_DIS_ARMV8_CH2,
			       qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS2080A:
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS1046A:
		if (!(qpriv->ecc_addr || ecc_initialized))
			return -EINVAL;
		else if (qpriv->ecc_addr && !ecc_initialized)
			writel(readl(qpriv->ecc_addr) |
			       ECC_DIS_ARMV8_CH2,
			       qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS1028A:
	case AHCI_LS1088A:
	case AHCI_LX2160A:
		if (!(qpriv->ecc_addr || ecc_initialized))
			return -EINVAL;
		else if (qpriv->ecc_addr && !ecc_initialized)
			writel(readl(qpriv->ecc_addr) |
			       ECC_DIS_LS1088A,
			       qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS2088A:
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;
	}

	ecc_initialized = true;
	return 0;
}

static int ahci_qoriq_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	const struct acpi_device_id *acpi_id;
	struct device *dev = &pdev->dev;
	struct ahci_host_priv *hpriv;
	struct ahci_qoriq_priv *qoriq_priv;
	const struct of_device_id *of_id;
	struct resource *res;
	int rc;

	hpriv = ahci_platform_get_resources(pdev, 0);
	if (IS_ERR(hpriv))
		return PTR_ERR(hpriv);

	of_id = of_match_node(ahci_qoriq_of_match, np);
	acpi_id = acpi_match_device(ahci_qoriq_acpi_match, &pdev->dev);
	if (!(of_id || acpi_id))
		return -ENODEV;

	qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
	if (!qoriq_priv)
		return -ENOMEM;

	if (of_id)
		qoriq_priv->type = (unsigned long)of_id->data;
	else
		qoriq_priv->type = (enum ahci_qoriq_type)acpi_id->driver_data;

	if (unlikely(!ecc_initialized)) {
		res = platform_get_resource_byname(pdev,
						   IORESOURCE_MEM,
						   "sata-ecc");
		if (res) {
			qoriq_priv->ecc_addr =
				devm_ioremap_resource(dev, res);
			if (IS_ERR(qoriq_priv->ecc_addr))
				return PTR_ERR(qoriq_priv->ecc_addr);
		}
	}

	if (device_get_dma_attr(&pdev->dev) == DEV_DMA_COHERENT)
		qoriq_priv->is_dmacoherent = true;

	rc = ahci_platform_enable_resources(hpriv);
	if (rc)
		return rc;

	hpriv->plat_data = qoriq_priv;
	rc = ahci_qoriq_phy_init(hpriv);
	if (rc)
		goto disable_resources;

	rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
				     &ahci_qoriq_sht);
	if (rc)
		goto disable_resources;

	return 0;

disable_resources:
	ahci_platform_disable_resources(hpriv);

	return rc;
}

#ifdef CONFIG_PM_SLEEP
static int ahci_qoriq_resume(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	int rc;

	rc = ahci_platform_enable_resources(hpriv);
	if (rc)
		return rc;

	rc = ahci_qoriq_phy_init(hpriv);
	if (rc)
		goto disable_resources;

	rc = ahci_platform_resume_host(dev);
	if (rc)
		goto disable_resources;

	/* We resumed so update PM runtime state */
	pm_runtime_disable(dev);
	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);

	return 0;

disable_resources:
	ahci_platform_disable_resources(hpriv);

	return rc;
}
#endif

static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
			 ahci_qoriq_resume);

static struct platform_driver ahci_qoriq_driver = {
	.probe = ahci_qoriq_probe,
	.remove = ata_platform_remove_one,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = ahci_qoriq_of_match,
		.acpi_match_table = ahci_qoriq_acpi_match,
		.pm = &ahci_qoriq_pm_ops,
	},
};
module_platform_driver(ahci_qoriq_driver);

MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
8d7c56d0	1	// SPDX-License-Identifier: GPL-2.0-or-later
ecfb4598 TY	2	/*
	3	* Freescale QorIQ AHCI SATA platform driver
	4	*
	5	* Copyright 2015 Freescale, Inc.
	6	* Tang Yuantian <Yuantian.Tang@freescale.com>
ecfb4598 TY	7	*/
ecfb4598 TY	8
564a7eed	9	#include <linux/acpi.h>
ecfb4598 TY	10	#include <linux/kernel.h>
	11	#include <linux/module.h>
	12	#include <linux/pm.h>
	13	#include <linux/ahci_platform.h>
	14	#include <linux/device.h>
	15	#include <linux/of_address.h>
	16	#include <linux/of.h>
	17	#include <linux/of_device.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/libata.h>
	20	#include "ahci.h"
	21
	22	#define DRV_NAME "ahci-qoriq"
	23
	24	/* port register definition */
	25	#define PORT_PHY1 0xA8
	26	#define PORT_PHY2 0xAC
	27	#define PORT_PHY3 0xB0
	28	#define PORT_PHY4 0xB4
	29	#define PORT_PHY5 0xB8
16af080e	30	#define PORT_AXICC 0xBC
ecfb4598 TY	31	#define PORT_TRANS 0xC8
	32
	33	/* port register default value */
	34	#define AHCI_PORT_PHY_1_CFG 0xa003fffe
ce179cbd YT	35	#define AHCI_PORT_PHY2_CFG 0x28184d1f
ce179cbd YT	36	#define AHCI_PORT_PHY3_CFG 0x0e081509
e3a6dadc	37	#define AHCI_PORT_TRANS_CFG 0x08000029
16af080e	38	#define AHCI_PORT_AXICC_CFG 0x3fffffff
dfcdc5fe TY	39
	40	/* for ls1021a */
	41	#define LS1021A_PORT_PHY2 0x28183414
	42	#define LS1021A_PORT_PHY3 0x0e080e06
	43	#define LS1021A_PORT_PHY4 0x064a080b
	44	#define LS1021A_PORT_PHY5 0x2aa86470
16af080e	45	#define LS1021A_AXICC_ADDR 0xC0
ecfb4598 TY	46
ecfb4598 TY	47	#define SATA_ECC_DISABLE 0x00020000
01f2901a	48	#define ECC_DIS_ARMV8_CH2 0x80000000
0cee73f7	49	#define ECC_DIS_LS1088A 0x40000000
ecfb4598 TY	50
	51	enum ahci_qoriq_type {
	52	AHCI_LS1021A,
a1d78317	53	AHCI_LS1028A,
ecfb4598	54	AHCI_LS1043A,
d19f9aaf	55	AHCI_LS2080A,
2facc6da	56	AHCI_LS1046A,
0cee73f7	57	AHCI_LS1088A,
ce8f4537	58	AHCI_LS2088A,
2be8481a	59	AHCI_LX2160A,
ecfb4598 TY	60	};
	61
	62	struct ahci_qoriq_priv {
	63	struct ccsr_ahci *reg_base;
	64	enum ahci_qoriq_type type;
	65	void __iomem *ecc_addr;
386dc3b8	66	bool is_dmacoherent;
ecfb4598 TY	67	};
ecfb4598 TY	68
2be8481a PM	69	static bool ecc_initialized;
2be8481a PM	70
ecfb4598 TY	71	static const struct of_device_id ahci_qoriq_of_match[] = {
ecfb4598 TY	72	{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
a1d78317	73	{ .compatible = "fsl,ls1028a-ahci", .data = (void *)AHCI_LS1028A},
ecfb4598	74	{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
d19f9aaf	75	{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
2facc6da	76	{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
0cee73f7	77	{ .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
ce8f4537	78	{ .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
2be8481a	79	{ .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
5e776d7b	80	{ /* sentinel */ }
ecfb4598 TY	81	};
	82	MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
	83
564a7eed YT	84	static const struct acpi_device_id ahci_qoriq_acpi_match[] = {
	85	{"NXP0004", .driver_data = (kernel_ulong_t)AHCI_LX2160A},
	86	{ }
	87	};
	88	MODULE_DEVICE_TABLE(acpi, ahci_qoriq_acpi_match);
	89
ecfb4598 TY	90	static int ahci_qoriq_hardreset(struct ata_link link, unsigned int class,
	91	unsigned long deadline)
	92	{
	93	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
	94	void __iomem *port_mmio = ahci_port_base(link->ap);
	95	u32 px_cmd, px_is, px_val;
	96	struct ata_port *ap = link->ap;
	97	struct ahci_port_priv *pp = ap->private_data;
	98	struct ahci_host_priv *hpriv = ap->host->private_data;
	99	struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
	100	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	101	struct ata_taskfile tf;
	102	bool online;
	103	int rc;
eb351031	104	bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);
ecfb4598	105
fa89f53b	106	hpriv->stop_engine(ap);
ecfb4598 TY	107
	108	/*
	109	* There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
	110	* A-009042: The device detection initialization sequence
	111	* mistakenly resets some registers.
	112	*
	113	* Workaround for this is:
	114	* The software should read and store PxCMD and PxIS values
	115	* before issuing the device detection initialization sequence.
	116	* After the sequence is complete, software should restore the
	117	* PxCMD and PxIS with the stored values.
	118	*/
eb351031	119	if (ls1021a_workaround) {
ecfb4598 TY	120	px_cmd = readl(port_mmio + PORT_CMD);
	121	px_is = readl(port_mmio + PORT_IRQ_STAT);
	122	}
	123
	124	/* clear D2H reception area to properly wait for D2H FIS */
	125	ata_tf_init(link->device, &tf);
efcef265	126	tf.status = ATA_BUSY;
ecfb4598 TY	127	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
	128
	129	rc = sata_link_hardreset(link, timing, deadline, &online,
	130	ahci_check_ready);
	131
	132	/* restore the PxCMD and PxIS on ls1021 */
eb351031	133	if (ls1021a_workaround) {
ecfb4598 TY	134	px_val = readl(port_mmio + PORT_CMD);
	135	if (px_val != px_cmd)
	136	writel(px_cmd, port_mmio + PORT_CMD);
	137
	138	px_val = readl(port_mmio + PORT_IRQ_STAT);
	139	if (px_val != px_is)
	140	writel(px_is, port_mmio + PORT_IRQ_STAT);
	141	}
	142
	143	hpriv->start_engine(ap);
	144
	145	if (online)
	146	*class = ahci_dev_classify(ap);
ecfb4598 TY	147	return rc;
	148	}
	149
	150	static struct ata_port_operations ahci_qoriq_ops = {
	151	.inherits = &ahci_ops,
	152	.hardreset = ahci_qoriq_hardreset,
	153	};
	154
1ce788d2	155	static const struct ata_port_info ahci_qoriq_port_info = {
ecfb4598 TY	156	.flags = AHCI_FLAG_COMMON \| ATA_FLAG_NCQ,
	157	.pio_mask = ATA_PIO4,
	158	.udma_mask = ATA_UDMA6,
	159	.port_ops = &ahci_qoriq_ops,
	160	};
	161
25df73d9	162	static const struct scsi_host_template ahci_qoriq_sht = {
ecfb4598 TY	163	AHCI_SHT(DRV_NAME),
	164	};
	165
	166	static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
	167	{
	168	struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
	169	void __iomem *reg_base = hpriv->mmio;
	170
	171	switch (qpriv->type) {
	172	case AHCI_LS1021A:
2be8481a	173	if (!(qpriv->ecc_addr \|\| ecc_initialized))
01f2901a	174	return -EINVAL;
2be8481a PM	175	else if (qpriv->ecc_addr && !ecc_initialized)
2be8481a PM	176	writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
ecfb4598	177	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
dfcdc5fe TY	178	writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
	179	writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
	180	writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
	181	writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
ecfb4598	182	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	183	if (qpriv->is_dmacoherent)
	184	writel(AHCI_PORT_AXICC_CFG,
	185	reg_base + LS1021A_AXICC_ADDR);
ecfb4598 TY	186	break;
	187
	188	case AHCI_LS1043A:
2be8481a	189	if (!(qpriv->ecc_addr \|\| ecc_initialized))
01f2901a	190	return -EINVAL;
2be8481a PM	191	else if (qpriv->ecc_addr && !ecc_initialized)
	192	writel(readl(qpriv->ecc_addr) \|
	193	ECC_DIS_ARMV8_CH2,
	194	qpriv->ecc_addr);
ef0cc7fe	195	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	196	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	197	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
ef0cc7fe	198	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	199	if (qpriv->is_dmacoherent)
386dc3b8 TY	200	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
ef0cc7fe TY	201	break;
ef0cc7fe TY	202
d19f9aaf	203	case AHCI_LS2080A:
ecfb4598	204	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	205	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	206	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
e3a6dadc	207	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	208	if (qpriv->is_dmacoherent)
386dc3b8 TY	209	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
ecfb4598	210	break;
2facc6da TY	211
2facc6da TY	212	case AHCI_LS1046A:
2be8481a	213	if (!(qpriv->ecc_addr \|\| ecc_initialized))
01f2901a	214	return -EINVAL;
2be8481a PM	215	else if (qpriv->ecc_addr && !ecc_initialized)
	216	writel(readl(qpriv->ecc_addr) \|
	217	ECC_DIS_ARMV8_CH2,
	218	qpriv->ecc_addr);
2facc6da	219	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	220	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	221	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
2facc6da	222	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	223	if (qpriv->is_dmacoherent)
386dc3b8 TY	224	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
2facc6da	225	break;
ce8f4537	226
a1d78317	227	case AHCI_LS1028A:
0cee73f7	228	case AHCI_LS1088A:
2be8481a PM	229	case AHCI_LX2160A:
2be8481a PM	230	if (!(qpriv->ecc_addr \|\| ecc_initialized))
0cee73f7	231	return -EINVAL;
2be8481a PM	232	else if (qpriv->ecc_addr && !ecc_initialized)
	233	writel(readl(qpriv->ecc_addr) \|
	234	ECC_DIS_LS1088A,
	235	qpriv->ecc_addr);
0cee73f7	236	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	237	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	238	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
0cee73f7 YT	239	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
	240	if (qpriv->is_dmacoherent)
	241	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
	242	break;
	243
ce8f4537 TY	244	case AHCI_LS2088A:
ce8f4537 TY	245	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	246	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	247	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
ce8f4537 TY	248	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
	249	if (qpriv->is_dmacoherent)
	250	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
	251	break;
ecfb4598 TY	252	}
ecfb4598 TY	253
2be8481a	254	ecc_initialized = true;
ecfb4598 TY	255	return 0;
	256	}
	257
	258	static int ahci_qoriq_probe(struct platform_device *pdev)
	259	{
	260	struct device_node *np = pdev->dev.of_node;
564a7eed	261	const struct acpi_device_id *acpi_id;
ecfb4598 TY	262	struct device *dev = &pdev->dev;
	263	struct ahci_host_priv *hpriv;
	264	struct ahci_qoriq_priv *qoriq_priv;
	265	const struct of_device_id *of_id;
	266	struct resource *res;
	267	int rc;
	268
16af2d65	269	hpriv = ahci_platform_get_resources(pdev, 0);
ecfb4598 TY	270	if (IS_ERR(hpriv))
	271	return PTR_ERR(hpriv);
	272
	273	of_id = of_match_node(ahci_qoriq_of_match, np);
564a7eed YT	274	acpi_id = acpi_match_device(ahci_qoriq_acpi_match, &pdev->dev);
564a7eed YT	275	if (!(of_id \|\| acpi_id))
ecfb4598 TY	276	return -ENODEV;
	277
	278	qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
	279	if (!qoriq_priv)
	280	return -ENOMEM;
	281
564a7eed	282	if (of_id)
2ce3a0bf	283	qoriq_priv->type = (unsigned long)of_id->data;
564a7eed YT	284	else
564a7eed YT	285	qoriq_priv->type = (enum ahci_qoriq_type)acpi_id->driver_data;
ecfb4598	286
2be8481a PM	287	if (unlikely(!ecc_initialized)) {
	288	res = platform_get_resource_byname(pdev,
	289	IORESOURCE_MEM,
	290	"sata-ecc");
	291	if (res) {
	292	qoriq_priv->ecc_addr =
	293	devm_ioremap_resource(dev, res);
	294	if (IS_ERR(qoriq_priv->ecc_addr))
	295	return PTR_ERR(qoriq_priv->ecc_addr);
	296	}
ecfb4598	297	}
2be8481a	298
564a7eed YT	299	if (device_get_dma_attr(&pdev->dev) == DEV_DMA_COHERENT)
564a7eed YT	300	qoriq_priv->is_dmacoherent = true;
ecfb4598 TY	301
	302	rc = ahci_platform_enable_resources(hpriv);
	303	if (rc)
	304	return rc;
	305
	306	hpriv->plat_data = qoriq_priv;
	307	rc = ahci_qoriq_phy_init(hpriv);
	308	if (rc)
	309	goto disable_resources;
	310
	311	rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
	312	&ahci_qoriq_sht);
	313	if (rc)
	314	goto disable_resources;
	315
	316	return 0;
	317
	318	disable_resources:
	319	ahci_platform_disable_resources(hpriv);
	320
	321	return rc;
	322	}
	323
	324	#ifdef CONFIG_PM_SLEEP
	325	static int ahci_qoriq_resume(struct device *dev)
	326	{
	327	struct ata_host *host = dev_get_drvdata(dev);
	328	struct ahci_host_priv *hpriv = host->private_data;
	329	int rc;
	330
	331	rc = ahci_platform_enable_resources(hpriv);
	332	if (rc)
	333	return rc;
	334
	335	rc = ahci_qoriq_phy_init(hpriv);
	336	if (rc)
	337	goto disable_resources;
	338
	339	rc = ahci_platform_resume_host(dev);
	340	if (rc)
	341	goto disable_resources;
	342
	343	/* We resumed so update PM runtime state */
	344	pm_runtime_disable(dev);
	345	pm_runtime_set_active(dev);
	346	pm_runtime_enable(dev);
	347
	348	return 0;
	349
	350	disable_resources:
	351	ahci_platform_disable_resources(hpriv);
	352
	353	return rc;
	354	}
	355	#endif
	356
	357	static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
	358	ahci_qoriq_resume);
	359
	360	static struct platform_driver ahci_qoriq_driver = {
	361	.probe = ahci_qoriq_probe,
	362	.remove = ata_platform_remove_one,
	363	.driver = {
	364	.name = DRV_NAME,
365	.of_match_table = ahci_qoriq_of_match,
564a7eed	366	.acpi_match_table = ahci_qoriq_acpi_match,
ecfb4598 TY	367	.pm = &ahci_qoriq_pm_ops,
	368	},
	369	};
	370	module_platform_driver(ahci_qoriq_driver);
	371
	372	MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
	373	MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
	374	MODULE_LICENSE("GPL");