[linux-2.6-block.git] / drivers / ata / ahci_imx.c

/*
 * copyright (c) 2013 Freescale Semiconductor, Inc.
 * Freescale IMX AHCI SATA platform driver
 *
 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program. If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/ahci_platform.h>
#include <linux/of_device.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/libata.h>
#include "ahci.h"

enum {
	/* Timer 1-ms Register */
	IMX_TIMER1MS				= 0x00e0,
	/* Port0 PHY Control Register */
	IMX_P0PHYCR				= 0x0178,
	IMX_P0PHYCR_TEST_PDDQ			= 1 << 20,
	IMX_P0PHYCR_CR_READ			= 1 << 19,
	IMX_P0PHYCR_CR_WRITE			= 1 << 18,
	IMX_P0PHYCR_CR_CAP_DATA			= 1 << 17,
	IMX_P0PHYCR_CR_CAP_ADDR			= 1 << 16,
	/* Port0 PHY Status Register */
	IMX_P0PHYSR				= 0x017c,
	IMX_P0PHYSR_CR_ACK			= 1 << 18,
	IMX_P0PHYSR_CR_DATA_OUT			= 0xffff << 0,
	/* Lane0 Output Status Register */
	IMX_LANE0_OUT_STAT			= 0x2003,
	IMX_LANE0_OUT_STAT_RX_PLL_STATE		= 1 << 1,
	/* Clock Reset Register */
	IMX_CLOCK_RESET				= 0x7f3f,
	IMX_CLOCK_RESET_RESET			= 1 << 0,
};

enum ahci_imx_type {
	AHCI_IMX53,
	AHCI_IMX6Q,
};

struct imx_ahci_priv {
	struct platform_device *ahci_pdev;
	enum ahci_imx_type type;
	struct clk *ahb_clk;
	struct regmap *gpr;
	bool no_device;
	bool first_time;
};

static int ahci_imx_hotplug;
module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");

static void ahci_imx_host_stop(struct ata_host *host);

static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert)
{
	int timeout = 10;
	u32 crval;
	u32 srval;

	/* Assert or deassert the bit */
	crval = readl(mmio + IMX_P0PHYCR);
	if (assert)
		crval |= bit;
	else
		crval &= ~bit;
	writel(crval, mmio + IMX_P0PHYCR);

	/* Wait for the cr_ack signal */
	do {
		srval = readl(mmio + IMX_P0PHYSR);
		if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK)
			break;
		usleep_range(100, 200);
	} while (--timeout);

	return timeout ? 0 : -ETIMEDOUT;
}

static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio)
{
	u32 crval = addr;
	int ret;

	/* Supply the address on cr_data_in */
	writel(crval, mmio + IMX_P0PHYCR);

	/* Assert the cr_cap_addr signal */
	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true);
	if (ret)
		return ret;

	/* Deassert cr_cap_addr */
	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false);
	if (ret)
		return ret;

	return 0;
}

static int imx_phy_reg_write(u16 val, void __iomem *mmio)
{
	u32 crval = val;
	int ret;

	/* Supply the data on cr_data_in */
	writel(crval, mmio + IMX_P0PHYCR);

	/* Assert the cr_cap_data signal */
	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true);
	if (ret)
		return ret;

	/* Deassert cr_cap_data */
	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false);
	if (ret)
		return ret;

	if (val & IMX_CLOCK_RESET_RESET) {
		/*
		 * In case we're resetting the phy, it's unable to acknowledge,
		 * so we return immediately here.
		 */
		crval |= IMX_P0PHYCR_CR_WRITE;
		writel(crval, mmio + IMX_P0PHYCR);
		goto out;
	}

	/* Assert the cr_write signal */
	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true);
	if (ret)
		return ret;

	/* Deassert cr_write */
	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false);
	if (ret)
		return ret;

out:
	return 0;
}

static int imx_phy_reg_read(u16 *val, void __iomem *mmio)
{
	int ret;

	/* Assert the cr_read signal */
	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true);
	if (ret)
		return ret;

	/* Capture the data from cr_data_out[] */
	*val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT;

	/* Deassert cr_read */
	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false);
	if (ret)
		return ret;

	return 0;
}

static int imx_sata_phy_reset(struct ahci_host_priv *hpriv)
{
	void __iomem *mmio = hpriv->mmio;
	int timeout = 10;
	u16 val;
	int ret;

	/* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */
	ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);
	if (ret)
		return ret;
	ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio);
	if (ret)
		return ret;

	/* Wait for PHY RX_PLL to be stable */
	do {
		usleep_range(100, 200);
		ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio);
		if (ret)
			return ret;
		ret = imx_phy_reg_read(&val, mmio);
		if (ret)
			return ret;
		if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE)
			break;
	} while (--timeout);

	return timeout ? 0 : -ETIMEDOUT;
}

static int imx_sata_enable(struct ahci_host_priv *hpriv)
{
	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
	struct device *dev = &imxpriv->ahci_pdev->dev;
	int ret;

	if (imxpriv->no_device)
		return 0;

	if (hpriv->target_pwr) {
		ret = regulator_enable(hpriv->target_pwr);
		if (ret)
			return ret;
	}

	ret = ahci_platform_enable_clks(hpriv);
	if (ret < 0)
		goto disable_regulator;

	if (imxpriv->type == AHCI_IMX6Q) {
		/*
		 * set PHY Paremeters, two steps to configure the GPR13,
		 * one write for rest of parameters, mask of first write
		 * is 0x07ffffff, and the other one write for setting
		 * the mpll_clk_en.
		 */
		regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
				   IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK |
				   IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK |
				   IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK |
				   IMX6Q_GPR13_SATA_SPD_MODE_MASK |
				   IMX6Q_GPR13_SATA_MPLL_SS_EN |
				   IMX6Q_GPR13_SATA_TX_ATTEN_MASK |
				   IMX6Q_GPR13_SATA_TX_BOOST_MASK |
				   IMX6Q_GPR13_SATA_TX_LVL_MASK |
				   IMX6Q_GPR13_SATA_MPLL_CLK_EN |
				   IMX6Q_GPR13_SATA_TX_EDGE_RATE,
				   IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB |
				   IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
				   IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
				   IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
				   IMX6Q_GPR13_SATA_MPLL_SS_EN |
				   IMX6Q_GPR13_SATA_TX_ATTEN_9_16 |
				   IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB |
				   IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
		regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
				   IMX6Q_GPR13_SATA_MPLL_CLK_EN,
				   IMX6Q_GPR13_SATA_MPLL_CLK_EN);

		ret = imx_sata_phy_reset(hpriv);
		if (ret) {
			dev_err(dev, "failed to reset phy: %d\n", ret);
			goto disable_regulator;
		}
	}

	usleep_range(1000, 2000);

	return 0;

disable_regulator:
	if (hpriv->target_pwr)
		regulator_disable(hpriv->target_pwr);

	return ret;
}

static void imx_sata_disable(struct ahci_host_priv *hpriv)
{
	struct imx_ahci_priv *imxpriv = hpriv->plat_data;

	if (imxpriv->no_device)
		return;

	if (imxpriv->type == AHCI_IMX6Q) {
		regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
				   IMX6Q_GPR13_SATA_MPLL_CLK_EN,
				   !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	}

	ahci_platform_disable_clks(hpriv);

	if (hpriv->target_pwr)
		regulator_disable(hpriv->target_pwr);
}

static void ahci_imx_error_handler(struct ata_port *ap)
{
	u32 reg_val;
	struct ata_device *dev;
	struct ata_host *host = dev_get_drvdata(ap->dev);
	struct ahci_host_priv *hpriv = host->private_data;
	void __iomem *mmio = hpriv->mmio;
	struct imx_ahci_priv *imxpriv = hpriv->plat_data;

	ahci_error_handler(ap);

	if (!(imxpriv->first_time) || ahci_imx_hotplug)
		return;

	imxpriv->first_time = false;

	ata_for_each_dev(dev, &ap->link, ENABLED)
		return;
	/*
	 * Disable link to save power.  An imx ahci port can't be recovered
	 * without full reset once the pddq mode is enabled making it
	 * impossible to use as part of libata LPM.
	 */
	reg_val = readl(mmio + IMX_P0PHYCR);
	writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
	imx_sata_disable(hpriv);
	imxpriv->no_device = true;
}

static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
		       unsigned long deadline)
{
	struct ata_port *ap = link->ap;
	struct ata_host *host = dev_get_drvdata(ap->dev);
	struct ahci_host_priv *hpriv = host->private_data;
	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
	int ret = -EIO;

	if (imxpriv->type == AHCI_IMX53)
		ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
	else if (imxpriv->type == AHCI_IMX6Q)
		ret = ahci_ops.softreset(link, class, deadline);

	return ret;
}

static struct ata_port_operations ahci_imx_ops = {
	.inherits	= &ahci_ops,
	.host_stop	= ahci_imx_host_stop,
	.error_handler	= ahci_imx_error_handler,
	.softreset	= ahci_imx_softreset,
};

static const struct ata_port_info ahci_imx_port_info = {
	.flags		= AHCI_FLAG_COMMON,
	.pio_mask	= ATA_PIO4,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &ahci_imx_ops,
};

static const struct of_device_id imx_ahci_of_match[] = {
	{ .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
	{ .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
	{},
};
MODULE_DEVICE_TABLE(of, imx_ahci_of_match);

static int imx_ahci_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	const struct of_device_id *of_id;
	struct ahci_host_priv *hpriv;
	struct imx_ahci_priv *imxpriv;
	unsigned int reg_val;
	int ret;

	of_id = of_match_device(imx_ahci_of_match, dev);
	if (!of_id)
		return -EINVAL;

	imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
	if (!imxpriv)
		return -ENOMEM;

	imxpriv->ahci_pdev = pdev;
	imxpriv->no_device = false;
	imxpriv->first_time = true;
	imxpriv->type = (enum ahci_imx_type)of_id->data;
	imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
	if (IS_ERR(imxpriv->ahb_clk)) {
		dev_err(dev, "can't get ahb clock.\n");
		return PTR_ERR(imxpriv->ahb_clk);
	}

	if (imxpriv->type == AHCI_IMX6Q) {
		imxpriv->gpr = syscon_regmap_lookup_by_compatible(
							"fsl,imx6q-iomuxc-gpr");
		if (IS_ERR(imxpriv->gpr)) {
			dev_err(dev,
				"failed to find fsl,imx6q-iomux-gpr regmap\n");
			return PTR_ERR(imxpriv->gpr);
		}
	}

	hpriv = ahci_platform_get_resources(pdev);
	if (IS_ERR(hpriv))
		return PTR_ERR(hpriv);

	hpriv->plat_data = imxpriv;

	ret = imx_sata_enable(hpriv);
	if (ret)
		return ret;

	/*
	 * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
	 * and IP vendor specific register IMX_TIMER1MS.
	 * Configure CAP_SSS (support stagered spin up).
	 * Implement the port0.
	 * Get the ahb clock rate, and configure the TIMER1MS register.
	 */
	reg_val = readl(hpriv->mmio + HOST_CAP);
	if (!(reg_val & HOST_CAP_SSS)) {
		reg_val |= HOST_CAP_SSS;
		writel(reg_val, hpriv->mmio + HOST_CAP);
	}
	reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
	if (!(reg_val & 0x1)) {
		reg_val |= 0x1;
		writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
	}

	reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
	writel(reg_val, hpriv->mmio + IMX_TIMER1MS);

	ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info, 0, 0);
	if (ret)
		imx_sata_disable(hpriv);

	return ret;
}

static void ahci_imx_host_stop(struct ata_host *host)
{
	struct ahci_host_priv *hpriv = host->private_data;

	imx_sata_disable(hpriv);
}

#ifdef CONFIG_PM_SLEEP
static int imx_ahci_suspend(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	int ret;

	ret = ahci_platform_suspend_host(dev);
	if (ret)
		return ret;

	imx_sata_disable(hpriv);

	return 0;
}

static int imx_ahci_resume(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	int ret;

	ret = imx_sata_enable(hpriv);
	if (ret)
		return ret;

	return ahci_platform_resume_host(dev);
}
#endif

static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume);

static struct platform_driver imx_ahci_driver = {
	.probe = imx_ahci_probe,
	.remove = ata_platform_remove_one,
	.driver = {
		.name = "ahci-imx",
		.owner = THIS_MODULE,
		.of_match_table = imx_ahci_of_match,
		.pm = &ahci_imx_pm_ops,
	},
};
module_platform_driver(imx_ahci_driver);

MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("ahci:imx");
Commit	Line	Data
9e54eae2	1	/*
8b789d89	2	* copyright (c) 2013 Freescale Semiconductor, Inc.
9e54eae2	3	* Freescale IMX AHCI SATA platform driver
9e54eae2 RZ	4	*
	5	* based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/regmap.h>
	24	#include <linux/ahci_platform.h>
	25	#include <linux/of_device.h>
	26	#include <linux/mfd/syscon.h>
	27	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
8b789d89	28	#include <linux/libata.h>
9e54eae2 RZ	29	#include "ahci.h"
	30
	31	enum {
24a9ad5b SG	32	/* Timer 1-ms Register */
	33	IMX_TIMER1MS = 0x00e0,
	34	/* Port0 PHY Control Register */
	35	IMX_P0PHYCR = 0x0178,
	36	IMX_P0PHYCR_TEST_PDDQ = 1 << 20,
e783c51c SG	37	IMX_P0PHYCR_CR_READ = 1 << 19,
	38	IMX_P0PHYCR_CR_WRITE = 1 << 18,
	39	IMX_P0PHYCR_CR_CAP_DATA = 1 << 17,
	40	IMX_P0PHYCR_CR_CAP_ADDR = 1 << 16,
	41	/* Port0 PHY Status Register */
	42	IMX_P0PHYSR = 0x017c,
	43	IMX_P0PHYSR_CR_ACK = 1 << 18,
	44	IMX_P0PHYSR_CR_DATA_OUT = 0xffff << 0,
	45	/* Lane0 Output Status Register */
	46	IMX_LANE0_OUT_STAT = 0x2003,
	47	IMX_LANE0_OUT_STAT_RX_PLL_STATE = 1 << 1,
	48	/* Clock Reset Register */
	49	IMX_CLOCK_RESET = 0x7f3f,
	50	IMX_CLOCK_RESET_RESET = 1 << 0,
9e54eae2 RZ	51	};
9e54eae2 RZ	52
4a23d179 MV	53	enum ahci_imx_type {
	54	AHCI_IMX53,
	55	AHCI_IMX6Q,
	56	};
	57
9e54eae2 RZ	58	struct imx_ahci_priv {
9e54eae2 RZ	59	struct platform_device *ahci_pdev;
4a23d179	60	enum ahci_imx_type type;
9e54eae2 RZ	61	struct clk *ahb_clk;
9e54eae2 RZ	62	struct regmap *gpr;
8b789d89 RZ	63	bool no_device;
	64	bool first_time;
	65	};
	66
	67	static int ahci_imx_hotplug;
	68	module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
	69	MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
	70
90870d79 HG	71	static void ahci_imx_host_stop(struct ata_host *host);
90870d79 HG	72
e783c51c SG	73	static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert)
	74	{
	75	int timeout = 10;
	76	u32 crval;
	77	u32 srval;
	78
	79	/* Assert or deassert the bit */
	80	crval = readl(mmio + IMX_P0PHYCR);
	81	if (assert)
	82	crval \|= bit;
	83	else
	84	crval &= ~bit;
	85	writel(crval, mmio + IMX_P0PHYCR);
	86
	87	/* Wait for the cr_ack signal */
	88	do {
	89	srval = readl(mmio + IMX_P0PHYSR);
	90	if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK)
	91	break;
	92	usleep_range(100, 200);
	93	} while (--timeout);
	94
	95	return timeout ? 0 : -ETIMEDOUT;
	96	}
	97
	98	static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio)
	99	{
	100	u32 crval = addr;
	101	int ret;
	102
	103	/* Supply the address on cr_data_in */
	104	writel(crval, mmio + IMX_P0PHYCR);
	105
	106	/* Assert the cr_cap_addr signal */
	107	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true);
	108	if (ret)
	109	return ret;
	110
	111	/* Deassert cr_cap_addr */
	112	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false);
	113	if (ret)
	114	return ret;
	115
	116	return 0;
	117	}
	118
	119	static int imx_phy_reg_write(u16 val, void __iomem *mmio)
	120	{
	121	u32 crval = val;
	122	int ret;
	123
	124	/* Supply the data on cr_data_in */
	125	writel(crval, mmio + IMX_P0PHYCR);
	126
	127	/* Assert the cr_cap_data signal */
	128	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true);
	129	if (ret)
	130	return ret;
	131
	132	/* Deassert cr_cap_data */
	133	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false);
	134	if (ret)
	135	return ret;
	136
137	if (val & IMX_CLOCK_RESET_RESET) {
138	/*
139	* In case we're resetting the phy, it's unable to acknowledge,
140	* so we return immediately here.
141	*/
142	crval \|= IMX_P0PHYCR_CR_WRITE;
143	writel(crval, mmio + IMX_P0PHYCR);
144	goto out;
145	}
146
147	/* Assert the cr_write signal */
148	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true);
149	if (ret)
150	return ret;
151
152	/* Deassert cr_write */
153	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false);
154	if (ret)
155	return ret;
156
157	out:
158	return 0;
159	}
160
161	static int imx_phy_reg_read(u16 val, void __iomem mmio)
162	{
163	int ret;
164
165	/* Assert the cr_read signal */
166	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true);
167	if (ret)
168	return ret;
169
170	/* Capture the data from cr_data_out[] */
171	*val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT;
172
173	/* Deassert cr_read */
174	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false);
175	if (ret)
176	return ret;
177
178	return 0;
179	}
180
181	static int imx_sata_phy_reset(struct ahci_host_priv *hpriv)
182	{
183	void __iomem *mmio = hpriv->mmio;
184	int timeout = 10;
185	u16 val;
186	int ret;
187
188	/* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */
189	ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);
190	if (ret)
191	return ret;
192	ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio);
193	if (ret)
194	return ret;
195
196	/* Wait for PHY RX_PLL to be stable */
197	do {
198	usleep_range(100, 200);
199	ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio);
200	if (ret)
201	return ret;
202	ret = imx_phy_reg_read(&val, mmio);
203	if (ret)
204	return ret;
205	if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE)
206	break;
207	} while (--timeout);
208
209	return timeout ? 0 : -ETIMEDOUT;
210	}
211
90870d79	212	static int imx_sata_enable(struct ahci_host_priv *hpriv)
8403e2ec	213	{
90870d79	214	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
e783c51c	215	struct device *dev = &imxpriv->ahci_pdev->dev;
8403e2ec MV	216	int ret;
8403e2ec MV	217
90870d79 HG	218	if (imxpriv->no_device)
	219	return 0;
	220
	221	if (hpriv->target_pwr) {
	222	ret = regulator_enable(hpriv->target_pwr);
	223	if (ret)
4a23d179	224	return ret;
4a23d179 MV	225	}
4a23d179 MV	226
90870d79 HG	227	ret = ahci_platform_enable_clks(hpriv);
	228	if (ret < 0)
	229	goto disable_regulator;
8403e2ec	230
4a23d179	231	if (imxpriv->type == AHCI_IMX6Q) {
90870d79 HG	232	/*
	233	* set PHY Paremeters, two steps to configure the GPR13,
	234	* one write for rest of parameters, mask of first write
	235	* is 0x07ffffff, and the other one write for setting
	236	* the mpll_clk_en.
	237	*/
	238	regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
	239	IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK \|
	240	IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK \|
	241	IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK \|
	242	IMX6Q_GPR13_SATA_SPD_MODE_MASK \|
	243	IMX6Q_GPR13_SATA_MPLL_SS_EN \|
	244	IMX6Q_GPR13_SATA_TX_ATTEN_MASK \|
	245	IMX6Q_GPR13_SATA_TX_BOOST_MASK \|
	246	IMX6Q_GPR13_SATA_TX_LVL_MASK \|
	247	IMX6Q_GPR13_SATA_MPLL_CLK_EN \|
	248	IMX6Q_GPR13_SATA_TX_EDGE_RATE,
	249	IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB \|
	250	IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M \|
	251	IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F \|
	252	IMX6Q_GPR13_SATA_SPD_MODE_3P0G \|
	253	IMX6Q_GPR13_SATA_MPLL_SS_EN \|
	254	IMX6Q_GPR13_SATA_TX_ATTEN_9_16 \|
	255	IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB \|
	256	IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
4a23d179 MV	257	regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
	258	IMX6Q_GPR13_SATA_MPLL_CLK_EN,
	259	IMX6Q_GPR13_SATA_MPLL_CLK_EN);
e783c51c SG	260
	261	ret = imx_sata_phy_reset(hpriv);
	262	if (ret) {
	263	dev_err(dev, "failed to reset phy: %d\n", ret);
	264	goto disable_regulator;
	265	}
4a23d179	266	}
8403e2ec MV	267
	268	usleep_range(1000, 2000);
	269
	270	return 0;
4a23d179	271
90870d79 HG	272	disable_regulator:
	273	if (hpriv->target_pwr)
	274	regulator_disable(hpriv->target_pwr);
	275
4a23d179	276	return ret;
8403e2ec MV	277	}
8403e2ec MV	278
90870d79	279	static void imx_sata_disable(struct ahci_host_priv *hpriv)
8403e2ec	280	{
90870d79 HG	281	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
	282
	283	if (imxpriv->no_device)
	284	return;
8403e2ec	285
4a23d179 MV	286	if (imxpriv->type == AHCI_IMX6Q) {
	287	regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
	288	IMX6Q_GPR13_SATA_MPLL_CLK_EN,
	289	!IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	290	}
	291
90870d79	292	ahci_platform_disable_clks(hpriv);
4a23d179	293
90870d79 HG	294	if (hpriv->target_pwr)
90870d79 HG	295	regulator_disable(hpriv->target_pwr);
8403e2ec MV	296	}
8403e2ec MV	297
8b789d89 RZ	298	static void ahci_imx_error_handler(struct ata_port *ap)
	299	{
	300	u32 reg_val;
	301	struct ata_device *dev;
	302	struct ata_host *host = dev_get_drvdata(ap->dev);
	303	struct ahci_host_priv *hpriv = host->private_data;
	304	void __iomem *mmio = hpriv->mmio;
90870d79	305	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
8b789d89 RZ	306
	307	ahci_error_handler(ap);
	308
	309	if (!(imxpriv->first_time) \|\| ahci_imx_hotplug)
	310	return;
	311
	312	imxpriv->first_time = false;
	313
	314	ata_for_each_dev(dev, &ap->link, ENABLED)
	315	return;
	316	/*
	317	* Disable link to save power. An imx ahci port can't be recovered
	318	* without full reset once the pddq mode is enabled making it
	319	* impossible to use as part of libata LPM.
	320	*/
24a9ad5b SG	321	reg_val = readl(mmio + IMX_P0PHYCR);
24a9ad5b SG	322	writel(reg_val \| IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
90870d79	323	imx_sata_disable(hpriv);
8b789d89 RZ	324	imxpriv->no_device = true;
	325	}
	326
ee4e5a9a	327	static int ahci_imx_softreset(struct ata_link link, unsigned int class,
4a23d179 MV	328	unsigned long deadline)
	329	{
	330	struct ata_port *ap = link->ap;
90870d79 HG	331	struct ata_host *host = dev_get_drvdata(ap->dev);
	332	struct ahci_host_priv *hpriv = host->private_data;
	333	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
4a23d179 MV	334	int ret = -EIO;
	335
	336	if (imxpriv->type == AHCI_IMX53)
	337	ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
	338	else if (imxpriv->type == AHCI_IMX6Q)
	339	ret = ahci_ops.softreset(link, class, deadline);
	340
	341	return ret;
	342	}
	343
8b789d89	344	static struct ata_port_operations ahci_imx_ops = {
90870d79 HG	345	.inherits = &ahci_ops,
90870d79 HG	346	.host_stop = ahci_imx_host_stop,
8b789d89	347	.error_handler = ahci_imx_error_handler,
4a23d179	348	.softreset = ahci_imx_softreset,
8b789d89 RZ	349	};
	350
	351	static const struct ata_port_info ahci_imx_port_info = {
	352	.flags = AHCI_FLAG_COMMON,
	353	.pio_mask = ATA_PIO4,
	354	.udma_mask = ATA_UDMA6,
	355	.port_ops = &ahci_imx_ops,
9e54eae2 RZ	356	};
9e54eae2 RZ	357
9e54eae2	358	static const struct of_device_id imx_ahci_of_match[] = {
4a23d179 MV	359	{ .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
4a23d179 MV	360	{ .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
9e54eae2 RZ	361	{},
	362	};
	363	MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
	364
	365	static int imx_ahci_probe(struct platform_device *pdev)
	366	{
	367	struct device *dev = &pdev->dev;
9e54eae2	368	const struct of_device_id *of_id;
90870d79	369	struct ahci_host_priv *hpriv;
9e54eae2	370	struct imx_ahci_priv *imxpriv;
90870d79	371	unsigned int reg_val;
9e54eae2 RZ	372	int ret;
9e54eae2 RZ	373
4a23d179 MV	374	of_id = of_match_device(imx_ahci_of_match, dev);
	375	if (!of_id)
	376	return -EINVAL;
	377
9e54eae2	378	imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
90870d79	379	if (!imxpriv)
9e54eae2	380	return -ENOMEM;
9e54eae2	381
e783c51c	382	imxpriv->ahci_pdev = pdev;
8b789d89 RZ	383	imxpriv->no_device = false;
8b789d89 RZ	384	imxpriv->first_time = true;
90870d79	385	imxpriv->type = (enum ahci_imx_type)of_id->data;
9e54eae2 RZ	386	imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
	387	if (IS_ERR(imxpriv->ahb_clk)) {
	388	dev_err(dev, "can't get ahb clock.\n");
90870d79	389	return PTR_ERR(imxpriv->ahb_clk);
9e54eae2 RZ	390	}
9e54eae2 RZ	391
90870d79 HG	392	if (imxpriv->type == AHCI_IMX6Q) {
	393	imxpriv->gpr = syscon_regmap_lookup_by_compatible(
	394	"fsl,imx6q-iomuxc-gpr");
	395	if (IS_ERR(imxpriv->gpr)) {
	396	dev_err(dev,
	397	"failed to find fsl,imx6q-iomux-gpr regmap\n");
	398	return PTR_ERR(imxpriv->gpr);
4a23d179 MV	399	}
	400	}
	401
90870d79 HG	402	hpriv = ahci_platform_get_resources(pdev);
	403	if (IS_ERR(hpriv))
	404	return PTR_ERR(hpriv);
	405
	406	hpriv->plat_data = imxpriv;
9e54eae2	407
90870d79 HG	408	ret = imx_sata_enable(hpriv);
	409	if (ret)
	410	return ret;
9e54eae2	411
90870d79 HG	412	/*
90870d79 HG	413	* Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
24a9ad5b	414	* and IP vendor specific register IMX_TIMER1MS.
90870d79 HG	415	* Configure CAP_SSS (support stagered spin up).
	416	* Implement the port0.
	417	* Get the ahb clock rate, and configure the TIMER1MS register.
	418	*/
	419	reg_val = readl(hpriv->mmio + HOST_CAP);
	420	if (!(reg_val & HOST_CAP_SSS)) {
	421	reg_val \|= HOST_CAP_SSS;
	422	writel(reg_val, hpriv->mmio + HOST_CAP);
	423	}
	424	reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
	425	if (!(reg_val & 0x1)) {
	426	reg_val \|= 0x1;
	427	writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
9e54eae2 RZ	428	}
9e54eae2 RZ	429
90870d79	430	reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
24a9ad5b	431	writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
9e54eae2	432
90870d79 HG	433	ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info, 0, 0);
	434	if (ret)
	435	imx_sata_disable(hpriv);
9e54eae2	436
90870d79 HG	437	return ret;
90870d79 HG	438	}
4a23d179	439
90870d79 HG	440	static void ahci_imx_host_stop(struct ata_host *host)
	441	{
	442	struct ahci_host_priv *hpriv = host->private_data;
8403e2ec	443
90870d79 HG	444	imx_sata_disable(hpriv);
90870d79 HG	445	}
9e54eae2	446
46ce6b74	447	#ifdef CONFIG_PM_SLEEP
90870d79 HG	448	static int imx_ahci_suspend(struct device *dev)
	449	{
	450	struct ata_host *host = dev_get_drvdata(dev);
	451	struct ahci_host_priv *hpriv = host->private_data;
	452	int ret;
9e54eae2	453
90870d79 HG	454	ret = ahci_platform_suspend_host(dev);
90870d79 HG	455	if (ret)
9e54eae2	456	return ret;
90870d79 HG	457
90870d79 HG	458	imx_sata_disable(hpriv);
9e54eae2 RZ	459
	460	return 0;
	461	}
	462
90870d79	463	static int imx_ahci_resume(struct device *dev)
9e54eae2	464	{
90870d79 HG	465	struct ata_host *host = dev_get_drvdata(dev);
	466	struct ahci_host_priv *hpriv = host->private_data;
	467	int ret;
9e54eae2	468
90870d79 HG	469	ret = imx_sata_enable(hpriv);
	470	if (ret)
	471	return ret;
	472
	473	return ahci_platform_resume_host(dev);
9e54eae2	474	}
46ce6b74	475	#endif
9e54eae2	476
90870d79 HG	477	static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume);
90870d79 HG	478
9e54eae2 RZ	479	static struct platform_driver imx_ahci_driver = {
9e54eae2 RZ	480	.probe = imx_ahci_probe,
90870d79	481	.remove = ata_platform_remove_one,
9e54eae2 RZ	482	.driver = {
	483	.name = "ahci-imx",
	484	.owner = THIS_MODULE,
	485	.of_match_table = imx_ahci_of_match,
90870d79	486	.pm = &ahci_imx_pm_ops,
9e54eae2 RZ	487	},
	488	};
	489	module_platform_driver(imx_ahci_driver);
	490
	491	MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
	492	MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
	493	MODULE_LICENSE("GPL");
	494	MODULE_ALIAS("ahci:imx");