[linux-2.6-block.git] / drivers / ata / ahci_da850.c

/*
 * DaVinci DA850 AHCI SATA platform driver
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/libata.h>
#include <linux/ahci_platform.h>
#include "ahci.h"

#define DRV_NAME		"ahci_da850"
#define HARDRESET_RETRIES	5

/* SATA PHY Control Register offset from AHCI base */
#define SATA_P0PHYCR_REG	0x178

#define SATA_PHY_MPY(x)		((x) << 0)
#define SATA_PHY_LOS(x)		((x) << 6)
#define SATA_PHY_RXCDR(x)	((x) << 10)
#define SATA_PHY_RXEQ(x)	((x) << 13)
#define SATA_PHY_TXSWING(x)	((x) << 19)
#define SATA_PHY_ENPLL(x)	((x) << 31)

/*
 * The multiplier needed for 1.5GHz PLL output.
 *
 * NOTE: This is currently hardcoded to be suitable for 100MHz crystal
 * frequency (which is used by DA850 EVM board) and may need to be changed
 * if you would like to use this driver on some other board.
 */
#define DA850_SATA_CLK_MULTIPLIER	7

static void da850_sata_init(struct device *dev, void __iomem *pwrdn_reg,
			    void __iomem *ahci_base)
{
	unsigned int val;

	/* Enable SATA clock receiver */
	val = readl(pwrdn_reg);
	val &= ~BIT(0);
	writel(val, pwrdn_reg);

	val = SATA_PHY_MPY(DA850_SATA_CLK_MULTIPLIER + 1) | SATA_PHY_LOS(1) |
	      SATA_PHY_RXCDR(4) | SATA_PHY_RXEQ(1) | SATA_PHY_TXSWING(3) |
	      SATA_PHY_ENPLL(1);

	writel(val, ahci_base + SATA_P0PHYCR_REG);
}

static int ahci_da850_softreset(struct ata_link *link,
				unsigned int *class, unsigned long deadline)
{
	int pmp, ret;

	pmp = sata_srst_pmp(link);

	/*
	 * There's an issue with the SATA controller on da850 SoCs: if we
	 * enable Port Multiplier support, but the drive is connected directly
	 * to the board, it can't be detected. As a workaround: if PMP is
	 * enabled, we first call ahci_do_softreset() and pass it the result of
	 * sata_srst_pmp(). If this call fails, we retry with pmp = 0.
	 */
	ret = ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
	if (pmp && ret == -EBUSY)
		return ahci_do_softreset(link, class, 0,
					 deadline, ahci_check_ready);

	return ret;
}

static int ahci_da850_hardreset(struct ata_link *link,
				unsigned int *class, unsigned long deadline)
{
	int ret, retry = HARDRESET_RETRIES;
	bool online;

	/*
	 * In order to correctly service the LCD controller of the da850 SoC,
	 * we increased the PLL0 frequency to 456MHz from the default 300MHz.
	 *
	 * This made the SATA controller unstable and the hardreset operation
	 * does not always succeed the first time. Before really giving up to
	 * bring up the link, retry the reset a couple times.
	 */
	do {
		ret = ahci_do_hardreset(link, class, deadline, &online);
		if (online)
			return ret;
	} while (retry--);

	return ret;
}

static struct ata_port_operations ahci_da850_port_ops = {
	.inherits = &ahci_platform_ops,
	.softreset = ahci_da850_softreset,
	/*
	 * No need to override .pmp_softreset - it's only used for actual
	 * PMP-enabled ports.
	 */
	.hardreset = ahci_da850_hardreset,
	.pmp_hardreset = ahci_da850_hardreset,
};

static const struct ata_port_info ahci_da850_port_info = {
	.flags		= AHCI_FLAG_COMMON,
	.pio_mask	= ATA_PIO4,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &ahci_da850_port_ops,
};

static struct scsi_host_template ahci_platform_sht = {
	AHCI_SHT(DRV_NAME),
};

static int ahci_da850_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct ahci_host_priv *hpriv;
	struct resource *res;
	void __iomem *pwrdn_reg;
	struct clk *clk;
	int rc;

	hpriv = ahci_platform_get_resources(pdev);
	if (IS_ERR(hpriv))
		return PTR_ERR(hpriv);

	/*
	 * Internally ahci_platform_get_resources() calls clk_get(dev, NULL)
	 * when trying to obtain the functional clock. This SATA controller
	 * uses two clocks for which we specify two connection ids. If we don't
	 * have the functional clock at this point - call clk_get() again with
	 * con_id = "fck".
	 */
	if (!hpriv->clks[0]) {
		clk = clk_get(dev, "fck");
		if (IS_ERR(clk))
			return PTR_ERR(clk);

		hpriv->clks[0] = clk;
	}

	rc = ahci_platform_enable_resources(hpriv);
	if (rc)
		return rc;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!res)
		goto disable_resources;

	pwrdn_reg = devm_ioremap(dev, res->start, resource_size(res));
	if (!pwrdn_reg)
		goto disable_resources;

	da850_sata_init(dev, pwrdn_reg, hpriv->mmio);

	rc = ahci_platform_init_host(pdev, hpriv, &ahci_da850_port_info,
				     &ahci_platform_sht);
	if (rc)
		goto disable_resources;

	return 0;
disable_resources:
	ahci_platform_disable_resources(hpriv);
	return rc;
}

static SIMPLE_DEV_PM_OPS(ahci_da850_pm_ops, ahci_platform_suspend,
			 ahci_platform_resume);

static const struct of_device_id ahci_da850_of_match[] = {
	{ .compatible = "ti,da850-ahci", },
	{ },
};
MODULE_DEVICE_TABLE(of, ahci_da850_of_match);

static struct platform_driver ahci_da850_driver = {
	.probe = ahci_da850_probe,
	.remove = ata_platform_remove_one,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = ahci_da850_of_match,
		.pm = &ahci_da850_pm_ops,
	},
};
module_platform_driver(ahci_da850_driver);

MODULE_DESCRIPTION("DaVinci DA850 AHCI SATA platform driver");
MODULE_AUTHOR("Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
ae8723f8 BZ	1	/*
	2	* DaVinci DA850 AHCI SATA platform driver
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2, or (at your option)
	7	* any later version.
	8	*/
	9
	10	#include <linux/kernel.h>
	11	#include <linux/module.h>
	12	#include <linux/pm.h>
	13	#include <linux/device.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/libata.h>
	16	#include <linux/ahci_platform.h>
	17	#include "ahci.h"
	18
d3d557cf BG	19	#define DRV_NAME "ahci_da850"
d3d557cf BG	20	#define HARDRESET_RETRIES 5
018d5ef2	21
ae8723f8 BZ	22	/* SATA PHY Control Register offset from AHCI base */
	23	#define SATA_P0PHYCR_REG 0x178
	24
	25	#define SATA_PHY_MPY(x) ((x) << 0)
	26	#define SATA_PHY_LOS(x) ((x) << 6)
	27	#define SATA_PHY_RXCDR(x) ((x) << 10)
	28	#define SATA_PHY_RXEQ(x) ((x) << 13)
	29	#define SATA_PHY_TXSWING(x) ((x) << 19)
	30	#define SATA_PHY_ENPLL(x) ((x) << 31)
	31
	32	/*
	33	* The multiplier needed for 1.5GHz PLL output.
	34	*
	35	* NOTE: This is currently hardcoded to be suitable for 100MHz crystal
	36	* frequency (which is used by DA850 EVM board) and may need to be changed
	37	* if you would like to use this driver on some other board.
	38	*/
	39	#define DA850_SATA_CLK_MULTIPLIER 7
	40
	41	static void da850_sata_init(struct device dev, void __iomem pwrdn_reg,
	42	void __iomem *ahci_base)
	43	{
	44	unsigned int val;
	45
	46	/* Enable SATA clock receiver */
	47	val = readl(pwrdn_reg);
	48	val &= ~BIT(0);
	49	writel(val, pwrdn_reg);
	50
	51	val = SATA_PHY_MPY(DA850_SATA_CLK_MULTIPLIER + 1) \| SATA_PHY_LOS(1) \|
	52	SATA_PHY_RXCDR(4) \| SATA_PHY_RXEQ(1) \| SATA_PHY_TXSWING(3) \|
	53	SATA_PHY_ENPLL(1);
	54
	55	writel(val, ahci_base + SATA_P0PHYCR_REG);
	56	}
	57
f4d435f3 BG	58	static int ahci_da850_softreset(struct ata_link *link,
	59	unsigned int *class, unsigned long deadline)
	60	{
	61	int pmp, ret;
	62
	63	pmp = sata_srst_pmp(link);
	64
	65	/*
	66	* There's an issue with the SATA controller on da850 SoCs: if we
	67	* enable Port Multiplier support, but the drive is connected directly
	68	* to the board, it can't be detected. As a workaround: if PMP is
	69	* enabled, we first call ahci_do_softreset() and pass it the result of
	70	* sata_srst_pmp(). If this call fails, we retry with pmp = 0.
	71	*/
	72	ret = ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
	73	if (pmp && ret == -EBUSY)
	74	return ahci_do_softreset(link, class, 0,
	75	deadline, ahci_check_ready);
	76
	77	return ret;
	78	}
	79
d3d557cf BG	80	static int ahci_da850_hardreset(struct ata_link *link,
	81	unsigned int *class, unsigned long deadline)
	82	{
	83	int ret, retry = HARDRESET_RETRIES;
	84	bool online;
	85
	86	/*
	87	* In order to correctly service the LCD controller of the da850 SoC,
	88	* we increased the PLL0 frequency to 456MHz from the default 300MHz.
	89	*
	90	* This made the SATA controller unstable and the hardreset operation
	91	* does not always succeed the first time. Before really giving up to
	92	* bring up the link, retry the reset a couple times.
	93	*/
	94	do {
	95	ret = ahci_do_hardreset(link, class, deadline, &online);
	96	if (online)
	97	return ret;
	98	} while (retry--);
	99
	100	return ret;
	101	}
	102
f4d435f3 BG	103	static struct ata_port_operations ahci_da850_port_ops = {
	104	.inherits = &ahci_platform_ops,
	105	.softreset = ahci_da850_softreset,
	106	/*
	107	* No need to override .pmp_softreset - it's only used for actual
	108	* PMP-enabled ports.
	109	*/
d3d557cf BG	110	.hardreset = ahci_da850_hardreset,
d3d557cf BG	111	.pmp_hardreset = ahci_da850_hardreset,
f4d435f3 BG	112	};
f4d435f3 BG	113
ae8723f8 BZ	114	static const struct ata_port_info ahci_da850_port_info = {
	115	.flags = AHCI_FLAG_COMMON,
	116	.pio_mask = ATA_PIO4,
	117	.udma_mask = ATA_UDMA6,
f4d435f3	118	.port_ops = &ahci_da850_port_ops,
ae8723f8 BZ	119	};
ae8723f8 BZ	120
018d5ef2 AM	121	static struct scsi_host_template ahci_platform_sht = {
	122	AHCI_SHT(DRV_NAME),
	123	};
	124
ae8723f8 BZ	125	static int ahci_da850_probe(struct platform_device *pdev)
	126	{
	127	struct device *dev = &pdev->dev;
	128	struct ahci_host_priv *hpriv;
	129	struct resource *res;
	130	void __iomem *pwrdn_reg;
82dbe1a6	131	struct clk *clk;
ae8723f8 BZ	132	int rc;
	133
	134	hpriv = ahci_platform_get_resources(pdev);
	135	if (IS_ERR(hpriv))
	136	return PTR_ERR(hpriv);
	137
82dbe1a6 BG	138	/*
	139	* Internally ahci_platform_get_resources() calls clk_get(dev, NULL)
	140	* when trying to obtain the functional clock. This SATA controller
	141	* uses two clocks for which we specify two connection ids. If we don't
	142	* have the functional clock at this point - call clk_get() again with
	143	* con_id = "fck".
	144	*/
	145	if (!hpriv->clks[0]) {
	146	clk = clk_get(dev, "fck");
	147	if (IS_ERR(clk))
	148	return PTR_ERR(clk);
	149
	150	hpriv->clks[0] = clk;
	151	}
	152
ae8723f8 BZ	153	rc = ahci_platform_enable_resources(hpriv);
	154	if (rc)
	155	return rc;
	156
	157	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	158	if (!res)
	159	goto disable_resources;
	160
	161	pwrdn_reg = devm_ioremap(dev, res->start, resource_size(res));
	162	if (!pwrdn_reg)
	163	goto disable_resources;
	164
	165	da850_sata_init(dev, pwrdn_reg, hpriv->mmio);
	166
018d5ef2 AM	167	rc = ahci_platform_init_host(pdev, hpriv, &ahci_da850_port_info,
018d5ef2 AM	168	&ahci_platform_sht);
ae8723f8 BZ	169	if (rc)
	170	goto disable_resources;
	171
	172	return 0;
	173	disable_resources:
	174	ahci_platform_disable_resources(hpriv);
	175	return rc;
	176	}
	177
	178	static SIMPLE_DEV_PM_OPS(ahci_da850_pm_ops, ahci_platform_suspend,
	179	ahci_platform_resume);
	180
bf4ae3f0 BG	181	static const struct of_device_id ahci_da850_of_match[] = {
	182	{ .compatible = "ti,da850-ahci", },
	183	{ },
	184	};
	185	MODULE_DEVICE_TABLE(of, ahci_da850_of_match);
	186
ae8723f8 BZ	187	static struct platform_driver ahci_da850_driver = {
	188	.probe = ahci_da850_probe,
	189	.remove = ata_platform_remove_one,
	190	.driver = {
018d5ef2	191	.name = DRV_NAME,
bf4ae3f0	192	.of_match_table = ahci_da850_of_match,
ae8723f8 BZ	193	.pm = &ahci_da850_pm_ops,
	194	},
	195	};
	196	module_platform_driver(ahci_da850_driver);
	197
	198	MODULE_DESCRIPTION("DaVinci DA850 AHCI SATA platform driver");
	199	MODULE_AUTHOR("Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>");
	200	MODULE_LICENSE("GPL");