[linux-block.git] / drivers / ata / ahci_da850.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * DaVinci DA850 AHCI SATA platform driver
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/libata.h>
#include <linux/ahci_platform.h>
#include "ahci.h"

#define DRV_NAME		"ahci_da850"
#define HARDRESET_RETRIES	5

/* SATA PHY Control Register offset from AHCI base */
#define SATA_P0PHYCR_REG	0x178

#define SATA_PHY_MPY(x)		((x) << 0)
#define SATA_PHY_LOS(x)		((x) << 6)
#define SATA_PHY_RXCDR(x)	((x) << 10)
#define SATA_PHY_RXEQ(x)	((x) << 13)
#define SATA_PHY_TXSWING(x)	((x) << 19)
#define SATA_PHY_ENPLL(x)	((x) << 31)

static void da850_sata_init(struct device *dev, void __iomem *pwrdn_reg,
			    void __iomem *ahci_base, u32 mpy)
{
	unsigned int val;

	/* Enable SATA clock receiver */
	val = readl(pwrdn_reg);
	val &= ~BIT(0);
	writel(val, pwrdn_reg);

	val = SATA_PHY_MPY(mpy) | SATA_PHY_LOS(1) | SATA_PHY_RXCDR(4) |
	      SATA_PHY_RXEQ(1) | SATA_PHY_TXSWING(3) | SATA_PHY_ENPLL(1);

	writel(val, ahci_base + SATA_P0PHYCR_REG);
}

static u32 ahci_da850_calculate_mpy(unsigned long refclk_rate)
{
	u32 pll_output = 1500000000, needed;

	/*
	 * We need to determine the value of the multiplier (MPY) bits.
	 * In order to include the 12.5 multiplier we need to first divide
	 * the refclk rate by ten.
	 *
	 * __div64_32() turned out to be unreliable, sometimes returning
	 * false results.
	 */
	WARN((refclk_rate % 10) != 0, "refclk must be divisible by 10");
	needed = pll_output / (refclk_rate / 10);

	/*
	 * What we have now is (multiplier * 10).
	 *
	 * Let's determine the actual register value we need to write.
	 */

	switch (needed) {
	case 50:
		return 0x1;
	case 60:
		return 0x2;
	case 80:
		return 0x4;
	case 100:
		return 0x5;
	case 120:
		return 0x6;
	case 125:
		return 0x7;
	case 150:
		return 0x8;
	case 200:
		return 0x9;
	case 250:
		return 0xa;
	default:
		/*
		 * We should have divided evenly - if not, return an invalid
		 * value.
		 */
		return 0;
	}
}

static int ahci_da850_softreset(struct ata_link *link,
				unsigned int *class, unsigned long deadline)
{
	int pmp, ret;

	pmp = sata_srst_pmp(link);

	/*
	 * There's an issue with the SATA controller on da850 SoCs: if we
	 * enable Port Multiplier support, but the drive is connected directly
	 * to the board, it can't be detected. As a workaround: if PMP is
	 * enabled, we first call ahci_do_softreset() and pass it the result of
	 * sata_srst_pmp(). If this call fails, we retry with pmp = 0.
	 */
	ret = ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
	if (pmp && ret == -EBUSY)
		return ahci_do_softreset(link, class, 0,
					 deadline, ahci_check_ready);

	return ret;
}

static int ahci_da850_hardreset(struct ata_link *link,
				unsigned int *class, unsigned long deadline)
{
	int ret, retry = HARDRESET_RETRIES;
	bool online;

	/*
	 * In order to correctly service the LCD controller of the da850 SoC,
	 * we increased the PLL0 frequency to 456MHz from the default 300MHz.
	 *
	 * This made the SATA controller unstable and the hardreset operation
	 * does not always succeed the first time. Before really giving up to
	 * bring up the link, retry the reset a couple times.
	 */
	do {
		ret = ahci_do_hardreset(link, class, deadline, &online);
		if (online)
			return ret;
	} while (retry--);

	return ret;
}

static struct ata_port_operations ahci_da850_port_ops = {
	.inherits = &ahci_platform_ops,
	.softreset = ahci_da850_softreset,
	/*
	 * No need to override .pmp_softreset - it's only used for actual
	 * PMP-enabled ports.
	 */
	.hardreset = ahci_da850_hardreset,
	.pmp_hardreset = ahci_da850_hardreset,
};

static const struct ata_port_info ahci_da850_port_info = {
	.flags		= AHCI_FLAG_COMMON,
	.pio_mask	= ATA_PIO4,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &ahci_da850_port_ops,
};

static const struct scsi_host_template ahci_platform_sht = {
	AHCI_SHT(DRV_NAME),
};

static int ahci_da850_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct ahci_host_priv *hpriv;
	void __iomem *pwrdn_reg;
	struct resource *res;
	u32 mpy;
	int rc;

	hpriv = ahci_platform_get_resources(pdev, 0);
	if (IS_ERR(hpriv))
		return PTR_ERR(hpriv);

	/*
	 * Internally ahci_platform_get_resources() calls the bulk clocks
	 * get method or falls back to using a single clk_get_optional().
	 * This AHCI SATA controller uses two clocks: functional clock
	 * with "fck" connection id and external reference clock with
	 * "refclk" id. If we haven't got all of them re-try the clocks
	 * getting procedure with the explicitly specified ids.
	 */
	if (hpriv->n_clks < 2) {
		hpriv->clks = devm_kcalloc(dev, 2, sizeof(*hpriv->clks), GFP_KERNEL);
		if (!hpriv->clks)
			return -ENOMEM;

		hpriv->clks[0].id = "fck";
		hpriv->clks[1].id = "refclk";
		hpriv->n_clks = 2;

		rc = devm_clk_bulk_get(dev, hpriv->n_clks, hpriv->clks);
		if (rc)
			return rc;
	}

	mpy = ahci_da850_calculate_mpy(clk_get_rate(hpriv->clks[1].clk));
	if (mpy == 0) {
		dev_err(dev, "invalid REFCLK multiplier value: 0x%x", mpy);
		return -EINVAL;
	}

	rc = ahci_platform_enable_resources(hpriv);
	if (rc)
		return rc;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!res) {
		rc = -ENODEV;
		goto disable_resources;
	}

	pwrdn_reg = devm_ioremap(dev, res->start, resource_size(res));
	if (!pwrdn_reg) {
		rc = -ENOMEM;
		goto disable_resources;
	}

	da850_sata_init(dev, pwrdn_reg, hpriv->mmio, mpy);

	rc = ahci_platform_init_host(pdev, hpriv, &ahci_da850_port_info,
				     &ahci_platform_sht);
	if (rc)
		goto disable_resources;

	return 0;
disable_resources:
	ahci_platform_disable_resources(hpriv);
	return rc;
}

static SIMPLE_DEV_PM_OPS(ahci_da850_pm_ops, ahci_platform_suspend,
			 ahci_platform_resume);

static const struct of_device_id ahci_da850_of_match[] = {
	{ .compatible = "ti,da850-ahci", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, ahci_da850_of_match);

static struct platform_driver ahci_da850_driver = {
	.probe = ahci_da850_probe,
	.remove = ata_platform_remove_one,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = ahci_da850_of_match,
		.pm = &ahci_da850_pm_ops,
	},
};
module_platform_driver(ahci_da850_driver);

MODULE_DESCRIPTION("DaVinci DA850 AHCI SATA platform driver");
MODULE_AUTHOR("Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
8d7c56d0	1	// SPDX-License-Identifier: GPL-2.0-or-later
ae8723f8 BZ	2	/*
ae8723f8 BZ	3	* DaVinci DA850 AHCI SATA platform driver
ae8723f8 BZ	4	*/
	5
	6	#include <linux/kernel.h>
	7	#include <linux/module.h>
	8	#include <linux/pm.h>
	9	#include <linux/device.h>
	10	#include <linux/platform_device.h>
	11	#include <linux/libata.h>
	12	#include <linux/ahci_platform.h>
	13	#include "ahci.h"
	14
d3d557cf BG	15	#define DRV_NAME "ahci_da850"
d3d557cf BG	16	#define HARDRESET_RETRIES 5
018d5ef2	17
ae8723f8 BZ	18	/* SATA PHY Control Register offset from AHCI base */
	19	#define SATA_P0PHYCR_REG 0x178
	20
	21	#define SATA_PHY_MPY(x) ((x) << 0)
	22	#define SATA_PHY_LOS(x) ((x) << 6)
	23	#define SATA_PHY_RXCDR(x) ((x) << 10)
	24	#define SATA_PHY_RXEQ(x) ((x) << 13)
	25	#define SATA_PHY_TXSWING(x) ((x) << 19)
	26	#define SATA_PHY_ENPLL(x) ((x) << 31)
	27
ae8723f8	28	static void da850_sata_init(struct device dev, void __iomem pwrdn_reg,
cdf0ead3	29	void __iomem *ahci_base, u32 mpy)
ae8723f8 BZ	30	{
	31	unsigned int val;
	32
	33	/* Enable SATA clock receiver */
	34	val = readl(pwrdn_reg);
	35	val &= ~BIT(0);
	36	writel(val, pwrdn_reg);
	37
cdf0ead3 BG	38	val = SATA_PHY_MPY(mpy) \| SATA_PHY_LOS(1) \| SATA_PHY_RXCDR(4) \|
cdf0ead3 BG	39	SATA_PHY_RXEQ(1) \| SATA_PHY_TXSWING(3) \| SATA_PHY_ENPLL(1);
ae8723f8 BZ	40
	41	writel(val, ahci_base + SATA_P0PHYCR_REG);
	42	}
	43
cdf0ead3 BG	44	static u32 ahci_da850_calculate_mpy(unsigned long refclk_rate)
	45	{
	46	u32 pll_output = 1500000000, needed;
	47
	48	/*
	49	* We need to determine the value of the multiplier (MPY) bits.
	50	* In order to include the 12.5 multiplier we need to first divide
	51	* the refclk rate by ten.
	52	*
	53	* __div64_32() turned out to be unreliable, sometimes returning
	54	* false results.
	55	*/
	56	WARN((refclk_rate % 10) != 0, "refclk must be divisible by 10");
	57	needed = pll_output / (refclk_rate / 10);
	58
	59	/*
	60	* What we have now is (multiplier * 10).
	61	*
	62	* Let's determine the actual register value we need to write.
	63	*/
	64
	65	switch (needed) {
	66	case 50:
	67	return 0x1;
	68	case 60:
	69	return 0x2;
	70	case 80:
	71	return 0x4;
	72	case 100:
	73	return 0x5;
	74	case 120:
	75	return 0x6;
	76	case 125:
	77	return 0x7;
	78	case 150:
	79	return 0x8;
	80	case 200:
	81	return 0x9;
	82	case 250:
	83	return 0xa;
	84	default:
	85	/*
	86	* We should have divided evenly - if not, return an invalid
	87	* value.
	88	*/
	89	return 0;
	90	}
	91	}
	92
f4d435f3 BG	93	static int ahci_da850_softreset(struct ata_link *link,
	94	unsigned int *class, unsigned long deadline)
	95	{
	96	int pmp, ret;
	97
	98	pmp = sata_srst_pmp(link);
	99
	100	/*
	101	* There's an issue with the SATA controller on da850 SoCs: if we
	102	* enable Port Multiplier support, but the drive is connected directly
	103	* to the board, it can't be detected. As a workaround: if PMP is
	104	* enabled, we first call ahci_do_softreset() and pass it the result of
	105	* sata_srst_pmp(). If this call fails, we retry with pmp = 0.
	106	*/
	107	ret = ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
	108	if (pmp && ret == -EBUSY)
	109	return ahci_do_softreset(link, class, 0,
	110	deadline, ahci_check_ready);
	111
	112	return ret;
	113	}
	114
d3d557cf BG	115	static int ahci_da850_hardreset(struct ata_link *link,
	116	unsigned int *class, unsigned long deadline)
	117	{
	118	int ret, retry = HARDRESET_RETRIES;
	119	bool online;
	120
	121	/*
	122	* In order to correctly service the LCD controller of the da850 SoC,
	123	* we increased the PLL0 frequency to 456MHz from the default 300MHz.
	124	*
	125	* This made the SATA controller unstable and the hardreset operation
	126	* does not always succeed the first time. Before really giving up to
	127	* bring up the link, retry the reset a couple times.
	128	*/
	129	do {
	130	ret = ahci_do_hardreset(link, class, deadline, &online);
	131	if (online)
	132	return ret;
	133	} while (retry--);
	134
	135	return ret;
	136	}
	137
f4d435f3 BG	138	static struct ata_port_operations ahci_da850_port_ops = {
	139	.inherits = &ahci_platform_ops,
	140	.softreset = ahci_da850_softreset,
	141	/*
	142	* No need to override .pmp_softreset - it's only used for actual
	143	* PMP-enabled ports.
	144	*/
d3d557cf BG	145	.hardreset = ahci_da850_hardreset,
d3d557cf BG	146	.pmp_hardreset = ahci_da850_hardreset,
f4d435f3 BG	147	};
f4d435f3 BG	148
ae8723f8 BZ	149	static const struct ata_port_info ahci_da850_port_info = {
	150	.flags = AHCI_FLAG_COMMON,
	151	.pio_mask = ATA_PIO4,
	152	.udma_mask = ATA_UDMA6,
f4d435f3	153	.port_ops = &ahci_da850_port_ops,
ae8723f8 BZ	154	};
ae8723f8 BZ	155
25df73d9	156	static const struct scsi_host_template ahci_platform_sht = {
018d5ef2 AM	157	AHCI_SHT(DRV_NAME),
	158	};
	159
ae8723f8 BZ	160	static int ahci_da850_probe(struct platform_device *pdev)
	161	{
	162	struct device *dev = &pdev->dev;
	163	struct ahci_host_priv *hpriv;
ae8723f8	164	void __iomem *pwrdn_reg;
cdf0ead3	165	struct resource *res;
cdf0ead3	166	u32 mpy;
ae8723f8 BZ	167	int rc;
ae8723f8 BZ	168
16af2d65	169	hpriv = ahci_platform_get_resources(pdev, 0);
ae8723f8 BZ	170	if (IS_ERR(hpriv))
	171	return PTR_ERR(hpriv);
	172
82dbe1a6	173	/*
e28b3abf SS	174	* Internally ahci_platform_get_resources() calls the bulk clocks
	175	* get method or falls back to using a single clk_get_optional().
	176	* This AHCI SATA controller uses two clocks: functional clock
	177	* with "fck" connection id and external reference clock with
	178	* "refclk" id. If we haven't got all of them re-try the clocks
	179	* getting procedure with the explicitly specified ids.
82dbe1a6	180	*/
e28b3abf SS	181	if (hpriv->n_clks < 2) {
	182	hpriv->clks = devm_kcalloc(dev, 2, sizeof(*hpriv->clks), GFP_KERNEL);
	183	if (!hpriv->clks)
	184	return -ENOMEM;
	185
	186	hpriv->clks[0].id = "fck";
	187	hpriv->clks[1].id = "refclk";
	188	hpriv->n_clks = 2;
	189
	190	rc = devm_clk_bulk_get(dev, hpriv->n_clks, hpriv->clks);
	191	if (rc)
	192	return rc;
cdf0ead3 BG	193	}
cdf0ead3 BG	194
e28b3abf	195	mpy = ahci_da850_calculate_mpy(clk_get_rate(hpriv->clks[1].clk));
cdf0ead3 BG	196	if (mpy == 0) {
	197	dev_err(dev, "invalid REFCLK multiplier value: 0x%x", mpy);
	198	return -EINVAL;
	199	}
	200
ae8723f8 BZ	201	rc = ahci_platform_enable_resources(hpriv);
	202	if (rc)
	203	return rc;
	204
	205	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
c88c0949 CJ	206	if (!res) {
c88c0949 CJ	207	rc = -ENODEV;
ae8723f8	208	goto disable_resources;
c88c0949	209	}
ae8723f8 BZ	210
ae8723f8 BZ	211	pwrdn_reg = devm_ioremap(dev, res->start, resource_size(res));
c88c0949 CJ	212	if (!pwrdn_reg) {
c88c0949 CJ	213	rc = -ENOMEM;
ae8723f8	214	goto disable_resources;
c88c0949	215	}
ae8723f8	216
cdf0ead3	217	da850_sata_init(dev, pwrdn_reg, hpriv->mmio, mpy);
ae8723f8	218
018d5ef2 AM	219	rc = ahci_platform_init_host(pdev, hpriv, &ahci_da850_port_info,
018d5ef2 AM	220	&ahci_platform_sht);
ae8723f8 BZ	221	if (rc)
	222	goto disable_resources;
	223
	224	return 0;
	225	disable_resources:
	226	ahci_platform_disable_resources(hpriv);
	227	return rc;
	228	}
	229
	230	static SIMPLE_DEV_PM_OPS(ahci_da850_pm_ops, ahci_platform_suspend,
	231	ahci_platform_resume);
	232
bf4ae3f0 BG	233	static const struct of_device_id ahci_da850_of_match[] = {
bf4ae3f0 BG	234	{ .compatible = "ti,da850-ahci", },
5e776d7b	235	{ /* sentinel */ }
bf4ae3f0 BG	236	};
	237	MODULE_DEVICE_TABLE(of, ahci_da850_of_match);
	238
ae8723f8 BZ	239	static struct platform_driver ahci_da850_driver = {
	240	.probe = ahci_da850_probe,
	241	.remove = ata_platform_remove_one,
	242	.driver = {
018d5ef2	243	.name = DRV_NAME,
bf4ae3f0	244	.of_match_table = ahci_da850_of_match,
ae8723f8 BZ	245	.pm = &ahci_da850_pm_ops,
	246	},
	247	};
	248	module_platform_driver(ahci_da850_driver);
	249
	250	MODULE_DESCRIPTION("DaVinci DA850 AHCI SATA platform driver");
	251	MODULE_AUTHOR("Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>");
	252	MODULE_LICENSE("GPL");