[linux-2.6-block.git] / drivers / ata / ahci_brcm.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Broadcom SATA3 AHCI Controller Driver
 *
 * Copyright © 2009-2015 Broadcom Corporation
 */

#include <linux/ahci_platform.h>
#include <linux/compiler.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/libata.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/string.h>

#include "ahci.h"

#define DRV_NAME					"brcm-ahci"

#define SATA_TOP_CTRL_VERSION				0x0
#define SATA_TOP_CTRL_BUS_CTRL				0x4
 #define MMIO_ENDIAN_SHIFT				0 /* CPU->AHCI */
 #define DMADESC_ENDIAN_SHIFT				2 /* AHCI->DDR */
 #define DMADATA_ENDIAN_SHIFT				4 /* AHCI->DDR */
 #define PIODATA_ENDIAN_SHIFT				6
  #define ENDIAN_SWAP_NONE				0
  #define ENDIAN_SWAP_FULL				2
#define SATA_TOP_CTRL_TP_CTRL				0x8
#define SATA_TOP_CTRL_PHY_CTRL				0xc
 #define SATA_TOP_CTRL_PHY_CTRL_1			0x0
  #define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE	BIT(14)
 #define SATA_TOP_CTRL_PHY_CTRL_2			0x4
  #define SATA_TOP_CTRL_2_SW_RST_MDIOREG		BIT(0)
  #define SATA_TOP_CTRL_2_SW_RST_OOB			BIT(1)
  #define SATA_TOP_CTRL_2_SW_RST_RX			BIT(2)
  #define SATA_TOP_CTRL_2_SW_RST_TX			BIT(3)
  #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET		BIT(14)
 #define SATA_TOP_CTRL_PHY_OFFS				0x8
 #define SATA_TOP_MAX_PHYS				2

#define SATA_FIRST_PORT_CTRL				0x700
#define SATA_NEXT_PORT_CTRL_OFFSET			0x80
#define SATA_PORT_PCTRL6(reg_base)			(reg_base + 0x18)

/* On big-endian MIPS, buses are reversed to big endian, so switch them back */
#if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
#define DATA_ENDIAN			 2 /* AHCI->DDR inbound accesses */
#define MMIO_ENDIAN			 2 /* CPU->AHCI outbound accesses */
#else
#define DATA_ENDIAN			 0
#define MMIO_ENDIAN			 0
#endif

#define BUS_CTRL_ENDIAN_CONF				\
	((DATA_ENDIAN << DMADATA_ENDIAN_SHIFT) |	\
	(DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) |		\
	(MMIO_ENDIAN << MMIO_ENDIAN_SHIFT))

#define BUS_CTRL_ENDIAN_NSP_CONF			\
	(0x02 << DMADATA_ENDIAN_SHIFT | 0x02 << DMADESC_ENDIAN_SHIFT)

#define BUS_CTRL_ENDIAN_CONF_MASK			\
	(0x3 << MMIO_ENDIAN_SHIFT | 0x3 << DMADESC_ENDIAN_SHIFT |	\
	 0x3 << DMADATA_ENDIAN_SHIFT | 0x3 << PIODATA_ENDIAN_SHIFT)

enum brcm_ahci_version {
	BRCM_SATA_BCM7425 = 1,
	BRCM_SATA_BCM7445,
	BRCM_SATA_NSP,
	BRCM_SATA_BCM7216,
};

enum brcm_ahci_quirks {
	BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE	= BIT(0),
};

struct brcm_ahci_priv {
	struct device *dev;
	void __iomem *top_ctrl;
	u32 port_mask;
	u32 quirks;
	enum brcm_ahci_version version;
	struct reset_control *rcdev_rescal;
	struct reset_control *rcdev_ahci;
};

static inline u32 brcm_sata_readreg(void __iomem *addr)
{
	/*
	 * MIPS endianness is configured by boot strap, which also reverses all
	 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
	 * endian I/O).
	 *
	 * Other architectures (e.g., ARM) either do not support big endian, or
	 * else leave I/O in little endian mode.
	 */
	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
		return __raw_readl(addr);
	else
		return readl_relaxed(addr);
}

static inline void brcm_sata_writereg(u32 val, void __iomem *addr)
{
	/* See brcm_sata_readreg() comments */
	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
		__raw_writel(val, addr);
	else
		writel_relaxed(val, addr);
}

static void brcm_sata_alpm_init(struct ahci_host_priv *hpriv)
{
	struct brcm_ahci_priv *priv = hpriv->plat_data;
	u32 port_ctrl, host_caps;
	int i;

	/* Enable support for ALPM */
	host_caps = readl(hpriv->mmio + HOST_CAP);
	if (!(host_caps & HOST_CAP_ALPM))
		hpriv->flags |= AHCI_HFLAG_YES_ALPM;

	/*
	 * Adjust timeout to allow PLL sufficient time to lock while waking
	 * up from slumber mode.
	 */
	for (i = 0, port_ctrl = SATA_FIRST_PORT_CTRL;
	     i < SATA_TOP_MAX_PHYS;
	     i++, port_ctrl += SATA_NEXT_PORT_CTRL_OFFSET) {
		if (priv->port_mask & BIT(i))
			writel(0xff1003fc,
			       hpriv->mmio + SATA_PORT_PCTRL6(port_ctrl));
	}
}

static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
{
	void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
				(port * SATA_TOP_CTRL_PHY_OFFS);
	void __iomem *p;
	u32 reg;

	if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
		return;

	/* clear PHY_DEFAULT_POWER_STATE */
	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
	reg = brcm_sata_readreg(p);
	reg &= ~SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
	brcm_sata_writereg(reg, p);

	/* reset the PHY digital logic */
	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
	reg = brcm_sata_readreg(p);
	reg &= ~(SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
		 SATA_TOP_CTRL_2_SW_RST_RX);
	reg |= SATA_TOP_CTRL_2_SW_RST_TX;
	brcm_sata_writereg(reg, p);
	reg = brcm_sata_readreg(p);
	reg |= SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
	brcm_sata_writereg(reg, p);
	reg = brcm_sata_readreg(p);
	reg &= ~SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
	brcm_sata_writereg(reg, p);
	(void)brcm_sata_readreg(p);
}

static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
{
	void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
				(port * SATA_TOP_CTRL_PHY_OFFS);
	void __iomem *p;
	u32 reg;

	if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
		return;

	/* power-off the PHY digital logic */
	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
	reg = brcm_sata_readreg(p);
	reg |= (SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
		SATA_TOP_CTRL_2_SW_RST_RX | SATA_TOP_CTRL_2_SW_RST_TX |
		SATA_TOP_CTRL_2_PHY_GLOBAL_RESET);
	brcm_sata_writereg(reg, p);

	/* set PHY_DEFAULT_POWER_STATE */
	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
	reg = brcm_sata_readreg(p);
	reg |= SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
	brcm_sata_writereg(reg, p);
}

static void brcm_sata_phys_enable(struct brcm_ahci_priv *priv)
{
	int i;

	for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
		if (priv->port_mask & BIT(i))
			brcm_sata_phy_enable(priv, i);
}

static void brcm_sata_phys_disable(struct brcm_ahci_priv *priv)
{
	int i;

	for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
		if (priv->port_mask & BIT(i))
			brcm_sata_phy_disable(priv, i);
}

static u32 brcm_ahci_get_portmask(struct ahci_host_priv *hpriv,
				  struct brcm_ahci_priv *priv)
{
	u32 impl;

	impl = readl(hpriv->mmio + HOST_PORTS_IMPL);

	if (fls(impl) > SATA_TOP_MAX_PHYS)
		dev_warn(priv->dev, "warning: more ports than PHYs (%#x)\n",
			 impl);
	else if (!impl)
		dev_info(priv->dev, "no ports found\n");

	return impl;
}

static void brcm_sata_init(struct brcm_ahci_priv *priv)
{
	void __iomem *ctrl = priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL;
	u32 data;

	/* Configure endianness */
	data = brcm_sata_readreg(ctrl);
	data &= ~BUS_CTRL_ENDIAN_CONF_MASK;
	if (priv->version == BRCM_SATA_NSP)
		data |= BUS_CTRL_ENDIAN_NSP_CONF;
	else
		data |= BUS_CTRL_ENDIAN_CONF;
	brcm_sata_writereg(data, ctrl);
}

static unsigned int brcm_ahci_read_id(struct ata_device *dev,
				      struct ata_taskfile *tf, __le16 *id)
{
	struct ata_port *ap = dev->link->ap;
	struct ata_host *host = ap->host;
	struct ahci_host_priv *hpriv = host->private_data;
	struct brcm_ahci_priv *priv = hpriv->plat_data;
	void __iomem *mmio = hpriv->mmio;
	unsigned int err_mask;
	unsigned long flags;
	int i, rc;
	u32 ctl;

	/* Try to read the device ID and, if this fails, proceed with the
	 * recovery sequence below
	 */
	err_mask = ata_do_dev_read_id(dev, tf, id);
	if (likely(!err_mask))
		return err_mask;

	/* Disable host interrupts */
	spin_lock_irqsave(&host->lock, flags);
	ctl = readl(mmio + HOST_CTL);
	ctl &= ~HOST_IRQ_EN;
	writel(ctl, mmio + HOST_CTL);
	readl(mmio + HOST_CTL); /* flush */
	spin_unlock_irqrestore(&host->lock, flags);

	/* Perform the SATA PHY reset sequence */
	brcm_sata_phy_disable(priv, ap->port_no);

	/* Reset the SATA clock */
	ahci_platform_disable_clks(hpriv);
	msleep(10);

	ahci_platform_enable_clks(hpriv);
	msleep(10);

	/* Bring the PHY back on */
	brcm_sata_phy_enable(priv, ap->port_no);

	/* Re-initialize and calibrate the PHY */
	for (i = 0; i < hpriv->nports; i++) {
		rc = phy_init(hpriv->phys[i]);
		if (rc)
			goto disable_phys;

		rc = phy_calibrate(hpriv->phys[i]);
		if (rc) {
			phy_exit(hpriv->phys[i]);
			goto disable_phys;
		}
	}

	/* Re-enable host interrupts */
	spin_lock_irqsave(&host->lock, flags);
	ctl = readl(mmio + HOST_CTL);
	ctl |= HOST_IRQ_EN;
	writel(ctl, mmio + HOST_CTL);
	readl(mmio + HOST_CTL); /* flush */
	spin_unlock_irqrestore(&host->lock, flags);

	return ata_do_dev_read_id(dev, tf, id);

disable_phys:
	while (--i >= 0) {
		phy_power_off(hpriv->phys[i]);
		phy_exit(hpriv->phys[i]);
	}

	return AC_ERR_OTHER;
}

static void brcm_ahci_host_stop(struct ata_host *host)
{
	struct ahci_host_priv *hpriv = host->private_data;

	ahci_platform_disable_resources(hpriv);
}

static struct ata_port_operations ahci_brcm_platform_ops = {
	.inherits	= &ahci_ops,
	.host_stop	= brcm_ahci_host_stop,
	.read_id	= brcm_ahci_read_id,
};

static const struct ata_port_info ahci_brcm_port_info = {
	.flags		= AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
	.link_flags	= ATA_LFLAG_NO_DEBOUNCE_DELAY,
	.pio_mask	= ATA_PIO4,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &ahci_brcm_platform_ops,
};

static int brcm_ahci_suspend(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	struct brcm_ahci_priv *priv = hpriv->plat_data;
	int ret;

	brcm_sata_phys_disable(priv);

	if (IS_ENABLED(CONFIG_PM_SLEEP))
		ret = ahci_platform_suspend(dev);
	else
		ret = 0;

	reset_control_assert(priv->rcdev_ahci);
	reset_control_rearm(priv->rcdev_rescal);

	return ret;
}

static int __maybe_unused brcm_ahci_resume(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	struct brcm_ahci_priv *priv = hpriv->plat_data;
	int ret = 0;

	ret = reset_control_deassert(priv->rcdev_ahci);
	if (ret)
		return ret;
	ret = reset_control_reset(priv->rcdev_rescal);
	if (ret)
		return ret;

	/* Make sure clocks are turned on before re-configuration */
	ret = ahci_platform_enable_clks(hpriv);
	if (ret)
		return ret;

	ret = ahci_platform_enable_regulators(hpriv);
	if (ret)
		goto out_disable_clks;

	brcm_sata_init(priv);
	brcm_sata_phys_enable(priv);
	brcm_sata_alpm_init(hpriv);

	/* Since we had to enable clocks earlier on, we cannot use
	 * ahci_platform_resume() as-is since a second call to
	 * ahci_platform_enable_resources() would bump up the resources
	 * (regulators, clocks, PHYs) count artificially so we copy the part
	 * after ahci_platform_enable_resources().
	 */
	ret = ahci_platform_enable_phys(hpriv);
	if (ret)
		goto out_disable_phys;

	ret = ahci_platform_resume_host(dev);
	if (ret)
		goto out_disable_platform_phys;

	/* We resumed so update PM runtime state */
	pm_runtime_disable(dev);
	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);

	return 0;

out_disable_platform_phys:
	ahci_platform_disable_phys(hpriv);
out_disable_phys:
	brcm_sata_phys_disable(priv);
	ahci_platform_disable_regulators(hpriv);
out_disable_clks:
	ahci_platform_disable_clks(hpriv);
	return ret;
}

static const struct scsi_host_template ahci_platform_sht = {
	AHCI_SHT(DRV_NAME),
};

static const struct of_device_id ahci_of_match[] = {
	{.compatible = "brcm,bcm7425-ahci", .data = (void *)BRCM_SATA_BCM7425},
	{.compatible = "brcm,bcm7445-ahci", .data = (void *)BRCM_SATA_BCM7445},
	{.compatible = "brcm,bcm63138-ahci", .data = (void *)BRCM_SATA_BCM7445},
	{.compatible = "brcm,bcm-nsp-ahci", .data = (void *)BRCM_SATA_NSP},
	{.compatible = "brcm,bcm7216-ahci", .data = (void *)BRCM_SATA_BCM7216},
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, ahci_of_match);

static int brcm_ahci_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id;
	struct device *dev = &pdev->dev;
	struct brcm_ahci_priv *priv;
	struct ahci_host_priv *hpriv;
	struct resource *res;
	int ret;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	of_id = of_match_node(ahci_of_match, pdev->dev.of_node);
	if (!of_id)
		return -ENODEV;

	priv->version = (unsigned long)of_id->data;
	priv->dev = dev;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "top-ctrl");
	priv->top_ctrl = devm_ioremap_resource(dev, res);
	if (IS_ERR(priv->top_ctrl))
		return PTR_ERR(priv->top_ctrl);

	if (priv->version == BRCM_SATA_BCM7216) {
		priv->rcdev_rescal = devm_reset_control_get_optional_shared(
			&pdev->dev, "rescal");
		if (IS_ERR(priv->rcdev_rescal))
			return PTR_ERR(priv->rcdev_rescal);
	}
	priv->rcdev_ahci = devm_reset_control_get_optional(&pdev->dev, "ahci");
	if (IS_ERR(priv->rcdev_ahci))
		return PTR_ERR(priv->rcdev_ahci);

	hpriv = ahci_platform_get_resources(pdev, 0);
	if (IS_ERR(hpriv))
		return PTR_ERR(hpriv);

	hpriv->plat_data = priv;
	hpriv->flags = AHCI_HFLAG_WAKE_BEFORE_STOP | AHCI_HFLAG_NO_WRITE_TO_RO;

	switch (priv->version) {
	case BRCM_SATA_BCM7425:
		hpriv->flags |= AHCI_HFLAG_DELAY_ENGINE;
		fallthrough;
	case BRCM_SATA_NSP:
		hpriv->flags |= AHCI_HFLAG_NO_NCQ;
		priv->quirks |= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE;
		break;
	default:
		break;
	}

	ret = reset_control_reset(priv->rcdev_rescal);
	if (ret)
		return ret;
	ret = reset_control_deassert(priv->rcdev_ahci);
	if (ret)
		return ret;

	ret = ahci_platform_enable_clks(hpriv);
	if (ret)
		goto out_reset;

	ret = ahci_platform_enable_regulators(hpriv);
	if (ret)
		goto out_disable_clks;

	/* Must be first so as to configure endianness including that
	 * of the standard AHCI register space.
	 */
	brcm_sata_init(priv);

	/* Initializes priv->port_mask which is used below */
	priv->port_mask = brcm_ahci_get_portmask(hpriv, priv);
	if (!priv->port_mask) {
		ret = -ENODEV;
		goto out_disable_regulators;
	}

	/* Must be done before ahci_platform_enable_phys() */
	brcm_sata_phys_enable(priv);

	brcm_sata_alpm_init(hpriv);

	ret = ahci_platform_enable_phys(hpriv);
	if (ret)
		goto out_disable_phys;

	ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info,
				      &ahci_platform_sht);
	if (ret)
		goto out_disable_platform_phys;

	dev_info(dev, "Broadcom AHCI SATA3 registered\n");

	return 0;

out_disable_platform_phys:
	ahci_platform_disable_phys(hpriv);
out_disable_phys:
	brcm_sata_phys_disable(priv);
out_disable_regulators:
	ahci_platform_disable_regulators(hpriv);
out_disable_clks:
	ahci_platform_disable_clks(hpriv);
out_reset:
	reset_control_assert(priv->rcdev_ahci);
	reset_control_rearm(priv->rcdev_rescal);
	return ret;
}

static void brcm_ahci_remove(struct platform_device *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	struct ahci_host_priv *hpriv = host->private_data;
	struct brcm_ahci_priv *priv = hpriv->plat_data;

	brcm_sata_phys_disable(priv);

	ata_platform_remove_one(pdev);
}

static void brcm_ahci_shutdown(struct platform_device *pdev)
{
	int ret;

	/* All resources releasing happens via devres, but our device, unlike a
	 * proper remove is not disappearing, therefore using
	 * brcm_ahci_suspend() here which does explicit power management is
	 * appropriate.
	 */
	ret = brcm_ahci_suspend(&pdev->dev);
	if (ret)
		dev_err(&pdev->dev, "failed to shutdown\n");
}

static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume);

static struct platform_driver brcm_ahci_driver = {
	.probe = brcm_ahci_probe,
	.remove_new = brcm_ahci_remove,
	.shutdown = brcm_ahci_shutdown,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = ahci_of_match,
		.pm = &ahci_brcm_pm_ops,
	},
};
module_platform_driver(brcm_ahci_driver);

MODULE_DESCRIPTION("Broadcom SATA3 AHCI Controller Driver");
MODULE_AUTHOR("Brian Norris");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:sata-brcmstb");
Commit	Line	Data
3e0a4e85	1	// SPDX-License-Identifier: GPL-2.0-or-later
766a2d97 BN	2	/*
	3	* Broadcom SATA3 AHCI Controller Driver
	4	*
	5	* Copyright © 2009-2015 Broadcom Corporation
766a2d97 BN	6	*/
	7
	8	#include <linux/ahci_platform.h>
	9	#include <linux/compiler.h>
	10	#include <linux/device.h>
	11	#include <linux/init.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/io.h>
	14	#include <linux/kernel.h>
	15	#include <linux/libata.h>
	16	#include <linux/module.h>
	17	#include <linux/of.h>
	18	#include <linux/platform_device.h>
2b2c47d9	19	#include <linux/reset.h>
766a2d97 BN	20	#include <linux/string.h>
	21
	22	#include "ahci.h"
	23
	24	#define DRV_NAME "brcm-ahci"
	25
	26	#define SATA_TOP_CTRL_VERSION 0x0
	27	#define SATA_TOP_CTRL_BUS_CTRL 0x4
	28	#define MMIO_ENDIAN_SHIFT 0 /* CPU->AHCI */
	29	#define DMADESC_ENDIAN_SHIFT 2 /* AHCI->DDR */
	30	#define DMADATA_ENDIAN_SHIFT 4 /* AHCI->DDR */
	31	#define PIODATA_ENDIAN_SHIFT 6
	32	#define ENDIAN_SWAP_NONE 0
	33	#define ENDIAN_SWAP_FULL 2
766a2d97 BN	34	#define SATA_TOP_CTRL_TP_CTRL 0x8
	35	#define SATA_TOP_CTRL_PHY_CTRL 0xc
	36	#define SATA_TOP_CTRL_PHY_CTRL_1 0x0
	37	#define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE BIT(14)
	38	#define SATA_TOP_CTRL_PHY_CTRL_2 0x4
	39	#define SATA_TOP_CTRL_2_SW_RST_MDIOREG BIT(0)
	40	#define SATA_TOP_CTRL_2_SW_RST_OOB BIT(1)
	41	#define SATA_TOP_CTRL_2_SW_RST_RX BIT(2)
	42	#define SATA_TOP_CTRL_2_SW_RST_TX BIT(3)
	43	#define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET BIT(14)
	44	#define SATA_TOP_CTRL_PHY_OFFS 0x8
	45	#define SATA_TOP_MAX_PHYS 2
766a2d97	46
6863caaf DP	47	#define SATA_FIRST_PORT_CTRL 0x700
	48	#define SATA_NEXT_PORT_CTRL_OFFSET 0x80
	49	#define SATA_PORT_PCTRL6(reg_base) (reg_base + 0x18)
	50
766a2d97 BN	51	/* On big-endian MIPS, buses are reversed to big endian, so switch them back */
	52	#if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
	53	#define DATA_ENDIAN 2 /* AHCI->DDR inbound accesses */
	54	#define MMIO_ENDIAN 2 /* CPU->AHCI outbound accesses */
	55	#else
	56	#define DATA_ENDIAN 0
	57	#define MMIO_ENDIAN 0
	58	#endif
	59
	60	#define BUS_CTRL_ENDIAN_CONF \
	61	((DATA_ENDIAN << DMADATA_ENDIAN_SHIFT) \| \
	62	(DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) \| \
	63	(MMIO_ENDIAN << MMIO_ENDIAN_SHIFT))
	64
36fffd6a FF	65	#define BUS_CTRL_ENDIAN_NSP_CONF \
	66	(0x02 << DMADATA_ENDIAN_SHIFT \| 0x02 << DMADESC_ENDIAN_SHIFT)
	67
	68	#define BUS_CTRL_ENDIAN_CONF_MASK \
	69	(0x3 << MMIO_ENDIAN_SHIFT \| 0x3 << DMADESC_ENDIAN_SHIFT \| \
	70	0x3 << DMADATA_ENDIAN_SHIFT \| 0x3 << PIODATA_ENDIAN_SHIFT)
	71
3ee2e6dc YRDR	72	enum brcm_ahci_version {
	73	BRCM_SATA_BCM7425 = 1,
	74	BRCM_SATA_BCM7445,
	75	BRCM_SATA_NSP,
c345ec6a	76	BRCM_SATA_BCM7216,
3ee2e6dc YRDR	77	};
3ee2e6dc YRDR	78
7de32445	79	enum brcm_ahci_quirks {
1a3d78cb	80	BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE = BIT(0),
7de32445 JS	81	};
7de32445 JS	82
766a2d97 BN	83	struct brcm_ahci_priv {
	84	struct device *dev;
	85	void __iomem *top_ctrl;
	86	u32 port_mask;
7de32445	87	u32 quirks;
3ee2e6dc	88	enum brcm_ahci_version version;
e8d6f9e5 JQ	89	struct reset_control *rcdev_rescal;
e8d6f9e5 JQ	90	struct reset_control *rcdev_ahci;
766a2d97 BN	91	};
766a2d97 BN	92
766a2d97 BN	93	static inline u32 brcm_sata_readreg(void __iomem *addr)
	94	{
	95	/*
	96	* MIPS endianness is configured by boot strap, which also reverses all
	97	* bus endianness (i.e., big-endian CPU + big endian bus ==> native
	98	* endian I/O).
	99	*
	100	* Other architectures (e.g., ARM) either do not support big endian, or
	101	* else leave I/O in little endian mode.
	102	*/
f9114d35	103	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
766a2d97 BN	104	return __raw_readl(addr);
	105	else
	106	return readl_relaxed(addr);
	107	}
	108
	109	static inline void brcm_sata_writereg(u32 val, void __iomem *addr)
	110	{
	111	/* See brcm_sata_readreg() comments */
f9114d35	112	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
766a2d97 BN	113	__raw_writel(val, addr);
	114	else
	115	writel_relaxed(val, addr);
	116	}
	117
6863caaf DP	118	static void brcm_sata_alpm_init(struct ahci_host_priv *hpriv)
	119	{
	120	struct brcm_ahci_priv *priv = hpriv->plat_data;
da8fa9cc	121	u32 port_ctrl, host_caps;
6863caaf DP	122	int i;
	123
	124	/* Enable support for ALPM */
6863caaf	125	host_caps = readl(hpriv->mmio + HOST_CAP);
da8fa9cc DB	126	if (!(host_caps & HOST_CAP_ALPM))
da8fa9cc DB	127	hpriv->flags \|= AHCI_HFLAG_YES_ALPM;
6863caaf DP	128
	129	/*
	130	* Adjust timeout to allow PLL sufficient time to lock while waking
	131	* up from slumber mode.
	132	*/
	133	for (i = 0, port_ctrl = SATA_FIRST_PORT_CTRL;
	134	i < SATA_TOP_MAX_PHYS;
	135	i++, port_ctrl += SATA_NEXT_PORT_CTRL_OFFSET) {
	136	if (priv->port_mask & BIT(i))
	137	writel(0xff1003fc,
	138	hpriv->mmio + SATA_PORT_PCTRL6(port_ctrl));
	139	}
	140	}
	141
766a2d97 BN	142	static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
	143	{
	144	void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
	145	(port * SATA_TOP_CTRL_PHY_OFFS);
	146	void __iomem *p;
	147	u32 reg;
	148
b46f79bc JS	149	if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
	150	return;
	151
766a2d97 BN	152	/* clear PHY_DEFAULT_POWER_STATE */
	153	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
	154	reg = brcm_sata_readreg(p);
	155	reg &= ~SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
	156	brcm_sata_writereg(reg, p);
	157
	158	/* reset the PHY digital logic */
	159	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
	160	reg = brcm_sata_readreg(p);
	161	reg &= ~(SATA_TOP_CTRL_2_SW_RST_MDIOREG \| SATA_TOP_CTRL_2_SW_RST_OOB \|
	162	SATA_TOP_CTRL_2_SW_RST_RX);
	163	reg \|= SATA_TOP_CTRL_2_SW_RST_TX;
	164	brcm_sata_writereg(reg, p);
	165	reg = brcm_sata_readreg(p);
	166	reg \|= SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
	167	brcm_sata_writereg(reg, p);
	168	reg = brcm_sata_readreg(p);
	169	reg &= ~SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
	170	brcm_sata_writereg(reg, p);
	171	(void)brcm_sata_readreg(p);
	172	}
	173
	174	static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
	175	{
	176	void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
	177	(port * SATA_TOP_CTRL_PHY_OFFS);
	178	void __iomem *p;
	179	u32 reg;
	180
b46f79bc JS	181	if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
	182	return;
	183
766a2d97 BN	184	/* power-off the PHY digital logic */
	185	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
	186	reg = brcm_sata_readreg(p);
	187	reg \|= (SATA_TOP_CTRL_2_SW_RST_MDIOREG \| SATA_TOP_CTRL_2_SW_RST_OOB \|
	188	SATA_TOP_CTRL_2_SW_RST_RX \| SATA_TOP_CTRL_2_SW_RST_TX \|
	189	SATA_TOP_CTRL_2_PHY_GLOBAL_RESET);
	190	brcm_sata_writereg(reg, p);
	191
	192	/* set PHY_DEFAULT_POWER_STATE */
	193	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
	194	reg = brcm_sata_readreg(p);
	195	reg \|= SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
	196	brcm_sata_writereg(reg, p);
	197	}
	198
	199	static void brcm_sata_phys_enable(struct brcm_ahci_priv *priv)
	200	{
	201	int i;
	202
	203	for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
	204	if (priv->port_mask & BIT(i))
	205	brcm_sata_phy_enable(priv, i);
	206	}
	207
	208	static void brcm_sata_phys_disable(struct brcm_ahci_priv *priv)
	209	{
	210	int i;
	211
	212	for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
	213	if (priv->port_mask & BIT(i))
	214	brcm_sata_phy_disable(priv, i);
	215	}
	216
c0cdf2ac	217	static u32 brcm_ahci_get_portmask(struct ahci_host_priv *hpriv,
766a2d97 BN	218	struct brcm_ahci_priv *priv)
766a2d97 BN	219	{
766a2d97 BN	220	u32 impl;
766a2d97 BN	221
c0cdf2ac	222	impl = readl(hpriv->mmio + HOST_PORTS_IMPL);
766a2d97 BN	223
	224	if (fls(impl) > SATA_TOP_MAX_PHYS)
	225	dev_warn(priv->dev, "warning: more ports than PHYs (%#x)\n",
	226	impl);
	227	else if (!impl)
	228	dev_info(priv->dev, "no ports found\n");
	229
766a2d97 BN	230	return impl;
	231	}
	232
	233	static void brcm_sata_init(struct brcm_ahci_priv *priv)
	234	{
3ee2e6dc	235	void __iomem *ctrl = priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL;
36fffd6a	236	u32 data;
3ee2e6dc	237
766a2d97	238	/* Configure endianness */
36fffd6a FF	239	data = brcm_sata_readreg(ctrl);
	240	data &= ~BUS_CTRL_ENDIAN_CONF_MASK;
	241	if (priv->version == BRCM_SATA_NSP)
	242	data \|= BUS_CTRL_ENDIAN_NSP_CONF;
	243	else
	244	data \|= BUS_CTRL_ENDIAN_CONF;
	245	brcm_sata_writereg(data, ctrl);
766a2d97 BN	246	}
766a2d97 BN	247
eb73390a	248	static unsigned int brcm_ahci_read_id(struct ata_device *dev,
0561e514	249	struct ata_taskfile tf, __le16 id)
eb73390a FF	250	{
	251	struct ata_port *ap = dev->link->ap;
	252	struct ata_host *host = ap->host;
	253	struct ahci_host_priv *hpriv = host->private_data;
	254	struct brcm_ahci_priv *priv = hpriv->plat_data;
	255	void __iomem *mmio = hpriv->mmio;
	256	unsigned int err_mask;
	257	unsigned long flags;
	258	int i, rc;
	259	u32 ctl;
	260
	261	/* Try to read the device ID and, if this fails, proceed with the
	262	* recovery sequence below
	263	*/
	264	err_mask = ata_do_dev_read_id(dev, tf, id);
	265	if (likely(!err_mask))
	266	return err_mask;
	267
	268	/* Disable host interrupts */
	269	spin_lock_irqsave(&host->lock, flags);
	270	ctl = readl(mmio + HOST_CTL);
	271	ctl &= ~HOST_IRQ_EN;
	272	writel(ctl, mmio + HOST_CTL);
	273	readl(mmio + HOST_CTL); /* flush */
	274	spin_unlock_irqrestore(&host->lock, flags);
	275
	276	/* Perform the SATA PHY reset sequence */
	277	brcm_sata_phy_disable(priv, ap->port_no);
	278
bf0e5013 FF	279	/* Reset the SATA clock */
	280	ahci_platform_disable_clks(hpriv);
	281	msleep(10);
	282
	283	ahci_platform_enable_clks(hpriv);
	284	msleep(10);
	285
eb73390a FF	286	/* Bring the PHY back on */
	287	brcm_sata_phy_enable(priv, ap->port_no);
	288
	289	/* Re-initialize and calibrate the PHY */
	290	for (i = 0; i < hpriv->nports; i++) {
	291	rc = phy_init(hpriv->phys[i]);
	292	if (rc)
	293	goto disable_phys;
	294
	295	rc = phy_calibrate(hpriv->phys[i]);
	296	if (rc) {
	297	phy_exit(hpriv->phys[i]);
	298	goto disable_phys;
	299	}
	300	}
	301
	302	/* Re-enable host interrupts */
	303	spin_lock_irqsave(&host->lock, flags);
	304	ctl = readl(mmio + HOST_CTL);
	305	ctl \|= HOST_IRQ_EN;
	306	writel(ctl, mmio + HOST_CTL);
	307	readl(mmio + HOST_CTL); /* flush */
	308	spin_unlock_irqrestore(&host->lock, flags);
	309
	310	return ata_do_dev_read_id(dev, tf, id);
	311
	312	disable_phys:
	313	while (--i >= 0) {
	314	phy_power_off(hpriv->phys[i]);
	315	phy_exit(hpriv->phys[i]);
	316	}
	317
	318	return AC_ERR_OTHER;
	319	}
	320
	321	static void brcm_ahci_host_stop(struct ata_host *host)
	322	{
	323	struct ahci_host_priv *hpriv = host->private_data;
	324
	325	ahci_platform_disable_resources(hpriv);
	326	}
	327
	328	static struct ata_port_operations ahci_brcm_platform_ops = {
	329	.inherits = &ahci_ops,
	330	.host_stop = brcm_ahci_host_stop,
	331	.read_id = brcm_ahci_read_id,
	332	};
	333
	334	static const struct ata_port_info ahci_brcm_port_info = {
	335	.flags = AHCI_FLAG_COMMON \| ATA_FLAG_NO_DIPM,
b9ba367c	336	.link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY,
eb73390a FF	337	.pio_mask = ATA_PIO4,
	338	.udma_mask = ATA_UDMA6,
	339	.port_ops = &ahci_brcm_platform_ops,
	340	};
	341
766a2d97 BN	342	static int brcm_ahci_suspend(struct device *dev)
	343	{
	344	struct ata_host *host = dev_get_drvdata(dev);
	345	struct ahci_host_priv *hpriv = host->private_data;
	346	struct brcm_ahci_priv *priv = hpriv->plat_data;
3c696ac4	347	int ret;
766a2d97	348
766a2d97	349	brcm_sata_phys_disable(priv);
c0cdf2ac	350
ed87ad19 AB	351	if (IS_ENABLED(CONFIG_PM_SLEEP))
	352	ret = ahci_platform_suspend(dev);
	353	else
	354	ret = 0;
3c696ac4	355
e8d6f9e5 JQ	356	reset_control_assert(priv->rcdev_ahci);
e8d6f9e5 JQ	357	reset_control_rearm(priv->rcdev_rescal);
3c696ac4 FF	358
3c696ac4 FF	359	return ret;
766a2d97 BN	360	}
766a2d97 BN	361
ed87ad19	362	static int __maybe_unused brcm_ahci_resume(struct device *dev)
766a2d97 BN	363	{
	364	struct ata_host *host = dev_get_drvdata(dev);
	365	struct ahci_host_priv *hpriv = host->private_data;
	366	struct brcm_ahci_priv *priv = hpriv->plat_data;
3c696ac4 FF	367	int ret = 0;
3c696ac4 FF	368
e8d6f9e5 JQ	369	ret = reset_control_deassert(priv->rcdev_ahci);
	370	if (ret)
	371	return ret;
	372	ret = reset_control_reset(priv->rcdev_rescal);
3c696ac4 FF	373	if (ret)
3c696ac4 FF	374	return ret;
c0cdf2ac FF	375
	376	/* Make sure clocks are turned on before re-configuration */
	377	ret = ahci_platform_enable_clks(hpriv);
	378	if (ret)
	379	return ret;
766a2d97	380
10340f8d FF	381	ret = ahci_platform_enable_regulators(hpriv);
	382	if (ret)
	383	goto out_disable_clks;
	384
766a2d97 BN	385	brcm_sata_init(priv);
766a2d97 BN	386	brcm_sata_phys_enable(priv);
6863caaf	387	brcm_sata_alpm_init(hpriv);
c0cdf2ac FF	388
	389	/* Since we had to enable clocks earlier on, we cannot use
	390	* ahci_platform_resume() as-is since a second call to
	391	* ahci_platform_enable_resources() would bump up the resources
	392	* (regulators, clocks, PHYs) count artificially so we copy the part
	393	* after ahci_platform_enable_resources().
	394	*/
	395	ret = ahci_platform_enable_phys(hpriv);
	396	if (ret)
	397	goto out_disable_phys;
	398
	399	ret = ahci_platform_resume_host(dev);
	400	if (ret)
	401	goto out_disable_platform_phys;
	402
	403	/* We resumed so update PM runtime state */
	404	pm_runtime_disable(dev);
	405	pm_runtime_set_active(dev);
	406	pm_runtime_enable(dev);
	407
	408	return 0;
	409
	410	out_disable_platform_phys:
	411	ahci_platform_disable_phys(hpriv);
	412	out_disable_phys:
	413	brcm_sata_phys_disable(priv);
10340f8d FF	414	ahci_platform_disable_regulators(hpriv);
10340f8d FF	415	out_disable_clks:
c0cdf2ac FF	416	ahci_platform_disable_clks(hpriv);
c0cdf2ac FF	417	return ret;
766a2d97 BN	418	}
766a2d97 BN	419
25df73d9	420	static const struct scsi_host_template ahci_platform_sht = {
766a2d97 BN	421	AHCI_SHT(DRV_NAME),
	422	};
	423
3ee2e6dc YRDR	424	static const struct of_device_id ahci_of_match[] = {
	425	{.compatible = "brcm,bcm7425-ahci", .data = (void *)BRCM_SATA_BCM7425},
	426	{.compatible = "brcm,bcm7445-ahci", .data = (void *)BRCM_SATA_BCM7445},
fb8506f1	427	{.compatible = "brcm,bcm63138-ahci", .data = (void *)BRCM_SATA_BCM7445},
3ee2e6dc	428	{.compatible = "brcm,bcm-nsp-ahci", .data = (void *)BRCM_SATA_NSP},
c345ec6a	429	{.compatible = "brcm,bcm7216-ahci", .data = (void *)BRCM_SATA_BCM7216},
5e776d7b	430	{ /* sentinel */ }
3ee2e6dc YRDR	431	};
	432	MODULE_DEVICE_TABLE(of, ahci_of_match);
	433
766a2d97 BN	434	static int brcm_ahci_probe(struct platform_device *pdev)
766a2d97 BN	435	{
3ee2e6dc	436	const struct of_device_id *of_id;
766a2d97 BN	437	struct device *dev = &pdev->dev;
	438	struct brcm_ahci_priv *priv;
	439	struct ahci_host_priv *hpriv;
	440	struct resource *res;
	441	int ret;
	442
	443	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	444	if (!priv)
	445	return -ENOMEM;
3ee2e6dc YRDR	446
	447	of_id = of_match_node(ahci_of_match, pdev->dev.of_node);
	448	if (!of_id)
	449	return -ENODEV;
	450
7d7b0c85	451	priv->version = (unsigned long)of_id->data;
766a2d97 BN	452	priv->dev = dev;
	453
	454	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "top-ctrl");
	455	priv->top_ctrl = devm_ioremap_resource(dev, res);
	456	if (IS_ERR(priv->top_ctrl))
	457	return PTR_ERR(priv->top_ctrl);
	458
e8d6f9e5 JQ	459	if (priv->version == BRCM_SATA_BCM7216) {
	460	priv->rcdev_rescal = devm_reset_control_get_optional_shared(
	461	&pdev->dev, "rescal");
	462	if (IS_ERR(priv->rcdev_rescal))
	463	return PTR_ERR(priv->rcdev_rescal);
	464	}
	465	priv->rcdev_ahci = devm_reset_control_get_optional(&pdev->dev, "ahci");
	466	if (IS_ERR(priv->rcdev_ahci))
	467	return PTR_ERR(priv->rcdev_ahci);
6fedae3c	468
c0cdf2ac	469	hpriv = ahci_platform_get_resources(pdev, 0);
1a0600d1 FF	470	if (IS_ERR(hpriv))
1a0600d1 FF	471	return PTR_ERR(hpriv);
c0cdf2ac	472
1a3d78cb FF	473	hpriv->plat_data = priv;
	474	hpriv->flags = AHCI_HFLAG_WAKE_BEFORE_STOP \| AHCI_HFLAG_NO_WRITE_TO_RO;
	475
	476	switch (priv->version) {
	477	case BRCM_SATA_BCM7425:
	478	hpriv->flags \|= AHCI_HFLAG_DELAY_ENGINE;
df561f66	479	fallthrough;
1a3d78cb FF	480	case BRCM_SATA_NSP:
	481	hpriv->flags \|= AHCI_HFLAG_NO_NCQ;
	482	priv->quirks \|= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE;
	483	break;
	484	default:
	485	break;
	486	}
	487
e8d6f9e5 JQ	488	ret = reset_control_reset(priv->rcdev_rescal);
	489	if (ret)
	490	return ret;
	491	ret = reset_control_deassert(priv->rcdev_ahci);
1a0600d1 FF	492	if (ret)
	493	return ret;
	494
c0cdf2ac FF	495	ret = ahci_platform_enable_clks(hpriv);
	496	if (ret)
	497	goto out_reset;
	498
10340f8d FF	499	ret = ahci_platform_enable_regulators(hpriv);
	500	if (ret)
	501	goto out_disable_clks;
	502
c0cdf2ac FF	503	/* Must be first so as to configure endianness including that
	504	* of the standard AHCI register space.
	505	*/
766a2d97 BN	506	brcm_sata_init(priv);
766a2d97 BN	507
c0cdf2ac FF	508	/* Initializes priv->port_mask which is used below */
	509	priv->port_mask = brcm_ahci_get_portmask(hpriv, priv);
	510	if (!priv->port_mask) {
	511	ret = -ENODEV;
10340f8d	512	goto out_disable_regulators;
c0cdf2ac	513	}
766a2d97	514
c0cdf2ac	515	/* Must be done before ahci_platform_enable_phys() */
766a2d97 BN	516	brcm_sata_phys_enable(priv);
766a2d97 BN	517
6863caaf DP	518	brcm_sata_alpm_init(hpriv);
6863caaf DP	519
c0cdf2ac FF	520	ret = ahci_platform_enable_phys(hpriv);
	521	if (ret)
	522	goto out_disable_phys;
	523
766a2d97 BN	524	ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info,
	525	&ahci_platform_sht);
	526	if (ret)
c0cdf2ac	527	goto out_disable_platform_phys;
766a2d97 BN	528
	529	dev_info(dev, "Broadcom AHCI SATA3 registered\n");
	530
	531	return 0;
c0cdf2ac FF	532
	533	out_disable_platform_phys:
	534	ahci_platform_disable_phys(hpriv);
	535	out_disable_phys:
	536	brcm_sata_phys_disable(priv);
10340f8d FF	537	out_disable_regulators:
10340f8d FF	538	ahci_platform_disable_regulators(hpriv);
c0cdf2ac FF	539	out_disable_clks:
	540	ahci_platform_disable_clks(hpriv);
	541	out_reset:
e8d6f9e5 JQ	542	reset_control_assert(priv->rcdev_ahci);
e8d6f9e5 JQ	543	reset_control_rearm(priv->rcdev_rescal);
c0cdf2ac	544	return ret;
766a2d97 BN	545	}
766a2d97 BN	546
a7eb54d4	547	static void brcm_ahci_remove(struct platform_device *pdev)
766a2d97 BN	548	{
	549	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	550	struct ahci_host_priv *hpriv = host->private_data;
	551	struct brcm_ahci_priv *priv = hpriv->plat_data;
766a2d97	552
c0cdf2ac FF	553	brcm_sata_phys_disable(priv);
c0cdf2ac FF	554
a7eb54d4	555	ata_platform_remove_one(pdev);
766a2d97 BN	556	}
766a2d97 BN	557
7de9b168 FF	558	static void brcm_ahci_shutdown(struct platform_device *pdev)
	559	{
	560	int ret;
	561
	562	/* All resources releasing happens via devres, but our device, unlike a
	563	* proper remove is not disappearing, therefore using
	564	* brcm_ahci_suspend() here which does explicit power management is
	565	* appropriate.
	566	*/
	567	ret = brcm_ahci_suspend(&pdev->dev);
	568	if (ret)
	569	dev_err(&pdev->dev, "failed to shutdown\n");
	570	}
	571
766a2d97 BN	572	static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume);
	573
	574	static struct platform_driver brcm_ahci_driver = {
	575	.probe = brcm_ahci_probe,
a7eb54d4	576	.remove_new = brcm_ahci_remove,
7de9b168	577	.shutdown = brcm_ahci_shutdown,
766a2d97 BN	578	.driver = {
	579	.name = DRV_NAME,
	580	.of_match_table = ahci_of_match,
	581	.pm = &ahci_brcm_pm_ops,
	582	},
	583	};
	584	module_platform_driver(brcm_ahci_driver);
	585
	586	MODULE_DESCRIPTION("Broadcom SATA3 AHCI Controller Driver");
	587	MODULE_AUTHOR("Brian Norris");
	588	MODULE_LICENSE("GPL");
	589	MODULE_ALIAS("platform:sata-brcmstb");