[linux-block.git] / drivers / ata / ahci_brcm.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Broadcom SATA3 AHCI Controller Driver
 *
 * Copyright © 2009-2015 Broadcom Corporation
 */

#include <linux/ahci_platform.h>
#include <linux/compiler.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/libata.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/string.h>

#include "ahci.h"

#define DRV_NAME					"brcm-ahci"

#define SATA_TOP_CTRL_VERSION				0x0
#define SATA_TOP_CTRL_BUS_CTRL				0x4
 #define MMIO_ENDIAN_SHIFT				0 /* CPU->AHCI */
 #define DMADESC_ENDIAN_SHIFT				2 /* AHCI->DDR */
 #define DMADATA_ENDIAN_SHIFT				4 /* AHCI->DDR */
 #define PIODATA_ENDIAN_SHIFT				6
  #define ENDIAN_SWAP_NONE				0
  #define ENDIAN_SWAP_FULL				2
#define SATA_TOP_CTRL_TP_CTRL				0x8
#define SATA_TOP_CTRL_PHY_CTRL				0xc
 #define SATA_TOP_CTRL_PHY_CTRL_1			0x0
  #define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE	BIT(14)
 #define SATA_TOP_CTRL_PHY_CTRL_2			0x4
  #define SATA_TOP_CTRL_2_SW_RST_MDIOREG		BIT(0)
  #define SATA_TOP_CTRL_2_SW_RST_OOB			BIT(1)
  #define SATA_TOP_CTRL_2_SW_RST_RX			BIT(2)
  #define SATA_TOP_CTRL_2_SW_RST_TX			BIT(3)
  #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET		BIT(14)
 #define SATA_TOP_CTRL_PHY_OFFS				0x8
 #define SATA_TOP_MAX_PHYS				2

#define SATA_FIRST_PORT_CTRL				0x700
#define SATA_NEXT_PORT_CTRL_OFFSET			0x80
#define SATA_PORT_PCTRL6(reg_base)			(reg_base + 0x18)

/* On big-endian MIPS, buses are reversed to big endian, so switch them back */
#if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
#define DATA_ENDIAN			 2 /* AHCI->DDR inbound accesses */
#define MMIO_ENDIAN			 2 /* CPU->AHCI outbound accesses */
#else
#define DATA_ENDIAN			 0
#define MMIO_ENDIAN			 0
#endif

#define BUS_CTRL_ENDIAN_CONF				\
	((DATA_ENDIAN << DMADATA_ENDIAN_SHIFT) |	\
	(DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) |		\
	(MMIO_ENDIAN << MMIO_ENDIAN_SHIFT))

#define BUS_CTRL_ENDIAN_NSP_CONF			\
	(0x02 << DMADATA_ENDIAN_SHIFT | 0x02 << DMADESC_ENDIAN_SHIFT)

#define BUS_CTRL_ENDIAN_CONF_MASK			\
	(0x3 << MMIO_ENDIAN_SHIFT | 0x3 << DMADESC_ENDIAN_SHIFT |	\
	 0x3 << DMADATA_ENDIAN_SHIFT | 0x3 << PIODATA_ENDIAN_SHIFT)

enum brcm_ahci_version {
	BRCM_SATA_BCM7425 = 1,
	BRCM_SATA_BCM7445,
	BRCM_SATA_NSP,
	BRCM_SATA_BCM7216,
};

enum brcm_ahci_quirks {
	BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE	= BIT(0),
};

struct brcm_ahci_priv {
	struct device *dev;
	void __iomem *top_ctrl;
	u32 port_mask;
	u32 quirks;
	enum brcm_ahci_version version;
	struct reset_control *rcdev;
};

static inline u32 brcm_sata_readreg(void __iomem *addr)
{
	/*
	 * MIPS endianness is configured by boot strap, which also reverses all
	 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
	 * endian I/O).
	 *
	 * Other architectures (e.g., ARM) either do not support big endian, or
	 * else leave I/O in little endian mode.
	 */
	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
		return __raw_readl(addr);
	else
		return readl_relaxed(addr);
}

static inline void brcm_sata_writereg(u32 val, void __iomem *addr)
{
	/* See brcm_sata_readreg() comments */
	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
		__raw_writel(val, addr);
	else
		writel_relaxed(val, addr);
}

static void brcm_sata_alpm_init(struct ahci_host_priv *hpriv)
{
	struct brcm_ahci_priv *priv = hpriv->plat_data;
	u32 port_ctrl, host_caps;
	int i;

	/* Enable support for ALPM */
	host_caps = readl(hpriv->mmio + HOST_CAP);
	if (!(host_caps & HOST_CAP_ALPM))
		hpriv->flags |= AHCI_HFLAG_YES_ALPM;

	/*
	 * Adjust timeout to allow PLL sufficient time to lock while waking
	 * up from slumber mode.
	 */
	for (i = 0, port_ctrl = SATA_FIRST_PORT_CTRL;
	     i < SATA_TOP_MAX_PHYS;
	     i++, port_ctrl += SATA_NEXT_PORT_CTRL_OFFSET) {
		if (priv->port_mask & BIT(i))
			writel(0xff1003fc,
			       hpriv->mmio + SATA_PORT_PCTRL6(port_ctrl));
	}
}

static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
{
	void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
				(port * SATA_TOP_CTRL_PHY_OFFS);
	void __iomem *p;
	u32 reg;

	if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
		return;

	/* clear PHY_DEFAULT_POWER_STATE */
	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
	reg = brcm_sata_readreg(p);
	reg &= ~SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
	brcm_sata_writereg(reg, p);

	/* reset the PHY digital logic */
	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
	reg = brcm_sata_readreg(p);
	reg &= ~(SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
		 SATA_TOP_CTRL_2_SW_RST_RX);
	reg |= SATA_TOP_CTRL_2_SW_RST_TX;
	brcm_sata_writereg(reg, p);
	reg = brcm_sata_readreg(p);
	reg |= SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
	brcm_sata_writereg(reg, p);
	reg = brcm_sata_readreg(p);
	reg &= ~SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
	brcm_sata_writereg(reg, p);
	(void)brcm_sata_readreg(p);
}

static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
{
	void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
				(port * SATA_TOP_CTRL_PHY_OFFS);
	void __iomem *p;
	u32 reg;

	if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
		return;

	/* power-off the PHY digital logic */
	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
	reg = brcm_sata_readreg(p);
	reg |= (SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
		SATA_TOP_CTRL_2_SW_RST_RX | SATA_TOP_CTRL_2_SW_RST_TX |
		SATA_TOP_CTRL_2_PHY_GLOBAL_RESET);
	brcm_sata_writereg(reg, p);

	/* set PHY_DEFAULT_POWER_STATE */
	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
	reg = brcm_sata_readreg(p);
	reg |= SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
	brcm_sata_writereg(reg, p);
}

static void brcm_sata_phys_enable(struct brcm_ahci_priv *priv)
{
	int i;

	for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
		if (priv->port_mask & BIT(i))
			brcm_sata_phy_enable(priv, i);
}

static void brcm_sata_phys_disable(struct brcm_ahci_priv *priv)
{
	int i;

	for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
		if (priv->port_mask & BIT(i))
			brcm_sata_phy_disable(priv, i);
}

static u32 brcm_ahci_get_portmask(struct ahci_host_priv *hpriv,
				  struct brcm_ahci_priv *priv)
{
	u32 impl;

	impl = readl(hpriv->mmio + HOST_PORTS_IMPL);

	if (fls(impl) > SATA_TOP_MAX_PHYS)
		dev_warn(priv->dev, "warning: more ports than PHYs (%#x)\n",
			 impl);
	else if (!impl)
		dev_info(priv->dev, "no ports found\n");

	return impl;
}

static void brcm_sata_init(struct brcm_ahci_priv *priv)
{
	void __iomem *ctrl = priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL;
	u32 data;

	/* Configure endianness */
	data = brcm_sata_readreg(ctrl);
	data &= ~BUS_CTRL_ENDIAN_CONF_MASK;
	if (priv->version == BRCM_SATA_NSP)
		data |= BUS_CTRL_ENDIAN_NSP_CONF;
	else
		data |= BUS_CTRL_ENDIAN_CONF;
	brcm_sata_writereg(data, ctrl);
}

static unsigned int brcm_ahci_read_id(struct ata_device *dev,
				      struct ata_taskfile *tf, u16 *id)
{
	struct ata_port *ap = dev->link->ap;
	struct ata_host *host = ap->host;
	struct ahci_host_priv *hpriv = host->private_data;
	struct brcm_ahci_priv *priv = hpriv->plat_data;
	void __iomem *mmio = hpriv->mmio;
	unsigned int err_mask;
	unsigned long flags;
	int i, rc;
	u32 ctl;

	/* Try to read the device ID and, if this fails, proceed with the
	 * recovery sequence below
	 */
	err_mask = ata_do_dev_read_id(dev, tf, id);
	if (likely(!err_mask))
		return err_mask;

	/* Disable host interrupts */
	spin_lock_irqsave(&host->lock, flags);
	ctl = readl(mmio + HOST_CTL);
	ctl &= ~HOST_IRQ_EN;
	writel(ctl, mmio + HOST_CTL);
	readl(mmio + HOST_CTL); /* flush */
	spin_unlock_irqrestore(&host->lock, flags);

	/* Perform the SATA PHY reset sequence */
	brcm_sata_phy_disable(priv, ap->port_no);

	/* Reset the SATA clock */
	ahci_platform_disable_clks(hpriv);
	msleep(10);

	ahci_platform_enable_clks(hpriv);
	msleep(10);

	/* Bring the PHY back on */
	brcm_sata_phy_enable(priv, ap->port_no);

	/* Re-initialize and calibrate the PHY */
	for (i = 0; i < hpriv->nports; i++) {
		rc = phy_init(hpriv->phys[i]);
		if (rc)
			goto disable_phys;

		rc = phy_calibrate(hpriv->phys[i]);
		if (rc) {
			phy_exit(hpriv->phys[i]);
			goto disable_phys;
		}
	}

	/* Re-enable host interrupts */
	spin_lock_irqsave(&host->lock, flags);
	ctl = readl(mmio + HOST_CTL);
	ctl |= HOST_IRQ_EN;
	writel(ctl, mmio + HOST_CTL);
	readl(mmio + HOST_CTL); /* flush */
	spin_unlock_irqrestore(&host->lock, flags);

	return ata_do_dev_read_id(dev, tf, id);

disable_phys:
	while (--i >= 0) {
		phy_power_off(hpriv->phys[i]);
		phy_exit(hpriv->phys[i]);
	}

	return AC_ERR_OTHER;
}

static void brcm_ahci_host_stop(struct ata_host *host)
{
	struct ahci_host_priv *hpriv = host->private_data;

	ahci_platform_disable_resources(hpriv);
}

static struct ata_port_operations ahci_brcm_platform_ops = {
	.inherits	= &ahci_ops,
	.host_stop	= brcm_ahci_host_stop,
	.read_id	= brcm_ahci_read_id,
};

static const struct ata_port_info ahci_brcm_port_info = {
	.flags		= AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
	.link_flags	= ATA_LFLAG_NO_DB_DELAY,
	.pio_mask	= ATA_PIO4,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &ahci_brcm_platform_ops,
};

static int brcm_ahci_suspend(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	struct brcm_ahci_priv *priv = hpriv->plat_data;
	int ret;

	brcm_sata_phys_disable(priv);

	if (IS_ENABLED(CONFIG_PM_SLEEP))
		ret = ahci_platform_suspend(dev);
	else
		ret = 0;

	if (priv->version != BRCM_SATA_BCM7216)
		reset_control_assert(priv->rcdev);

	return ret;
}

static int __maybe_unused brcm_ahci_resume(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	struct brcm_ahci_priv *priv = hpriv->plat_data;
	int ret = 0;

	if (priv->version == BRCM_SATA_BCM7216)
		ret = reset_control_reset(priv->rcdev);
	else
		ret = reset_control_deassert(priv->rcdev);
	if (ret)
		return ret;

	/* Make sure clocks are turned on before re-configuration */
	ret = ahci_platform_enable_clks(hpriv);
	if (ret)
		return ret;

	brcm_sata_init(priv);
	brcm_sata_phys_enable(priv);
	brcm_sata_alpm_init(hpriv);

	/* Since we had to enable clocks earlier on, we cannot use
	 * ahci_platform_resume() as-is since a second call to
	 * ahci_platform_enable_resources() would bump up the resources
	 * (regulators, clocks, PHYs) count artificially so we copy the part
	 * after ahci_platform_enable_resources().
	 */
	ret = ahci_platform_enable_phys(hpriv);
	if (ret)
		goto out_disable_phys;

	ret = ahci_platform_resume_host(dev);
	if (ret)
		goto out_disable_platform_phys;

	/* We resumed so update PM runtime state */
	pm_runtime_disable(dev);
	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);

	return 0;

out_disable_platform_phys:
	ahci_platform_disable_phys(hpriv);
out_disable_phys:
	brcm_sata_phys_disable(priv);
	ahci_platform_disable_clks(hpriv);
	return ret;
}

static struct scsi_host_template ahci_platform_sht = {
	AHCI_SHT(DRV_NAME),
};

static const struct of_device_id ahci_of_match[] = {
	{.compatible = "brcm,bcm7425-ahci", .data = (void *)BRCM_SATA_BCM7425},
	{.compatible = "brcm,bcm7445-ahci", .data = (void *)BRCM_SATA_BCM7445},
	{.compatible = "brcm,bcm63138-ahci", .data = (void *)BRCM_SATA_BCM7445},
	{.compatible = "brcm,bcm-nsp-ahci", .data = (void *)BRCM_SATA_NSP},
	{.compatible = "brcm,bcm7216-ahci", .data = (void *)BRCM_SATA_BCM7216},
	{},
};
MODULE_DEVICE_TABLE(of, ahci_of_match);

static int brcm_ahci_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id;
	struct device *dev = &pdev->dev;
	const char *reset_name = NULL;
	struct brcm_ahci_priv *priv;
	struct ahci_host_priv *hpriv;
	struct resource *res;
	int ret;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	of_id = of_match_node(ahci_of_match, pdev->dev.of_node);
	if (!of_id)
		return -ENODEV;

	priv->version = (enum brcm_ahci_version)of_id->data;
	priv->dev = dev;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "top-ctrl");
	priv->top_ctrl = devm_ioremap_resource(dev, res);
	if (IS_ERR(priv->top_ctrl))
		return PTR_ERR(priv->top_ctrl);

	/* Reset is optional depending on platform and named differently */
	if (priv->version == BRCM_SATA_BCM7216)
		reset_name = "rescal";
	else
		reset_name = "ahci";

	priv->rcdev = devm_reset_control_get_optional(&pdev->dev, reset_name);
	if (IS_ERR(priv->rcdev))
		return PTR_ERR(priv->rcdev);

	hpriv = ahci_platform_get_resources(pdev, 0);
	if (IS_ERR(hpriv))
		return PTR_ERR(hpriv);

	hpriv->plat_data = priv;
	hpriv->flags = AHCI_HFLAG_WAKE_BEFORE_STOP | AHCI_HFLAG_NO_WRITE_TO_RO;

	switch (priv->version) {
	case BRCM_SATA_BCM7425:
		hpriv->flags |= AHCI_HFLAG_DELAY_ENGINE;
		fallthrough;
	case BRCM_SATA_NSP:
		hpriv->flags |= AHCI_HFLAG_NO_NCQ;
		priv->quirks |= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE;
		break;
	default:
		break;
	}

	if (priv->version == BRCM_SATA_BCM7216)
		ret = reset_control_reset(priv->rcdev);
	else
		ret = reset_control_deassert(priv->rcdev);
	if (ret)
		return ret;

	ret = ahci_platform_enable_clks(hpriv);
	if (ret)
		goto out_reset;

	/* Must be first so as to configure endianness including that
	 * of the standard AHCI register space.
	 */
	brcm_sata_init(priv);

	/* Initializes priv->port_mask which is used below */
	priv->port_mask = brcm_ahci_get_portmask(hpriv, priv);
	if (!priv->port_mask) {
		ret = -ENODEV;
		goto out_disable_clks;
	}

	/* Must be done before ahci_platform_enable_phys() */
	brcm_sata_phys_enable(priv);

	brcm_sata_alpm_init(hpriv);

	ret = ahci_platform_enable_phys(hpriv);
	if (ret)
		goto out_disable_phys;

	ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info,
				      &ahci_platform_sht);
	if (ret)
		goto out_disable_platform_phys;

	dev_info(dev, "Broadcom AHCI SATA3 registered\n");

	return 0;

out_disable_platform_phys:
	ahci_platform_disable_phys(hpriv);
out_disable_phys:
	brcm_sata_phys_disable(priv);
out_disable_clks:
	ahci_platform_disable_clks(hpriv);
out_reset:
	if (priv->version != BRCM_SATA_BCM7216)
		reset_control_assert(priv->rcdev);
	return ret;
}

static int brcm_ahci_remove(struct platform_device *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	struct ahci_host_priv *hpriv = host->private_data;
	struct brcm_ahci_priv *priv = hpriv->plat_data;
	int ret;

	brcm_sata_phys_disable(priv);

	ret = ata_platform_remove_one(pdev);
	if (ret)
		return ret;

	return 0;
}

static void brcm_ahci_shutdown(struct platform_device *pdev)
{
	int ret;

	/* All resources releasing happens via devres, but our device, unlike a
	 * proper remove is not disappearing, therefore using
	 * brcm_ahci_suspend() here which does explicit power management is
	 * appropriate.
	 */
	ret = brcm_ahci_suspend(&pdev->dev);
	if (ret)
		dev_err(&pdev->dev, "failed to shutdown\n");
}

static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume);

static struct platform_driver brcm_ahci_driver = {
	.probe = brcm_ahci_probe,
	.remove = brcm_ahci_remove,
	.shutdown = brcm_ahci_shutdown,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = ahci_of_match,
		.pm = &ahci_brcm_pm_ops,
	},
};
module_platform_driver(brcm_ahci_driver);

MODULE_DESCRIPTION("Broadcom SATA3 AHCI Controller Driver");
MODULE_AUTHOR("Brian Norris");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:sata-brcmstb");
Commit	Line	Data
3e0a4e85	1	// SPDX-License-Identifier: GPL-2.0-or-later
766a2d97 BN	2	/*
	3	* Broadcom SATA3 AHCI Controller Driver
	4	*
	5	* Copyright © 2009-2015 Broadcom Corporation
766a2d97 BN	6	*/
	7
	8	#include <linux/ahci_platform.h>
	9	#include <linux/compiler.h>
	10	#include <linux/device.h>
	11	#include <linux/init.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/io.h>
	14	#include <linux/kernel.h>
	15	#include <linux/libata.h>
	16	#include <linux/module.h>
	17	#include <linux/of.h>
	18	#include <linux/platform_device.h>
2b2c47d9	19	#include <linux/reset.h>
766a2d97 BN	20	#include <linux/string.h>
	21
	22	#include "ahci.h"
	23
	24	#define DRV_NAME "brcm-ahci"
	25
	26	#define SATA_TOP_CTRL_VERSION 0x0
	27	#define SATA_TOP_CTRL_BUS_CTRL 0x4
	28	#define MMIO_ENDIAN_SHIFT 0 /* CPU->AHCI */
	29	#define DMADESC_ENDIAN_SHIFT 2 /* AHCI->DDR */
	30	#define DMADATA_ENDIAN_SHIFT 4 /* AHCI->DDR */
	31	#define PIODATA_ENDIAN_SHIFT 6
	32	#define ENDIAN_SWAP_NONE 0
	33	#define ENDIAN_SWAP_FULL 2
766a2d97 BN	34	#define SATA_TOP_CTRL_TP_CTRL 0x8
	35	#define SATA_TOP_CTRL_PHY_CTRL 0xc
	36	#define SATA_TOP_CTRL_PHY_CTRL_1 0x0
	37	#define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE BIT(14)
	38	#define SATA_TOP_CTRL_PHY_CTRL_2 0x4
	39	#define SATA_TOP_CTRL_2_SW_RST_MDIOREG BIT(0)
	40	#define SATA_TOP_CTRL_2_SW_RST_OOB BIT(1)
	41	#define SATA_TOP_CTRL_2_SW_RST_RX BIT(2)
	42	#define SATA_TOP_CTRL_2_SW_RST_TX BIT(3)
	43	#define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET BIT(14)
	44	#define SATA_TOP_CTRL_PHY_OFFS 0x8
	45	#define SATA_TOP_MAX_PHYS 2
766a2d97	46
6863caaf DP	47	#define SATA_FIRST_PORT_CTRL 0x700
	48	#define SATA_NEXT_PORT_CTRL_OFFSET 0x80
	49	#define SATA_PORT_PCTRL6(reg_base) (reg_base + 0x18)
	50
766a2d97 BN	51	/* On big-endian MIPS, buses are reversed to big endian, so switch them back */
	52	#if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
	53	#define DATA_ENDIAN 2 /* AHCI->DDR inbound accesses */
	54	#define MMIO_ENDIAN 2 /* CPU->AHCI outbound accesses */
	55	#else
	56	#define DATA_ENDIAN 0
	57	#define MMIO_ENDIAN 0
	58	#endif
	59
	60	#define BUS_CTRL_ENDIAN_CONF \
	61	((DATA_ENDIAN << DMADATA_ENDIAN_SHIFT) \| \
	62	(DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) \| \
	63	(MMIO_ENDIAN << MMIO_ENDIAN_SHIFT))
	64
36fffd6a FF	65	#define BUS_CTRL_ENDIAN_NSP_CONF \
	66	(0x02 << DMADATA_ENDIAN_SHIFT \| 0x02 << DMADESC_ENDIAN_SHIFT)
	67
	68	#define BUS_CTRL_ENDIAN_CONF_MASK \
	69	(0x3 << MMIO_ENDIAN_SHIFT \| 0x3 << DMADESC_ENDIAN_SHIFT \| \
	70	0x3 << DMADATA_ENDIAN_SHIFT \| 0x3 << PIODATA_ENDIAN_SHIFT)
	71
3ee2e6dc YRDR	72	enum brcm_ahci_version {
	73	BRCM_SATA_BCM7425 = 1,
	74	BRCM_SATA_BCM7445,
	75	BRCM_SATA_NSP,
c345ec6a	76	BRCM_SATA_BCM7216,
3ee2e6dc YRDR	77	};
3ee2e6dc YRDR	78
7de32445	79	enum brcm_ahci_quirks {
1a3d78cb	80	BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE = BIT(0),
7de32445 JS	81	};
7de32445 JS	82
766a2d97 BN	83	struct brcm_ahci_priv {
	84	struct device *dev;
	85	void __iomem *top_ctrl;
	86	u32 port_mask;
7de32445	87	u32 quirks;
3ee2e6dc	88	enum brcm_ahci_version version;
2b2c47d9	89	struct reset_control *rcdev;
766a2d97 BN	90	};
766a2d97 BN	91
766a2d97 BN	92	static inline u32 brcm_sata_readreg(void __iomem *addr)
	93	{
	94	/*
	95	* MIPS endianness is configured by boot strap, which also reverses all
	96	* bus endianness (i.e., big-endian CPU + big endian bus ==> native
	97	* endian I/O).
	98	*
	99	* Other architectures (e.g., ARM) either do not support big endian, or
	100	* else leave I/O in little endian mode.
	101	*/
f9114d35	102	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
766a2d97 BN	103	return __raw_readl(addr);
	104	else
	105	return readl_relaxed(addr);
	106	}
	107
	108	static inline void brcm_sata_writereg(u32 val, void __iomem *addr)
	109	{
	110	/* See brcm_sata_readreg() comments */
f9114d35	111	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
766a2d97 BN	112	__raw_writel(val, addr);
	113	else
	114	writel_relaxed(val, addr);
	115	}
	116
6863caaf DP	117	static void brcm_sata_alpm_init(struct ahci_host_priv *hpriv)
	118	{
	119	struct brcm_ahci_priv *priv = hpriv->plat_data;
da8fa9cc	120	u32 port_ctrl, host_caps;
6863caaf DP	121	int i;
	122
	123	/* Enable support for ALPM */
6863caaf	124	host_caps = readl(hpriv->mmio + HOST_CAP);
da8fa9cc DB	125	if (!(host_caps & HOST_CAP_ALPM))
da8fa9cc DB	126	hpriv->flags \|= AHCI_HFLAG_YES_ALPM;
6863caaf DP	127
	128	/*
	129	* Adjust timeout to allow PLL sufficient time to lock while waking
	130	* up from slumber mode.
	131	*/
	132	for (i = 0, port_ctrl = SATA_FIRST_PORT_CTRL;
	133	i < SATA_TOP_MAX_PHYS;
	134	i++, port_ctrl += SATA_NEXT_PORT_CTRL_OFFSET) {
	135	if (priv->port_mask & BIT(i))
	136	writel(0xff1003fc,
	137	hpriv->mmio + SATA_PORT_PCTRL6(port_ctrl));
	138	}
	139	}
	140
766a2d97 BN	141	static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
	142	{
	143	void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
	144	(port * SATA_TOP_CTRL_PHY_OFFS);
	145	void __iomem *p;
	146	u32 reg;
	147
b46f79bc JS	148	if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
	149	return;
	150
766a2d97 BN	151	/* clear PHY_DEFAULT_POWER_STATE */
	152	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
	153	reg = brcm_sata_readreg(p);
	154	reg &= ~SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
	155	brcm_sata_writereg(reg, p);
	156
	157	/* reset the PHY digital logic */
	158	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
	159	reg = brcm_sata_readreg(p);
	160	reg &= ~(SATA_TOP_CTRL_2_SW_RST_MDIOREG \| SATA_TOP_CTRL_2_SW_RST_OOB \|
	161	SATA_TOP_CTRL_2_SW_RST_RX);
	162	reg \|= SATA_TOP_CTRL_2_SW_RST_TX;
	163	brcm_sata_writereg(reg, p);
	164	reg = brcm_sata_readreg(p);
	165	reg \|= SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
	166	brcm_sata_writereg(reg, p);
	167	reg = brcm_sata_readreg(p);
	168	reg &= ~SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
	169	brcm_sata_writereg(reg, p);
	170	(void)brcm_sata_readreg(p);
	171	}
	172
	173	static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
	174	{
	175	void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
	176	(port * SATA_TOP_CTRL_PHY_OFFS);
	177	void __iomem *p;
	178	u32 reg;
	179
b46f79bc JS	180	if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
	181	return;
	182
766a2d97 BN	183	/* power-off the PHY digital logic */
	184	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
	185	reg = brcm_sata_readreg(p);
	186	reg \|= (SATA_TOP_CTRL_2_SW_RST_MDIOREG \| SATA_TOP_CTRL_2_SW_RST_OOB \|
	187	SATA_TOP_CTRL_2_SW_RST_RX \| SATA_TOP_CTRL_2_SW_RST_TX \|
	188	SATA_TOP_CTRL_2_PHY_GLOBAL_RESET);
	189	brcm_sata_writereg(reg, p);
	190
	191	/* set PHY_DEFAULT_POWER_STATE */
	192	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
	193	reg = brcm_sata_readreg(p);
	194	reg \|= SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
	195	brcm_sata_writereg(reg, p);
	196	}
	197
	198	static void brcm_sata_phys_enable(struct brcm_ahci_priv *priv)
	199	{
	200	int i;
	201
	202	for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
	203	if (priv->port_mask & BIT(i))
	204	brcm_sata_phy_enable(priv, i);
	205	}
	206
	207	static void brcm_sata_phys_disable(struct brcm_ahci_priv *priv)
	208	{
	209	int i;
	210
	211	for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
	212	if (priv->port_mask & BIT(i))
	213	brcm_sata_phy_disable(priv, i);
	214	}
	215
c0cdf2ac	216	static u32 brcm_ahci_get_portmask(struct ahci_host_priv *hpriv,
766a2d97 BN	217	struct brcm_ahci_priv *priv)
766a2d97 BN	218	{
766a2d97 BN	219	u32 impl;
766a2d97 BN	220
c0cdf2ac	221	impl = readl(hpriv->mmio + HOST_PORTS_IMPL);
766a2d97 BN	222
	223	if (fls(impl) > SATA_TOP_MAX_PHYS)
	224	dev_warn(priv->dev, "warning: more ports than PHYs (%#x)\n",
	225	impl);
	226	else if (!impl)
	227	dev_info(priv->dev, "no ports found\n");
	228
766a2d97 BN	229	return impl;
	230	}
	231
	232	static void brcm_sata_init(struct brcm_ahci_priv *priv)
	233	{
3ee2e6dc	234	void __iomem *ctrl = priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL;
36fffd6a	235	u32 data;
3ee2e6dc	236
766a2d97	237	/* Configure endianness */
36fffd6a FF	238	data = brcm_sata_readreg(ctrl);
	239	data &= ~BUS_CTRL_ENDIAN_CONF_MASK;
	240	if (priv->version == BRCM_SATA_NSP)
	241	data \|= BUS_CTRL_ENDIAN_NSP_CONF;
	242	else
	243	data \|= BUS_CTRL_ENDIAN_CONF;
	244	brcm_sata_writereg(data, ctrl);
766a2d97 BN	245	}
766a2d97 BN	246
eb73390a FF	247	static unsigned int brcm_ahci_read_id(struct ata_device *dev,
	248	struct ata_taskfile tf, u16 id)
	249	{
	250	struct ata_port *ap = dev->link->ap;
	251	struct ata_host *host = ap->host;
	252	struct ahci_host_priv *hpriv = host->private_data;
	253	struct brcm_ahci_priv *priv = hpriv->plat_data;
	254	void __iomem *mmio = hpriv->mmio;
	255	unsigned int err_mask;
	256	unsigned long flags;
	257	int i, rc;
	258	u32 ctl;
	259
	260	/* Try to read the device ID and, if this fails, proceed with the
	261	* recovery sequence below
	262	*/
	263	err_mask = ata_do_dev_read_id(dev, tf, id);
	264	if (likely(!err_mask))
	265	return err_mask;
	266
	267	/* Disable host interrupts */
	268	spin_lock_irqsave(&host->lock, flags);
	269	ctl = readl(mmio + HOST_CTL);
	270	ctl &= ~HOST_IRQ_EN;
	271	writel(ctl, mmio + HOST_CTL);
	272	readl(mmio + HOST_CTL); /* flush */
	273	spin_unlock_irqrestore(&host->lock, flags);
	274
	275	/* Perform the SATA PHY reset sequence */
	276	brcm_sata_phy_disable(priv, ap->port_no);
	277
bf0e5013 FF	278	/* Reset the SATA clock */
	279	ahci_platform_disable_clks(hpriv);
	280	msleep(10);
	281
	282	ahci_platform_enable_clks(hpriv);
	283	msleep(10);
	284
eb73390a FF	285	/* Bring the PHY back on */
	286	brcm_sata_phy_enable(priv, ap->port_no);
	287
	288	/* Re-initialize and calibrate the PHY */
	289	for (i = 0; i < hpriv->nports; i++) {
	290	rc = phy_init(hpriv->phys[i]);
	291	if (rc)
	292	goto disable_phys;
	293
	294	rc = phy_calibrate(hpriv->phys[i]);
	295	if (rc) {
	296	phy_exit(hpriv->phys[i]);
	297	goto disable_phys;
	298	}
	299	}
	300
	301	/* Re-enable host interrupts */
	302	spin_lock_irqsave(&host->lock, flags);
	303	ctl = readl(mmio + HOST_CTL);
	304	ctl \|= HOST_IRQ_EN;
	305	writel(ctl, mmio + HOST_CTL);
	306	readl(mmio + HOST_CTL); /* flush */
	307	spin_unlock_irqrestore(&host->lock, flags);
	308
	309	return ata_do_dev_read_id(dev, tf, id);
	310
	311	disable_phys:
	312	while (--i >= 0) {
	313	phy_power_off(hpriv->phys[i]);
	314	phy_exit(hpriv->phys[i]);
	315	}
	316
	317	return AC_ERR_OTHER;
	318	}
	319
	320	static void brcm_ahci_host_stop(struct ata_host *host)
	321	{
	322	struct ahci_host_priv *hpriv = host->private_data;
	323
	324	ahci_platform_disable_resources(hpriv);
	325	}
	326
	327	static struct ata_port_operations ahci_brcm_platform_ops = {
	328	.inherits = &ahci_ops,
	329	.host_stop = brcm_ahci_host_stop,
	330	.read_id = brcm_ahci_read_id,
	331	};
	332
	333	static const struct ata_port_info ahci_brcm_port_info = {
	334	.flags = AHCI_FLAG_COMMON \| ATA_FLAG_NO_DIPM,
	335	.link_flags = ATA_LFLAG_NO_DB_DELAY,
	336	.pio_mask = ATA_PIO4,
	337	.udma_mask = ATA_UDMA6,
	338	.port_ops = &ahci_brcm_platform_ops,
	339	};
	340
766a2d97 BN	341	static int brcm_ahci_suspend(struct device *dev)
	342	{
	343	struct ata_host *host = dev_get_drvdata(dev);
	344	struct ahci_host_priv *hpriv = host->private_data;
	345	struct brcm_ahci_priv *priv = hpriv->plat_data;
3c696ac4	346	int ret;
766a2d97	347
766a2d97	348	brcm_sata_phys_disable(priv);
c0cdf2ac	349
ed87ad19 AB	350	if (IS_ENABLED(CONFIG_PM_SLEEP))
	351	ret = ahci_platform_suspend(dev);
	352	else
	353	ret = 0;
3c696ac4	354
272ecd60 FF	355	if (priv->version != BRCM_SATA_BCM7216)
272ecd60 FF	356	reset_control_assert(priv->rcdev);
3c696ac4 FF	357
3c696ac4 FF	358	return ret;
766a2d97 BN	359	}
766a2d97 BN	360
ed87ad19	361	static int __maybe_unused brcm_ahci_resume(struct device *dev)
766a2d97 BN	362	{
	363	struct ata_host *host = dev_get_drvdata(dev);
	364	struct ahci_host_priv *hpriv = host->private_data;
	365	struct brcm_ahci_priv *priv = hpriv->plat_data;
3c696ac4 FF	366	int ret = 0;
3c696ac4 FF	367
272ecd60 FF	368	if (priv->version == BRCM_SATA_BCM7216)
	369	ret = reset_control_reset(priv->rcdev);
	370	else
	371	ret = reset_control_deassert(priv->rcdev);
3c696ac4 FF	372	if (ret)
3c696ac4 FF	373	return ret;
c0cdf2ac FF	374
	375	/* Make sure clocks are turned on before re-configuration */
	376	ret = ahci_platform_enable_clks(hpriv);
	377	if (ret)
	378	return ret;
766a2d97 BN	379
	380	brcm_sata_init(priv);
	381	brcm_sata_phys_enable(priv);
6863caaf	382	brcm_sata_alpm_init(hpriv);
c0cdf2ac FF	383
	384	/* Since we had to enable clocks earlier on, we cannot use
	385	* ahci_platform_resume() as-is since a second call to
	386	* ahci_platform_enable_resources() would bump up the resources
	387	* (regulators, clocks, PHYs) count artificially so we copy the part
	388	* after ahci_platform_enable_resources().
	389	*/
	390	ret = ahci_platform_enable_phys(hpriv);
	391	if (ret)
	392	goto out_disable_phys;
	393
	394	ret = ahci_platform_resume_host(dev);
	395	if (ret)
	396	goto out_disable_platform_phys;
	397
	398	/* We resumed so update PM runtime state */
	399	pm_runtime_disable(dev);
	400	pm_runtime_set_active(dev);
	401	pm_runtime_enable(dev);
	402
	403	return 0;
	404
	405	out_disable_platform_phys:
	406	ahci_platform_disable_phys(hpriv);
	407	out_disable_phys:
	408	brcm_sata_phys_disable(priv);
	409	ahci_platform_disable_clks(hpriv);
	410	return ret;
766a2d97 BN	411	}
	412
	413	static struct scsi_host_template ahci_platform_sht = {
	414	AHCI_SHT(DRV_NAME),
	415	};
	416
3ee2e6dc YRDR	417	static const struct of_device_id ahci_of_match[] = {
	418	{.compatible = "brcm,bcm7425-ahci", .data = (void *)BRCM_SATA_BCM7425},
	419	{.compatible = "brcm,bcm7445-ahci", .data = (void *)BRCM_SATA_BCM7445},
fb8506f1	420	{.compatible = "brcm,bcm63138-ahci", .data = (void *)BRCM_SATA_BCM7445},
3ee2e6dc	421	{.compatible = "brcm,bcm-nsp-ahci", .data = (void *)BRCM_SATA_NSP},
c345ec6a	422	{.compatible = "brcm,bcm7216-ahci", .data = (void *)BRCM_SATA_BCM7216},
3ee2e6dc YRDR	423	{},
	424	};
	425	MODULE_DEVICE_TABLE(of, ahci_of_match);
	426
766a2d97 BN	427	static int brcm_ahci_probe(struct platform_device *pdev)
766a2d97 BN	428	{
3ee2e6dc	429	const struct of_device_id *of_id;
766a2d97	430	struct device *dev = &pdev->dev;
c345ec6a	431	const char *reset_name = NULL;
766a2d97 BN	432	struct brcm_ahci_priv *priv;
	433	struct ahci_host_priv *hpriv;
	434	struct resource *res;
	435	int ret;
	436
	437	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	438	if (!priv)
	439	return -ENOMEM;
3ee2e6dc YRDR	440
	441	of_id = of_match_node(ahci_of_match, pdev->dev.of_node);
	442	if (!of_id)
	443	return -ENODEV;
	444
	445	priv->version = (enum brcm_ahci_version)of_id->data;
766a2d97 BN	446	priv->dev = dev;
	447
	448	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "top-ctrl");
	449	priv->top_ctrl = devm_ioremap_resource(dev, res);
	450	if (IS_ERR(priv->top_ctrl))
	451	return PTR_ERR(priv->top_ctrl);
	452
c345ec6a FF	453	/* Reset is optional depending on platform and named differently */
	454	if (priv->version == BRCM_SATA_BCM7216)
	455	reset_name = "rescal";
	456	else
	457	reset_name = "ahci";
	458
6fedae3c AB	459	priv->rcdev = devm_reset_control_get_optional(&pdev->dev, reset_name);
	460	if (IS_ERR(priv->rcdev))
	461	return PTR_ERR(priv->rcdev);
	462
c0cdf2ac	463	hpriv = ahci_platform_get_resources(pdev, 0);
1a0600d1 FF	464	if (IS_ERR(hpriv))
1a0600d1 FF	465	return PTR_ERR(hpriv);
c0cdf2ac	466
1a3d78cb FF	467	hpriv->plat_data = priv;
	468	hpriv->flags = AHCI_HFLAG_WAKE_BEFORE_STOP \| AHCI_HFLAG_NO_WRITE_TO_RO;
	469
	470	switch (priv->version) {
	471	case BRCM_SATA_BCM7425:
	472	hpriv->flags \|= AHCI_HFLAG_DELAY_ENGINE;
df561f66	473	fallthrough;
1a3d78cb FF	474	case BRCM_SATA_NSP:
	475	hpriv->flags \|= AHCI_HFLAG_NO_NCQ;
	476	priv->quirks \|= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE;
	477	break;
	478	default:
	479	break;
	480	}
	481
272ecd60 FF	482	if (priv->version == BRCM_SATA_BCM7216)
	483	ret = reset_control_reset(priv->rcdev);
	484	else
	485	ret = reset_control_deassert(priv->rcdev);
1a0600d1 FF	486	if (ret)
	487	return ret;
	488
c0cdf2ac FF	489	ret = ahci_platform_enable_clks(hpriv);
	490	if (ret)
	491	goto out_reset;
	492
	493	/* Must be first so as to configure endianness including that
	494	* of the standard AHCI register space.
	495	*/
766a2d97 BN	496	brcm_sata_init(priv);
766a2d97 BN	497
c0cdf2ac FF	498	/* Initializes priv->port_mask which is used below */
	499	priv->port_mask = brcm_ahci_get_portmask(hpriv, priv);
	500	if (!priv->port_mask) {
	501	ret = -ENODEV;
	502	goto out_disable_clks;
	503	}
766a2d97	504
c0cdf2ac	505	/* Must be done before ahci_platform_enable_phys() */
766a2d97 BN	506	brcm_sata_phys_enable(priv);
766a2d97 BN	507
6863caaf DP	508	brcm_sata_alpm_init(hpriv);
6863caaf DP	509
c0cdf2ac FF	510	ret = ahci_platform_enable_phys(hpriv);
	511	if (ret)
	512	goto out_disable_phys;
	513
766a2d97 BN	514	ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info,
	515	&ahci_platform_sht);
	516	if (ret)
c0cdf2ac	517	goto out_disable_platform_phys;
766a2d97 BN	518
	519	dev_info(dev, "Broadcom AHCI SATA3 registered\n");
	520
	521	return 0;
c0cdf2ac FF	522
	523	out_disable_platform_phys:
	524	ahci_platform_disable_phys(hpriv);
	525	out_disable_phys:
	526	brcm_sata_phys_disable(priv);
	527	out_disable_clks:
	528	ahci_platform_disable_clks(hpriv);
	529	out_reset:
272ecd60 FF	530	if (priv->version != BRCM_SATA_BCM7216)
272ecd60 FF	531	reset_control_assert(priv->rcdev);
c0cdf2ac	532	return ret;
766a2d97 BN	533	}
	534
	535	static int brcm_ahci_remove(struct platform_device *pdev)
	536	{
	537	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	538	struct ahci_host_priv *hpriv = host->private_data;
	539	struct brcm_ahci_priv *priv = hpriv->plat_data;
	540	int ret;
	541
c0cdf2ac FF	542	brcm_sata_phys_disable(priv);
c0cdf2ac FF	543
766a2d97 BN	544	ret = ata_platform_remove_one(pdev);
	545	if (ret)
	546	return ret;
	547
766a2d97 BN	548	return 0;
	549	}
	550
7de9b168 FF	551	static void brcm_ahci_shutdown(struct platform_device *pdev)
	552	{
	553	int ret;
	554
	555	/* All resources releasing happens via devres, but our device, unlike a
	556	* proper remove is not disappearing, therefore using
	557	* brcm_ahci_suspend() here which does explicit power management is
	558	* appropriate.
	559	*/
	560	ret = brcm_ahci_suspend(&pdev->dev);
	561	if (ret)
	562	dev_err(&pdev->dev, "failed to shutdown\n");
	563	}
	564
766a2d97 BN	565	static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume);
	566
	567	static struct platform_driver brcm_ahci_driver = {
	568	.probe = brcm_ahci_probe,
	569	.remove = brcm_ahci_remove,
7de9b168	570	.shutdown = brcm_ahci_shutdown,
766a2d97 BN	571	.driver = {
	572	.name = DRV_NAME,
	573	.of_match_table = ahci_of_match,
	574	.pm = &ahci_brcm_pm_ops,
	575	},
	576	};
	577	module_platform_driver(brcm_ahci_driver);
	578
	579	MODULE_DESCRIPTION("Broadcom SATA3 AHCI Controller Driver");
	580	MODULE_AUTHOR("Brian Norris");
	581	MODULE_LICENSE("GPL");
	582	MODULE_ALIAS("platform:sata-brcmstb");