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Merge tag 'pm-6.16-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
[linux-block.git] / drivers / ata / ahci.c
CommitLineData
c82ee6d3 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4
LT		 2/*
3 * ahci.c - AHCI SATA support
4 *
8c3d3d4b 5 * Maintained by: Tejun Heo <tj@kernel.org>
af36d7f0
JG		 6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
af36d7f0 11 * libata documentation is available via 'make {ps|pdf}docs',
19285f3c 12 * as Documentation/driver-api/libata.rst
af36d7f0
JG		 13 *
14 * AHCI hardware documentation:
1da177e4 15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
1da177e4
LT		 22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <linux/interrupt.h>
87507cfd 25#include <linux/dma-mapping.h>
a9524a76 26#include <linux/device.h>
edc93052 27#include <linux/dmi.h>
5a0e3ad6 28#include <linux/gfp.h>
1da177e4 29#include <scsi/scsi_host.h>
193515d5 30#include <scsi/scsi_cmnd.h>
1da177e4 31#include <linux/libata.h>
aecec8b6
CH		 32#include <linux/ahci-remap.h>
33#include <linux/io-64-nonatomic-lo-hi.h>
365cfa1e 34#include "ahci.h"
1da177e4
LT		 35
36#define DRV_NAME "ahci"
7d50b60b 37#define DRV_VERSION "3.0"
1da177e4 38
1da177e4 39enum {
318893e1 40 AHCI_PCI_BAR_STA2X11 = 0,
b7ae128d 41 AHCI_PCI_BAR_CAVIUM = 0,
e49bd683 42 AHCI_PCI_BAR_LOONGSON = 0,
7f9c9f8e 43 AHCI_PCI_BAR_ENMOTUS = 2,
b1314e3f 44 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
318893e1 45 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 46};
47
48enum board_ids {
49 /* board IDs by feature in alphabetical order */
50 board_ahci,
20730e9b 51 board_ahci_43bit_dma,
441577ef 52 board_ahci_ign_iferr,
a17ab7ab 53 board_ahci_no_debounce_delay,
87312151 54 board_ahci_no_msi,
7edbb605
NC		 55 /*
56 * board_ahci_pcs_quirk is for legacy Intel platforms.
57 * Modern Intel platforms should use board_ahci instead.
58 * (Some modern Intel platforms might have been added with
59 * board_ahci_pcs_quirk, however, we cannot change them to board_ahci
60 * without testing that the platform actually works without the quirk.)
61 */
62 board_ahci_pcs_quirk,
bf6f1581 63 board_ahci_pcs_quirk_no_devslp,
f2b70a26 64 board_ahci_pcs_quirk_no_sntf,
5f173107 65 board_ahci_yes_fbs,
0507c777 66 board_ahci_yes_fbs_atapi_dma,
1da177e4 67
441577ef 68 /* board IDs for specific chipsets in alphabetical order */
7d523bdc 69 board_ahci_al,
dbfe8ef5 70 board_ahci_avn,
441577ef 71 board_ahci_mcp65,
83f2b963
TH		 72 board_ahci_mcp77,
73 board_ahci_mcp89,
441577ef
TH		 74 board_ahci_mv,
75 board_ahci_sb600,
76 board_ahci_sb700, /* for SB700 and SB800 */
77 board_ahci_vt8251,
78
79 /* aliases */
80 board_ahci_mcp_linux = board_ahci_mcp65,
81 board_ahci_mcp67 = board_ahci_mcp65,
82 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 83 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 84};
85
2dcb407e 86static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
02e53293 87static void ahci_remove_one(struct pci_dev *dev);
10a663a1 88static void ahci_shutdown_one(struct pci_dev *dev);
37e14e4f 89static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv);
a1efdaba
TH		 90static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
91 unsigned long deadline);
dbfe8ef5
DW		 92static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
93 unsigned long deadline);
cb85696d
JL		 94static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
95static bool is_mcp89_apple(struct pci_dev *pdev);
a1efdaba
TH		 96static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
97 unsigned long deadline);
02e53293
MW		 98#ifdef CONFIG_PM
99static int ahci_pci_device_runtime_suspend(struct device *dev);
100static int ahci_pci_device_runtime_resume(struct device *dev);
f1d848f9
MW		 101#ifdef CONFIG_PM_SLEEP
102static int ahci_pci_device_suspend(struct device *dev);
103static int ahci_pci_device_resume(struct device *dev);
438ac6d5 104#endif
02e53293 105#endif /* CONFIG_PM */
ad616ffb 106
25df73d9 107static const struct scsi_host_template ahci_sht = {
fad16e7a
TH		 108 AHCI_SHT("ahci"),
109};
110
029cfd6b
TH		 111static struct ata_port_operations ahci_vt8251_ops = {
112 .inherits = &ahci_ops,
a1efdaba 113 .hardreset = ahci_vt8251_hardreset,
029cfd6b 114};
edc93052 115
029cfd6b
TH		 116static struct ata_port_operations ahci_p5wdh_ops = {
117 .inherits = &ahci_ops,
a1efdaba 118 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 119};
120
dbfe8ef5
DW		 121static struct ata_port_operations ahci_avn_ops = {
122 .inherits = &ahci_ops,
123 .hardreset = ahci_avn_hardreset,
124};
125
98ac62de 126static const struct ata_port_info ahci_port_info[] = {
441577ef 127 /* by features */
facb8fa6 128 [board_ahci] = {
1188c0d8 129 .flags = AHCI_FLAG_COMMON,
14bdef98 130 .pio_mask = ATA_PIO4,
469248ab 131 .udma_mask = ATA_UDMA6,
1da177e4
LT		 132 .port_ops = &ahci_ops,
133 },
20730e9b
LB		 134 [board_ahci_43bit_dma] = {
135 AHCI_HFLAGS (AHCI_HFLAG_43BIT_ONLY),
136 .flags = AHCI_FLAG_COMMON,
137 .pio_mask = ATA_PIO4,
138 .udma_mask = ATA_UDMA6,
139 .port_ops = &ahci_ops,
140 },
facb8fa6 141 [board_ahci_ign_iferr] = {
441577ef 142 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 143 .flags = AHCI_FLAG_COMMON,
14bdef98 144 .pio_mask = ATA_PIO4,
469248ab 145 .udma_mask = ATA_UDMA6,
441577ef 146 .port_ops = &ahci_ops,
bf2af2a2 147 },
a17ab7ab 148 [board_ahci_no_debounce_delay] = {
ebb82e3c 149 .flags = AHCI_FLAG_COMMON,
a17ab7ab 150 .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY,
ebb82e3c
HG		 151 .pio_mask = ATA_PIO4,
152 .udma_mask = ATA_UDMA6,
153 .port_ops = &ahci_ops,
154 },
87312151 155 [board_ahci_no_msi] = {
66a7cbc3 156 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
a17ab7ab 157 .flags = AHCI_FLAG_COMMON,
a17ab7ab
PM		 158 .pio_mask = ATA_PIO4,
159 .udma_mask = ATA_UDMA6,
160 .port_ops = &ahci_ops,
161 },
f2b70a26
NC		 162 [board_ahci_pcs_quirk] = {
163 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK),
66a7cbc3
TH		 164 .flags = AHCI_FLAG_COMMON,
165 .pio_mask = ATA_PIO4,
166 .udma_mask = ATA_UDMA6,
167 .port_ops = &ahci_ops,
168 },
bf6f1581
NC		 169 [board_ahci_pcs_quirk_no_devslp] = {
170 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK |
171 AHCI_HFLAG_NO_DEVSLP),
67809f85
LK		 172 .flags = AHCI_FLAG_COMMON,
173 .pio_mask = ATA_PIO4,
174 .udma_mask = ATA_UDMA6,
175 .port_ops = &ahci_ops,
176 },
f2b70a26
NC		 177 [board_ahci_pcs_quirk_no_sntf] = {
178 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK |
179 AHCI_HFLAG_NO_SNTF),
417a1a6d 180 .flags = AHCI_FLAG_COMMON,
14bdef98 181 .pio_mask = ATA_PIO4,
469248ab 182 .udma_mask = ATA_UDMA6,
41669553
TH		 183 .port_ops = &ahci_ops,
184 },
facb8fa6 185 [board_ahci_yes_fbs] = {
5f173107
TH		 186 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_ops,
191 },
0507c777
HC		 192 [board_ahci_yes_fbs_atapi_dma] = {
193 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS |
194 AHCI_HFLAG_ATAPI_DMA_QUIRK),
195 .flags = AHCI_FLAG_COMMON,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_ops,
199 },
441577ef 200 /* by chipsets */
7d523bdc
HH		 201 [board_ahci_al] = {
202 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
203 .flags = AHCI_FLAG_COMMON,
204 .pio_mask = ATA_PIO4,
205 .udma_mask = ATA_UDMA6,
206 .port_ops = &ahci_ops,
207 },
dbfe8ef5 208 [board_ahci_avn] = {
7edbb605 209 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK),
dbfe8ef5
DW		 210 .flags = AHCI_FLAG_COMMON,
211 .pio_mask = ATA_PIO4,
212 .udma_mask = ATA_UDMA6,
213 .port_ops = &ahci_avn_ops,
214 },
facb8fa6 215 [board_ahci_mcp65] = {
83f2b963
TH		 216 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
217 AHCI_HFLAG_YES_NCQ),
ae01b249 218 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 219 .pio_mask = ATA_PIO4,
220 .udma_mask = ATA_UDMA6,
221 .port_ops = &ahci_ops,
222 },
facb8fa6 223 [board_ahci_mcp77] = {
83f2b963
TH		 224 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
225 .flags = AHCI_FLAG_COMMON,
226 .pio_mask = ATA_PIO4,
227 .udma_mask = ATA_UDMA6,
228 .port_ops = &ahci_ops,
229 },
facb8fa6 230 [board_ahci_mcp89] = {
83f2b963 231 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 232 .flags = AHCI_FLAG_COMMON,
14bdef98 233 .pio_mask = ATA_PIO4,
469248ab 234 .udma_mask = ATA_UDMA6,
441577ef 235 .port_ops = &ahci_ops,
55a61604 236 },
facb8fa6 237 [board_ahci_mv] = {
417a1a6d 238 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 239 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 240 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 241 .pio_mask = ATA_PIO4,
cd70c266
JG		 242 .udma_mask = ATA_UDMA6,
243 .port_ops = &ahci_ops,
244 },
facb8fa6 245 [board_ahci_sb600] = {
441577ef
TH		 246 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
247 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
248 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 249 .flags = AHCI_FLAG_COMMON,
14bdef98 250 .pio_mask = ATA_PIO4,
e39fc8c9 251 .udma_mask = ATA_UDMA6,
345347c5 252 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 253 },
facb8fa6 254 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 255 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 256 .flags = AHCI_FLAG_COMMON,
257 .pio_mask = ATA_PIO4,
258 .udma_mask = ATA_UDMA6,
345347c5 259 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 260 },
facb8fa6 261 [board_ahci_vt8251] = {
441577ef 262 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 263 .flags = AHCI_FLAG_COMMON,
264 .pio_mask = ATA_PIO4,
265 .udma_mask = ATA_UDMA6,
441577ef 266 .port_ops = &ahci_vt8251_ops,
1b677afd 267 },
1da177e4
LT		 268};
269
3b7d697d 270static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 271 /* Intel */
7edbb605
NC		 272 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci_pcs_quirk }, /* Comet Lake PCH-H RAID */
273 { PCI_VDEVICE(INTEL, 0x2652), board_ahci_pcs_quirk }, /* ICH6 */
274 { PCI_VDEVICE(INTEL, 0x2653), board_ahci_pcs_quirk }, /* ICH6M */
275 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci_pcs_quirk }, /* ICH7 */
276 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci_pcs_quirk }, /* ICH7M */
277 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci_pcs_quirk }, /* ICH7R */
82490c09 278 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
7edbb605
NC		 279 { PCI_VDEVICE(INTEL, 0x2681), board_ahci_pcs_quirk }, /* ESB2 */
280 { PCI_VDEVICE(INTEL, 0x2682), board_ahci_pcs_quirk }, /* ESB2 */
281 { PCI_VDEVICE(INTEL, 0x2683), board_ahci_pcs_quirk }, /* ESB2 */
282 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci_pcs_quirk }, /* ICH7-M DH */
283 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pcs_quirk }, /* ICH8 */
f2b70a26 284 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pcs_quirk_no_sntf }, /* ICH8/Lewisburg RAID*/
7edbb605
NC		 285 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pcs_quirk }, /* ICH8 */
286 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pcs_quirk }, /* ICH8M */
287 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pcs_quirk }, /* ICH8M */
288 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pcs_quirk }, /* ICH9 */
289 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pcs_quirk }, /* ICH9 */
290 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pcs_quirk }, /* ICH9 */
291 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pcs_quirk }, /* ICH9 */
292 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pcs_quirk }, /* ICH9 */
293 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pcs_quirk }, /* ICH9M */
294 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pcs_quirk }, /* ICH9M */
295 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pcs_quirk }, /* ICH9M */
296 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pcs_quirk }, /* ICH9M */
297 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pcs_quirk }, /* ICH9M */
298 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pcs_quirk }, /* ICH9 */
299 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pcs_quirk }, /* ICH9M */
300 { PCI_VDEVICE(INTEL, 0x502a), board_ahci_pcs_quirk }, /* Tolapai */
301 { PCI_VDEVICE(INTEL, 0x502b), board_ahci_pcs_quirk }, /* Tolapai */
302 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci_pcs_quirk }, /* ICH10 */
303 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci_pcs_quirk }, /* ICH10 */
304 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci_pcs_quirk }, /* ICH10 */
305 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci_pcs_quirk }, /* PCH AHCI */
306 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci_pcs_quirk }, /* PCH AHCI */
307 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci_pcs_quirk }, /* PCH RAID */
308 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci_pcs_quirk }, /* PCH RAID */
309 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_pcs_quirk }, /* PCH M AHCI */
310 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci_pcs_quirk }, /* PCH RAID */
311 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_pcs_quirk }, /* PCH M RAID */
312 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci_pcs_quirk }, /* PCH AHCI */
313 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
314 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
315 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
316 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
317 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
318 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
319 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
320 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
321 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
322 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
323 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
324 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
325 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
326 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
327 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
328 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
329 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
330 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
331 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
332 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
333 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci_pcs_quirk }, /* CPT AHCI */
334 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_pcs_quirk }, /* CPT M AHCI */
335 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci_pcs_quirk }, /* CPT RAID */
336 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_pcs_quirk }, /* CPT M RAID */
337 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci_pcs_quirk }, /* CPT RAID */
338 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci_pcs_quirk }, /* CPT RAID */
339 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci_pcs_quirk }, /* PBG AHCI */
340 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci_pcs_quirk }, /* PBG RAID */
341 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci_pcs_quirk }, /* PBG RAID */
342 { PCI_VDEVICE(INTEL, 0x2323), board_ahci_pcs_quirk }, /* DH89xxCC AHCI */
343 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci_pcs_quirk }, /* Panther Point AHCI */
344 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_pcs_quirk }, /* Panther M AHCI */
345 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci_pcs_quirk }, /* Panther Point RAID */
346 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci_pcs_quirk }, /* Panther Point RAID */
347 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci_pcs_quirk }, /* Panther Point RAID */
348 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_pcs_quirk }, /* Panther M RAID */
349 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci_pcs_quirk }, /* Panther Point RAID */
350 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci_pcs_quirk }, /* Lynx Point AHCI */
351 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_pcs_quirk }, /* Lynx M AHCI */
352 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci_pcs_quirk }, /* Lynx Point RAID */
353 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_pcs_quirk }, /* Lynx M RAID */
354 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci_pcs_quirk }, /* Lynx Point RAID */
355 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_pcs_quirk }, /* Lynx M RAID */
356 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci_pcs_quirk }, /* Lynx Point RAID */
357 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_pcs_quirk }, /* Lynx M RAID */
358 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_pcs_quirk }, /* Lynx LP AHCI */
359 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_pcs_quirk }, /* Lynx LP AHCI */
360 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_pcs_quirk }, /* Lynx LP RAID */
361 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_pcs_quirk }, /* Lynx LP RAID */
362 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_pcs_quirk }, /* Lynx LP RAID */
363 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_pcs_quirk }, /* Lynx LP RAID */
364 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_pcs_quirk }, /* Lynx LP RAID */
365 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_pcs_quirk }, /* Lynx LP RAID */
366 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_pcs_quirk }, /* Cannon Lake PCH-LP AHCI */
367 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci_pcs_quirk }, /* Avoton AHCI */
368 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci_pcs_quirk }, /* Avoton AHCI */
369 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci_pcs_quirk }, /* Avoton RAID */
370 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci_pcs_quirk }, /* Avoton RAID */
371 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci_pcs_quirk }, /* Avoton RAID */
372 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci_pcs_quirk }, /* Avoton RAID */
373 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci_pcs_quirk }, /* Avoton RAID */
374 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci_pcs_quirk }, /* Avoton RAID */
dbfe8ef5
DW		 375 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
376 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
377 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
378 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
379 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
380 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
381 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
382 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
7edbb605
NC		 383 { PCI_VDEVICE(INTEL, 0x2823), board_ahci_pcs_quirk }, /* Wellsburg/Lewisburg AHCI*/
384 { PCI_VDEVICE(INTEL, 0x2826), board_ahci_pcs_quirk }, /* *burg SATA0 'RAID' */
385 { PCI_VDEVICE(INTEL, 0x2827), board_ahci_pcs_quirk }, /* *burg SATA1 'RAID' */
386 { PCI_VDEVICE(INTEL, 0x282f), board_ahci_pcs_quirk }, /* *burg SATA2 'RAID' */
387 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */
388 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */
389 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */
390 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */
391 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci_pcs_quirk }, /* Wellsburg AHCI */
392 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci_pcs_quirk }, /* Wellsburg RAID */
393 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci_pcs_quirk }, /* Wellsburg RAID */
394 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci_pcs_quirk }, /* Wellsburg RAID */
395 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci_pcs_quirk }, /* Wellsburg AHCI */
396 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci_pcs_quirk }, /* Wellsburg RAID */
397 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci_pcs_quirk }, /* Wellsburg RAID */
398 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci_pcs_quirk }, /* Wellsburg RAID */
399 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci_pcs_quirk }, /* Coleto Creek AHCI */
400 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_pcs_quirk }, /* Wildcat LP AHCI */
401 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_pcs_quirk }, /* Wildcat LP RAID */
402 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_pcs_quirk }, /* Wildcat LP RAID */
403 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_pcs_quirk }, /* Wildcat LP RAID */
404 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci_pcs_quirk }, /* 9 Series AHCI */
405 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_pcs_quirk }, /* 9 Series M AHCI */
406 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci_pcs_quirk }, /* 9 Series RAID */
407 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_pcs_quirk }, /* 9 Series M RAID */
408 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci_pcs_quirk }, /* 9 Series RAID */
409 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_pcs_quirk }, /* 9 Series M RAID */
410 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci_pcs_quirk }, /* 9 Series RAID */
411 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_pcs_quirk }, /* 9 Series M RAID */
412 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_pcs_quirk }, /* Sunrise LP AHCI */
413 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_pcs_quirk }, /* Sunrise LP RAID */
414 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_pcs_quirk }, /* Sunrise LP RAID */
415 { PCI_VDEVICE(INTEL, 0xa102), board_ahci_pcs_quirk }, /* Sunrise Point-H AHCI */
416 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_pcs_quirk }, /* Sunrise M AHCI */
417 { PCI_VDEVICE(INTEL, 0xa105), board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */
418 { PCI_VDEVICE(INTEL, 0xa106), board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */
419 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_pcs_quirk }, /* Sunrise M RAID */
420 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */
421 { PCI_VDEVICE(INTEL, 0xa182), board_ahci_pcs_quirk }, /* Lewisburg AHCI*/
422 { PCI_VDEVICE(INTEL, 0xa186), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
423 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
424 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
425 { PCI_VDEVICE(INTEL, 0xa202), board_ahci_pcs_quirk }, /* Lewisburg AHCI*/
426 { PCI_VDEVICE(INTEL, 0xa206), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
427 { PCI_VDEVICE(INTEL, 0xa252), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
428 { PCI_VDEVICE(INTEL, 0xa256), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
429 { PCI_VDEVICE(INTEL, 0xa356), board_ahci_pcs_quirk }, /* Cannon Lake PCH-H RAID */
430 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci_pcs_quirk }, /* Comet Lake-H RAID */
431 { PCI_VDEVICE(INTEL, 0xa386), board_ahci_pcs_quirk }, /* Comet Lake PCH-V RAID */
432 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_pcs_quirk }, /* Bay Trail AHCI */
bf6f1581 433 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_pcs_quirk_no_devslp }, /* Bay Trail AHCI */
7edbb605
NC		 434 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_pcs_quirk }, /* Cherry Tr. AHCI */
435 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_pcs_quirk }, /* ApolloLake AHCI */
436 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_pcs_quirk }, /* Ice Lake LP AHCI */
437 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_pcs_quirk }, /* Comet Lake PCH-U AHCI */
438 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_pcs_quirk }, /* Comet Lake PCH RAID */
2a2df98e 439 /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */
7edbb605 440 { PCI_VDEVICE(INTEL, 0x4b63), board_ahci_pcs_quirk }, /* Elkhart Lake AHCI */
fe7fa31a 441
e34bb370
TH		 442 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
443 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
444 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
1fefb8fd
BH		 445 /* JMicron 362B and 362C have an AHCI function with IDE class code */
446 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
447 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
91f15fb3 448 /* May need to update quirk_jmicron_async_suspend() for additions */
fe7fa31a
JG		 449
450 /* ATI */
c65ec1c2 451 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 452 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
453 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
454 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
455 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
456 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
457 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 458
7d523bdc
HH		 459 /* Amazon's Annapurna Labs support */
460 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
461 .class = PCI_CLASS_STORAGE_SATA_AHCI,
462 .class_mask = 0xffffff,
463 board_ahci_al },
e2dd90b1 464 /* AMD */
5deab536 465 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
a17ab7ab 466 { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
fafe5c3d 467 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
7627a0ed 468 { PCI_VDEVICE(AMD, 0x7901), board_ahci }, /* AMD Green Sardine */
e2dd90b1
SH		 469 /* AMD is using RAID class only for ahci controllers */
470 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
471 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
9c54cd10
CR		 472
473 /* Dell S140/S150 */
474 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
7edbb605 475 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci_pcs_quirk },
e2dd90b1 476
fe7fa31a 477 /* VIA */
54bb3a94 478 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 479 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 480
481 /* NVIDIA */
e297d99e
TH		 482 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
483 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
484 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
485 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
486 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
487 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
488 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
489 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 490 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
491 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
492 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
493 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
494 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
495 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
496 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
497 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
498 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
499 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
500 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
501 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
502 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
503 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
504 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
505 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
506 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
507 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
508 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
509 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
510 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
511 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
512 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
513 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
514 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
515 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
516 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
517 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
518 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
519 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
520 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
521 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
522 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
523 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
524 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
525 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
526 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
527 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
528 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
529 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
530 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
531 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
532 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
533 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
534 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
535 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
536 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
537 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
538 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
539 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
540 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
541 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
542 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
543 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
544 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
545 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
546 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
547 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
548 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
549 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
550 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
551 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
552 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
553 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
554 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
555 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
556 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
557 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
558 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
559 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
560 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
561 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
562 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
563 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
564 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
565 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 566
95916edd 567 /* SiS */
20e2de4a
TH		 568 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
569 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
570 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 571
318893e1
AR		 572 /* ST Microelectronics */
573 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
574
cd70c266
JG		 575 /* Marvell */
576 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 577 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
69fd3157 578 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
10aca06c
AH		 579 .class = PCI_CLASS_STORAGE_SATA_AHCI,
580 .class_mask = 0xffffff,
5f173107 581 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
69fd3157 582 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
467b41c6 583 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
e098f5cb
SG		 584 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
585 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
586 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
69fd3157 587 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
642d8925 588 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
fcce9a35 589 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
c5edfff9
MK		 590 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
591 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
fcce9a35 592 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
69fd3157 593 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
17c60c6b 594 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
754a292f
AS		 595 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
596 .driver_data = board_ahci_yes_fbs },
a40cf3f3
JT		 597 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
598 .driver_data = board_ahci_yes_fbs },
69fd3157 599 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
50be5e36 600 .driver_data = board_ahci_yes_fbs },
885251dc 601 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9215),
0507c777 602 .driver_data = board_ahci_yes_fbs_atapi_dma },
6d5278a6
SB		 603 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
604 .driver_data = board_ahci_yes_fbs },
f4a8d4f2
PM		 605 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235),
606 .driver_data = board_ahci_no_debounce_delay },
28b2182d
HG		 607 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
608 .driver_data = board_ahci_yes_fbs },
609 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
d2518365 610 .driver_data = board_ahci_yes_fbs },
cd70c266 611
c77a036b
MN		 612 /* Promise */
613 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
b32bfc06 614 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
c77a036b 615
20730e9b 616 /* ASMedia */
51af8f25
LB		 617 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci_43bit_dma }, /* ASM1060 */
618 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci_43bit_dma }, /* ASM1060 */
20730e9b
LB		 619 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci_43bit_dma }, /* ASM1061 */
620 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci_43bit_dma }, /* ASM1061/1062 */
51af8f25
LB		 621 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci_43bit_dma }, /* ASM1061R */
622 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci_43bit_dma }, /* ASM1062R */
623 { PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci_43bit_dma }, /* ASM1062+JMB575 */
3bf61410
SC		 624 { PCI_VDEVICE(ASMEDIA, 0x1062), board_ahci }, /* ASM1062A */
625 { PCI_VDEVICE(ASMEDIA, 0x1064), board_ahci }, /* ASM1064 */
626 { PCI_VDEVICE(ASMEDIA, 0x1164), board_ahci }, /* ASM1164 */
627 { PCI_VDEVICE(ASMEDIA, 0x1165), board_ahci }, /* ASM1165 */
628 { PCI_VDEVICE(ASMEDIA, 0x1166), board_ahci }, /* ASM1166 */
c9703765 629
67809f85 630 /*
66a7cbc3
TH		 631 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
632 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
67809f85 633 */
87312151
NC		 634 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_no_msi },
635 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_no_msi },
67809f85 636
7f9c9f8e
HD		 637 /* Enmotus */
638 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
639
e49bd683
TY		 640 /* Loongson */
641 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
642
415ae2b5
JG		 643 /* Generic, PCI class code for AHCI */
644 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 645 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 646
1da177e4
LT		 647 { } /* terminate list */
648};
649
f1d848f9
MW		 650static const struct dev_pm_ops ahci_pci_pm_ops = {
651 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
02e53293
MW		 652 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
653 ahci_pci_device_runtime_resume, NULL)
f1d848f9 654};
1da177e4
LT		 655
656static struct pci_driver ahci_pci_driver = {
657 .name = DRV_NAME,
658 .id_table = ahci_pci_tbl,
659 .probe = ahci_init_one,
02e53293 660 .remove = ahci_remove_one,
10a663a1 661 .shutdown = ahci_shutdown_one,
f1d848f9
MW		 662 .driver = {
663 .pm = &ahci_pci_pm_ops,
664 },
365cfa1e 665};
1da177e4 666
5219d653 667#if IS_ENABLED(CONFIG_PATA_MARVELL)
365cfa1e
AV		 668static int marvell_enable;
669#else
670static int marvell_enable = 1;
671#endif
672module_param(marvell_enable, int, 0644);
673MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 674
b1a9585c 675static int mobile_lpm_policy = -1;
ebb82e3c
HG		 676module_param(mobile_lpm_policy, int, 0644);
677MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
1da177e4 678
24cfd864
DLM		 679static char *ahci_mask_port_map;
680module_param_named(mask_port_map, ahci_mask_port_map, charp, 0444);
681MODULE_PARM_DESC(mask_port_map,
682 "32-bits port map masks to ignore controllers ports. "
683 "Valid values are: "
684 "\"<mask>\" to apply the same mask to all AHCI controller "
685 "devices, and \"<pci_dev>=<mask>,<pci_dev>=<mask>,...\" to "
686 "specify different masks for the controllers specified, "
687 "where <pci_dev> is the PCI ID of an AHCI controller in the "
688 "form \"domain:bus:dev.func\"");
689
690static void ahci_apply_port_map_mask(struct device *dev,
691 struct ahci_host_priv *hpriv, char *mask_s)
692{
693 unsigned int mask;
694
695 if (kstrtouint(mask_s, 0, &mask)) {
696 dev_err(dev, "Invalid port map mask\n");
697 return;
698 }
699
700 hpriv->mask_port_map = mask;
701}
702
703static void ahci_get_port_map_mask(struct device *dev,
704 struct ahci_host_priv *hpriv)
705{
706 char *param, *end, *str, *mask_s;
707 char *name;
708
709 if (!strlen(ahci_mask_port_map))
710 return;
711
712 str = kstrdup(ahci_mask_port_map, GFP_KERNEL);
713 if (!str)
714 return;
715
716 /* Handle single mask case */
717 if (!strchr(str, '=')) {
718 ahci_apply_port_map_mask(dev, hpriv, str);
719 goto free;
720 }
721
722 /*
723 * Mask list case: parse the parameter to apply the mask only if
724 * the device name matches.
725 */
726 param = str;
727 end = param + strlen(param);
728 while (param && param < end && *param) {
729 name = param;
730 param = strchr(name, '=');
731 if (!param)
732 break;
733
734 *param = '\0';
735 param++;
736 if (param >= end)
737 break;
738
739 if (strcmp(dev_name(dev), name) != 0) {
740 param = strchr(param, ',');
741 if (param)
742 param++;
743 continue;
744 }
745
746 mask_s = param;
747 param = strchr(mask_s, ',');
748 if (param) {
749 *param = '\0';
750 param++;
751 }
752
753 ahci_apply_port_map_mask(dev, hpriv, mask_s);
754 }
755
756free:
757 kfree(str);
758}
759
365cfa1e
AV		 760static void ahci_pci_save_initial_config(struct pci_dev *pdev,
761 struct ahci_host_priv *hpriv)
762{
365cfa1e
AV		 763 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
764 dev_info(&pdev->dev, "JMB361 has only one port\n");
88589772 765 hpriv->saved_port_map = 1;
1da177e4
LT		 766 }
767
365cfa1e
AV		 768 /*
769 * Temporary Marvell 6145 hack: PATA port presence
770 * is asserted through the standard AHCI port
771 * presence register, as bit 4 (counting from 0)
d28f87aa 772 */
365cfa1e
AV		 773 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
774 if (pdev->device == 0x6121)
9a23c1d6 775 hpriv->mask_port_map = 0x3;
365cfa1e 776 else
9a23c1d6 777 hpriv->mask_port_map = 0xf;
365cfa1e
AV		 778 dev_info(&pdev->dev,
779 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
780 }
1da177e4 781
24cfd864
DLM		 782 /* Handle port map masks passed as module parameter. */
783 if (ahci_mask_port_map)
784 ahci_get_port_map_mask(&pdev->dev, hpriv);
785
725c7b57 786 ahci_save_initial_config(&pdev->dev, hpriv);
1da177e4
LT		 787}
788
37e14e4f
AV		 789static int ahci_pci_reset_controller(struct ata_host *host)
790{
791 struct pci_dev *pdev = to_pci_dev(host->dev);
792 struct ahci_host_priv *hpriv = host->private_data;
793 int rc;
794
795 rc = ahci_reset_controller(host);
796 if (rc)
797 return rc;
798
799 /*
800 * If platform firmware failed to enable ports, try to enable
801 * them here.
802 */
803 ahci_intel_pcs_quirk(pdev, hpriv);
804
805 return 0;
806}
807
365cfa1e 808static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 809{
365cfa1e
AV		 810 struct ahci_host_priv *hpriv = host->private_data;
811 struct pci_dev *pdev = to_pci_dev(host->dev);
812 void __iomem *port_mmio;
78cd52d0 813 u32 tmp;
365cfa1e 814 int mv;
78cd52d0 815
365cfa1e
AV		 816 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
817 if (pdev->device == 0x6121)
818 mv = 2;
819 else
820 mv = 4;
7cbbfbe0 821 port_mmio = __ahci_port_base(hpriv, mv);
78cd52d0 822
365cfa1e 823 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 824
365cfa1e
AV		 825 /* clear port IRQ */
826 tmp = readl(port_mmio + PORT_IRQ_STAT);
93c77114 827 dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
365cfa1e
AV		 828 if (tmp)
829 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 830 }
831
365cfa1e 832 ahci_init_controller(host);
edc93052
TH		 833}
834
365cfa1e
AV		 835static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
836 unsigned long deadline)
d6ef3153 837{
365cfa1e 838 struct ata_port *ap = link->ap;
039ece38 839 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 840 bool online;
d6ef3153
SH		 841 int rc;
842
fa89f53b 843 hpriv->stop_engine(ap);
d6ef3153 844
365cfa1e
AV		 845 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
846 deadline, &online, NULL);
d6ef3153 847
039ece38 848 hpriv->start_engine(ap);
d6ef3153 849
365cfa1e
AV		 850 /* vt8251 doesn't clear BSY on signature FIS reception,
851 * request follow-up softreset.
852 */
853 return online ? -EAGAIN : rc;
7d50b60b
TH		 854}
855
365cfa1e
AV		 856static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
857 unsigned long deadline)
7d50b60b 858{
365cfa1e 859 struct ata_port *ap = link->ap;
1c954a4d 860 struct ahci_port_priv *pp = ap->private_data;
039ece38 861 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 862 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
863 struct ata_taskfile tf;
864 bool online;
865 int rc;
7d50b60b 866
fa89f53b 867 hpriv->stop_engine(ap);
028a2596 868
365cfa1e
AV		 869 /* clear D2H reception area to properly wait for D2H FIS */
870 ata_tf_init(link->device, &tf);
efcef265 871 tf.status = ATA_BUSY;
365cfa1e 872 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 873
365cfa1e
AV		 874 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
875 deadline, &online, NULL);
028a2596 876
039ece38 877 hpriv->start_engine(ap);
c1332875 878
365cfa1e
AV		 879 /* The pseudo configuration device on SIMG4726 attached to
880 * ASUS P5W-DH Deluxe doesn't send signature FIS after
881 * hardreset if no device is attached to the first downstream
882 * port && the pseudo device locks up on SRST w/ PMP==0. To
883 * work around this, wait for !BSY only briefly. If BSY isn't
884 * cleared, perform CLO and proceed to IDENTIFY (achieved by
885 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
886 *
887 * Wait for two seconds. Devices attached to downstream port
888 * which can't process the following IDENTIFY after this will
889 * have to be reset again. For most cases, this should
890 * suffice while making probing snappish enough.
891 */
892 if (online) {
893 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
894 ahci_check_ready);
895 if (rc)
896 ahci_kick_engine(ap);
c1332875 897 }
c1332875
TH		 898 return rc;
899}
900
dbfe8ef5
DW		 901/*
902 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
903 *
904 * It has been observed with some SSDs that the timing of events in the
905 * link synchronization phase can leave the port in a state that can not
906 * be recovered by a SATA-hard-reset alone. The failing signature is
907 * SStatus.DET stuck at 1 ("Device presence detected but Phy
908 * communication not established"). It was found that unloading and
909 * reloading the driver when this problem occurs allows the drive
910 * connection to be recovered (DET advanced to 0x3). The critical
911 * component of reloading the driver is that the port state machines are
912 * reset by bouncing "port enable" in the AHCI PCS configuration
913 * register. So, reproduce that effect by bouncing a port whenever we
914 * see DET==1 after a reset.
915 */
916static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
917 unsigned long deadline)
918{
d14d41cc 919 const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
dbfe8ef5
DW		 920 struct ata_port *ap = link->ap;
921 struct ahci_port_priv *pp = ap->private_data;
922 struct ahci_host_priv *hpriv = ap->host->private_data;
923 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
924 unsigned long tmo = deadline - jiffies;
925 struct ata_taskfile tf;
926 bool online;
927 int rc, i;
928
fa89f53b 929 hpriv->stop_engine(ap);
dbfe8ef5
DW		 930
931 for (i = 0; i < 2; i++) {
932 u16 val;
933 u32 sstatus;
934 int port = ap->port_no;
935 struct ata_host *host = ap->host;
936 struct pci_dev *pdev = to_pci_dev(host->dev);
937
938 /* clear D2H reception area to properly wait for D2H FIS */
939 ata_tf_init(link->device, &tf);
efcef265 940 tf.status = ATA_BUSY;
dbfe8ef5
DW		 941 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
942
943 rc = sata_link_hardreset(link, timing, deadline, &online,
944 ahci_check_ready);
945
946 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
947 (sstatus & 0xf) != 1)
948 break;
949
e276c9bd 950 ata_link_info(link, "avn bounce port%d\n", port);
dbfe8ef5
DW		 951
952 pci_read_config_word(pdev, 0x92, &val);
953 val &= ~(1 << port);
954 pci_write_config_word(pdev, 0x92, val);
955 ata_msleep(ap, 1000);
956 val |= 1 << port;
957 pci_write_config_word(pdev, 0x92, val);
958 deadline += tmo;
959 }
960
961 hpriv->start_engine(ap);
962
963 if (online)
964 *class = ahci_dev_classify(ap);
965
dbfe8ef5
DW		 966 return rc;
967}
968
969
02e53293
MW		 970#ifdef CONFIG_PM
971static void ahci_pci_disable_interrupts(struct ata_host *host)
c1332875 972{
9b10ae86 973 struct ahci_host_priv *hpriv = host->private_data;
d8993349 974 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 975 u32 ctl;
976
f1d848f9
MW		 977 /* AHCI spec rev1.1 section 8.3.3:
978 * Software must disable interrupts prior to requesting a
979 * transition of the HBA to D3 state.
980 */
981 ctl = readl(mmio + HOST_CTL);
982 ctl &= ~HOST_IRQ_EN;
983 writel(ctl, mmio + HOST_CTL);
984 readl(mmio + HOST_CTL); /* flush */
02e53293
MW		 985}
986
987static int ahci_pci_device_runtime_suspend(struct device *dev)
988{
989 struct pci_dev *pdev = to_pci_dev(dev);
990 struct ata_host *host = pci_get_drvdata(pdev);
c1332875 991
02e53293
MW		 992 ahci_pci_disable_interrupts(host);
993 return 0;
994}
995
996static int ahci_pci_device_runtime_resume(struct device *dev)
997{
998 struct pci_dev *pdev = to_pci_dev(dev);
999 struct ata_host *host = pci_get_drvdata(pdev);
1000 int rc;
1001
37e14e4f 1002 rc = ahci_pci_reset_controller(host);
02e53293
MW		 1003 if (rc)
1004 return rc;
1005 ahci_pci_init_controller(host);
1006 return 0;
1007}
1008
1009#ifdef CONFIG_PM_SLEEP
1010static int ahci_pci_device_suspend(struct device *dev)
1011{
1012 struct pci_dev *pdev = to_pci_dev(dev);
1013 struct ata_host *host = pci_get_drvdata(pdev);
1014 struct ahci_host_priv *hpriv = host->private_data;
1015
1016 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
1017 dev_err(&pdev->dev,
1018 "BIOS update required for suspend/resume\n");
1019 return -EIO;
1020 }
1021
1022 ahci_pci_disable_interrupts(host);
ec87cf37
SS		 1023 ata_host_suspend(host, PMSG_SUSPEND);
1024 return 0;
c1332875
TH		 1025}
1026
f1d848f9 1027static int ahci_pci_device_resume(struct device *dev)
c1332875 1028{
f1d848f9 1029 struct pci_dev *pdev = to_pci_dev(dev);
0a86e1c8 1030 struct ata_host *host = pci_get_drvdata(pdev);
c1332875
TH		 1031 int rc;
1032
cb85696d
JL		 1033 /* Apple BIOS helpfully mangles the registers on resume */
1034 if (is_mcp89_apple(pdev))
1035 ahci_mcp89_apple_enable(pdev);
1036
c1332875 1037 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
37e14e4f 1038 rc = ahci_pci_reset_controller(host);
c1332875
TH		 1039 if (rc)
1040 return rc;
1041
781d6550 1042 ahci_pci_init_controller(host);
c1332875
TH		 1043 }
1044
cca3974e 1045 ata_host_resume(host);
c1332875
TH		 1046
1047 return 0;
1048}
438ac6d5 1049#endif
c1332875 1050
02e53293
MW		 1051#endif /* CONFIG_PM */
1052
20730e9b
LB		 1053static int ahci_configure_dma_masks(struct pci_dev *pdev,
1054 struct ahci_host_priv *hpriv)
1da177e4 1055{
20730e9b 1056 int dma_bits;
1da177e4 1057 int rc;
1da177e4 1058
20730e9b
LB		 1059 if (hpriv->cap & HOST_CAP_64) {
1060 dma_bits = 64;
1061 if (hpriv->flags & AHCI_HFLAG_43BIT_ONLY)
1062 dma_bits = 43;
1063 } else {
1064 dma_bits = 32;
1065 }
1066
318893e1
AR		 1067 /*
1068 * If the device fixup already set the dma_mask to some non-standard
1069 * value, don't extend it here. This happens on STA2X11, for example.
b1716871
CH		 1070 *
1071 * XXX: manipulating the DMA mask from platform code is completely
a7ba70f1 1072 * bogus, platform code should use dev->bus_dma_limit instead..
318893e1
AR		 1073 */
1074 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
1075 return 0;
1076
b1716871
CH		 1077 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
1078 if (rc)
1079 dev_err(&pdev->dev, "DMA enable failed\n");
1080 return rc;
1da177e4
LT		 1081}
1082
439fcaec
AV		 1083static void ahci_pci_print_info(struct ata_host *host)
1084{
1085 struct pci_dev *pdev = to_pci_dev(host->dev);
1086 u16 cc;
1087 const char *scc_s;
1088
1089 pci_read_config_word(pdev, 0x0a, &cc);
1090 if (cc == PCI_CLASS_STORAGE_IDE)
1091 scc_s = "IDE";
1092 else if (cc == PCI_CLASS_STORAGE_SATA)
1093 scc_s = "SATA";
1094 else if (cc == PCI_CLASS_STORAGE_RAID)
1095 scc_s = "RAID";
1096 else
1097 scc_s = "unknown";
1098
1099 ahci_print_info(host, scc_s);
1100}
1101
edc93052
TH		 1102/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
1103 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
1104 * support PMP and the 4726 either directly exports the device
1105 * attached to the first downstream port or acts as a hardware storage
1106 * controller and emulate a single ATA device (can be RAID 0/1 or some
1107 * other configuration).
1108 *
1109 * When there's no device attached to the first downstream port of the
1110 * 4726, "Config Disk" appears, which is a pseudo ATA device to
1111 * configure the 4726. However, ATA emulation of the device is very
1112 * lame. It doesn't send signature D2H Reg FIS after the initial
1113 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
1114 *
1115 * The following function works around the problem by always using
1116 * hardreset on the port and not depending on receiving signature FIS
1117 * afterward. If signature FIS isn't received soon, ATA class is
1118 * assumed without follow-up softreset.
1119 */
1120static void ahci_p5wdh_workaround(struct ata_host *host)
1121{
1bd06867 1122 static const struct dmi_system_id sysids[] = {
edc93052
TH		 1123 {
1124 .ident = "P5W DH Deluxe",
1125 .matches = {
1126 DMI_MATCH(DMI_SYS_VENDOR,
1127 "ASUSTEK COMPUTER INC"),
1128 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
1129 },
1130 },
1131 { }
1132 };
1133 struct pci_dev *pdev = to_pci_dev(host->dev);
1134
1135 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
1136 dmi_check_system(sysids)) {
1137 struct ata_port *ap = host->ports[1];
1138
a44fec1f
JP		 1139 dev_info(&pdev->dev,
1140 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 1141
1142 ap->ops = &ahci_p5wdh_ops;
1143 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1144 }
1145}
1146
cb85696d
JL		 1147/*
1148 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1149 * booting in BIOS compatibility mode. We restore the registers but not ID.
1150 */
1151static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1152{
1153 u32 val;
1154
1155 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1156
1157 pci_read_config_dword(pdev, 0xf8, &val);
1158 val |= 1 << 0x1b;
1159 /* the following changes the device ID, but appears not to affect function */
1160 /* val = (val & ~0xf0000000) | 0x80000000; */
1161 pci_write_config_dword(pdev, 0xf8, val);
1162
1163 pci_read_config_dword(pdev, 0x54c, &val);
1164 val |= 1 << 0xc;
1165 pci_write_config_dword(pdev, 0x54c, val);
1166
1167 pci_read_config_dword(pdev, 0x4a4, &val);
1168 val &= 0xff;
1169 val |= 0x01060100;
1170 pci_write_config_dword(pdev, 0x4a4, val);
1171
1172 pci_read_config_dword(pdev, 0x54c, &val);
1173 val &= ~(1 << 0xc);
1174 pci_write_config_dword(pdev, 0x54c, val);
1175
1176 pci_read_config_dword(pdev, 0xf8, &val);
1177 val &= ~(1 << 0x1b);
1178 pci_write_config_dword(pdev, 0xf8, val);
1179}
1180
1181static bool is_mcp89_apple(struct pci_dev *pdev)
1182{
1183 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1184 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1185 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1186 pdev->subsystem_device == 0xcb89;
1187}
1188
2fcad9d2
TH		 1189/* only some SB600 ahci controllers can do 64bit DMA */
1190static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 1191{
1192 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 1193 /*
1194 * The oldest version known to be broken is 0901 and
1195 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 1196 * Enable 64bit DMA on 1501 and anything newer.
1197 *
03d783bf
TH		 1198 * Please read bko#9412 for more info.
1199 */
58a09b38
SH		 1200 {
1201 .ident = "ASUS M2A-VM",
1202 .matches = {
1203 DMI_MATCH(DMI_BOARD_VENDOR,
1204 "ASUSTeK Computer INC."),
1205 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1206 },
03d783bf 1207 .driver_data = "20071026", /* yyyymmdd */
58a09b38 1208 },
e65cc194
MN		 1209 /*
1210 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1211 * support 64bit DMA.
1212 *
1213 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1214 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1215 * This spelling mistake was fixed in BIOS version 1.5, so
1216 * 1.5 and later have the Manufacturer as
1217 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1218 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1219 *
1220 * BIOS versions earlier than 1.9 had a Board Product Name
1221 * DMI field of "MS-7376". This was changed to be
1222 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1223 * match on DMI_BOARD_NAME of "MS-7376".
1224 */
1225 {
1226 .ident = "MSI K9A2 Platinum",
1227 .matches = {
1228 DMI_MATCH(DMI_BOARD_VENDOR,
1229 "MICRO-STAR INTER"),
1230 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1231 },
1232 },
ff0173c1
MN		 1233 /*
1234 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1235 * 64bit DMA.
1236 *
1237 * This board also had the typo mentioned above in the
1238 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1239 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1240 */
1241 {
1242 .ident = "MSI K9AGM2",
1243 .matches = {
1244 DMI_MATCH(DMI_BOARD_VENDOR,
1245 "MICRO-STAR INTER"),
1246 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1247 },
1248 },
3c4aa91f
MN		 1249 /*
1250 * All BIOS versions for the Asus M3A support 64bit DMA.
1251 * (all release versions from 0301 to 1206 were tested)
1252 */
1253 {
1254 .ident = "ASUS M3A",
1255 .matches = {
1256 DMI_MATCH(DMI_BOARD_VENDOR,
1257 "ASUSTeK Computer INC."),
1258 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1259 },
1260 },
58a09b38
SH		 1261 { }
1262 };
03d783bf 1263 const struct dmi_system_id *match;
2fcad9d2
TH		 1264 int year, month, date;
1265 char buf[9];
58a09b38 1266
03d783bf 1267 match = dmi_first_match(sysids);
58a09b38 1268 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 1269 !match)
58a09b38
SH		 1270 return false;
1271
e65cc194
MN		 1272 if (!match->driver_data)
1273 goto enable_64bit;
1274
2fcad9d2
TH		 1275 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1276 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 1277
e65cc194
MN		 1278 if (strcmp(buf, match->driver_data) >= 0)
1279 goto enable_64bit;
1280 else {
a44fec1f
JP		 1281 dev_warn(&pdev->dev,
1282 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1283 match->ident);
2fcad9d2
TH		 1284 return false;
1285 }
e65cc194
MN		 1286
1287enable_64bit:
a44fec1f 1288 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 1289 return true;
58a09b38
SH		 1290}
1291
1fd68434
RW		 1292static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1293{
1294 static const struct dmi_system_id broken_systems[] = {
1295 {
1296 .ident = "HP Compaq nx6310",
1297 .matches = {
1298 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1299 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1300 },
1301 /* PCI slot number of the controller */
1302 .driver_data = (void *)0x1FUL,
1303 },
d2f9c061
MR		 1304 {
1305 .ident = "HP Compaq 6720s",
1306 .matches = {
1307 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1308 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1309 },
1310 /* PCI slot number of the controller */
1311 .driver_data = (void *)0x1FUL,
1312 },
1fd68434
RW		 1313
1314 { } /* terminate list */
1315 };
1316 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1317
1318 if (dmi) {
1319 unsigned long slot = (unsigned long)dmi->driver_data;
1320 /* apply the quirk only to on-board controllers */
1321 return slot == PCI_SLOT(pdev->devfn);
1322 }
1323
1324 return false;
1325}
1326
9b10ae86
TH		 1327static bool ahci_broken_suspend(struct pci_dev *pdev)
1328{
1329 static const struct dmi_system_id sysids[] = {
1330 /*
1331 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1332 * to the harddisk doesn't become online after
1333 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 1334 *
1335 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1336 *
1337 * Use dates instead of versions to match as HP is
1338 * apparently recycling both product and version
1339 * strings.
1340 *
1341 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 1342 */
1343 {
1344 .ident = "dv4",
1345 .matches = {
1346 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1347 DMI_MATCH(DMI_PRODUCT_NAME,
1348 "HP Pavilion dv4 Notebook PC"),
1349 },
9deb3431 1350 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 1351 },
1352 {
1353 .ident = "dv5",
1354 .matches = {
1355 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1356 DMI_MATCH(DMI_PRODUCT_NAME,
1357 "HP Pavilion dv5 Notebook PC"),
1358 },
9deb3431 1359 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 1360 },
1361 {
1362 .ident = "dv6",
1363 .matches = {
1364 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1365 DMI_MATCH(DMI_PRODUCT_NAME,
1366 "HP Pavilion dv6 Notebook PC"),
1367 },
9deb3431 1368 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 1369 },
1370 {
1371 .ident = "HDX18",
1372 .matches = {
1373 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1374 DMI_MATCH(DMI_PRODUCT_NAME,
1375 "HP HDX18 Notebook PC"),
1376 },
9deb3431 1377 .driver_data = "20090430", /* F.23 */
9b10ae86 1378 },
cedc9bf9
TH		 1379 /*
1380 * Acer eMachines G725 has the same problem. BIOS
1381 * V1.03 is known to be broken. V3.04 is known to
25985edc 1382 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9 1383 * that we don't have much idea about. For now,
ca8040b0 1384 * assume that anything older than V3.04 is broken.
9deb3431
TH		 1385 *
1386 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 1387 */
1388 {
1389 .ident = "G725",
1390 .matches = {
1391 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1392 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1393 },
9deb3431 1394 .driver_data = "20091216", /* V3.04 */
cedc9bf9 1395 },
9b10ae86
TH		 1396 { } /* terminate list */
1397 };
1398 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 1399 int year, month, date;
1400 char buf[9];
9b10ae86
TH		 1401
1402 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1403 return false;
1404
9deb3431
TH		 1405 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1406 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 1407
9deb3431 1408 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 1409}
1410
240630e6
HG		 1411static bool ahci_broken_lpm(struct pci_dev *pdev)
1412{
b5acc362
NC		 1413 /*
1414 * Platforms with LPM problems.
1415 * If driver_data is NULL, there is no existing BIOS version with
1416 * functioning LPM.
1417 * If driver_data is non-NULL, then driver_data contains the DMI BIOS
1418 * build date of the first BIOS version with functioning LPM (i.e. older
1419 * BIOS versions have broken LPM).
1420 */
240630e6 1421 static const struct dmi_system_id sysids[] = {
240630e6
HG		 1422 {
1423 .matches = {
1424 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1425 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1426 },
1427 .driver_data = "20180406", /* 1.31 */
1428 },
1429 {
1430 .matches = {
1431 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1432 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1433 },
1434 .driver_data = "20180420", /* 1.28 */
1435 },
1436 {
1437 .matches = {
1438 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1439 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1440 },
1441 .driver_data = "20180315", /* 1.33 */
1442 },
1443 {
1444 .matches = {
1445 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1446 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1447 },
6f29d393 1448 .driver_data = "20180409", /* 2.35 */
240630e6 1449 },
b5acc362
NC		 1450 {
1451 .matches = {
1452 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
3e0809b1 1453 DMI_MATCH(DMI_PRODUCT_NAME, "ASUSPRO D840MB_M840SA"),
b5acc362 1454 },
a7b3b77f
MK		 1455 /* 320 is broken, there is no known good version. */
1456 },
1457 {
1458 /*
1459 * AMD 500 Series Chipset SATA Controller [1022:43eb]
1460 * on this motherboard timeouts on ports 5 and 6 when
1461 * LPM is enabled, at least with WDC WD20EFAX-68FB5N0
1462 * hard drives. LPM with the same drive works fine on
1463 * all other ports on the same controller.
1464 */
1465 .matches = {
1466 DMI_MATCH(DMI_BOARD_VENDOR,
1467 "ASUSTeK COMPUTER INC."),
1468 DMI_MATCH(DMI_BOARD_NAME,
1469 "ROG STRIX B550-F GAMING (WI-FI)"),
1470 },
1471 /* 3621 is broken, there is no known good version. */
b5acc362 1472 },
240630e6
HG		 1473 { } /* terminate list */
1474 };
1475 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1476 int year, month, date;
1477 char buf[9];
1478
1479 if (!dmi)
1480 return false;
1481
b5acc362
NC		 1482 if (!dmi->driver_data)
1483 return true;
1484
240630e6
HG		 1485 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1486 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1487
1488 return strcmp(buf, dmi->driver_data) < 0;
1489}
1490
5594639a
TH		 1491static bool ahci_broken_online(struct pci_dev *pdev)
1492{
1493#define ENCODE_BUSDEVFN(bus, slot, func) \
1494 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1495 static const struct dmi_system_id sysids[] = {
1496 /*
1497 * There are several gigabyte boards which use
1498 * SIMG5723s configured as hardware RAID. Certain
1499 * 5723 firmware revisions shipped there keep the link
1500 * online but fail to answer properly to SRST or
1501 * IDENTIFY when no device is attached downstream
1502 * causing libata to retry quite a few times leading
1503 * to excessive detection delay.
1504 *
1505 * As these firmwares respond to the second reset try
1506 * with invalid device signature, considering unknown
1507 * sig as offline works around the problem acceptably.
1508 */
1509 {
1510 .ident = "EP45-DQ6",
1511 .matches = {
1512 DMI_MATCH(DMI_BOARD_VENDOR,
1513 "Gigabyte Technology Co., Ltd."),
1514 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1515 },
1516 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1517 },
1518 {
1519 .ident = "EP45-DS5",
1520 .matches = {
1521 DMI_MATCH(DMI_BOARD_VENDOR,
1522 "Gigabyte Technology Co., Ltd."),
1523 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1524 },
1525 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1526 },
1527 { } /* terminate list */
1528 };
1529#undef ENCODE_BUSDEVFN
1530 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1531 unsigned int val;
1532
1533 if (!dmi)
1534 return false;
1535
1536 val = (unsigned long)dmi->driver_data;
1537
1538 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1539}
1540
8e513217 1541#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1542static void ahci_gtf_filter_workaround(struct ata_host *host)
1543{
1544 static const struct dmi_system_id sysids[] = {
1545 /*
1546 * Aspire 3810T issues a bunch of SATA enable commands
1547 * via _GTF including an invalid one and one which is
1548 * rejected by the device. Among the successful ones
1549 * is FPDMA non-zero offset enable which when enabled
1550 * only on the drive side leads to NCQ command
1551 * failures. Filter it out.
1552 */
1553 {
1554 .ident = "Aspire 3810T",
1555 .matches = {
1556 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1557 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1558 },
1559 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1560 },
1561 { }
1562 };
1563 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1564 unsigned int filter;
1565 int i;
1566
1567 if (!dmi)
1568 return;
1569
1570 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1571 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1572 filter, dmi->ident);
f80ae7e4
TH		 1573
1574 for (i = 0; i < host->n_ports; i++) {
1575 struct ata_port *ap = host->ports[i];
1576 struct ata_link *link;
1577 struct ata_device *dev;
1578
1579 ata_for_each_link(link, ap, EDGE)
1580 ata_for_each_dev(dev, link, ALL)
1581 dev->gtf_filter |= filter;
1582 }
1583}
8e513217
MT		 1584#else
1585static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1586{}
1587#endif
f80ae7e4 1588
8bfd1743
SC		 1589/*
1590 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1591 * as DUMMY, or detected but eventually get a "link down" and never get up
1592 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1593 * port_map may hold a value of 0x00.
1594 *
1595 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1596 * and can significantly reduce the occurrence of the problem.
1597 *
1598 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1599 */
1600static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1601 struct pci_dev *pdev)
1602{
1603 static const struct dmi_system_id sysids[] = {
1604 {
1605 .ident = "Acer Switch Alpha 12",
1606 .matches = {
1607 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1608 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1609 },
1610 },
1611 { }
1612 };
1613
1614 if (dmi_check_system(sysids)) {
1615 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1616 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1617 hpriv->port_map = 0x7;
1618 hpriv->cap = 0xC734FF02;
1619 }
1620 }
1621}
1622
d243bed3
TC		 1623#ifdef CONFIG_ARM64
1624/*
1625 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1626 * Workaround is to make sure all pending IRQs are served before leaving
1627 * handler.
1628 */
1629static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1630{
1631 struct ata_host *host = dev_instance;
1632 struct ahci_host_priv *hpriv;
1633 unsigned int rc = 0;
1634 void __iomem *mmio;
1635 u32 irq_stat, irq_masked;
1636 unsigned int handled = 1;
1637
d243bed3
TC		 1638 hpriv = host->private_data;
1639 mmio = hpriv->mmio;
1640 irq_stat = readl(mmio + HOST_IRQ_STAT);
1641 if (!irq_stat)
1642 return IRQ_NONE;
1643
1644 do {
1645 irq_masked = irq_stat & hpriv->port_map;
1646 spin_lock(&host->lock);
1647 rc = ahci_handle_port_intr(host, irq_masked);
1648 if (!rc)
1649 handled = 0;
1650 writel(irq_stat, mmio + HOST_IRQ_STAT);
1651 irq_stat = readl(mmio + HOST_IRQ_STAT);
1652 spin_unlock(&host->lock);
1653 } while (irq_stat);
d243bed3
TC		 1654
1655 return IRQ_RETVAL(handled);
1656}
1657#endif
1658
aecec8b6
CH		 1659static void ahci_remap_check(struct pci_dev *pdev, int bar,
1660 struct ahci_host_priv *hpriv)
1661{
894fba7f 1662 int i;
aecec8b6
CH		 1663 u32 cap;
1664
1665 /*
1666 * Check if this device might have remapped nvme devices.
1667 */
1668 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1669 pci_resource_len(pdev, bar) < SZ_512K ||
1670 bar != AHCI_PCI_BAR_STANDARD ||
1671 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1672 return;
1673
1674 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1675 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1676 if ((cap & (1 << i)) == 0)
1677 continue;
1678 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1679 != PCI_CLASS_STORAGE_EXPRESS)
1680 continue;
1681
1682 /* We've found a remapped device */
894fba7f 1683 hpriv->remapped_nvme++;
aecec8b6
CH		 1684 }
1685
894fba7f 1686 if (!hpriv->remapped_nvme)
aecec8b6
CH		 1687 return;
1688
894fba7f
KHF		 1689 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1690 hpriv->remapped_nvme);
f723fa4e
CH		 1691 dev_warn(&pdev->dev,
1692 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1693
1694 /*
1695 * Don't rely on the msi-x capability in the remap case,
1696 * share the legacy interrupt across ahci and remapped devices.
1697 */
1698 hpriv->flags |= AHCI_HFLAG_NO_MSI;
aecec8b6
CH		 1699}
1700
0b9e2988 1701static int ahci_get_irq_vector(struct ata_host *host, int port)
5ca72c4f 1702{
0b9e2988 1703 return pci_irq_vector(to_pci_dev(host->dev), port);
ee2aad42
RR		 1704}
1705
565d065a 1706static void ahci_init_irq(struct pci_dev *pdev, unsigned int n_ports,
a1c82311 1707 struct ahci_host_priv *hpriv)
5ca72c4f 1708{
0b9e2988 1709 int nvec;
5ca72c4f 1710
565d065a
TH		 1711 if (hpriv->flags & AHCI_HFLAG_NO_MSI) {
1712 pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_INTX);
1713 return;
1714 }
7b92b4f6 1715
7b92b4f6
AG		 1716 /*
1717 * If number of MSIs is less than number of ports then Sharing Last
1718 * Message mode could be enforced. In this case assume that advantage
794007a8 1719 * of multiple MSIs is negated and use single MSI mode instead.
7b92b4f6 1720 */
17a51f12
CH		 1721 if (n_ports > 1) {
1722 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1723 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1724 if (nvec > 0) {
1725 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1726 hpriv->get_irq_vector = ahci_get_irq_vector;
1727 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
565d065a 1728 return;
17a51f12 1729 }
5ca72c4f 1730
17a51f12
CH		 1731 /*
1732 * Fallback to single MSI mode if the controller
1733 * enforced MRSM mode.
1734 */
1735 printk(KERN_INFO
1736 "ahci: MRSM is on, fallback to single MSI\n");
1737 pci_free_irq_vectors(pdev);
1738 }
a478b097 1739 }
d684a90d 1740
0b9e2988
CH		 1741 /*
1742 * If the host is not capable of supporting per-port vectors, fall
565d065a
TH		 1743 * back to single MSI before finally attempting single MSI-X or
1744 * a legacy INTx.
0b9e2988
CH		 1745 */
1746 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1747 if (nvec == 1)
565d065a
TH		 1748 return;
1749 pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX | PCI_IRQ_INTX);
5ca72c4f
AG		 1750}
1751
f7131935 1752static void ahci_mark_external_port(struct ata_port *ap)
b1a9585c 1753{
f7131935
NC		 1754 struct ahci_host_priv *hpriv = ap->host->private_data;
1755 void __iomem *port_mmio = ahci_port_base(ap);
1756 u32 tmp;
b1a9585c 1757
45b96d65 1758 /* mark external ports (hotplug-capable, eSATA) */
f7131935 1759 tmp = readl(port_mmio + PORT_CMD);
45b96d65
NC		 1760 if (((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)) ||
1761 (tmp & PORT_CMD_HPCP))
f7131935
NC		 1762 ap->pflags |= ATA_PFLAG_EXTERNAL;
1763}
b1a9585c 1764
04d5fb7f 1765static void ahci_update_initial_lpm_policy(struct ata_port *ap)
b1a9585c 1766{
04d5fb7f 1767 struct ahci_host_priv *hpriv = ap->host->private_data;
55b01415 1768 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
b1a9585c 1769
ae1f3db0
NC		 1770 /*
1771 * AHCI contains a known incompatibility between LPM and hot-plug
1772 * removal events, see 7.3.1 Hot Plug Removal Detection and Power
1773 * Management Interaction in AHCI 1.3.1. Therefore, do not enable
1774 * LPM if the port advertises itself as an external port.
1775 */
f97106b1
NC		 1776 if (ap->pflags & ATA_PFLAG_EXTERNAL) {
1777 ata_port_dbg(ap, "external port, not enabling LPM\n");
b1a9585c 1778 return;
f97106b1 1779 }
b1a9585c 1780
fa997b05
NC		 1781 /* If no LPM states are supported by the HBA, do not bother with LPM */
1782 if ((ap->host->flags & ATA_HOST_NO_PART) &&
1783 (ap->host->flags & ATA_HOST_NO_SSC) &&
1784 (ap->host->flags & ATA_HOST_NO_DEVSLP)) {
1785 ata_port_dbg(ap, "no LPM states supported, not enabling LPM\n");
1786 return;
1787 }
1788
b1a9585c
SP		 1789 /* user modified policy via module param */
1790 if (mobile_lpm_policy != -1) {
1791 policy = mobile_lpm_policy;
1792 goto update_policy;
1793 }
1794
fee60730 1795 if (policy > ATA_LPM_MED_POWER && pm_suspend_default_s2idle()) {
b1a9585c
SP		 1796 if (hpriv->cap & HOST_CAP_PART)
1797 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1798 else if (hpriv->cap & HOST_CAP_SSC)
1799 policy = ATA_LPM_MIN_POWER;
1800 }
b1a9585c
SP		 1801
1802update_policy:
1803 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1804 ap->target_lpm_policy = policy;
1805}
1806
c312ef17
DW		 1807static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1808{
c312ef17
DW		 1809 u16 tmp16;
1810
7edbb605 1811 if (!(hpriv->flags & AHCI_HFLAG_INTEL_PCS_QUIRK))
c312ef17
DW		 1812 return;
1813
1814 /*
1815 * port_map is determined from PORTS_IMPL PCI register which is
1816 * implemented as write or write-once register. If the register
1817 * isn't programmed, ahci automatically generates it from number
1818 * of ports, which is good enough for PCS programming. It is
1819 * otherwise expected that platform firmware enables the ports
1820 * before the OS boots.
1821 */
1822 pci_read_config_word(pdev, PCS_6, &tmp16);
1823 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1824 tmp16 |= hpriv->port_map;
1825 pci_write_config_word(pdev, PCS_6, tmp16);
1826 }
1827}
1828
894fba7f
KHF		 1829static ssize_t remapped_nvme_show(struct device *dev,
1830 struct device_attribute *attr,
1831 char *buf)
1832{
1833 struct ata_host *host = dev_get_drvdata(dev);
1834 struct ahci_host_priv *hpriv = host->private_data;
1835
179a0282 1836 return sysfs_emit(buf, "%u\n", hpriv->remapped_nvme);
894fba7f
KHF		 1837}
1838
1839static DEVICE_ATTR_RO(remapped_nvme);
1840
24dc5f33 1841static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1842{
e297d99e
TH		 1843 unsigned int board_id = ent->driver_data;
1844 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1845 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1846 struct device *dev = &pdev->dev;
1da177e4 1847 struct ahci_host_priv *hpriv;
4447d351 1848 struct ata_host *host;
c3ebd6a9 1849 int n_ports, i, rc;
318893e1 1850 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4 1851
b429dd59 1852 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1853
06296a1e 1854 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1855
5b66c829
AC		 1856 /* The AHCI driver can only drive the SATA ports, the PATA driver
1857 can drive them all so if both drivers are selected make sure
1858 AHCI stays out of the way */
1859 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1860 return -ENODEV;
1861
cb85696d
JL		 1862 /* Apple BIOS on MCP89 prevents us using AHCI */
1863 if (is_mcp89_apple(pdev))
1864 ahci_mcp89_apple_enable(pdev);
c6353b45 1865
7a02267e
MN		 1866 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1867 * At the moment, we can only use the AHCI mode. Let the users know
1868 * that for SAS drives they're out of luck.
1869 */
1870 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1871 dev_info(&pdev->dev,
1872 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1873
b7ae128d 1874 /* Some devices use non-standard BARs */
318893e1
AR		 1875 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1876 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
7f9c9f8e
HD		 1877 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1878 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
b1314e3f
RMC		 1879 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1880 if (pdev->device == 0xa01c)
1881 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1882 if (pdev->device == 0xa084)
1883 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
e49bd683
TY		 1884 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1885 if (pdev->device == 0x7a08)
1886 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
b1314e3f 1887 }
318893e1 1888
4447d351 1889 /* acquire resources */
24dc5f33 1890 rc = pcim_enable_device(pdev);
1da177e4
LT		 1891 if (rc)
1892 return rc;
1893
c4f7792c
TH		 1894 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1895 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1896 u8 map;
1897
1898 /* ICH6s share the same PCI ID for both piix and ahci
1899 * modes. Enabling ahci mode while MAP indicates
1900 * combined mode is a bad idea. Yield to ata_piix.
1901 */
1902 pci_read_config_byte(pdev, ICH_MAP, &map);
1903 if (map & 0x3) {
a44fec1f
JP		 1904 dev_info(&pdev->dev,
1905 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1906 return -ENODEV;
1907 }
1908 }
1909
6fec8871
PB		 1910 /* AHCI controllers often implement SFF compatible interface.
1911 * Grab all PCI BARs just in case.
1912 */
bdcddd0c 1913 rc = pcim_request_all_regions(pdev, DRV_NAME);
6fec8871
PB		 1914 if (rc == -EBUSY)
1915 pcim_pin_device(pdev);
1916 if (rc)
1917 return rc;
1918
24dc5f33
TH		 1919 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1920 if (!hpriv)
1921 return -ENOMEM;
417a1a6d
TH		 1922 hpriv->flags |= (unsigned long)pi.private_data;
1923
e297d99e
TH		 1924 /* MCP65 revision A1 and A2 can't do MSI */
1925 if (board_id == board_ahci_mcp65 &&
1926 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1927 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1928
e427fe04
SH		 1929 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1930 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1931 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1932
2fcad9d2
TH		 1933 /* only some SB600s can do 64bit DMA */
1934 if (ahci_sb600_enable_64bit(pdev))
1935 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1936
bdcddd0c
PS		 1937 hpriv->mmio = pcim_iomap(pdev, ahci_pci_bar, 0);
1938 if (!hpriv->mmio)
1939 return -ENOMEM;
d8993349 1940
aecec8b6
CH		 1941 /* detect remapped nvme devices */
1942 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1943
894fba7f
KHF		 1944 sysfs_add_file_to_group(&pdev->dev.kobj,
1945 &dev_attr_remapped_nvme.attr,
1946 NULL);
1947
d243bed3 1948#ifdef CONFIG_ARM64
234e6d2c
XY		 1949 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1950 pdev->device == 0xa235 &&
1951 pdev->revision < 0x30)
1952 hpriv->flags |= AHCI_HFLAG_NO_SXS;
1953
d243bed3
TC		 1954 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1955 hpriv->irq_handler = ahci_thunderx_irq_handler;
1956#endif
1957
4447d351 1958 /* save initial config */
394d6e53 1959 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1960
4447d351 1961 /* prepare host */
453d3131
RH		 1962 if (hpriv->cap & HOST_CAP_NCQ) {
1963 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1964 /*
1965 * Auto-activate optimization is supposed to be
1966 * supported on all AHCI controllers indicating NCQ
1967 * capability, but it seems to be broken on some
1968 * chipsets including NVIDIAs.
1969 */
1970 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131 1971 pi.flags |= ATA_FLAG_FPDMA_AA;
40fb59e7
MC		 1972
1973 /*
1974 * All AHCI controllers should be forward-compatible
1975 * with the new auxiliary field. This code should be
1976 * conditionalized if any buggy AHCI controllers are
1977 * encountered.
1978 */
1979 pi.flags |= ATA_FLAG_FPDMA_AUX;
453d3131 1980 }
1da177e4 1981
7d50b60b
TH		 1982 if (hpriv->cap & HOST_CAP_PMP)
1983 pi.flags |= ATA_FLAG_PMP;
1984
0cbb0e77 1985 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1986
1fd68434
RW		 1987 if (ahci_broken_system_poweroff(pdev)) {
1988 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1989 dev_info(&pdev->dev,
1990 "quirky BIOS, skipping spindown on poweroff\n");
1991 }
1992
240630e6
HG		 1993 if (ahci_broken_lpm(pdev)) {
1994 pi.flags |= ATA_FLAG_NO_LPM;
1995 dev_warn(&pdev->dev,
1996 "BIOS update required for Link Power Management support\n");
1997 }
1998
9b10ae86
TH		 1999 if (ahci_broken_suspend(pdev)) {
2000 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 2001 dev_warn(&pdev->dev,
2002 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 2003 }
2004
5594639a
TH		 2005 if (ahci_broken_online(pdev)) {
2006 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
2007 dev_info(&pdev->dev,
2008 "online status unreliable, applying workaround\n");
2009 }
2010
8bfd1743
SC		 2011
2012 /* Acer SA5-271 workaround modifies private_data */
2013 acer_sa5_271_workaround(hpriv, pdev);
2014
837f5f8f
TH		 2015 /* CAP.NP sometimes indicate the index of the last enabled
2016 * port, at other times, that of the last possible port, so
2017 * determining the maximum port number requires looking at
2018 * both CAP.NP and port_map.
2019 */
2020 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2021
2022 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
eeb25a09
NC		 2023 if (!host) {
2024 rc = -ENOMEM;
2025 goto err_rm_sysfs_file;
2026 }
4447d351 2027 host->private_data = hpriv;
0b9e2988 2028
565d065a
TH		 2029 ahci_init_irq(pdev, n_ports, hpriv);
2030
0ce57f8a 2031 hpriv->irq = pci_irq_vector(pdev, 0);
21bfd1aa 2032
f3d7f23f 2033 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 2034 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f 2035 else
d2782d96 2036 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
886ad09f 2037
24e0e61d
NC		 2038 if (!(hpriv->cap & HOST_CAP_PART))
2039 host->flags |= ATA_HOST_NO_PART;
2040
2041 if (!(hpriv->cap & HOST_CAP_SSC))
2042 host->flags |= ATA_HOST_NO_SSC;
2043
2044 if (!(hpriv->cap2 & HOST_CAP2_SDS))
2045 host->flags |= ATA_HOST_NO_DEVSLP;
2046
18f7ba4c
KCA		 2047 if (pi.flags & ATA_FLAG_EM)
2048 ahci_reset_em(host);
2049
4447d351 2050 for (i = 0; i < host->n_ports; i++) {
dab632e8 2051 struct ata_port *ap = host->ports[i];
4447d351 2052
318893e1
AR		 2053 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
2054 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 2055 0x100 + ap->port_no * 0x80, "port");
2056
18f7ba4c
KCA		 2057 /* set enclosure management message type */
2058 if (ap->flags & ATA_FLAG_EM)
008dbd61 2059 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c 2060
f7131935
NC		 2061 ahci_mark_external_port(ap);
2062
04d5fb7f 2063 ahci_update_initial_lpm_policy(ap);
18f7ba4c 2064
dab632e8 2065 /* disabled/not-implemented port */
350756f6 2066 if (!(hpriv->port_map & (1 << i)))
dab632e8 2067 ap->ops = &ata_dummy_port_ops;
4447d351 2068 }
d447df14 2069
edc93052
TH		 2070 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2071 ahci_p5wdh_workaround(host);
2072
f80ae7e4
TH		 2073 /* apply gtf filter quirk */
2074 ahci_gtf_filter_workaround(host);
2075
4447d351 2076 /* initialize adapter */
20730e9b 2077 rc = ahci_configure_dma_masks(pdev, hpriv);
1da177e4 2078 if (rc)
eeb25a09 2079 goto err_rm_sysfs_file;
1da177e4 2080
37e14e4f 2081 rc = ahci_pci_reset_controller(host);
4447d351 2082 if (rc)
eeb25a09 2083 goto err_rm_sysfs_file;
1da177e4 2084
781d6550 2085 ahci_pci_init_controller(host);
439fcaec 2086 ahci_pci_print_info(host);
1da177e4 2087
4447d351 2088 pci_set_master(pdev);
5ca72c4f 2089
02e53293
MW		 2090 rc = ahci_host_activate(host, &ahci_sht);
2091 if (rc)
eeb25a09 2092 goto err_rm_sysfs_file;
02e53293
MW		 2093
2094 pm_runtime_put_noidle(&pdev->dev);
2095 return 0;
eeb25a09
NC		 2096
2097err_rm_sysfs_file:
2098 sysfs_remove_file_from_group(&pdev->dev.kobj,
2099 &dev_attr_remapped_nvme.attr, NULL);
2100 return rc;
02e53293
MW		 2101}
2102
10a663a1
PK		 2103static void ahci_shutdown_one(struct pci_dev *pdev)
2104{
2105 ata_pci_shutdown_one(pdev);
2106}
2107
02e53293
MW		 2108static void ahci_remove_one(struct pci_dev *pdev)
2109{
894fba7f
KHF		 2110 sysfs_remove_file_from_group(&pdev->dev.kobj,
2111 &dev_attr_remapped_nvme.attr,
2112 NULL);
02e53293
MW		 2113 pm_runtime_get_noresume(&pdev->dev);
2114 ata_pci_remove_one(pdev);
907f4678 2115}
1da177e4 2116
2fc75da0 2117module_pci_driver(ahci_pci_driver);
1da177e4
LT		 2118
2119MODULE_AUTHOR("Jeff Garzik");
2120MODULE_DESCRIPTION("AHCI SATA low-level driver");
2121MODULE_LICENSE("GPL");
2122MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 2123MODULE_VERSION(DRV_VERSION);
Linux 6.x block layer and io_uring tree(s)