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1da177e4 LT |
1 | /* |
2 | * ahci.c - AHCI SATA support | |
3 | * | |
af36d7f0 JG |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004-2005 Red Hat, Inc. | |
9 | * | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * AHCI hardware documentation: | |
1da177e4 | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
af36d7f0 | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
1da177e4 LT |
32 | * |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/blkdev.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/interrupt.h> | |
87507cfd | 42 | #include <linux/dma-mapping.h> |
a9524a76 | 43 | #include <linux/device.h> |
1da177e4 | 44 | #include <scsi/scsi_host.h> |
193515d5 | 45 | #include <scsi/scsi_cmnd.h> |
1da177e4 | 46 | #include <linux/libata.h> |
1da177e4 LT |
47 | |
48 | #define DRV_NAME "ahci" | |
cb48cab7 | 49 | #define DRV_VERSION "2.1" |
1da177e4 LT |
50 | |
51 | ||
52 | enum { | |
53 | AHCI_PCI_BAR = 5, | |
648a88be | 54 | AHCI_MAX_PORTS = 32, |
1da177e4 LT |
55 | AHCI_MAX_SG = 168, /* hardware max is 64K */ |
56 | AHCI_DMA_BOUNDARY = 0xffffffff, | |
57 | AHCI_USE_CLUSTERING = 0, | |
12fad3f9 | 58 | AHCI_MAX_CMDS = 32, |
dd410ff1 | 59 | AHCI_CMD_SZ = 32, |
12fad3f9 | 60 | AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
1da177e4 | 61 | AHCI_RX_FIS_SZ = 256, |
a0ea7328 | 62 | AHCI_CMD_TBL_CDB = 0x40, |
dd410ff1 TH |
63 | AHCI_CMD_TBL_HDR_SZ = 0x80, |
64 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), | |
65 | AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, | |
66 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + | |
1da177e4 LT |
67 | AHCI_RX_FIS_SZ, |
68 | AHCI_IRQ_ON_SG = (1 << 31), | |
69 | AHCI_CMD_ATAPI = (1 << 5), | |
70 | AHCI_CMD_WRITE = (1 << 6), | |
4b10e559 | 71 | AHCI_CMD_PREFETCH = (1 << 7), |
22b49985 TH |
72 | AHCI_CMD_RESET = (1 << 8), |
73 | AHCI_CMD_CLR_BUSY = (1 << 10), | |
1da177e4 LT |
74 | |
75 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ | |
0291f95f | 76 | RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ |
78cd52d0 | 77 | RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
1da177e4 LT |
78 | |
79 | board_ahci = 0, | |
648a88be TH |
80 | board_ahci_pi = 1, |
81 | board_ahci_vt8251 = 2, | |
82 | board_ahci_ign_iferr = 3, | |
55a61604 | 83 | board_ahci_sb600 = 4, |
1da177e4 LT |
84 | |
85 | /* global controller registers */ | |
86 | HOST_CAP = 0x00, /* host capabilities */ | |
87 | HOST_CTL = 0x04, /* global host control */ | |
88 | HOST_IRQ_STAT = 0x08, /* interrupt status */ | |
89 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ | |
90 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ | |
91 | ||
92 | /* HOST_CTL bits */ | |
93 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ | |
94 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ | |
95 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ | |
96 | ||
97 | /* HOST_CAP bits */ | |
0be0aa98 | 98 | HOST_CAP_SSC = (1 << 14), /* Slumber capable */ |
22b49985 | 99 | HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
0be0aa98 | 100 | HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ |
979db803 | 101 | HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ |
dd410ff1 | 102 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
1da177e4 LT |
103 | |
104 | /* registers for each SATA port */ | |
105 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ | |
106 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ | |
107 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ | |
108 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ | |
109 | PORT_IRQ_STAT = 0x10, /* interrupt status */ | |
110 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ | |
111 | PORT_CMD = 0x18, /* port command */ | |
112 | PORT_TFDATA = 0x20, /* taskfile data */ | |
113 | PORT_SIG = 0x24, /* device TF signature */ | |
114 | PORT_CMD_ISSUE = 0x38, /* command issue */ | |
115 | PORT_SCR = 0x28, /* SATA phy register block */ | |
116 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ | |
117 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ | |
118 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ | |
119 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ | |
120 | ||
121 | /* PORT_IRQ_{STAT,MASK} bits */ | |
122 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ | |
123 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ | |
124 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ | |
125 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ | |
126 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ | |
127 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ | |
128 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ | |
129 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ | |
130 | ||
131 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ | |
132 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ | |
133 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ | |
134 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ | |
135 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ | |
136 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ | |
137 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ | |
138 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ | |
139 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ | |
140 | ||
78cd52d0 TH |
141 | PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
142 | PORT_IRQ_IF_ERR | | |
143 | PORT_IRQ_CONNECT | | |
4296971d | 144 | PORT_IRQ_PHYRDY | |
78cd52d0 TH |
145 | PORT_IRQ_UNK_FIS, |
146 | PORT_IRQ_ERROR = PORT_IRQ_FREEZE | | |
147 | PORT_IRQ_TF_ERR | | |
148 | PORT_IRQ_HBUS_DATA_ERR, | |
149 | DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | | |
150 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | | |
151 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, | |
1da177e4 LT |
152 | |
153 | /* PORT_CMD bits */ | |
02eaa666 | 154 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
1da177e4 LT |
155 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
156 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ | |
157 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ | |
22b49985 | 158 | PORT_CMD_CLO = (1 << 3), /* Command list override */ |
1da177e4 LT |
159 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
160 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ | |
161 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ | |
162 | ||
0be0aa98 | 163 | PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ |
1da177e4 LT |
164 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ |
165 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ | |
166 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ | |
4b0060f4 | 167 | |
bf2af2a2 | 168 | /* ap->flags bits */ |
4aeb0e32 TH |
169 | AHCI_FLAG_NO_NCQ = (1 << 24), |
170 | AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */ | |
648a88be | 171 | AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */ |
55a61604 | 172 | AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */ |
1da177e4 LT |
173 | }; |
174 | ||
175 | struct ahci_cmd_hdr { | |
176 | u32 opts; | |
177 | u32 status; | |
178 | u32 tbl_addr; | |
179 | u32 tbl_addr_hi; | |
180 | u32 reserved[4]; | |
181 | }; | |
182 | ||
183 | struct ahci_sg { | |
184 | u32 addr; | |
185 | u32 addr_hi; | |
186 | u32 reserved; | |
187 | u32 flags_size; | |
188 | }; | |
189 | ||
190 | struct ahci_host_priv { | |
1da177e4 LT |
191 | u32 cap; /* cache of HOST_CAP register */ |
192 | u32 port_map; /* cache of HOST_PORTS_IMPL reg */ | |
193 | }; | |
194 | ||
195 | struct ahci_port_priv { | |
196 | struct ahci_cmd_hdr *cmd_slot; | |
197 | dma_addr_t cmd_slot_dma; | |
198 | void *cmd_tbl; | |
199 | dma_addr_t cmd_tbl_dma; | |
1da177e4 LT |
200 | void *rx_fis; |
201 | dma_addr_t rx_fis_dma; | |
0291f95f | 202 | /* for NCQ spurious interrupt analysis */ |
0291f95f TH |
203 | unsigned int ncq_saw_d2h:1; |
204 | unsigned int ncq_saw_dmas:1; | |
afb2d552 | 205 | unsigned int ncq_saw_sdb:1; |
1da177e4 LT |
206 | }; |
207 | ||
208 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg); | |
209 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
210 | static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
9a3d9eb0 | 211 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
7d12e780 | 212 | static irqreturn_t ahci_interrupt (int irq, void *dev_instance); |
1da177e4 | 213 | static void ahci_irq_clear(struct ata_port *ap); |
1da177e4 LT |
214 | static int ahci_port_start(struct ata_port *ap); |
215 | static void ahci_port_stop(struct ata_port *ap); | |
1da177e4 LT |
216 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
217 | static void ahci_qc_prep(struct ata_queued_cmd *qc); | |
218 | static u8 ahci_check_status(struct ata_port *ap); | |
78cd52d0 TH |
219 | static void ahci_freeze(struct ata_port *ap); |
220 | static void ahci_thaw(struct ata_port *ap); | |
221 | static void ahci_error_handler(struct ata_port *ap); | |
ad616ffb | 222 | static void ahci_vt8251_error_handler(struct ata_port *ap); |
78cd52d0 | 223 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); |
438ac6d5 | 224 | #ifdef CONFIG_PM |
c1332875 TH |
225 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); |
226 | static int ahci_port_resume(struct ata_port *ap); | |
227 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); | |
228 | static int ahci_pci_device_resume(struct pci_dev *pdev); | |
438ac6d5 | 229 | #endif |
1da177e4 | 230 | |
193515d5 | 231 | static struct scsi_host_template ahci_sht = { |
1da177e4 LT |
232 | .module = THIS_MODULE, |
233 | .name = DRV_NAME, | |
234 | .ioctl = ata_scsi_ioctl, | |
235 | .queuecommand = ata_scsi_queuecmd, | |
12fad3f9 TH |
236 | .change_queue_depth = ata_scsi_change_queue_depth, |
237 | .can_queue = AHCI_MAX_CMDS - 1, | |
1da177e4 LT |
238 | .this_id = ATA_SHT_THIS_ID, |
239 | .sg_tablesize = AHCI_MAX_SG, | |
1da177e4 LT |
240 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
241 | .emulated = ATA_SHT_EMULATED, | |
242 | .use_clustering = AHCI_USE_CLUSTERING, | |
243 | .proc_name = DRV_NAME, | |
244 | .dma_boundary = AHCI_DMA_BOUNDARY, | |
245 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 246 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 247 | .bios_param = ata_std_bios_param, |
438ac6d5 | 248 | #ifdef CONFIG_PM |
c1332875 TH |
249 | .suspend = ata_scsi_device_suspend, |
250 | .resume = ata_scsi_device_resume, | |
438ac6d5 | 251 | #endif |
1da177e4 LT |
252 | }; |
253 | ||
057ace5e | 254 | static const struct ata_port_operations ahci_ops = { |
1da177e4 LT |
255 | .port_disable = ata_port_disable, |
256 | ||
257 | .check_status = ahci_check_status, | |
258 | .check_altstatus = ahci_check_status, | |
1da177e4 LT |
259 | .dev_select = ata_noop_dev_select, |
260 | ||
261 | .tf_read = ahci_tf_read, | |
262 | ||
1da177e4 LT |
263 | .qc_prep = ahci_qc_prep, |
264 | .qc_issue = ahci_qc_issue, | |
265 | ||
1da177e4 LT |
266 | .irq_handler = ahci_interrupt, |
267 | .irq_clear = ahci_irq_clear, | |
246ce3b6 AI |
268 | .irq_on = ata_dummy_irq_on, |
269 | .irq_ack = ata_dummy_irq_ack, | |
1da177e4 LT |
270 | |
271 | .scr_read = ahci_scr_read, | |
272 | .scr_write = ahci_scr_write, | |
273 | ||
78cd52d0 TH |
274 | .freeze = ahci_freeze, |
275 | .thaw = ahci_thaw, | |
276 | ||
277 | .error_handler = ahci_error_handler, | |
278 | .post_internal_cmd = ahci_post_internal_cmd, | |
279 | ||
438ac6d5 | 280 | #ifdef CONFIG_PM |
c1332875 TH |
281 | .port_suspend = ahci_port_suspend, |
282 | .port_resume = ahci_port_resume, | |
438ac6d5 | 283 | #endif |
c1332875 | 284 | |
1da177e4 LT |
285 | .port_start = ahci_port_start, |
286 | .port_stop = ahci_port_stop, | |
1da177e4 LT |
287 | }; |
288 | ||
ad616ffb TH |
289 | static const struct ata_port_operations ahci_vt8251_ops = { |
290 | .port_disable = ata_port_disable, | |
291 | ||
292 | .check_status = ahci_check_status, | |
293 | .check_altstatus = ahci_check_status, | |
294 | .dev_select = ata_noop_dev_select, | |
295 | ||
296 | .tf_read = ahci_tf_read, | |
297 | ||
298 | .qc_prep = ahci_qc_prep, | |
299 | .qc_issue = ahci_qc_issue, | |
300 | ||
301 | .irq_handler = ahci_interrupt, | |
302 | .irq_clear = ahci_irq_clear, | |
246ce3b6 AI |
303 | .irq_on = ata_dummy_irq_on, |
304 | .irq_ack = ata_dummy_irq_ack, | |
ad616ffb TH |
305 | |
306 | .scr_read = ahci_scr_read, | |
307 | .scr_write = ahci_scr_write, | |
308 | ||
309 | .freeze = ahci_freeze, | |
310 | .thaw = ahci_thaw, | |
311 | ||
312 | .error_handler = ahci_vt8251_error_handler, | |
313 | .post_internal_cmd = ahci_post_internal_cmd, | |
314 | ||
438ac6d5 | 315 | #ifdef CONFIG_PM |
ad616ffb TH |
316 | .port_suspend = ahci_port_suspend, |
317 | .port_resume = ahci_port_resume, | |
438ac6d5 | 318 | #endif |
ad616ffb TH |
319 | |
320 | .port_start = ahci_port_start, | |
321 | .port_stop = ahci_port_stop, | |
322 | }; | |
323 | ||
98ac62de | 324 | static const struct ata_port_info ahci_port_info[] = { |
1da177e4 LT |
325 | /* board_ahci */ |
326 | { | |
327 | .sht = &ahci_sht, | |
cca3974e | 328 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
4296971d TH |
329 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
330 | ATA_FLAG_SKIP_D2H_BSY, | |
7da79312 | 331 | .pio_mask = 0x1f, /* pio0-4 */ |
1da177e4 LT |
332 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ |
333 | .port_ops = &ahci_ops, | |
334 | }, | |
648a88be TH |
335 | /* board_ahci_pi */ |
336 | { | |
337 | .sht = &ahci_sht, | |
338 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
339 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | |
340 | ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI, | |
341 | .pio_mask = 0x1f, /* pio0-4 */ | |
342 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
343 | .port_ops = &ahci_ops, | |
344 | }, | |
bf2af2a2 BJ |
345 | /* board_ahci_vt8251 */ |
346 | { | |
347 | .sht = &ahci_sht, | |
cca3974e | 348 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
bf2af2a2 | 349 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
ad616ffb TH |
350 | ATA_FLAG_SKIP_D2H_BSY | |
351 | ATA_FLAG_HRST_TO_RESUME | AHCI_FLAG_NO_NCQ, | |
bf2af2a2 BJ |
352 | .pio_mask = 0x1f, /* pio0-4 */ |
353 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
ad616ffb | 354 | .port_ops = &ahci_vt8251_ops, |
bf2af2a2 | 355 | }, |
41669553 TH |
356 | /* board_ahci_ign_iferr */ |
357 | { | |
358 | .sht = &ahci_sht, | |
359 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
360 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | |
361 | ATA_FLAG_SKIP_D2H_BSY | | |
362 | AHCI_FLAG_IGN_IRQ_IF_ERR, | |
363 | .pio_mask = 0x1f, /* pio0-4 */ | |
364 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
365 | .port_ops = &ahci_ops, | |
366 | }, | |
55a61604 CH |
367 | /* board_ahci_sb600 */ |
368 | { | |
369 | .sht = &ahci_sht, | |
370 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
371 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | |
372 | ATA_FLAG_SKIP_D2H_BSY | | |
373 | AHCI_FLAG_IGN_SERR_INTERNAL, | |
374 | .pio_mask = 0x1f, /* pio0-4 */ | |
375 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
376 | .port_ops = &ahci_ops, | |
377 | }, | |
378 | ||
1da177e4 LT |
379 | }; |
380 | ||
3b7d697d | 381 | static const struct pci_device_id ahci_pci_tbl[] = { |
fe7fa31a | 382 | /* Intel */ |
54bb3a94 JG |
383 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ |
384 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ | |
385 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ | |
386 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ | |
387 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ | |
82490c09 | 388 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ |
54bb3a94 JG |
389 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ |
390 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ | |
391 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ | |
392 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ | |
648a88be TH |
393 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */ |
394 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */ | |
395 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */ | |
396 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */ | |
397 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */ | |
398 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */ | |
399 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */ | |
400 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */ | |
401 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */ | |
402 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */ | |
403 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */ | |
404 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */ | |
405 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */ | |
8af12cdb | 406 | { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pi }, /* ICH9M */ |
648a88be TH |
407 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */ |
408 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */ | |
409 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */ | |
fe7fa31a | 410 | |
e34bb370 TH |
411 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ |
412 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
413 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, | |
fe7fa31a JG |
414 | |
415 | /* ATI */ | |
55a61604 | 416 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 non-raid */ |
54bb3a94 | 417 | { PCI_VDEVICE(ATI, 0x4381), board_ahci }, /* ATI SB600 raid */ |
fe7fa31a JG |
418 | |
419 | /* VIA */ | |
54bb3a94 | 420 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
fe7fa31a JG |
421 | |
422 | /* NVIDIA */ | |
54bb3a94 JG |
423 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */ |
424 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */ | |
425 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */ | |
426 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */ | |
6fbf5ba4 PC |
427 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */ |
428 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */ | |
429 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */ | |
430 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */ | |
431 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */ | |
432 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */ | |
433 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */ | |
434 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */ | |
895663cd PC |
435 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */ |
436 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */ | |
437 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */ | |
438 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */ | |
439 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */ | |
440 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */ | |
441 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */ | |
442 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */ | |
fe7fa31a | 443 | |
95916edd | 444 | /* SiS */ |
54bb3a94 JG |
445 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ |
446 | { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */ | |
447 | { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ | |
95916edd | 448 | |
415ae2b5 JG |
449 | /* Generic, PCI class code for AHCI */ |
450 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
c9f89475 | 451 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, |
415ae2b5 | 452 | |
1da177e4 LT |
453 | { } /* terminate list */ |
454 | }; | |
455 | ||
456 | ||
457 | static struct pci_driver ahci_pci_driver = { | |
458 | .name = DRV_NAME, | |
459 | .id_table = ahci_pci_tbl, | |
460 | .probe = ahci_init_one, | |
24dc5f33 | 461 | .remove = ata_pci_remove_one, |
438ac6d5 | 462 | #ifdef CONFIG_PM |
c1332875 TH |
463 | .suspend = ahci_pci_device_suspend, |
464 | .resume = ahci_pci_device_resume, | |
438ac6d5 | 465 | #endif |
1da177e4 LT |
466 | }; |
467 | ||
468 | ||
98fa4b60 TH |
469 | static inline int ahci_nr_ports(u32 cap) |
470 | { | |
471 | return (cap & 0x1f) + 1; | |
472 | } | |
473 | ||
0d5ff566 TH |
474 | static inline void __iomem *ahci_port_base(void __iomem *base, |
475 | unsigned int port) | |
1da177e4 LT |
476 | { |
477 | return base + 0x100 + (port * 0x80); | |
478 | } | |
479 | ||
1da177e4 LT |
480 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in) |
481 | { | |
482 | unsigned int sc_reg; | |
483 | ||
484 | switch (sc_reg_in) { | |
485 | case SCR_STATUS: sc_reg = 0; break; | |
486 | case SCR_CONTROL: sc_reg = 1; break; | |
487 | case SCR_ERROR: sc_reg = 2; break; | |
488 | case SCR_ACTIVE: sc_reg = 3; break; | |
489 | default: | |
490 | return 0xffffffffU; | |
491 | } | |
492 | ||
0d5ff566 | 493 | return readl(ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
494 | } |
495 | ||
496 | ||
497 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in, | |
498 | u32 val) | |
499 | { | |
500 | unsigned int sc_reg; | |
501 | ||
502 | switch (sc_reg_in) { | |
503 | case SCR_STATUS: sc_reg = 0; break; | |
504 | case SCR_CONTROL: sc_reg = 1; break; | |
505 | case SCR_ERROR: sc_reg = 2; break; | |
506 | case SCR_ACTIVE: sc_reg = 3; break; | |
507 | default: | |
508 | return; | |
509 | } | |
510 | ||
0d5ff566 | 511 | writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
512 | } |
513 | ||
9f592056 | 514 | static void ahci_start_engine(void __iomem *port_mmio) |
7c76d1e8 | 515 | { |
7c76d1e8 TH |
516 | u32 tmp; |
517 | ||
d8fcd116 | 518 | /* start DMA */ |
9f592056 | 519 | tmp = readl(port_mmio + PORT_CMD); |
7c76d1e8 TH |
520 | tmp |= PORT_CMD_START; |
521 | writel(tmp, port_mmio + PORT_CMD); | |
522 | readl(port_mmio + PORT_CMD); /* flush */ | |
523 | } | |
524 | ||
254950cd TH |
525 | static int ahci_stop_engine(void __iomem *port_mmio) |
526 | { | |
527 | u32 tmp; | |
528 | ||
529 | tmp = readl(port_mmio + PORT_CMD); | |
530 | ||
d8fcd116 | 531 | /* check if the HBA is idle */ |
254950cd TH |
532 | if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) |
533 | return 0; | |
534 | ||
d8fcd116 | 535 | /* setting HBA to idle */ |
254950cd TH |
536 | tmp &= ~PORT_CMD_START; |
537 | writel(tmp, port_mmio + PORT_CMD); | |
538 | ||
d8fcd116 | 539 | /* wait for engine to stop. This could be as long as 500 msec */ |
254950cd TH |
540 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
541 | PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); | |
d8fcd116 | 542 | if (tmp & PORT_CMD_LIST_ON) |
254950cd TH |
543 | return -EIO; |
544 | ||
545 | return 0; | |
546 | } | |
547 | ||
0be0aa98 TH |
548 | static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap, |
549 | dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma) | |
550 | { | |
551 | u32 tmp; | |
552 | ||
553 | /* set FIS registers */ | |
554 | if (cap & HOST_CAP_64) | |
555 | writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI); | |
556 | writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); | |
557 | ||
558 | if (cap & HOST_CAP_64) | |
559 | writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI); | |
560 | writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); | |
561 | ||
562 | /* enable FIS reception */ | |
563 | tmp = readl(port_mmio + PORT_CMD); | |
564 | tmp |= PORT_CMD_FIS_RX; | |
565 | writel(tmp, port_mmio + PORT_CMD); | |
566 | ||
567 | /* flush */ | |
568 | readl(port_mmio + PORT_CMD); | |
569 | } | |
570 | ||
571 | static int ahci_stop_fis_rx(void __iomem *port_mmio) | |
572 | { | |
573 | u32 tmp; | |
574 | ||
575 | /* disable FIS reception */ | |
576 | tmp = readl(port_mmio + PORT_CMD); | |
577 | tmp &= ~PORT_CMD_FIS_RX; | |
578 | writel(tmp, port_mmio + PORT_CMD); | |
579 | ||
580 | /* wait for completion, spec says 500ms, give it 1000 */ | |
581 | tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, | |
582 | PORT_CMD_FIS_ON, 10, 1000); | |
583 | if (tmp & PORT_CMD_FIS_ON) | |
584 | return -EBUSY; | |
585 | ||
586 | return 0; | |
587 | } | |
588 | ||
589 | static void ahci_power_up(void __iomem *port_mmio, u32 cap) | |
590 | { | |
591 | u32 cmd; | |
592 | ||
593 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
594 | ||
595 | /* spin up device */ | |
596 | if (cap & HOST_CAP_SSS) { | |
597 | cmd |= PORT_CMD_SPIN_UP; | |
598 | writel(cmd, port_mmio + PORT_CMD); | |
599 | } | |
600 | ||
601 | /* wake up link */ | |
602 | writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); | |
603 | } | |
604 | ||
438ac6d5 | 605 | #ifdef CONFIG_PM |
0be0aa98 TH |
606 | static void ahci_power_down(void __iomem *port_mmio, u32 cap) |
607 | { | |
608 | u32 cmd, scontrol; | |
609 | ||
07c53dac TH |
610 | if (!(cap & HOST_CAP_SSS)) |
611 | return; | |
0be0aa98 | 612 | |
07c53dac TH |
613 | /* put device into listen mode, first set PxSCTL.DET to 0 */ |
614 | scontrol = readl(port_mmio + PORT_SCR_CTL); | |
615 | scontrol &= ~0xf; | |
616 | writel(scontrol, port_mmio + PORT_SCR_CTL); | |
0be0aa98 | 617 | |
07c53dac TH |
618 | /* then set PxCMD.SUD to 0 */ |
619 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
620 | cmd &= ~PORT_CMD_SPIN_UP; | |
621 | writel(cmd, port_mmio + PORT_CMD); | |
0be0aa98 | 622 | } |
438ac6d5 | 623 | #endif |
0be0aa98 TH |
624 | |
625 | static void ahci_init_port(void __iomem *port_mmio, u32 cap, | |
626 | dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma) | |
627 | { | |
0be0aa98 TH |
628 | /* enable FIS reception */ |
629 | ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma); | |
630 | ||
631 | /* enable DMA */ | |
632 | ahci_start_engine(port_mmio); | |
633 | } | |
634 | ||
635 | static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg) | |
636 | { | |
637 | int rc; | |
638 | ||
639 | /* disable DMA */ | |
640 | rc = ahci_stop_engine(port_mmio); | |
641 | if (rc) { | |
642 | *emsg = "failed to stop engine"; | |
643 | return rc; | |
644 | } | |
645 | ||
646 | /* disable FIS reception */ | |
647 | rc = ahci_stop_fis_rx(port_mmio); | |
648 | if (rc) { | |
649 | *emsg = "failed stop FIS RX"; | |
650 | return rc; | |
651 | } | |
652 | ||
0be0aa98 TH |
653 | return 0; |
654 | } | |
655 | ||
d91542c1 TH |
656 | static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev) |
657 | { | |
98fa4b60 | 658 | u32 cap_save, impl_save, tmp; |
d91542c1 TH |
659 | |
660 | cap_save = readl(mmio + HOST_CAP); | |
98fa4b60 | 661 | impl_save = readl(mmio + HOST_PORTS_IMPL); |
d91542c1 TH |
662 | |
663 | /* global controller reset */ | |
664 | tmp = readl(mmio + HOST_CTL); | |
665 | if ((tmp & HOST_RESET) == 0) { | |
666 | writel(tmp | HOST_RESET, mmio + HOST_CTL); | |
667 | readl(mmio + HOST_CTL); /* flush */ | |
668 | } | |
669 | ||
670 | /* reset must complete within 1 second, or | |
671 | * the hardware should be considered fried. | |
672 | */ | |
673 | ssleep(1); | |
674 | ||
675 | tmp = readl(mmio + HOST_CTL); | |
676 | if (tmp & HOST_RESET) { | |
677 | dev_printk(KERN_ERR, &pdev->dev, | |
678 | "controller reset failed (0x%x)\n", tmp); | |
679 | return -EIO; | |
680 | } | |
681 | ||
98fa4b60 | 682 | /* turn on AHCI mode */ |
d91542c1 TH |
683 | writel(HOST_AHCI_EN, mmio + HOST_CTL); |
684 | (void) readl(mmio + HOST_CTL); /* flush */ | |
98fa4b60 TH |
685 | |
686 | /* These write-once registers are normally cleared on reset. | |
687 | * Restore BIOS values... which we HOPE were present before | |
688 | * reset. | |
689 | */ | |
690 | if (!impl_save) { | |
691 | impl_save = (1 << ahci_nr_ports(cap_save)) - 1; | |
692 | dev_printk(KERN_WARNING, &pdev->dev, | |
693 | "PORTS_IMPL is zero, forcing 0x%x\n", impl_save); | |
694 | } | |
d91542c1 | 695 | writel(cap_save, mmio + HOST_CAP); |
98fa4b60 | 696 | writel(impl_save, mmio + HOST_PORTS_IMPL); |
d91542c1 TH |
697 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ |
698 | ||
699 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { | |
700 | u16 tmp16; | |
701 | ||
702 | /* configure PCS */ | |
703 | pci_read_config_word(pdev, 0x92, &tmp16); | |
704 | tmp16 |= 0xf; | |
705 | pci_write_config_word(pdev, 0x92, tmp16); | |
706 | } | |
707 | ||
708 | return 0; | |
709 | } | |
710 | ||
711 | static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev, | |
648a88be TH |
712 | int n_ports, unsigned int port_flags, |
713 | struct ahci_host_priv *hpriv) | |
d91542c1 TH |
714 | { |
715 | int i, rc; | |
716 | u32 tmp; | |
717 | ||
718 | for (i = 0; i < n_ports; i++) { | |
719 | void __iomem *port_mmio = ahci_port_base(mmio, i); | |
720 | const char *emsg = NULL; | |
721 | ||
648a88be TH |
722 | if ((port_flags & AHCI_FLAG_HONOR_PI) && |
723 | !(hpriv->port_map & (1 << i))) | |
d91542c1 | 724 | continue; |
d91542c1 TH |
725 | |
726 | /* make sure port is not active */ | |
648a88be | 727 | rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg); |
d91542c1 TH |
728 | if (rc) |
729 | dev_printk(KERN_WARNING, &pdev->dev, | |
730 | "%s (%d)\n", emsg, rc); | |
731 | ||
732 | /* clear SError */ | |
733 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
734 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); | |
735 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
736 | ||
f4b5cc87 | 737 | /* clear port IRQ */ |
d91542c1 TH |
738 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
739 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
740 | if (tmp) | |
741 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
742 | ||
743 | writel(1 << i, mmio + HOST_IRQ_STAT); | |
d91542c1 TH |
744 | } |
745 | ||
746 | tmp = readl(mmio + HOST_CTL); | |
747 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
748 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); | |
749 | tmp = readl(mmio + HOST_CTL); | |
750 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
751 | } | |
752 | ||
422b7595 | 753 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
1da177e4 | 754 | { |
0d5ff566 | 755 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
1da177e4 | 756 | struct ata_taskfile tf; |
422b7595 TH |
757 | u32 tmp; |
758 | ||
759 | tmp = readl(port_mmio + PORT_SIG); | |
760 | tf.lbah = (tmp >> 24) & 0xff; | |
761 | tf.lbam = (tmp >> 16) & 0xff; | |
762 | tf.lbal = (tmp >> 8) & 0xff; | |
763 | tf.nsect = (tmp) & 0xff; | |
764 | ||
765 | return ata_dev_classify(&tf); | |
766 | } | |
767 | ||
12fad3f9 TH |
768 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
769 | u32 opts) | |
cc9278ed | 770 | { |
12fad3f9 TH |
771 | dma_addr_t cmd_tbl_dma; |
772 | ||
773 | cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; | |
774 | ||
775 | pp->cmd_slot[tag].opts = cpu_to_le32(opts); | |
776 | pp->cmd_slot[tag].status = 0; | |
777 | pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); | |
778 | pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); | |
cc9278ed TH |
779 | } |
780 | ||
bf2af2a2 | 781 | static int ahci_clo(struct ata_port *ap) |
4658f79b | 782 | { |
0d5ff566 | 783 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
cca3974e | 784 | struct ahci_host_priv *hpriv = ap->host->private_data; |
bf2af2a2 BJ |
785 | u32 tmp; |
786 | ||
787 | if (!(hpriv->cap & HOST_CAP_CLO)) | |
788 | return -EOPNOTSUPP; | |
789 | ||
790 | tmp = readl(port_mmio + PORT_CMD); | |
791 | tmp |= PORT_CMD_CLO; | |
792 | writel(tmp, port_mmio + PORT_CMD); | |
793 | ||
794 | tmp = ata_wait_register(port_mmio + PORT_CMD, | |
795 | PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); | |
796 | if (tmp & PORT_CMD_CLO) | |
797 | return -EIO; | |
798 | ||
799 | return 0; | |
800 | } | |
801 | ||
802 | static int ahci_softreset(struct ata_port *ap, unsigned int *class) | |
803 | { | |
4658f79b | 804 | struct ahci_port_priv *pp = ap->private_data; |
0d5ff566 | 805 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
4658f79b TH |
806 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
807 | const u32 cmd_fis_len = 5; /* five dwords */ | |
808 | const char *reason = NULL; | |
809 | struct ata_taskfile tf; | |
75fe1806 | 810 | u32 tmp; |
4658f79b TH |
811 | u8 *fis; |
812 | int rc; | |
813 | ||
814 | DPRINTK("ENTER\n"); | |
815 | ||
81952c54 | 816 | if (ata_port_offline(ap)) { |
c2a65852 TH |
817 | DPRINTK("PHY reports no device\n"); |
818 | *class = ATA_DEV_NONE; | |
819 | return 0; | |
820 | } | |
821 | ||
4658f79b | 822 | /* prepare for SRST (AHCI-1.1 10.4.1) */ |
5457f219 | 823 | rc = ahci_stop_engine(port_mmio); |
4658f79b TH |
824 | if (rc) { |
825 | reason = "failed to stop engine"; | |
826 | goto fail_restart; | |
827 | } | |
828 | ||
829 | /* check BUSY/DRQ, perform Command List Override if necessary */ | |
1244a19c | 830 | if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) { |
bf2af2a2 | 831 | rc = ahci_clo(ap); |
4658f79b | 832 | |
bf2af2a2 BJ |
833 | if (rc == -EOPNOTSUPP) { |
834 | reason = "port busy but CLO unavailable"; | |
835 | goto fail_restart; | |
836 | } else if (rc) { | |
837 | reason = "port busy but CLO failed"; | |
4658f79b TH |
838 | goto fail_restart; |
839 | } | |
840 | } | |
841 | ||
842 | /* restart engine */ | |
5457f219 | 843 | ahci_start_engine(port_mmio); |
4658f79b | 844 | |
3373efd8 | 845 | ata_tf_init(ap->device, &tf); |
4658f79b TH |
846 | fis = pp->cmd_tbl; |
847 | ||
848 | /* issue the first D2H Register FIS */ | |
12fad3f9 TH |
849 | ahci_fill_cmd_slot(pp, 0, |
850 | cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY); | |
4658f79b TH |
851 | |
852 | tf.ctl |= ATA_SRST; | |
853 | ata_tf_to_fis(&tf, fis, 0); | |
854 | fis[1] &= ~(1 << 7); /* turn off Command FIS bit */ | |
855 | ||
856 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
4658f79b | 857 | |
75fe1806 TH |
858 | tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500); |
859 | if (tmp & 0x1) { | |
4658f79b TH |
860 | rc = -EIO; |
861 | reason = "1st FIS failed"; | |
862 | goto fail; | |
863 | } | |
864 | ||
865 | /* spec says at least 5us, but be generous and sleep for 1ms */ | |
866 | msleep(1); | |
867 | ||
868 | /* issue the second D2H Register FIS */ | |
12fad3f9 | 869 | ahci_fill_cmd_slot(pp, 0, cmd_fis_len); |
4658f79b TH |
870 | |
871 | tf.ctl &= ~ATA_SRST; | |
872 | ata_tf_to_fis(&tf, fis, 0); | |
873 | fis[1] &= ~(1 << 7); /* turn off Command FIS bit */ | |
874 | ||
875 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
876 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ | |
877 | ||
878 | /* spec mandates ">= 2ms" before checking status. | |
879 | * We wait 150ms, because that was the magic delay used for | |
880 | * ATAPI devices in Hale Landis's ATADRVR, for the period of time | |
881 | * between when the ATA command register is written, and then | |
882 | * status is checked. Because waiting for "a while" before | |
883 | * checking status is fine, post SRST, we perform this magic | |
884 | * delay here as well. | |
885 | */ | |
886 | msleep(150); | |
887 | ||
888 | *class = ATA_DEV_NONE; | |
81952c54 | 889 | if (ata_port_online(ap)) { |
4658f79b TH |
890 | if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) { |
891 | rc = -EIO; | |
892 | reason = "device not ready"; | |
893 | goto fail; | |
894 | } | |
895 | *class = ahci_dev_classify(ap); | |
896 | } | |
897 | ||
898 | DPRINTK("EXIT, class=%u\n", *class); | |
899 | return 0; | |
900 | ||
901 | fail_restart: | |
5457f219 | 902 | ahci_start_engine(port_mmio); |
4658f79b | 903 | fail: |
f15a1daf | 904 | ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason); |
4658f79b TH |
905 | return rc; |
906 | } | |
907 | ||
2bf2cb26 | 908 | static int ahci_hardreset(struct ata_port *ap, unsigned int *class) |
422b7595 | 909 | { |
4296971d TH |
910 | struct ahci_port_priv *pp = ap->private_data; |
911 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
912 | struct ata_taskfile tf; | |
0d5ff566 | 913 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
5457f219 | 914 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
4bd00f6a TH |
915 | int rc; |
916 | ||
917 | DPRINTK("ENTER\n"); | |
1da177e4 | 918 | |
5457f219 | 919 | ahci_stop_engine(port_mmio); |
4296971d TH |
920 | |
921 | /* clear D2H reception area to properly wait for D2H FIS */ | |
922 | ata_tf_init(ap->device, &tf); | |
dfd7a3db | 923 | tf.command = 0x80; |
4296971d TH |
924 | ata_tf_to_fis(&tf, d2h_fis, 0); |
925 | ||
2bf2cb26 | 926 | rc = sata_std_hardreset(ap, class); |
4296971d | 927 | |
5457f219 | 928 | ahci_start_engine(port_mmio); |
1da177e4 | 929 | |
81952c54 | 930 | if (rc == 0 && ata_port_online(ap)) |
4bd00f6a TH |
931 | *class = ahci_dev_classify(ap); |
932 | if (*class == ATA_DEV_UNKNOWN) | |
933 | *class = ATA_DEV_NONE; | |
1da177e4 | 934 | |
4bd00f6a TH |
935 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
936 | return rc; | |
937 | } | |
938 | ||
ad616ffb TH |
939 | static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class) |
940 | { | |
0d5ff566 | 941 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
ad616ffb TH |
942 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
943 | int rc; | |
944 | ||
945 | DPRINTK("ENTER\n"); | |
946 | ||
947 | ahci_stop_engine(port_mmio); | |
948 | ||
949 | rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context)); | |
950 | ||
951 | /* vt8251 needs SError cleared for the port to operate */ | |
952 | ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR)); | |
953 | ||
954 | ahci_start_engine(port_mmio); | |
955 | ||
956 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); | |
957 | ||
958 | /* vt8251 doesn't clear BSY on signature FIS reception, | |
959 | * request follow-up softreset. | |
960 | */ | |
961 | return rc ?: -EAGAIN; | |
962 | } | |
963 | ||
4bd00f6a TH |
964 | static void ahci_postreset(struct ata_port *ap, unsigned int *class) |
965 | { | |
0d5ff566 | 966 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
4bd00f6a TH |
967 | u32 new_tmp, tmp; |
968 | ||
969 | ata_std_postreset(ap, class); | |
02eaa666 JG |
970 | |
971 | /* Make sure port's ATAPI bit is set appropriately */ | |
972 | new_tmp = tmp = readl(port_mmio + PORT_CMD); | |
4bd00f6a | 973 | if (*class == ATA_DEV_ATAPI) |
02eaa666 JG |
974 | new_tmp |= PORT_CMD_ATAPI; |
975 | else | |
976 | new_tmp &= ~PORT_CMD_ATAPI; | |
977 | if (new_tmp != tmp) { | |
978 | writel(new_tmp, port_mmio + PORT_CMD); | |
979 | readl(port_mmio + PORT_CMD); /* flush */ | |
980 | } | |
1da177e4 LT |
981 | } |
982 | ||
983 | static u8 ahci_check_status(struct ata_port *ap) | |
984 | { | |
0d5ff566 | 985 | void __iomem *mmio = ap->ioaddr.cmd_addr; |
1da177e4 LT |
986 | |
987 | return readl(mmio + PORT_TFDATA) & 0xFF; | |
988 | } | |
989 | ||
1da177e4 LT |
990 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
991 | { | |
992 | struct ahci_port_priv *pp = ap->private_data; | |
993 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
994 | ||
995 | ata_tf_from_fis(d2h_fis, tf); | |
996 | } | |
997 | ||
12fad3f9 | 998 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) |
1da177e4 | 999 | { |
cedc9a47 JG |
1000 | struct scatterlist *sg; |
1001 | struct ahci_sg *ahci_sg; | |
828d09de | 1002 | unsigned int n_sg = 0; |
1da177e4 LT |
1003 | |
1004 | VPRINTK("ENTER\n"); | |
1005 | ||
1006 | /* | |
1007 | * Next, the S/G list. | |
1008 | */ | |
12fad3f9 | 1009 | ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; |
cedc9a47 JG |
1010 | ata_for_each_sg(sg, qc) { |
1011 | dma_addr_t addr = sg_dma_address(sg); | |
1012 | u32 sg_len = sg_dma_len(sg); | |
1013 | ||
1014 | ahci_sg->addr = cpu_to_le32(addr & 0xffffffff); | |
1015 | ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); | |
1016 | ahci_sg->flags_size = cpu_to_le32(sg_len - 1); | |
828d09de | 1017 | |
cedc9a47 | 1018 | ahci_sg++; |
828d09de | 1019 | n_sg++; |
1da177e4 | 1020 | } |
828d09de JG |
1021 | |
1022 | return n_sg; | |
1da177e4 LT |
1023 | } |
1024 | ||
1025 | static void ahci_qc_prep(struct ata_queued_cmd *qc) | |
1026 | { | |
a0ea7328 JG |
1027 | struct ata_port *ap = qc->ap; |
1028 | struct ahci_port_priv *pp = ap->private_data; | |
cc9278ed | 1029 | int is_atapi = is_atapi_taskfile(&qc->tf); |
12fad3f9 | 1030 | void *cmd_tbl; |
1da177e4 LT |
1031 | u32 opts; |
1032 | const u32 cmd_fis_len = 5; /* five dwords */ | |
828d09de | 1033 | unsigned int n_elem; |
1da177e4 | 1034 | |
1da177e4 LT |
1035 | /* |
1036 | * Fill in command table information. First, the header, | |
1037 | * a SATA Register - Host to Device command FIS. | |
1038 | */ | |
12fad3f9 TH |
1039 | cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; |
1040 | ||
1041 | ata_tf_to_fis(&qc->tf, cmd_tbl, 0); | |
cc9278ed | 1042 | if (is_atapi) { |
12fad3f9 TH |
1043 | memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); |
1044 | memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); | |
a0ea7328 | 1045 | } |
1da177e4 | 1046 | |
cc9278ed TH |
1047 | n_elem = 0; |
1048 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
12fad3f9 | 1049 | n_elem = ahci_fill_sg(qc, cmd_tbl); |
1da177e4 | 1050 | |
cc9278ed TH |
1051 | /* |
1052 | * Fill in command slot information. | |
1053 | */ | |
1054 | opts = cmd_fis_len | n_elem << 16; | |
1055 | if (qc->tf.flags & ATA_TFLAG_WRITE) | |
1056 | opts |= AHCI_CMD_WRITE; | |
1057 | if (is_atapi) | |
4b10e559 | 1058 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; |
828d09de | 1059 | |
12fad3f9 | 1060 | ahci_fill_cmd_slot(pp, qc->tag, opts); |
1da177e4 LT |
1061 | } |
1062 | ||
78cd52d0 | 1063 | static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) |
1da177e4 | 1064 | { |
78cd52d0 TH |
1065 | struct ahci_port_priv *pp = ap->private_data; |
1066 | struct ata_eh_info *ehi = &ap->eh_info; | |
1067 | unsigned int err_mask = 0, action = 0; | |
1068 | struct ata_queued_cmd *qc; | |
1069 | u32 serror; | |
1da177e4 | 1070 | |
78cd52d0 | 1071 | ata_ehi_clear_desc(ehi); |
1da177e4 | 1072 | |
78cd52d0 TH |
1073 | /* AHCI needs SError cleared; otherwise, it might lock up */ |
1074 | serror = ahci_scr_read(ap, SCR_ERROR); | |
1075 | ahci_scr_write(ap, SCR_ERROR, serror); | |
1da177e4 | 1076 | |
78cd52d0 TH |
1077 | /* analyze @irq_stat */ |
1078 | ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); | |
1079 | ||
41669553 TH |
1080 | /* some controllers set IRQ_IF_ERR on device errors, ignore it */ |
1081 | if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR) | |
1082 | irq_stat &= ~PORT_IRQ_IF_ERR; | |
1083 | ||
55a61604 | 1084 | if (irq_stat & PORT_IRQ_TF_ERR) { |
78cd52d0 | 1085 | err_mask |= AC_ERR_DEV; |
55a61604 CH |
1086 | if (ap->flags & AHCI_FLAG_IGN_SERR_INTERNAL) |
1087 | serror &= ~SERR_INTERNAL; | |
1088 | } | |
78cd52d0 TH |
1089 | |
1090 | if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { | |
1091 | err_mask |= AC_ERR_HOST_BUS; | |
1092 | action |= ATA_EH_SOFTRESET; | |
1da177e4 LT |
1093 | } |
1094 | ||
78cd52d0 TH |
1095 | if (irq_stat & PORT_IRQ_IF_ERR) { |
1096 | err_mask |= AC_ERR_ATA_BUS; | |
1097 | action |= ATA_EH_SOFTRESET; | |
1098 | ata_ehi_push_desc(ehi, ", interface fatal error"); | |
1099 | } | |
1da177e4 | 1100 | |
78cd52d0 | 1101 | if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { |
4296971d | 1102 | ata_ehi_hotplugged(ehi); |
78cd52d0 TH |
1103 | ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ? |
1104 | "connection status changed" : "PHY RDY changed"); | |
1105 | } | |
1106 | ||
1107 | if (irq_stat & PORT_IRQ_UNK_FIS) { | |
1108 | u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); | |
1da177e4 | 1109 | |
78cd52d0 TH |
1110 | err_mask |= AC_ERR_HSM; |
1111 | action |= ATA_EH_SOFTRESET; | |
1112 | ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x", | |
1113 | unk[0], unk[1], unk[2], unk[3]); | |
1114 | } | |
1da177e4 | 1115 | |
78cd52d0 TH |
1116 | /* okay, let's hand over to EH */ |
1117 | ehi->serror |= serror; | |
1118 | ehi->action |= action; | |
b8f6153e | 1119 | |
1da177e4 | 1120 | qc = ata_qc_from_tag(ap, ap->active_tag); |
78cd52d0 TH |
1121 | if (qc) |
1122 | qc->err_mask |= err_mask; | |
1123 | else | |
1124 | ehi->err_mask |= err_mask; | |
a72ec4ce | 1125 | |
78cd52d0 TH |
1126 | if (irq_stat & PORT_IRQ_FREEZE) |
1127 | ata_port_freeze(ap); | |
1128 | else | |
1129 | ata_port_abort(ap); | |
1da177e4 LT |
1130 | } |
1131 | ||
78cd52d0 | 1132 | static void ahci_host_intr(struct ata_port *ap) |
1da177e4 | 1133 | { |
0d5ff566 | 1134 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
ea6ba10b | 1135 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
12fad3f9 | 1136 | struct ata_eh_info *ehi = &ap->eh_info; |
0291f95f | 1137 | struct ahci_port_priv *pp = ap->private_data; |
12fad3f9 | 1138 | u32 status, qc_active; |
0291f95f | 1139 | int rc, known_irq = 0; |
1da177e4 LT |
1140 | |
1141 | status = readl(port_mmio + PORT_IRQ_STAT); | |
1142 | writel(status, port_mmio + PORT_IRQ_STAT); | |
1143 | ||
78cd52d0 TH |
1144 | if (unlikely(status & PORT_IRQ_ERROR)) { |
1145 | ahci_error_intr(ap, status); | |
1146 | return; | |
1da177e4 LT |
1147 | } |
1148 | ||
12fad3f9 TH |
1149 | if (ap->sactive) |
1150 | qc_active = readl(port_mmio + PORT_SCR_ACT); | |
1151 | else | |
1152 | qc_active = readl(port_mmio + PORT_CMD_ISSUE); | |
1153 | ||
1154 | rc = ata_qc_complete_multiple(ap, qc_active, NULL); | |
1155 | if (rc > 0) | |
1156 | return; | |
1157 | if (rc < 0) { | |
1158 | ehi->err_mask |= AC_ERR_HSM; | |
1159 | ehi->action |= ATA_EH_SOFTRESET; | |
1160 | ata_port_freeze(ap); | |
1161 | return; | |
1da177e4 LT |
1162 | } |
1163 | ||
2a3917a8 TH |
1164 | /* hmmm... a spurious interupt */ |
1165 | ||
0291f95f TH |
1166 | /* if !NCQ, ignore. No modern ATA device has broken HSM |
1167 | * implementation for non-NCQ commands. | |
1168 | */ | |
1169 | if (!ap->sactive) | |
12fad3f9 TH |
1170 | return; |
1171 | ||
0291f95f TH |
1172 | if (status & PORT_IRQ_D2H_REG_FIS) { |
1173 | if (!pp->ncq_saw_d2h) | |
1174 | ata_port_printk(ap, KERN_INFO, | |
1175 | "D2H reg with I during NCQ, " | |
1176 | "this message won't be printed again\n"); | |
1177 | pp->ncq_saw_d2h = 1; | |
1178 | known_irq = 1; | |
1179 | } | |
1180 | ||
1181 | if (status & PORT_IRQ_DMAS_FIS) { | |
1182 | if (!pp->ncq_saw_dmas) | |
1183 | ata_port_printk(ap, KERN_INFO, | |
1184 | "DMAS FIS during NCQ, " | |
1185 | "this message won't be printed again\n"); | |
1186 | pp->ncq_saw_dmas = 1; | |
1187 | known_irq = 1; | |
1188 | } | |
1189 | ||
a2bbd0c9 | 1190 | if (status & PORT_IRQ_SDB_FIS) { |
04d4f7a1 | 1191 | const __le32 *f = pp->rx_fis + RX_FIS_SDB; |
0291f95f | 1192 | |
afb2d552 TH |
1193 | if (le32_to_cpu(f[1])) { |
1194 | /* SDB FIS containing spurious completions | |
1195 | * might be dangerous, whine and fail commands | |
1196 | * with HSM violation. EH will turn off NCQ | |
1197 | * after several such failures. | |
1198 | */ | |
1199 | ata_ehi_push_desc(ehi, | |
1200 | "spurious completions during NCQ " | |
1201 | "issue=0x%x SAct=0x%x FIS=%08x:%08x", | |
1202 | readl(port_mmio + PORT_CMD_ISSUE), | |
1203 | readl(port_mmio + PORT_SCR_ACT), | |
1204 | le32_to_cpu(f[0]), le32_to_cpu(f[1])); | |
1205 | ehi->err_mask |= AC_ERR_HSM; | |
1206 | ehi->action |= ATA_EH_SOFTRESET; | |
1207 | ata_port_freeze(ap); | |
1208 | } else { | |
1209 | if (!pp->ncq_saw_sdb) | |
1210 | ata_port_printk(ap, KERN_INFO, | |
1211 | "spurious SDB FIS %08x:%08x during NCQ, " | |
1212 | "this message won't be printed again\n", | |
1213 | le32_to_cpu(f[0]), le32_to_cpu(f[1])); | |
1214 | pp->ncq_saw_sdb = 1; | |
1215 | } | |
0291f95f TH |
1216 | known_irq = 1; |
1217 | } | |
2a3917a8 | 1218 | |
0291f95f | 1219 | if (!known_irq) |
78cd52d0 | 1220 | ata_port_printk(ap, KERN_INFO, "spurious interrupt " |
0291f95f | 1221 | "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n", |
12fad3f9 | 1222 | status, ap->active_tag, ap->sactive); |
1da177e4 LT |
1223 | } |
1224 | ||
1225 | static void ahci_irq_clear(struct ata_port *ap) | |
1226 | { | |
1227 | /* TODO */ | |
1228 | } | |
1229 | ||
7d12e780 | 1230 | static irqreturn_t ahci_interrupt(int irq, void *dev_instance) |
1da177e4 | 1231 | { |
cca3974e | 1232 | struct ata_host *host = dev_instance; |
1da177e4 LT |
1233 | struct ahci_host_priv *hpriv; |
1234 | unsigned int i, handled = 0; | |
ea6ba10b | 1235 | void __iomem *mmio; |
1da177e4 LT |
1236 | u32 irq_stat, irq_ack = 0; |
1237 | ||
1238 | VPRINTK("ENTER\n"); | |
1239 | ||
cca3974e | 1240 | hpriv = host->private_data; |
0d5ff566 | 1241 | mmio = host->iomap[AHCI_PCI_BAR]; |
1da177e4 LT |
1242 | |
1243 | /* sigh. 0xffffffff is a valid return from h/w */ | |
1244 | irq_stat = readl(mmio + HOST_IRQ_STAT); | |
1245 | irq_stat &= hpriv->port_map; | |
1246 | if (!irq_stat) | |
1247 | return IRQ_NONE; | |
1248 | ||
cca3974e | 1249 | spin_lock(&host->lock); |
1da177e4 | 1250 | |
cca3974e | 1251 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 1252 | struct ata_port *ap; |
1da177e4 | 1253 | |
67846b30 JG |
1254 | if (!(irq_stat & (1 << i))) |
1255 | continue; | |
1256 | ||
cca3974e | 1257 | ap = host->ports[i]; |
67846b30 | 1258 | if (ap) { |
78cd52d0 | 1259 | ahci_host_intr(ap); |
67846b30 JG |
1260 | VPRINTK("port %u\n", i); |
1261 | } else { | |
1262 | VPRINTK("port %u (no irq)\n", i); | |
6971ed1f | 1263 | if (ata_ratelimit()) |
cca3974e | 1264 | dev_printk(KERN_WARNING, host->dev, |
a9524a76 | 1265 | "interrupt on disabled port %u\n", i); |
1da177e4 | 1266 | } |
67846b30 JG |
1267 | |
1268 | irq_ack |= (1 << i); | |
1da177e4 LT |
1269 | } |
1270 | ||
1271 | if (irq_ack) { | |
1272 | writel(irq_ack, mmio + HOST_IRQ_STAT); | |
1273 | handled = 1; | |
1274 | } | |
1275 | ||
cca3974e | 1276 | spin_unlock(&host->lock); |
1da177e4 LT |
1277 | |
1278 | VPRINTK("EXIT\n"); | |
1279 | ||
1280 | return IRQ_RETVAL(handled); | |
1281 | } | |
1282 | ||
9a3d9eb0 | 1283 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
1da177e4 LT |
1284 | { |
1285 | struct ata_port *ap = qc->ap; | |
0d5ff566 | 1286 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
1da177e4 | 1287 | |
12fad3f9 TH |
1288 | if (qc->tf.protocol == ATA_PROT_NCQ) |
1289 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); | |
1290 | writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); | |
1da177e4 LT |
1291 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
1292 | ||
1293 | return 0; | |
1294 | } | |
1295 | ||
78cd52d0 TH |
1296 | static void ahci_freeze(struct ata_port *ap) |
1297 | { | |
0d5ff566 | 1298 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
78cd52d0 TH |
1299 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1300 | ||
1301 | /* turn IRQ off */ | |
1302 | writel(0, port_mmio + PORT_IRQ_MASK); | |
1303 | } | |
1304 | ||
1305 | static void ahci_thaw(struct ata_port *ap) | |
1306 | { | |
0d5ff566 | 1307 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
78cd52d0 TH |
1308 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1309 | u32 tmp; | |
1310 | ||
1311 | /* clear IRQ */ | |
1312 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1313 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
a718728f | 1314 | writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); |
78cd52d0 TH |
1315 | |
1316 | /* turn IRQ back on */ | |
1317 | writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); | |
1318 | } | |
1319 | ||
1320 | static void ahci_error_handler(struct ata_port *ap) | |
1321 | { | |
0d5ff566 | 1322 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
5457f219 | 1323 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1324 | ||
b51e9e5d | 1325 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
78cd52d0 | 1326 | /* restart engine */ |
5457f219 | 1327 | ahci_stop_engine(port_mmio); |
1328 | ahci_start_engine(port_mmio); | |
78cd52d0 TH |
1329 | } |
1330 | ||
1331 | /* perform recovery */ | |
4aeb0e32 | 1332 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset, |
f5914a46 | 1333 | ahci_postreset); |
78cd52d0 TH |
1334 | } |
1335 | ||
ad616ffb TH |
1336 | static void ahci_vt8251_error_handler(struct ata_port *ap) |
1337 | { | |
0d5ff566 | 1338 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
ad616ffb TH |
1339 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1340 | ||
1341 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { | |
1342 | /* restart engine */ | |
1343 | ahci_stop_engine(port_mmio); | |
1344 | ahci_start_engine(port_mmio); | |
1345 | } | |
1346 | ||
1347 | /* perform recovery */ | |
1348 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset, | |
1349 | ahci_postreset); | |
1350 | } | |
1351 | ||
78cd52d0 TH |
1352 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) |
1353 | { | |
1354 | struct ata_port *ap = qc->ap; | |
0d5ff566 | 1355 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
5457f219 | 1356 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
78cd52d0 TH |
1357 | |
1358 | if (qc->flags & ATA_QCFLAG_FAILED) | |
1359 | qc->err_mask |= AC_ERR_OTHER; | |
1360 | ||
1361 | if (qc->err_mask) { | |
1362 | /* make DMA engine forget about the failed command */ | |
5457f219 | 1363 | ahci_stop_engine(port_mmio); |
1364 | ahci_start_engine(port_mmio); | |
78cd52d0 TH |
1365 | } |
1366 | } | |
1367 | ||
438ac6d5 | 1368 | #ifdef CONFIG_PM |
c1332875 TH |
1369 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) |
1370 | { | |
cca3974e | 1371 | struct ahci_host_priv *hpriv = ap->host->private_data; |
c1332875 | 1372 | struct ahci_port_priv *pp = ap->private_data; |
0d5ff566 | 1373 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
c1332875 TH |
1374 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1375 | const char *emsg = NULL; | |
1376 | int rc; | |
1377 | ||
1378 | rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg); | |
8e16f941 TH |
1379 | if (rc == 0) |
1380 | ahci_power_down(port_mmio, hpriv->cap); | |
1381 | else { | |
c1332875 TH |
1382 | ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); |
1383 | ahci_init_port(port_mmio, hpriv->cap, | |
1384 | pp->cmd_slot_dma, pp->rx_fis_dma); | |
1385 | } | |
1386 | ||
1387 | return rc; | |
1388 | } | |
1389 | ||
1390 | static int ahci_port_resume(struct ata_port *ap) | |
1391 | { | |
1392 | struct ahci_port_priv *pp = ap->private_data; | |
cca3974e | 1393 | struct ahci_host_priv *hpriv = ap->host->private_data; |
0d5ff566 | 1394 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
c1332875 TH |
1395 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1396 | ||
8e16f941 | 1397 | ahci_power_up(port_mmio, hpriv->cap); |
c1332875 TH |
1398 | ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma); |
1399 | ||
1400 | return 0; | |
1401 | } | |
1402 | ||
1403 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) | |
1404 | { | |
cca3974e | 1405 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
0d5ff566 | 1406 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
c1332875 TH |
1407 | u32 ctl; |
1408 | ||
1409 | if (mesg.event == PM_EVENT_SUSPEND) { | |
1410 | /* AHCI spec rev1.1 section 8.3.3: | |
1411 | * Software must disable interrupts prior to requesting a | |
1412 | * transition of the HBA to D3 state. | |
1413 | */ | |
1414 | ctl = readl(mmio + HOST_CTL); | |
1415 | ctl &= ~HOST_IRQ_EN; | |
1416 | writel(ctl, mmio + HOST_CTL); | |
1417 | readl(mmio + HOST_CTL); /* flush */ | |
1418 | } | |
1419 | ||
1420 | return ata_pci_device_suspend(pdev, mesg); | |
1421 | } | |
1422 | ||
1423 | static int ahci_pci_device_resume(struct pci_dev *pdev) | |
1424 | { | |
cca3974e JG |
1425 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
1426 | struct ahci_host_priv *hpriv = host->private_data; | |
0d5ff566 | 1427 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
c1332875 TH |
1428 | int rc; |
1429 | ||
553c4aa6 TH |
1430 | rc = ata_pci_device_do_resume(pdev); |
1431 | if (rc) | |
1432 | return rc; | |
c1332875 TH |
1433 | |
1434 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { | |
1435 | rc = ahci_reset_controller(mmio, pdev); | |
1436 | if (rc) | |
1437 | return rc; | |
1438 | ||
648a88be TH |
1439 | ahci_init_controller(mmio, pdev, host->n_ports, |
1440 | host->ports[0]->flags, hpriv); | |
c1332875 TH |
1441 | } |
1442 | ||
cca3974e | 1443 | ata_host_resume(host); |
c1332875 TH |
1444 | |
1445 | return 0; | |
1446 | } | |
438ac6d5 | 1447 | #endif |
c1332875 | 1448 | |
254950cd TH |
1449 | static int ahci_port_start(struct ata_port *ap) |
1450 | { | |
cca3974e JG |
1451 | struct device *dev = ap->host->dev; |
1452 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
254950cd | 1453 | struct ahci_port_priv *pp; |
0d5ff566 | 1454 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
254950cd TH |
1455 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1456 | void *mem; | |
1457 | dma_addr_t mem_dma; | |
1458 | int rc; | |
1459 | ||
24dc5f33 | 1460 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
254950cd TH |
1461 | if (!pp) |
1462 | return -ENOMEM; | |
254950cd TH |
1463 | |
1464 | rc = ata_pad_alloc(ap, dev); | |
24dc5f33 | 1465 | if (rc) |
254950cd | 1466 | return rc; |
254950cd | 1467 | |
24dc5f33 TH |
1468 | mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, |
1469 | GFP_KERNEL); | |
1470 | if (!mem) | |
254950cd | 1471 | return -ENOMEM; |
254950cd TH |
1472 | memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); |
1473 | ||
1474 | /* | |
1475 | * First item in chunk of DMA memory: 32-slot command table, | |
1476 | * 32 bytes each in size | |
1477 | */ | |
1478 | pp->cmd_slot = mem; | |
1479 | pp->cmd_slot_dma = mem_dma; | |
1480 | ||
1481 | mem += AHCI_CMD_SLOT_SZ; | |
1482 | mem_dma += AHCI_CMD_SLOT_SZ; | |
1483 | ||
1484 | /* | |
1485 | * Second item: Received-FIS area | |
1486 | */ | |
1487 | pp->rx_fis = mem; | |
1488 | pp->rx_fis_dma = mem_dma; | |
1489 | ||
1490 | mem += AHCI_RX_FIS_SZ; | |
1491 | mem_dma += AHCI_RX_FIS_SZ; | |
1492 | ||
1493 | /* | |
1494 | * Third item: data area for storing a single command | |
1495 | * and its scatter-gather table | |
1496 | */ | |
1497 | pp->cmd_tbl = mem; | |
1498 | pp->cmd_tbl_dma = mem_dma; | |
1499 | ||
1500 | ap->private_data = pp; | |
1501 | ||
8e16f941 TH |
1502 | /* power up port */ |
1503 | ahci_power_up(port_mmio, hpriv->cap); | |
1504 | ||
0be0aa98 TH |
1505 | /* initialize port */ |
1506 | ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma); | |
254950cd TH |
1507 | |
1508 | return 0; | |
1509 | } | |
1510 | ||
1511 | static void ahci_port_stop(struct ata_port *ap) | |
1512 | { | |
cca3974e | 1513 | struct ahci_host_priv *hpriv = ap->host->private_data; |
0d5ff566 | 1514 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
254950cd | 1515 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
0be0aa98 TH |
1516 | const char *emsg = NULL; |
1517 | int rc; | |
254950cd | 1518 | |
0be0aa98 TH |
1519 | /* de-initialize port */ |
1520 | rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg); | |
1521 | if (rc) | |
1522 | ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); | |
254950cd TH |
1523 | } |
1524 | ||
0d5ff566 | 1525 | static void ahci_setup_port(struct ata_ioports *port, void __iomem *base, |
1da177e4 LT |
1526 | unsigned int port_idx) |
1527 | { | |
1528 | VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx); | |
0d5ff566 | 1529 | base = ahci_port_base(base, port_idx); |
1da177e4 LT |
1530 | VPRINTK("base now==0x%lx\n", base); |
1531 | ||
1532 | port->cmd_addr = base; | |
1533 | port->scr_addr = base + PORT_SCR; | |
1534 | ||
1535 | VPRINTK("EXIT\n"); | |
1536 | } | |
1537 | ||
1538 | static int ahci_host_init(struct ata_probe_ent *probe_ent) | |
1539 | { | |
1540 | struct ahci_host_priv *hpriv = probe_ent->private_data; | |
1541 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); | |
0d5ff566 | 1542 | void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR]; |
648a88be | 1543 | unsigned int i, cap_n_ports, using_dac; |
1da177e4 | 1544 | int rc; |
1da177e4 | 1545 | |
d91542c1 TH |
1546 | rc = ahci_reset_controller(mmio, pdev); |
1547 | if (rc) | |
1548 | return rc; | |
1da177e4 LT |
1549 | |
1550 | hpriv->cap = readl(mmio + HOST_CAP); | |
1551 | hpriv->port_map = readl(mmio + HOST_PORTS_IMPL); | |
648a88be | 1552 | cap_n_ports = ahci_nr_ports(hpriv->cap); |
1da177e4 LT |
1553 | |
1554 | VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n", | |
648a88be TH |
1555 | hpriv->cap, hpriv->port_map, cap_n_ports); |
1556 | ||
1557 | if (probe_ent->port_flags & AHCI_FLAG_HONOR_PI) { | |
1558 | unsigned int n_ports = cap_n_ports; | |
1559 | u32 port_map = hpriv->port_map; | |
1560 | int max_port = 0; | |
1561 | ||
1562 | for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) { | |
1563 | if (port_map & (1 << i)) { | |
1564 | n_ports--; | |
1565 | port_map &= ~(1 << i); | |
1566 | max_port = i; | |
1567 | } else | |
1568 | probe_ent->dummy_port_mask |= 1 << i; | |
1569 | } | |
1570 | ||
1571 | if (n_ports || port_map) | |
1572 | dev_printk(KERN_WARNING, &pdev->dev, | |
1573 | "nr_ports (%u) and implemented port map " | |
1574 | "(0x%x) don't match\n", | |
1575 | cap_n_ports, hpriv->port_map); | |
1576 | ||
1577 | probe_ent->n_ports = max_port + 1; | |
1578 | } else | |
1579 | probe_ent->n_ports = cap_n_ports; | |
1da177e4 LT |
1580 | |
1581 | using_dac = hpriv->cap & HOST_CAP_64; | |
1582 | if (using_dac && | |
1583 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { | |
1584 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
1585 | if (rc) { | |
1586 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1587 | if (rc) { | |
a9524a76 JG |
1588 | dev_printk(KERN_ERR, &pdev->dev, |
1589 | "64-bit DMA enable failed\n"); | |
1da177e4 LT |
1590 | return rc; |
1591 | } | |
1592 | } | |
1da177e4 LT |
1593 | } else { |
1594 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
1595 | if (rc) { | |
a9524a76 JG |
1596 | dev_printk(KERN_ERR, &pdev->dev, |
1597 | "32-bit DMA enable failed\n"); | |
1da177e4 LT |
1598 | return rc; |
1599 | } | |
1600 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1601 | if (rc) { | |
a9524a76 JG |
1602 | dev_printk(KERN_ERR, &pdev->dev, |
1603 | "32-bit consistent DMA enable failed\n"); | |
1da177e4 LT |
1604 | return rc; |
1605 | } | |
1606 | } | |
1607 | ||
d91542c1 | 1608 | for (i = 0; i < probe_ent->n_ports; i++) |
0d5ff566 | 1609 | ahci_setup_port(&probe_ent->port[i], mmio, i); |
1da177e4 | 1610 | |
648a88be TH |
1611 | ahci_init_controller(mmio, pdev, probe_ent->n_ports, |
1612 | probe_ent->port_flags, hpriv); | |
1da177e4 LT |
1613 | |
1614 | pci_set_master(pdev); | |
1615 | ||
1616 | return 0; | |
1617 | } | |
1618 | ||
1da177e4 LT |
1619 | static void ahci_print_info(struct ata_probe_ent *probe_ent) |
1620 | { | |
1621 | struct ahci_host_priv *hpriv = probe_ent->private_data; | |
1622 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); | |
0d5ff566 | 1623 | void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR]; |
1da177e4 LT |
1624 | u32 vers, cap, impl, speed; |
1625 | const char *speed_s; | |
1626 | u16 cc; | |
1627 | const char *scc_s; | |
1628 | ||
1629 | vers = readl(mmio + HOST_VERSION); | |
1630 | cap = hpriv->cap; | |
1631 | impl = hpriv->port_map; | |
1632 | ||
1633 | speed = (cap >> 20) & 0xf; | |
1634 | if (speed == 1) | |
1635 | speed_s = "1.5"; | |
1636 | else if (speed == 2) | |
1637 | speed_s = "3"; | |
1638 | else | |
1639 | speed_s = "?"; | |
1640 | ||
1641 | pci_read_config_word(pdev, 0x0a, &cc); | |
c9f89475 | 1642 | if (cc == PCI_CLASS_STORAGE_IDE) |
1da177e4 | 1643 | scc_s = "IDE"; |
c9f89475 | 1644 | else if (cc == PCI_CLASS_STORAGE_SATA) |
1da177e4 | 1645 | scc_s = "SATA"; |
c9f89475 | 1646 | else if (cc == PCI_CLASS_STORAGE_RAID) |
1da177e4 LT |
1647 | scc_s = "RAID"; |
1648 | else | |
1649 | scc_s = "unknown"; | |
1650 | ||
a9524a76 JG |
1651 | dev_printk(KERN_INFO, &pdev->dev, |
1652 | "AHCI %02x%02x.%02x%02x " | |
1da177e4 LT |
1653 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
1654 | , | |
1da177e4 LT |
1655 | |
1656 | (vers >> 24) & 0xff, | |
1657 | (vers >> 16) & 0xff, | |
1658 | (vers >> 8) & 0xff, | |
1659 | vers & 0xff, | |
1660 | ||
1661 | ((cap >> 8) & 0x1f) + 1, | |
1662 | (cap & 0x1f) + 1, | |
1663 | speed_s, | |
1664 | impl, | |
1665 | scc_s); | |
1666 | ||
a9524a76 JG |
1667 | dev_printk(KERN_INFO, &pdev->dev, |
1668 | "flags: " | |
1da177e4 LT |
1669 | "%s%s%s%s%s%s" |
1670 | "%s%s%s%s%s%s%s\n" | |
1671 | , | |
1da177e4 LT |
1672 | |
1673 | cap & (1 << 31) ? "64bit " : "", | |
1674 | cap & (1 << 30) ? "ncq " : "", | |
1675 | cap & (1 << 28) ? "ilck " : "", | |
1676 | cap & (1 << 27) ? "stag " : "", | |
1677 | cap & (1 << 26) ? "pm " : "", | |
1678 | cap & (1 << 25) ? "led " : "", | |
1679 | ||
1680 | cap & (1 << 24) ? "clo " : "", | |
1681 | cap & (1 << 19) ? "nz " : "", | |
1682 | cap & (1 << 18) ? "only " : "", | |
1683 | cap & (1 << 17) ? "pmp " : "", | |
1684 | cap & (1 << 15) ? "pio " : "", | |
1685 | cap & (1 << 14) ? "slum " : "", | |
1686 | cap & (1 << 13) ? "part " : "" | |
1687 | ); | |
1688 | } | |
1689 | ||
24dc5f33 | 1690 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 LT |
1691 | { |
1692 | static int printed_version; | |
24dc5f33 TH |
1693 | unsigned int board_idx = (unsigned int) ent->driver_data; |
1694 | struct device *dev = &pdev->dev; | |
1695 | struct ata_probe_ent *probe_ent; | |
1da177e4 | 1696 | struct ahci_host_priv *hpriv; |
1da177e4 LT |
1697 | int rc; |
1698 | ||
1699 | VPRINTK("ENTER\n"); | |
1700 | ||
12fad3f9 TH |
1701 | WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
1702 | ||
1da177e4 | 1703 | if (!printed_version++) |
a9524a76 | 1704 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 1705 | |
24dc5f33 | 1706 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
1707 | if (rc) |
1708 | return rc; | |
1709 | ||
0d5ff566 TH |
1710 | rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); |
1711 | if (rc == -EBUSY) | |
24dc5f33 | 1712 | pcim_pin_device(pdev); |
0d5ff566 | 1713 | if (rc) |
24dc5f33 | 1714 | return rc; |
1da177e4 | 1715 | |
24dc5f33 | 1716 | if (pci_enable_msi(pdev)) |
907f4678 | 1717 | pci_intx(pdev, 1); |
1da177e4 | 1718 | |
24dc5f33 TH |
1719 | probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL); |
1720 | if (probe_ent == NULL) | |
1721 | return -ENOMEM; | |
1da177e4 | 1722 | |
1da177e4 LT |
1723 | probe_ent->dev = pci_dev_to_dev(pdev); |
1724 | INIT_LIST_HEAD(&probe_ent->node); | |
1725 | ||
24dc5f33 TH |
1726 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
1727 | if (!hpriv) | |
1728 | return -ENOMEM; | |
1da177e4 LT |
1729 | |
1730 | probe_ent->sht = ahci_port_info[board_idx].sht; | |
cca3974e | 1731 | probe_ent->port_flags = ahci_port_info[board_idx].flags; |
1da177e4 LT |
1732 | probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask; |
1733 | probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask; | |
1734 | probe_ent->port_ops = ahci_port_info[board_idx].port_ops; | |
1735 | ||
1736 | probe_ent->irq = pdev->irq; | |
1d6f359a | 1737 | probe_ent->irq_flags = IRQF_SHARED; |
0d5ff566 | 1738 | probe_ent->iomap = pcim_iomap_table(pdev); |
1da177e4 LT |
1739 | probe_ent->private_data = hpriv; |
1740 | ||
1741 | /* initialize adapter */ | |
1742 | rc = ahci_host_init(probe_ent); | |
1743 | if (rc) | |
24dc5f33 | 1744 | return rc; |
1da177e4 | 1745 | |
cca3974e | 1746 | if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) && |
71f0737b | 1747 | (hpriv->cap & HOST_CAP_NCQ)) |
cca3974e | 1748 | probe_ent->port_flags |= ATA_FLAG_NCQ; |
12fad3f9 | 1749 | |
1da177e4 LT |
1750 | ahci_print_info(probe_ent); |
1751 | ||
24dc5f33 TH |
1752 | if (!ata_device_add(probe_ent)) |
1753 | return -ENODEV; | |
1da177e4 | 1754 | |
24dc5f33 | 1755 | devm_kfree(dev, probe_ent); |
1da177e4 | 1756 | return 0; |
907f4678 | 1757 | } |
1da177e4 LT |
1758 | |
1759 | static int __init ahci_init(void) | |
1760 | { | |
b7887196 | 1761 | return pci_register_driver(&ahci_pci_driver); |
1da177e4 LT |
1762 | } |
1763 | ||
1da177e4 LT |
1764 | static void __exit ahci_exit(void) |
1765 | { | |
1766 | pci_unregister_driver(&ahci_pci_driver); | |
1767 | } | |
1768 | ||
1769 | ||
1770 | MODULE_AUTHOR("Jeff Garzik"); | |
1771 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); | |
1772 | MODULE_LICENSE("GPL"); | |
1773 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); | |
6885433c | 1774 | MODULE_VERSION(DRV_VERSION); |
1da177e4 LT |
1775 | |
1776 | module_init(ahci_init); | |
1777 | module_exit(ahci_exit); |