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ata: libahci: replace obsolete simple_strtoul() with kstrtouint()
[linux-block.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <tj@kernel.org>
af36d7f0
JG		 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
1da177e4
LT		 38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
87507cfd 41#include <linux/dma-mapping.h>
a9524a76 42#include <linux/device.h>
edc93052 43#include <linux/dmi.h>
5a0e3ad6 44#include <linux/gfp.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4 47#include <linux/libata.h>
365cfa1e 48#include "ahci.h"
1da177e4
LT		 49
50#define DRV_NAME "ahci"
7d50b60b 51#define DRV_VERSION "3.0"
1da177e4 52
1da177e4 53enum {
318893e1 54 AHCI_PCI_BAR_STA2X11 = 0,
7f9c9f8e 55 AHCI_PCI_BAR_ENMOTUS = 2,
318893e1 56 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 57};
58
59enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
63 board_ahci_nosntf,
5f173107 64 board_ahci_yes_fbs,
1da177e4 65
441577ef
TH		 66 /* board IDs for specific chipsets in alphabetical order */
67 board_ahci_mcp65,
83f2b963
TH		 68 board_ahci_mcp77,
69 board_ahci_mcp89,
441577ef
TH		 70 board_ahci_mv,
71 board_ahci_sb600,
72 board_ahci_sb700, /* for SB700 and SB800 */
73 board_ahci_vt8251,
74
75 /* aliases */
76 board_ahci_mcp_linux = board_ahci_mcp65,
77 board_ahci_mcp67 = board_ahci_mcp65,
78 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 79 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 80};
81
2dcb407e 82static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
a1efdaba
TH		 83static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
cb85696d
JL		 85static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
86static bool is_mcp89_apple(struct pci_dev *pdev);
a1efdaba
TH		 87static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
438ac6d5 89#ifdef CONFIG_PM
c1332875
TH		 90static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
91static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 92#endif
ad616ffb 93
fad16e7a
TH		 94static struct scsi_host_template ahci_sht = {
95 AHCI_SHT("ahci"),
96};
97
029cfd6b
TH		 98static struct ata_port_operations ahci_vt8251_ops = {
99 .inherits = &ahci_ops,
a1efdaba 100 .hardreset = ahci_vt8251_hardreset,
029cfd6b 101};
edc93052 102
029cfd6b
TH		 103static struct ata_port_operations ahci_p5wdh_ops = {
104 .inherits = &ahci_ops,
a1efdaba 105 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 106};
107
98ac62de 108static const struct ata_port_info ahci_port_info[] = {
441577ef 109 /* by features */
facb8fa6 110 [board_ahci] = {
1188c0d8 111 .flags = AHCI_FLAG_COMMON,
14bdef98 112 .pio_mask = ATA_PIO4,
469248ab 113 .udma_mask = ATA_UDMA6,
1da177e4
LT		 114 .port_ops = &ahci_ops,
115 },
facb8fa6 116 [board_ahci_ign_iferr] = {
441577ef 117 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 118 .flags = AHCI_FLAG_COMMON,
14bdef98 119 .pio_mask = ATA_PIO4,
469248ab 120 .udma_mask = ATA_UDMA6,
441577ef 121 .port_ops = &ahci_ops,
bf2af2a2 122 },
facb8fa6 123 [board_ahci_nosntf] = {
441577ef 124 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 125 .flags = AHCI_FLAG_COMMON,
14bdef98 126 .pio_mask = ATA_PIO4,
469248ab 127 .udma_mask = ATA_UDMA6,
41669553
TH		 128 .port_ops = &ahci_ops,
129 },
facb8fa6 130 [board_ahci_yes_fbs] = {
5f173107
TH		 131 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
132 .flags = AHCI_FLAG_COMMON,
133 .pio_mask = ATA_PIO4,
134 .udma_mask = ATA_UDMA6,
135 .port_ops = &ahci_ops,
136 },
441577ef 137 /* by chipsets */
facb8fa6 138 [board_ahci_mcp65] = {
83f2b963
TH		 139 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
140 AHCI_HFLAG_YES_NCQ),
ae01b249 141 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 142 .pio_mask = ATA_PIO4,
143 .udma_mask = ATA_UDMA6,
144 .port_ops = &ahci_ops,
145 },
facb8fa6 146 [board_ahci_mcp77] = {
83f2b963
TH		 147 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
148 .flags = AHCI_FLAG_COMMON,
149 .pio_mask = ATA_PIO4,
150 .udma_mask = ATA_UDMA6,
151 .port_ops = &ahci_ops,
152 },
facb8fa6 153 [board_ahci_mcp89] = {
83f2b963 154 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 155 .flags = AHCI_FLAG_COMMON,
14bdef98 156 .pio_mask = ATA_PIO4,
469248ab 157 .udma_mask = ATA_UDMA6,
441577ef 158 .port_ops = &ahci_ops,
55a61604 159 },
facb8fa6 160 [board_ahci_mv] = {
417a1a6d 161 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 162 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 163 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 164 .pio_mask = ATA_PIO4,
cd70c266
JG		 165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_ops,
167 },
facb8fa6 168 [board_ahci_sb600] = {
441577ef
TH		 169 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
170 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
171 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 172 .flags = AHCI_FLAG_COMMON,
14bdef98 173 .pio_mask = ATA_PIO4,
e39fc8c9 174 .udma_mask = ATA_UDMA6,
345347c5 175 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 176 },
facb8fa6 177 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 178 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 179 .flags = AHCI_FLAG_COMMON,
180 .pio_mask = ATA_PIO4,
181 .udma_mask = ATA_UDMA6,
345347c5 182 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 183 },
facb8fa6 184 [board_ahci_vt8251] = {
441577ef 185 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 186 .flags = AHCI_FLAG_COMMON,
187 .pio_mask = ATA_PIO4,
188 .udma_mask = ATA_UDMA6,
441577ef 189 .port_ops = &ahci_vt8251_ops,
1b677afd 190 },
1da177e4
LT		 191};
192
3b7d697d 193static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 194 /* Intel */
54bb3a94
JG		 195 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
196 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
197 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
198 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
199 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 200 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 201 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
202 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
203 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
204 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 205 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 206 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 207 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
208 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
209 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
210 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
211 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
212 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
213 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
214 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
215 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
216 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
217 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
218 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
219 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
220 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 222 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
223 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 224 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 225 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 226 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 227 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
228 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 229 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 230 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 231 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 232 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 233 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 234 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 235 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
236 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
237 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
238 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
239 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
240 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 241 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
242 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
243 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 244 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 245 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 246 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
247 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
248 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
249 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
250 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
251 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
2cab7a4c 252 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66
SH		 253 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
254 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
255 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
256 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
257 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
258 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
259 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
260 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
77b12bc9
JR		 261 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
262 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
263 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
264 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
265 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
266 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
267 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
268 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
29e674dd
SH		 269 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
270 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
271 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
272 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
273 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
274 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
275 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
276 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
277 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
278 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
279 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
280 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
efda332c
JR		 285 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
286 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
151743fd
JR		 287 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
288 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
289 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
290 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
291 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
292 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
293 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
294 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
1cfc7df3 295 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
9f961a5f
JR		 296 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
297 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
298 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
299 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
fe7fa31a 300
e34bb370
TH		 301 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
302 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
303 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
1fefb8fd
BH		 304 /* JMicron 362B and 362C have an AHCI function with IDE class code */
305 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
306 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
fe7fa31a
JG		 307
308 /* ATI */
c65ec1c2 309 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 310 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
311 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
312 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
313 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
314 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
315 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 316
e2dd90b1 317 /* AMD */
5deab536 318 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
fafe5c3d 319 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
e2dd90b1
SH		 320 /* AMD is using RAID class only for ahci controllers */
321 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
322 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
323
fe7fa31a 324 /* VIA */
54bb3a94 325 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 326 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 327
328 /* NVIDIA */
e297d99e
TH		 329 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
330 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
331 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
332 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
333 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
334 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
335 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
336 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 337 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
338 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
339 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
340 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
341 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
342 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
343 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
344 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
345 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
346 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
347 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
348 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
349 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
350 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
351 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
352 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
353 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
354 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
355 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
356 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
357 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
358 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
359 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
360 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
361 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
362 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
363 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
364 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
365 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
366 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
367 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
368 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
369 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
370 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
371 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
372 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
373 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
374 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
375 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
376 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
377 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
378 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
379 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
380 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
381 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
382 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
383 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
384 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
385 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
386 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
387 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
388 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
389 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
390 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
391 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
392 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
393 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
394 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
395 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
396 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
397 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
398 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
399 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
400 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
401 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
402 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
403 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
404 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
405 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
406 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
407 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
408 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
409 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
410 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
411 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
412 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 413
95916edd 414 /* SiS */
20e2de4a
TH		 415 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
416 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
417 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 418
318893e1
AR		 419 /* ST Microelectronics */
420 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
421
cd70c266
JG		 422 /* Marvell */
423 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 424 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
69fd3157 425 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
10aca06c
AH		 426 .class = PCI_CLASS_STORAGE_SATA_AHCI,
427 .class_mask = 0xffffff,
5f173107 428 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
69fd3157 429 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
467b41c6 430 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
e098f5cb
SG		 431 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
432 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
433 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
69fd3157 434 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
642d8925 435 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
fcce9a35
GS		 436 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
437 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
69fd3157 438 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
17c60c6b 439 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
69fd3157 440 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
50be5e36 441 .driver_data = board_ahci_yes_fbs },
6d5278a6
SB		 442 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
443 .driver_data = board_ahci_yes_fbs },
cd70c266 444
c77a036b
MN		 445 /* Promise */
446 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
447
c9703765 448 /* Asmedia */
7b4f6eca
AC		 449 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
450 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
451 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
452 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
c9703765 453
7f9c9f8e
HD		 454 /* Enmotus */
455 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
456
415ae2b5
JG		 457 /* Generic, PCI class code for AHCI */
458 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 459 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 460
1da177e4
LT		 461 { } /* terminate list */
462};
463
464
465static struct pci_driver ahci_pci_driver = {
466 .name = DRV_NAME,
467 .id_table = ahci_pci_tbl,
468 .probe = ahci_init_one,
24dc5f33 469 .remove = ata_pci_remove_one,
438ac6d5 470#ifdef CONFIG_PM
c1332875 471 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 472 .resume = ahci_pci_device_resume,
473#endif
474};
1da177e4 475
365cfa1e
AV		 476#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
477static int marvell_enable;
478#else
479static int marvell_enable = 1;
480#endif
481module_param(marvell_enable, int, 0644);
482MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 483
1da177e4 484
365cfa1e
AV		 485static void ahci_pci_save_initial_config(struct pci_dev *pdev,
486 struct ahci_host_priv *hpriv)
487{
488 unsigned int force_port_map = 0;
489 unsigned int mask_port_map = 0;
67846b30 490
365cfa1e
AV		 491 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
492 dev_info(&pdev->dev, "JMB361 has only one port\n");
493 force_port_map = 1;
1da177e4
LT		 494 }
495
365cfa1e
AV		 496 /*
497 * Temporary Marvell 6145 hack: PATA port presence
498 * is asserted through the standard AHCI port
499 * presence register, as bit 4 (counting from 0)
d28f87aa 500 */
365cfa1e
AV		 501 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
502 if (pdev->device == 0x6121)
503 mask_port_map = 0x3;
504 else
505 mask_port_map = 0xf;
506 dev_info(&pdev->dev,
507 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
508 }
1da177e4 509
365cfa1e
AV		 510 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
511 mask_port_map);
1da177e4
LT		 512}
513
365cfa1e 514static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 515{
365cfa1e 516 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 517
365cfa1e 518 ahci_reset_controller(host);
1da177e4 519
365cfa1e
AV		 520 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
521 struct ahci_host_priv *hpriv = host->private_data;
522 u16 tmp16;
d6ef3153 523
365cfa1e
AV		 524 /* configure PCS */
525 pci_read_config_word(pdev, 0x92, &tmp16);
526 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
527 tmp16 |= hpriv->port_map;
528 pci_write_config_word(pdev, 0x92, tmp16);
529 }
d6ef3153
SH		 530 }
531
1da177e4
LT		 532 return 0;
533}
534
365cfa1e 535static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 536{
365cfa1e
AV		 537 struct ahci_host_priv *hpriv = host->private_data;
538 struct pci_dev *pdev = to_pci_dev(host->dev);
539 void __iomem *port_mmio;
78cd52d0 540 u32 tmp;
365cfa1e 541 int mv;
78cd52d0 542
365cfa1e
AV		 543 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
544 if (pdev->device == 0x6121)
545 mv = 2;
546 else
547 mv = 4;
548 port_mmio = __ahci_port_base(host, mv);
78cd52d0 549
365cfa1e 550 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 551
365cfa1e
AV		 552 /* clear port IRQ */
553 tmp = readl(port_mmio + PORT_IRQ_STAT);
554 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
555 if (tmp)
556 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 557 }
558
365cfa1e 559 ahci_init_controller(host);
edc93052
TH		 560}
561
365cfa1e
AV		 562static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
563 unsigned long deadline)
d6ef3153 564{
365cfa1e
AV		 565 struct ata_port *ap = link->ap;
566 bool online;
d6ef3153
SH		 567 int rc;
568
365cfa1e 569 DPRINTK("ENTER\n");
d6ef3153 570
365cfa1e 571 ahci_stop_engine(ap);
d6ef3153 572
365cfa1e
AV		 573 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
574 deadline, &online, NULL);
d6ef3153
SH		 575
576 ahci_start_engine(ap);
d6ef3153 577
365cfa1e 578 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 579
365cfa1e
AV		 580 /* vt8251 doesn't clear BSY on signature FIS reception,
581 * request follow-up softreset.
582 */
583 return online ? -EAGAIN : rc;
7d50b60b
TH		 584}
585
365cfa1e
AV		 586static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
587 unsigned long deadline)
7d50b60b 588{
365cfa1e 589 struct ata_port *ap = link->ap;
1c954a4d 590 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 591 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
592 struct ata_taskfile tf;
593 bool online;
594 int rc;
7d50b60b 595
365cfa1e 596 ahci_stop_engine(ap);
028a2596 597
365cfa1e
AV		 598 /* clear D2H reception area to properly wait for D2H FIS */
599 ata_tf_init(link->device, &tf);
9bbb1b0e 600 tf.command = ATA_BUSY;
365cfa1e 601 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 602
365cfa1e
AV		 603 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
604 deadline, &online, NULL);
028a2596 605
365cfa1e 606 ahci_start_engine(ap);
c1332875 607
365cfa1e
AV		 608 /* The pseudo configuration device on SIMG4726 attached to
609 * ASUS P5W-DH Deluxe doesn't send signature FIS after
610 * hardreset if no device is attached to the first downstream
611 * port && the pseudo device locks up on SRST w/ PMP==0. To
612 * work around this, wait for !BSY only briefly. If BSY isn't
613 * cleared, perform CLO and proceed to IDENTIFY (achieved by
614 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
615 *
616 * Wait for two seconds. Devices attached to downstream port
617 * which can't process the following IDENTIFY after this will
618 * have to be reset again. For most cases, this should
619 * suffice while making probing snappish enough.
620 */
621 if (online) {
622 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
623 ahci_check_ready);
624 if (rc)
625 ahci_kick_engine(ap);
c1332875 626 }
c1332875
TH		 627 return rc;
628}
629
365cfa1e 630#ifdef CONFIG_PM
c1332875
TH		 631static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
632{
0a86e1c8 633 struct ata_host *host = pci_get_drvdata(pdev);
9b10ae86 634 struct ahci_host_priv *hpriv = host->private_data;
d8993349 635 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 636 u32 ctl;
637
9b10ae86
TH		 638 if (mesg.event & PM_EVENT_SUSPEND &&
639 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
a44fec1f
JP		 640 dev_err(&pdev->dev,
641 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 642 return -EIO;
643 }
644
3a2d5b70 645 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 646 /* AHCI spec rev1.1 section 8.3.3:
647 * Software must disable interrupts prior to requesting a
648 * transition of the HBA to D3 state.
649 */
650 ctl = readl(mmio + HOST_CTL);
651 ctl &= ~HOST_IRQ_EN;
652 writel(ctl, mmio + HOST_CTL);
653 readl(mmio + HOST_CTL); /* flush */
654 }
655
656 return ata_pci_device_suspend(pdev, mesg);
657}
658
659static int ahci_pci_device_resume(struct pci_dev *pdev)
660{
0a86e1c8 661 struct ata_host *host = pci_get_drvdata(pdev);
c1332875
TH		 662 int rc;
663
553c4aa6
TH		 664 rc = ata_pci_device_do_resume(pdev);
665 if (rc)
666 return rc;
c1332875 667
cb85696d
JL		 668 /* Apple BIOS helpfully mangles the registers on resume */
669 if (is_mcp89_apple(pdev))
670 ahci_mcp89_apple_enable(pdev);
671
c1332875 672 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 673 rc = ahci_pci_reset_controller(host);
c1332875
TH		 674 if (rc)
675 return rc;
676
781d6550 677 ahci_pci_init_controller(host);
c1332875
TH		 678 }
679
cca3974e 680 ata_host_resume(host);
c1332875
TH		 681
682 return 0;
683}
438ac6d5 684#endif
c1332875 685
4447d351 686static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 687{
1da177e4 688 int rc;
1da177e4 689
318893e1
AR		 690 /*
691 * If the device fixup already set the dma_mask to some non-standard
692 * value, don't extend it here. This happens on STA2X11, for example.
693 */
694 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
695 return 0;
696
1da177e4 697 if (using_dac &&
6a35528a
YH		 698 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
699 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 700 if (rc) {
284901a9 701 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 702 if (rc) {
a44fec1f
JP		 703 dev_err(&pdev->dev,
704 "64-bit DMA enable failed\n");
1da177e4
LT		 705 return rc;
706 }
707 }
1da177e4 708 } else {
284901a9 709 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 710 if (rc) {
a44fec1f 711 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 712 return rc;
713 }
284901a9 714 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 715 if (rc) {
a44fec1f
JP		 716 dev_err(&pdev->dev,
717 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 718 return rc;
719 }
720 }
1da177e4
LT		 721 return 0;
722}
723
439fcaec
AV		 724static void ahci_pci_print_info(struct ata_host *host)
725{
726 struct pci_dev *pdev = to_pci_dev(host->dev);
727 u16 cc;
728 const char *scc_s;
729
730 pci_read_config_word(pdev, 0x0a, &cc);
731 if (cc == PCI_CLASS_STORAGE_IDE)
732 scc_s = "IDE";
733 else if (cc == PCI_CLASS_STORAGE_SATA)
734 scc_s = "SATA";
735 else if (cc == PCI_CLASS_STORAGE_RAID)
736 scc_s = "RAID";
737 else
738 scc_s = "unknown";
739
740 ahci_print_info(host, scc_s);
741}
742
edc93052
TH		 743/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
744 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
745 * support PMP and the 4726 either directly exports the device
746 * attached to the first downstream port or acts as a hardware storage
747 * controller and emulate a single ATA device (can be RAID 0/1 or some
748 * other configuration).
749 *
750 * When there's no device attached to the first downstream port of the
751 * 4726, "Config Disk" appears, which is a pseudo ATA device to
752 * configure the 4726. However, ATA emulation of the device is very
753 * lame. It doesn't send signature D2H Reg FIS after the initial
754 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
755 *
756 * The following function works around the problem by always using
757 * hardreset on the port and not depending on receiving signature FIS
758 * afterward. If signature FIS isn't received soon, ATA class is
759 * assumed without follow-up softreset.
760 */
761static void ahci_p5wdh_workaround(struct ata_host *host)
762{
763 static struct dmi_system_id sysids[] = {
764 {
765 .ident = "P5W DH Deluxe",
766 .matches = {
767 DMI_MATCH(DMI_SYS_VENDOR,
768 "ASUSTEK COMPUTER INC"),
769 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
770 },
771 },
772 { }
773 };
774 struct pci_dev *pdev = to_pci_dev(host->dev);
775
776 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
777 dmi_check_system(sysids)) {
778 struct ata_port *ap = host->ports[1];
779
a44fec1f
JP		 780 dev_info(&pdev->dev,
781 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 782
783 ap->ops = &ahci_p5wdh_ops;
784 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
785 }
786}
787
cb85696d
JL		 788/*
789 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
790 * booting in BIOS compatibility mode. We restore the registers but not ID.
791 */
792static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
793{
794 u32 val;
795
796 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
797
798 pci_read_config_dword(pdev, 0xf8, &val);
799 val |= 1 << 0x1b;
800 /* the following changes the device ID, but appears not to affect function */
801 /* val = (val & ~0xf0000000) | 0x80000000; */
802 pci_write_config_dword(pdev, 0xf8, val);
803
804 pci_read_config_dword(pdev, 0x54c, &val);
805 val |= 1 << 0xc;
806 pci_write_config_dword(pdev, 0x54c, val);
807
808 pci_read_config_dword(pdev, 0x4a4, &val);
809 val &= 0xff;
810 val |= 0x01060100;
811 pci_write_config_dword(pdev, 0x4a4, val);
812
813 pci_read_config_dword(pdev, 0x54c, &val);
814 val &= ~(1 << 0xc);
815 pci_write_config_dword(pdev, 0x54c, val);
816
817 pci_read_config_dword(pdev, 0xf8, &val);
818 val &= ~(1 << 0x1b);
819 pci_write_config_dword(pdev, 0xf8, val);
820}
821
822static bool is_mcp89_apple(struct pci_dev *pdev)
823{
824 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
825 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
826 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
827 pdev->subsystem_device == 0xcb89;
828}
829
2fcad9d2
TH		 830/* only some SB600 ahci controllers can do 64bit DMA */
831static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 832{
833 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 834 /*
835 * The oldest version known to be broken is 0901 and
836 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 837 * Enable 64bit DMA on 1501 and anything newer.
838 *
03d783bf
TH		 839 * Please read bko#9412 for more info.
840 */
58a09b38
SH		 841 {
842 .ident = "ASUS M2A-VM",
843 .matches = {
844 DMI_MATCH(DMI_BOARD_VENDOR,
845 "ASUSTeK Computer INC."),
846 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
847 },
03d783bf 848 .driver_data = "20071026", /* yyyymmdd */
58a09b38 849 },
e65cc194
MN		 850 /*
851 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
852 * support 64bit DMA.
853 *
854 * BIOS versions earlier than 1.5 had the Manufacturer DMI
855 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
856 * This spelling mistake was fixed in BIOS version 1.5, so
857 * 1.5 and later have the Manufacturer as
858 * "MICRO-STAR INTERNATIONAL CO.,LTD".
859 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
860 *
861 * BIOS versions earlier than 1.9 had a Board Product Name
862 * DMI field of "MS-7376". This was changed to be
863 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
864 * match on DMI_BOARD_NAME of "MS-7376".
865 */
866 {
867 .ident = "MSI K9A2 Platinum",
868 .matches = {
869 DMI_MATCH(DMI_BOARD_VENDOR,
870 "MICRO-STAR INTER"),
871 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
872 },
873 },
ff0173c1
MN		 874 /*
875 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
876 * 64bit DMA.
877 *
878 * This board also had the typo mentioned above in the
879 * Manufacturer DMI field (fixed in BIOS version 1.5), so
880 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
881 */
882 {
883 .ident = "MSI K9AGM2",
884 .matches = {
885 DMI_MATCH(DMI_BOARD_VENDOR,
886 "MICRO-STAR INTER"),
887 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
888 },
889 },
3c4aa91f
MN		 890 /*
891 * All BIOS versions for the Asus M3A support 64bit DMA.
892 * (all release versions from 0301 to 1206 were tested)
893 */
894 {
895 .ident = "ASUS M3A",
896 .matches = {
897 DMI_MATCH(DMI_BOARD_VENDOR,
898 "ASUSTeK Computer INC."),
899 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
900 },
901 },
58a09b38
SH		 902 { }
903 };
03d783bf 904 const struct dmi_system_id *match;
2fcad9d2
TH		 905 int year, month, date;
906 char buf[9];
58a09b38 907
03d783bf 908 match = dmi_first_match(sysids);
58a09b38 909 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 910 !match)
58a09b38
SH		 911 return false;
912
e65cc194
MN		 913 if (!match->driver_data)
914 goto enable_64bit;
915
2fcad9d2
TH		 916 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
917 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 918
e65cc194
MN		 919 if (strcmp(buf, match->driver_data) >= 0)
920 goto enable_64bit;
921 else {
a44fec1f
JP		 922 dev_warn(&pdev->dev,
923 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
924 match->ident);
2fcad9d2
TH		 925 return false;
926 }
e65cc194
MN		 927
928enable_64bit:
a44fec1f 929 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 930 return true;
58a09b38
SH		 931}
932
1fd68434
RW		 933static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
934{
935 static const struct dmi_system_id broken_systems[] = {
936 {
937 .ident = "HP Compaq nx6310",
938 .matches = {
939 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
940 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
941 },
942 /* PCI slot number of the controller */
943 .driver_data = (void *)0x1FUL,
944 },
d2f9c061
MR		 945 {
946 .ident = "HP Compaq 6720s",
947 .matches = {
948 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
949 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
950 },
951 /* PCI slot number of the controller */
952 .driver_data = (void *)0x1FUL,
953 },
1fd68434
RW		 954
955 { } /* terminate list */
956 };
957 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
958
959 if (dmi) {
960 unsigned long slot = (unsigned long)dmi->driver_data;
961 /* apply the quirk only to on-board controllers */
962 return slot == PCI_SLOT(pdev->devfn);
963 }
964
965 return false;
966}
967
9b10ae86
TH		 968static bool ahci_broken_suspend(struct pci_dev *pdev)
969{
970 static const struct dmi_system_id sysids[] = {
971 /*
972 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
973 * to the harddisk doesn't become online after
974 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 975 *
976 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
977 *
978 * Use dates instead of versions to match as HP is
979 * apparently recycling both product and version
980 * strings.
981 *
982 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 983 */
984 {
985 .ident = "dv4",
986 .matches = {
987 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
988 DMI_MATCH(DMI_PRODUCT_NAME,
989 "HP Pavilion dv4 Notebook PC"),
990 },
9deb3431 991 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 992 },
993 {
994 .ident = "dv5",
995 .matches = {
996 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
997 DMI_MATCH(DMI_PRODUCT_NAME,
998 "HP Pavilion dv5 Notebook PC"),
999 },
9deb3431 1000 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 1001 },
1002 {
1003 .ident = "dv6",
1004 .matches = {
1005 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1006 DMI_MATCH(DMI_PRODUCT_NAME,
1007 "HP Pavilion dv6 Notebook PC"),
1008 },
9deb3431 1009 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 1010 },
1011 {
1012 .ident = "HDX18",
1013 .matches = {
1014 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1015 DMI_MATCH(DMI_PRODUCT_NAME,
1016 "HP HDX18 Notebook PC"),
1017 },
9deb3431 1018 .driver_data = "20090430", /* F.23 */
9b10ae86 1019 },
cedc9bf9
TH		 1020 /*
1021 * Acer eMachines G725 has the same problem. BIOS
1022 * V1.03 is known to be broken. V3.04 is known to
25985edc 1023 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 1024 * that we don't have much idea about. For now,
1025 * blacklist anything older than V3.04.
9deb3431
TH		 1026 *
1027 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 1028 */
1029 {
1030 .ident = "G725",
1031 .matches = {
1032 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1033 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1034 },
9deb3431 1035 .driver_data = "20091216", /* V3.04 */
cedc9bf9 1036 },
9b10ae86
TH		 1037 { } /* terminate list */
1038 };
1039 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 1040 int year, month, date;
1041 char buf[9];
9b10ae86
TH		 1042
1043 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1044 return false;
1045
9deb3431
TH		 1046 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1047 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 1048
9deb3431 1049 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 1050}
1051
5594639a
TH		 1052static bool ahci_broken_online(struct pci_dev *pdev)
1053{
1054#define ENCODE_BUSDEVFN(bus, slot, func) \
1055 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1056 static const struct dmi_system_id sysids[] = {
1057 /*
1058 * There are several gigabyte boards which use
1059 * SIMG5723s configured as hardware RAID. Certain
1060 * 5723 firmware revisions shipped there keep the link
1061 * online but fail to answer properly to SRST or
1062 * IDENTIFY when no device is attached downstream
1063 * causing libata to retry quite a few times leading
1064 * to excessive detection delay.
1065 *
1066 * As these firmwares respond to the second reset try
1067 * with invalid device signature, considering unknown
1068 * sig as offline works around the problem acceptably.
1069 */
1070 {
1071 .ident = "EP45-DQ6",
1072 .matches = {
1073 DMI_MATCH(DMI_BOARD_VENDOR,
1074 "Gigabyte Technology Co., Ltd."),
1075 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1076 },
1077 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1078 },
1079 {
1080 .ident = "EP45-DS5",
1081 .matches = {
1082 DMI_MATCH(DMI_BOARD_VENDOR,
1083 "Gigabyte Technology Co., Ltd."),
1084 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1085 },
1086 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1087 },
1088 { } /* terminate list */
1089 };
1090#undef ENCODE_BUSDEVFN
1091 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1092 unsigned int val;
1093
1094 if (!dmi)
1095 return false;
1096
1097 val = (unsigned long)dmi->driver_data;
1098
1099 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1100}
1101
8e513217 1102#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1103static void ahci_gtf_filter_workaround(struct ata_host *host)
1104{
1105 static const struct dmi_system_id sysids[] = {
1106 /*
1107 * Aspire 3810T issues a bunch of SATA enable commands
1108 * via _GTF including an invalid one and one which is
1109 * rejected by the device. Among the successful ones
1110 * is FPDMA non-zero offset enable which when enabled
1111 * only on the drive side leads to NCQ command
1112 * failures. Filter it out.
1113 */
1114 {
1115 .ident = "Aspire 3810T",
1116 .matches = {
1117 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1118 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1119 },
1120 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1121 },
1122 { }
1123 };
1124 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1125 unsigned int filter;
1126 int i;
1127
1128 if (!dmi)
1129 return;
1130
1131 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1132 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1133 filter, dmi->ident);
f80ae7e4
TH		 1134
1135 for (i = 0; i < host->n_ports; i++) {
1136 struct ata_port *ap = host->ports[i];
1137 struct ata_link *link;
1138 struct ata_device *dev;
1139
1140 ata_for_each_link(link, ap, EDGE)
1141 ata_for_each_dev(dev, link, ALL)
1142 dev->gtf_filter |= filter;
1143 }
1144}
8e513217
MT		 1145#else
1146static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1147{}
1148#endif
f80ae7e4 1149
e1ba8459 1150static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
7b92b4f6 1151 struct ahci_host_priv *hpriv)
5ca72c4f 1152{
7b92b4f6 1153 int rc, nvec;
5ca72c4f 1154
7b92b4f6
AG		 1155 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1156 goto intx;
1157
1158 rc = pci_msi_vec_count(pdev);
1159 if (rc < 0)
1160 goto intx;
1161
1162 /*
1163 * If number of MSIs is less than number of ports then Sharing Last
1164 * Message mode could be enforced. In this case assume that advantage
1165 * of multipe MSIs is negated and use single MSI mode instead.
1166 */
1167 if (rc < n_ports)
1168 goto single_msi;
1169
1170 nvec = rc;
1171 rc = pci_enable_msi_block(pdev, nvec);
1172 if (rc)
1173 goto intx;
5ca72c4f 1174
7b92b4f6
AG		 1175 return nvec;
1176
1177single_msi:
1178 rc = pci_enable_msi(pdev);
1179 if (rc)
1180 goto intx;
1181 return 1;
1182
1183intx:
5ca72c4f
AG		 1184 pci_intx(pdev, 1);
1185 return 0;
1186}
1187
1188/**
1189 * ahci_host_activate - start AHCI host, request IRQs and register it
1190 * @host: target ATA host
1191 * @irq: base IRQ number to request
1192 * @n_msis: number of MSIs allocated for this host
1193 * @irq_handler: irq_handler used when requesting IRQs
1194 * @irq_flags: irq_flags used when requesting IRQs
1195 *
1196 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1197 * when multiple MSIs were allocated. That is one MSI per port, starting
1198 * from @irq.
1199 *
1200 * LOCKING:
1201 * Inherited from calling layer (may sleep).
1202 *
1203 * RETURNS:
1204 * 0 on success, -errno otherwise.
1205 */
1206int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1207{
1208 int i, rc;
1209
1210 /* Sharing Last Message among several ports is not supported */
1211 if (n_msis < host->n_ports)
1212 return -EINVAL;
1213
1214 rc = ata_host_start(host);
1215 if (rc)
1216 return rc;
1217
1218 for (i = 0; i < host->n_ports; i++) {
c91bc6cc 1219 const char* desc;
b29900e6
AG		 1220 struct ahci_port_priv *pp = host->ports[i]->private_data;
1221
c91bc6cc
XF		 1222 /* pp is NULL for dummy ports */
1223 if (pp)
1224 desc = pp->irq_desc;
1225 else
1226 desc = dev_driver_string(host->dev);
1227
5ca72c4f
AG		 1228 rc = devm_request_threaded_irq(host->dev,
1229 irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED,
c91bc6cc 1230 desc, host->ports[i]);
5ca72c4f
AG		 1231 if (rc)
1232 goto out_free_irqs;
1233 }
1234
1235 for (i = 0; i < host->n_ports; i++)
1236 ata_port_desc(host->ports[i], "irq %d", irq + i);
1237
1238 rc = ata_host_register(host, &ahci_sht);
1239 if (rc)
1240 goto out_free_all_irqs;
1241
1242 return 0;
1243
1244out_free_all_irqs:
1245 i = host->n_ports;
1246out_free_irqs:
1247 for (i--; i >= 0; i--)
1248 devm_free_irq(host->dev, irq + i, host->ports[i]);
1249
1250 return rc;
1251}
1252
24dc5f33 1253static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1254{
e297d99e
TH		 1255 unsigned int board_id = ent->driver_data;
1256 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1257 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1258 struct device *dev = &pdev->dev;
1da177e4 1259 struct ahci_host_priv *hpriv;
4447d351 1260 struct ata_host *host;
5ca72c4f 1261 int n_ports, n_msis, i, rc;
318893e1 1262 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1263
1264 VPRINTK("ENTER\n");
1265
b429dd59 1266 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1267
06296a1e 1268 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1269
5b66c829
AC		 1270 /* The AHCI driver can only drive the SATA ports, the PATA driver
1271 can drive them all so if both drivers are selected make sure
1272 AHCI stays out of the way */
1273 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1274 return -ENODEV;
1275
cb85696d
JL		 1276 /* Apple BIOS on MCP89 prevents us using AHCI */
1277 if (is_mcp89_apple(pdev))
1278 ahci_mcp89_apple_enable(pdev);
c6353b45 1279
7a02267e
MN		 1280 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1281 * At the moment, we can only use the AHCI mode. Let the users know
1282 * that for SAS drives they're out of luck.
1283 */
1284 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1285 dev_info(&pdev->dev,
1286 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1287
7f9c9f8e 1288 /* Both Connext and Enmotus devices use non-standard BARs */
318893e1
AR		 1289 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1290 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
7f9c9f8e
HD		 1291 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1292 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
318893e1 1293
4447d351 1294 /* acquire resources */
24dc5f33 1295 rc = pcim_enable_device(pdev);
1da177e4
LT		 1296 if (rc)
1297 return rc;
1298
c4f7792c
TH		 1299 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1300 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1301 u8 map;
1302
1303 /* ICH6s share the same PCI ID for both piix and ahci
1304 * modes. Enabling ahci mode while MAP indicates
1305 * combined mode is a bad idea. Yield to ata_piix.
1306 */
1307 pci_read_config_byte(pdev, ICH_MAP, &map);
1308 if (map & 0x3) {
a44fec1f
JP		 1309 dev_info(&pdev->dev,
1310 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1311 return -ENODEV;
1312 }
1313 }
1314
6fec8871
PB		 1315 /* AHCI controllers often implement SFF compatible interface.
1316 * Grab all PCI BARs just in case.
1317 */
1318 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1319 if (rc == -EBUSY)
1320 pcim_pin_device(pdev);
1321 if (rc)
1322 return rc;
1323
24dc5f33
TH		 1324 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1325 if (!hpriv)
1326 return -ENOMEM;
417a1a6d
TH		 1327 hpriv->flags |= (unsigned long)pi.private_data;
1328
e297d99e
TH		 1329 /* MCP65 revision A1 and A2 can't do MSI */
1330 if (board_id == board_ahci_mcp65 &&
1331 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1332 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1333
e427fe04
SH		 1334 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1335 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1336 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1337
2fcad9d2
TH		 1338 /* only some SB600s can do 64bit DMA */
1339 if (ahci_sb600_enable_64bit(pdev))
1340 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1341
318893e1 1342 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1343
4447d351 1344 /* save initial config */
394d6e53 1345 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1346
4447d351 1347 /* prepare host */
453d3131
RH		 1348 if (hpriv->cap & HOST_CAP_NCQ) {
1349 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1350 /*
1351 * Auto-activate optimization is supposed to be
1352 * supported on all AHCI controllers indicating NCQ
1353 * capability, but it seems to be broken on some
1354 * chipsets including NVIDIAs.
1355 */
1356 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131 1357 pi.flags |= ATA_FLAG_FPDMA_AA;
40fb59e7
MC		 1358
1359 /*
1360 * All AHCI controllers should be forward-compatible
1361 * with the new auxiliary field. This code should be
1362 * conditionalized if any buggy AHCI controllers are
1363 * encountered.
1364 */
1365 pi.flags |= ATA_FLAG_FPDMA_AUX;
453d3131 1366 }
1da177e4 1367
7d50b60b
TH		 1368 if (hpriv->cap & HOST_CAP_PMP)
1369 pi.flags |= ATA_FLAG_PMP;
1370
0cbb0e77 1371 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1372
1fd68434
RW		 1373 if (ahci_broken_system_poweroff(pdev)) {
1374 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1375 dev_info(&pdev->dev,
1376 "quirky BIOS, skipping spindown on poweroff\n");
1377 }
1378
9b10ae86
TH		 1379 if (ahci_broken_suspend(pdev)) {
1380 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1381 dev_warn(&pdev->dev,
1382 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1383 }
1384
5594639a
TH		 1385 if (ahci_broken_online(pdev)) {
1386 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1387 dev_info(&pdev->dev,
1388 "online status unreliable, applying workaround\n");
1389 }
1390
837f5f8f
TH		 1391 /* CAP.NP sometimes indicate the index of the last enabled
1392 * port, at other times, that of the last possible port, so
1393 * determining the maximum port number requires looking at
1394 * both CAP.NP and port_map.
1395 */
1396 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1397
7b92b4f6
AG		 1398 n_msis = ahci_init_interrupts(pdev, n_ports, hpriv);
1399 if (n_msis > 1)
1400 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1401
837f5f8f 1402 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1403 if (!host)
1404 return -ENOMEM;
4447d351
TH		 1405 host->private_data = hpriv;
1406
f3d7f23f 1407 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1408 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f 1409 else
d2782d96 1410 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
886ad09f 1411
18f7ba4c
KCA		 1412 if (pi.flags & ATA_FLAG_EM)
1413 ahci_reset_em(host);
1414
4447d351 1415 for (i = 0; i < host->n_ports; i++) {
dab632e8 1416 struct ata_port *ap = host->ports[i];
4447d351 1417
318893e1
AR		 1418 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1419 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1420 0x100 + ap->port_no * 0x80, "port");
1421
18f7ba4c
KCA		 1422 /* set enclosure management message type */
1423 if (ap->flags & ATA_FLAG_EM)
008dbd61 1424 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1425
1426
dab632e8 1427 /* disabled/not-implemented port */
350756f6 1428 if (!(hpriv->port_map & (1 << i)))
dab632e8 1429 ap->ops = &ata_dummy_port_ops;
4447d351 1430 }
d447df14 1431
edc93052
TH		 1432 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1433 ahci_p5wdh_workaround(host);
1434
f80ae7e4
TH		 1435 /* apply gtf filter quirk */
1436 ahci_gtf_filter_workaround(host);
1437
4447d351
TH		 1438 /* initialize adapter */
1439 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1440 if (rc)
24dc5f33 1441 return rc;
1da177e4 1442
3303040d 1443 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1444 if (rc)
1445 return rc;
1da177e4 1446
781d6550 1447 ahci_pci_init_controller(host);
439fcaec 1448 ahci_pci_print_info(host);
1da177e4 1449
4447d351 1450 pci_set_master(pdev);
5ca72c4f
AG		 1451
1452 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1453 return ahci_host_activate(host, pdev->irq, n_msis);
1454
4447d351
TH		 1455 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1456 &ahci_sht);
907f4678 1457}
1da177e4 1458
2fc75da0 1459module_pci_driver(ahci_pci_driver);
1da177e4
LT		 1460
1461MODULE_AUTHOR("Jeff Garzik");
1462MODULE_DESCRIPTION("AHCI SATA low-level driver");
1463MODULE_LICENSE("GPL");
1464MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1465MODULE_VERSION(DRV_VERSION);
Linux 6.x block layer and io_uring tree(s)