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libata: add missing PM callbacks
[linux-2.6-block.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
1da177e4 44#include <scsi/scsi_host.h>
193515d5 45#include <scsi/scsi_cmnd.h>
1da177e4 46#include <linux/libata.h>
1da177e4
LT		 47
48#define DRV_NAME "ahci"
cb48cab7 49#define DRV_VERSION "2.1"
1da177e4
LT		 50
51
52enum {
53 AHCI_PCI_BAR = 5,
648a88be 54 AHCI_MAX_PORTS = 32,
1da177e4
LT		 55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
57 AHCI_USE_CLUSTERING = 0,
12fad3f9 58 AHCI_MAX_CMDS = 32,
dd410ff1 59 AHCI_CMD_SZ = 32,
12fad3f9 60 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
1da177e4 61 AHCI_RX_FIS_SZ = 256,
a0ea7328 62 AHCI_CMD_TBL_CDB = 0x40,
dd410ff1
TH		 63 AHCI_CMD_TBL_HDR_SZ = 0x80,
64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
65 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
66 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
1da177e4
LT		 67 AHCI_RX_FIS_SZ,
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
4b10e559 71 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 72 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 74
75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
0291f95f 76 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
78cd52d0 77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
1da177e4
LT		 78
79 board_ahci = 0,
648a88be
TH		 80 board_ahci_pi = 1,
81 board_ahci_vt8251 = 2,
82 board_ahci_ign_iferr = 3,
1da177e4
LT		 83
84 /* global controller registers */
85 HOST_CAP = 0x00, /* host capabilities */
86 HOST_CTL = 0x04, /* global host control */
87 HOST_IRQ_STAT = 0x08, /* interrupt status */
88 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
89 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
90
91 /* HOST_CTL bits */
92 HOST_RESET = (1 << 0), /* reset controller; self-clear */
93 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
94 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
95
96 /* HOST_CAP bits */
0be0aa98 97 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
22b49985 98 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
0be0aa98 99 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
979db803 100 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
dd410ff1 101 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
1da177e4
LT		 102
103 /* registers for each SATA port */
104 PORT_LST_ADDR = 0x00, /* command list DMA addr */
105 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
106 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
107 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
108 PORT_IRQ_STAT = 0x10, /* interrupt status */
109 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
110 PORT_CMD = 0x18, /* port command */
111 PORT_TFDATA = 0x20, /* taskfile data */
112 PORT_SIG = 0x24, /* device TF signature */
113 PORT_CMD_ISSUE = 0x38, /* command issue */
114 PORT_SCR = 0x28, /* SATA phy register block */
115 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
116 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
117 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
118 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
119
120 /* PORT_IRQ_{STAT,MASK} bits */
121 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
122 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
123 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
124 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
125 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
126 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
127 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
128 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
129
130 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
131 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
132 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
133 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
134 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
135 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
136 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
137 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
138 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
139
78cd52d0
TH		 140 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
141 PORT_IRQ_IF_ERR |
142 PORT_IRQ_CONNECT |
4296971d 143 PORT_IRQ_PHYRDY |
78cd52d0
TH		 144 PORT_IRQ_UNK_FIS,
145 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
146 PORT_IRQ_TF_ERR |
147 PORT_IRQ_HBUS_DATA_ERR,
148 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
149 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
150 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
1da177e4
LT		 151
152 /* PORT_CMD bits */
02eaa666 153 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
1da177e4
LT		 154 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
155 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
156 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 157 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 158 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
159 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
160 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
161
0be0aa98 162 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
1da177e4
LT		 163 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
164 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
165 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4 166
bf2af2a2 167 /* ap->flags bits */
4aeb0e32
TH		 168 AHCI_FLAG_NO_NCQ = (1 << 24),
169 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
648a88be 170 AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */
1da177e4
LT		 171};
172
173struct ahci_cmd_hdr {
174 u32 opts;
175 u32 status;
176 u32 tbl_addr;
177 u32 tbl_addr_hi;
178 u32 reserved[4];
179};
180
181struct ahci_sg {
182 u32 addr;
183 u32 addr_hi;
184 u32 reserved;
185 u32 flags_size;
186};
187
188struct ahci_host_priv {
1da177e4
LT		 189 u32 cap; /* cache of HOST_CAP register */
190 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
191};
192
193struct ahci_port_priv {
194 struct ahci_cmd_hdr *cmd_slot;
195 dma_addr_t cmd_slot_dma;
196 void *cmd_tbl;
197 dma_addr_t cmd_tbl_dma;
1da177e4
LT		 198 void *rx_fis;
199 dma_addr_t rx_fis_dma;
0291f95f 200 /* for NCQ spurious interrupt analysis */
0291f95f
TH		 201 unsigned int ncq_saw_d2h:1;
202 unsigned int ncq_saw_dmas:1;
afb2d552 203 unsigned int ncq_saw_sdb:1;
1da177e4
LT		 204};
205
206static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
207static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
208static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 209static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
7d12e780 210static irqreturn_t ahci_interrupt (int irq, void *dev_instance);
1da177e4 211static void ahci_irq_clear(struct ata_port *ap);
1da177e4
LT		 212static int ahci_port_start(struct ata_port *ap);
213static void ahci_port_stop(struct ata_port *ap);
1da177e4
LT		 214static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
215static void ahci_qc_prep(struct ata_queued_cmd *qc);
216static u8 ahci_check_status(struct ata_port *ap);
78cd52d0
TH		 217static void ahci_freeze(struct ata_port *ap);
218static void ahci_thaw(struct ata_port *ap);
219static void ahci_error_handler(struct ata_port *ap);
ad616ffb 220static void ahci_vt8251_error_handler(struct ata_port *ap);
78cd52d0 221static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
c1332875
TH		 222static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
223static int ahci_port_resume(struct ata_port *ap);
224static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
225static int ahci_pci_device_resume(struct pci_dev *pdev);
1da177e4 226
193515d5 227static struct scsi_host_template ahci_sht = {
1da177e4
LT		 228 .module = THIS_MODULE,
229 .name = DRV_NAME,
230 .ioctl = ata_scsi_ioctl,
231 .queuecommand = ata_scsi_queuecmd,
12fad3f9
TH		 232 .change_queue_depth = ata_scsi_change_queue_depth,
233 .can_queue = AHCI_MAX_CMDS - 1,
1da177e4
LT		 234 .this_id = ATA_SHT_THIS_ID,
235 .sg_tablesize = AHCI_MAX_SG,
1da177e4
LT		 236 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
237 .emulated = ATA_SHT_EMULATED,
238 .use_clustering = AHCI_USE_CLUSTERING,
239 .proc_name = DRV_NAME,
240 .dma_boundary = AHCI_DMA_BOUNDARY,
241 .slave_configure = ata_scsi_slave_config,
ccf68c34 242 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 243 .bios_param = ata_std_bios_param,
c1332875
TH		 244 .suspend = ata_scsi_device_suspend,
245 .resume = ata_scsi_device_resume,
1da177e4
LT		 246};
247
057ace5e 248static const struct ata_port_operations ahci_ops = {
1da177e4
LT		 249 .port_disable = ata_port_disable,
250
251 .check_status = ahci_check_status,
252 .check_altstatus = ahci_check_status,
1da177e4
LT		 253 .dev_select = ata_noop_dev_select,
254
255 .tf_read = ahci_tf_read,
256
1da177e4
LT		 257 .qc_prep = ahci_qc_prep,
258 .qc_issue = ahci_qc_issue,
259
1da177e4
LT		 260 .irq_handler = ahci_interrupt,
261 .irq_clear = ahci_irq_clear,
246ce3b6
AI		 262 .irq_on = ata_dummy_irq_on,
263 .irq_ack = ata_dummy_irq_ack,
1da177e4
LT		 264
265 .scr_read = ahci_scr_read,
266 .scr_write = ahci_scr_write,
267
78cd52d0
TH		 268 .freeze = ahci_freeze,
269 .thaw = ahci_thaw,
270
271 .error_handler = ahci_error_handler,
272 .post_internal_cmd = ahci_post_internal_cmd,
273
c1332875
TH		 274 .port_suspend = ahci_port_suspend,
275 .port_resume = ahci_port_resume,
276
1da177e4
LT		 277 .port_start = ahci_port_start,
278 .port_stop = ahci_port_stop,
1da177e4
LT		 279};
280
ad616ffb
TH		 281static const struct ata_port_operations ahci_vt8251_ops = {
282 .port_disable = ata_port_disable,
283
284 .check_status = ahci_check_status,
285 .check_altstatus = ahci_check_status,
286 .dev_select = ata_noop_dev_select,
287
288 .tf_read = ahci_tf_read,
289
290 .qc_prep = ahci_qc_prep,
291 .qc_issue = ahci_qc_issue,
292
293 .irq_handler = ahci_interrupt,
294 .irq_clear = ahci_irq_clear,
246ce3b6
AI		 295 .irq_on = ata_dummy_irq_on,
296 .irq_ack = ata_dummy_irq_ack,
ad616ffb
TH		 297
298 .scr_read = ahci_scr_read,
299 .scr_write = ahci_scr_write,
300
301 .freeze = ahci_freeze,
302 .thaw = ahci_thaw,
303
304 .error_handler = ahci_vt8251_error_handler,
305 .post_internal_cmd = ahci_post_internal_cmd,
306
307 .port_suspend = ahci_port_suspend,
308 .port_resume = ahci_port_resume,
309
310 .port_start = ahci_port_start,
311 .port_stop = ahci_port_stop,
312};
313
98ac62de 314static const struct ata_port_info ahci_port_info[] = {
1da177e4
LT		 315 /* board_ahci */
316 {
317 .sht = &ahci_sht,
cca3974e 318 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
4296971d
TH		 319 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
320 ATA_FLAG_SKIP_D2H_BSY,
7da79312 321 .pio_mask = 0x1f, /* pio0-4 */
1da177e4
LT		 322 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
323 .port_ops = &ahci_ops,
324 },
648a88be
TH		 325 /* board_ahci_pi */
326 {
327 .sht = &ahci_sht,
328 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
329 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
330 ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI,
331 .pio_mask = 0x1f, /* pio0-4 */
332 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
333 .port_ops = &ahci_ops,
334 },
bf2af2a2
BJ		 335 /* board_ahci_vt8251 */
336 {
337 .sht = &ahci_sht,
cca3974e 338 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
bf2af2a2 339 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
ad616ffb
TH		 340 ATA_FLAG_SKIP_D2H_BSY |
341 ATA_FLAG_HRST_TO_RESUME | AHCI_FLAG_NO_NCQ,
bf2af2a2
BJ		 342 .pio_mask = 0x1f, /* pio0-4 */
343 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
ad616ffb 344 .port_ops = &ahci_vt8251_ops,
bf2af2a2 345 },
41669553
TH		 346 /* board_ahci_ign_iferr */
347 {
348 .sht = &ahci_sht,
349 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
350 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
351 ATA_FLAG_SKIP_D2H_BSY |
352 AHCI_FLAG_IGN_IRQ_IF_ERR,
353 .pio_mask = 0x1f, /* pio0-4 */
354 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
355 .port_ops = &ahci_ops,
356 },
1da177e4
LT		 357};
358
3b7d697d 359static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 360 /* Intel */
54bb3a94
JG		 361 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
362 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
363 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
364 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
365 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 366 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 367 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
368 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
369 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
370 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
648a88be
TH		 371 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */
372 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */
373 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */
374 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */
375 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */
376 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */
377 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */
378 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */
379 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */
380 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */
381 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */
382 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */
383 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */
384 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */
385 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */
386 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */
fe7fa31a 387
e34bb370
TH		 388 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
389 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
390 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 391
392 /* ATI */
54bb3a94
JG		 393 { PCI_VDEVICE(ATI, 0x4380), board_ahci }, /* ATI SB600 non-raid */
394 { PCI_VDEVICE(ATI, 0x4381), board_ahci }, /* ATI SB600 raid */
fe7fa31a
JG		 395
396 /* VIA */
54bb3a94 397 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 398
399 /* NVIDIA */
54bb3a94
JG		 400 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
401 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
402 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
403 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
6fbf5ba4
PC		 404 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
405 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
406 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
407 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
408 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
409 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
410 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
411 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
895663cd
PC		 412 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
413 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
414 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
415 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
416 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
417 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
418 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
419 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
fe7fa31a 420
95916edd 421 /* SiS */
54bb3a94
JG		 422 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
423 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
424 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 425
415ae2b5
JG		 426 /* Generic, PCI class code for AHCI */
427 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 428 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 429
1da177e4
LT		 430 { } /* terminate list */
431};
432
433
434static struct pci_driver ahci_pci_driver = {
435 .name = DRV_NAME,
436 .id_table = ahci_pci_tbl,
437 .probe = ahci_init_one,
24dc5f33 438 .remove = ata_pci_remove_one,
c1332875
TH		 439 .suspend = ahci_pci_device_suspend,
440 .resume = ahci_pci_device_resume,
1da177e4
LT		 441};
442
443
98fa4b60
TH		 444static inline int ahci_nr_ports(u32 cap)
445{
446 return (cap & 0x1f) + 1;
447}
448
0d5ff566
TH		 449static inline void __iomem *ahci_port_base(void __iomem *base,
450 unsigned int port)
1da177e4
LT		 451{
452 return base + 0x100 + (port * 0x80);
453}
454
1da177e4
LT		 455static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
456{
457 unsigned int sc_reg;
458
459 switch (sc_reg_in) {
460 case SCR_STATUS: sc_reg = 0; break;
461 case SCR_CONTROL: sc_reg = 1; break;
462 case SCR_ERROR: sc_reg = 2; break;
463 case SCR_ACTIVE: sc_reg = 3; break;
464 default:
465 return 0xffffffffU;
466 }
467
0d5ff566 468 return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 469}
470
471
472static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
473 u32 val)
474{
475 unsigned int sc_reg;
476
477 switch (sc_reg_in) {
478 case SCR_STATUS: sc_reg = 0; break;
479 case SCR_CONTROL: sc_reg = 1; break;
480 case SCR_ERROR: sc_reg = 2; break;
481 case SCR_ACTIVE: sc_reg = 3; break;
482 default:
483 return;
484 }
485
0d5ff566 486 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 487}
488
9f592056 489static void ahci_start_engine(void __iomem *port_mmio)
7c76d1e8 490{
7c76d1e8
TH		 491 u32 tmp;
492
d8fcd116 493 /* start DMA */
9f592056 494 tmp = readl(port_mmio + PORT_CMD);
7c76d1e8
TH		 495 tmp |= PORT_CMD_START;
496 writel(tmp, port_mmio + PORT_CMD);
497 readl(port_mmio + PORT_CMD); /* flush */
498}
499
254950cd
TH		 500static int ahci_stop_engine(void __iomem *port_mmio)
501{
502 u32 tmp;
503
504 tmp = readl(port_mmio + PORT_CMD);
505
d8fcd116 506 /* check if the HBA is idle */
254950cd
TH		 507 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
508 return 0;
509
d8fcd116 510 /* setting HBA to idle */
254950cd
TH		 511 tmp &= ~PORT_CMD_START;
512 writel(tmp, port_mmio + PORT_CMD);
513
d8fcd116 514 /* wait for engine to stop. This could be as long as 500 msec */
254950cd
TH		 515 tmp = ata_wait_register(port_mmio + PORT_CMD,
516 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
d8fcd116 517 if (tmp & PORT_CMD_LIST_ON)
254950cd
TH		 518 return -EIO;
519
520 return 0;
521}
522
0be0aa98
TH		 523static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap,
524 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
525{
526 u32 tmp;
527
528 /* set FIS registers */
529 if (cap & HOST_CAP_64)
530 writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
531 writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
532
533 if (cap & HOST_CAP_64)
534 writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
535 writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
536
537 /* enable FIS reception */
538 tmp = readl(port_mmio + PORT_CMD);
539 tmp |= PORT_CMD_FIS_RX;
540 writel(tmp, port_mmio + PORT_CMD);
541
542 /* flush */
543 readl(port_mmio + PORT_CMD);
544}
545
546static int ahci_stop_fis_rx(void __iomem *port_mmio)
547{
548 u32 tmp;
549
550 /* disable FIS reception */
551 tmp = readl(port_mmio + PORT_CMD);
552 tmp &= ~PORT_CMD_FIS_RX;
553 writel(tmp, port_mmio + PORT_CMD);
554
555 /* wait for completion, spec says 500ms, give it 1000 */
556 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
557 PORT_CMD_FIS_ON, 10, 1000);
558 if (tmp & PORT_CMD_FIS_ON)
559 return -EBUSY;
560
561 return 0;
562}
563
564static void ahci_power_up(void __iomem *port_mmio, u32 cap)
565{
566 u32 cmd;
567
568 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
569
570 /* spin up device */
571 if (cap & HOST_CAP_SSS) {
572 cmd |= PORT_CMD_SPIN_UP;
573 writel(cmd, port_mmio + PORT_CMD);
574 }
575
576 /* wake up link */
577 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
578}
579
580static void ahci_power_down(void __iomem *port_mmio, u32 cap)
581{
582 u32 cmd, scontrol;
583
07c53dac
TH		 584 if (!(cap & HOST_CAP_SSS))
585 return;
0be0aa98 586
07c53dac
TH		 587 /* put device into listen mode, first set PxSCTL.DET to 0 */
588 scontrol = readl(port_mmio + PORT_SCR_CTL);
589 scontrol &= ~0xf;
590 writel(scontrol, port_mmio + PORT_SCR_CTL);
0be0aa98 591
07c53dac
TH		 592 /* then set PxCMD.SUD to 0 */
593 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
594 cmd &= ~PORT_CMD_SPIN_UP;
595 writel(cmd, port_mmio + PORT_CMD);
0be0aa98
TH		 596}
597
598static void ahci_init_port(void __iomem *port_mmio, u32 cap,
599 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
600{
0be0aa98
TH		 601 /* enable FIS reception */
602 ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma);
603
604 /* enable DMA */
605 ahci_start_engine(port_mmio);
606}
607
608static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg)
609{
610 int rc;
611
612 /* disable DMA */
613 rc = ahci_stop_engine(port_mmio);
614 if (rc) {
615 *emsg = "failed to stop engine";
616 return rc;
617 }
618
619 /* disable FIS reception */
620 rc = ahci_stop_fis_rx(port_mmio);
621 if (rc) {
622 *emsg = "failed stop FIS RX";
623 return rc;
624 }
625
0be0aa98
TH		 626 return 0;
627}
628
d91542c1
TH		 629static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev)
630{
98fa4b60 631 u32 cap_save, impl_save, tmp;
d91542c1
TH		 632
633 cap_save = readl(mmio + HOST_CAP);
98fa4b60 634 impl_save = readl(mmio + HOST_PORTS_IMPL);
d91542c1
TH		 635
636 /* global controller reset */
637 tmp = readl(mmio + HOST_CTL);
638 if ((tmp & HOST_RESET) == 0) {
639 writel(tmp | HOST_RESET, mmio + HOST_CTL);
640 readl(mmio + HOST_CTL); /* flush */
641 }
642
643 /* reset must complete within 1 second, or
644 * the hardware should be considered fried.
645 */
646 ssleep(1);
647
648 tmp = readl(mmio + HOST_CTL);
649 if (tmp & HOST_RESET) {
650 dev_printk(KERN_ERR, &pdev->dev,
651 "controller reset failed (0x%x)\n", tmp);
652 return -EIO;
653 }
654
98fa4b60 655 /* turn on AHCI mode */
d91542c1
TH		 656 writel(HOST_AHCI_EN, mmio + HOST_CTL);
657 (void) readl(mmio + HOST_CTL); /* flush */
98fa4b60
TH		 658
659 /* These write-once registers are normally cleared on reset.
660 * Restore BIOS values... which we HOPE were present before
661 * reset.
662 */
663 if (!impl_save) {
664 impl_save = (1 << ahci_nr_ports(cap_save)) - 1;
665 dev_printk(KERN_WARNING, &pdev->dev,
666 "PORTS_IMPL is zero, forcing 0x%x\n", impl_save);
667 }
d91542c1 668 writel(cap_save, mmio + HOST_CAP);
98fa4b60 669 writel(impl_save, mmio + HOST_PORTS_IMPL);
d91542c1
TH		 670 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
671
672 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
673 u16 tmp16;
674
675 /* configure PCS */
676 pci_read_config_word(pdev, 0x92, &tmp16);
677 tmp16 |= 0xf;
678 pci_write_config_word(pdev, 0x92, tmp16);
679 }
680
681 return 0;
682}
683
684static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev,
648a88be
TH		 685 int n_ports, unsigned int port_flags,
686 struct ahci_host_priv *hpriv)
d91542c1
TH		 687{
688 int i, rc;
689 u32 tmp;
690
691 for (i = 0; i < n_ports; i++) {
692 void __iomem *port_mmio = ahci_port_base(mmio, i);
693 const char *emsg = NULL;
694
648a88be
TH		 695 if ((port_flags & AHCI_FLAG_HONOR_PI) &&
696 !(hpriv->port_map & (1 << i)))
d91542c1 697 continue;
d91542c1
TH		 698
699 /* make sure port is not active */
648a88be 700 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
d91542c1
TH		 701 if (rc)
702 dev_printk(KERN_WARNING, &pdev->dev,
703 "%s (%d)\n", emsg, rc);
704
705 /* clear SError */
706 tmp = readl(port_mmio + PORT_SCR_ERR);
707 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
708 writel(tmp, port_mmio + PORT_SCR_ERR);
709
f4b5cc87 710 /* clear port IRQ */
d91542c1
TH		 711 tmp = readl(port_mmio + PORT_IRQ_STAT);
712 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
713 if (tmp)
714 writel(tmp, port_mmio + PORT_IRQ_STAT);
715
716 writel(1 << i, mmio + HOST_IRQ_STAT);
d91542c1
TH		 717 }
718
719 tmp = readl(mmio + HOST_CTL);
720 VPRINTK("HOST_CTL 0x%x\n", tmp);
721 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
722 tmp = readl(mmio + HOST_CTL);
723 VPRINTK("HOST_CTL 0x%x\n", tmp);
724}
725
422b7595 726static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4 727{
0d5ff566 728 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1da177e4 729 struct ata_taskfile tf;
422b7595
TH		 730 u32 tmp;
731
732 tmp = readl(port_mmio + PORT_SIG);
733 tf.lbah = (tmp >> 24) & 0xff;
734 tf.lbam = (tmp >> 16) & 0xff;
735 tf.lbal = (tmp >> 8) & 0xff;
736 tf.nsect = (tmp) & 0xff;
737
738 return ata_dev_classify(&tf);
739}
740
12fad3f9
TH		 741static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
742 u32 opts)
cc9278ed 743{
12fad3f9
TH		 744 dma_addr_t cmd_tbl_dma;
745
746 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
747
748 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
749 pp->cmd_slot[tag].status = 0;
750 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
751 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
cc9278ed
TH		 752}
753
bf2af2a2 754static int ahci_clo(struct ata_port *ap)
4658f79b 755{
0d5ff566 756 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
cca3974e 757 struct ahci_host_priv *hpriv = ap->host->private_data;
bf2af2a2
BJ		 758 u32 tmp;
759
760 if (!(hpriv->cap & HOST_CAP_CLO))
761 return -EOPNOTSUPP;
762
763 tmp = readl(port_mmio + PORT_CMD);
764 tmp |= PORT_CMD_CLO;
765 writel(tmp, port_mmio + PORT_CMD);
766
767 tmp = ata_wait_register(port_mmio + PORT_CMD,
768 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
769 if (tmp & PORT_CMD_CLO)
770 return -EIO;
771
772 return 0;
773}
774
775static int ahci_softreset(struct ata_port *ap, unsigned int *class)
776{
4658f79b 777 struct ahci_port_priv *pp = ap->private_data;
0d5ff566 778 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
4658f79b
TH		 779 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
780 const u32 cmd_fis_len = 5; /* five dwords */
781 const char *reason = NULL;
782 struct ata_taskfile tf;
75fe1806 783 u32 tmp;
4658f79b
TH		 784 u8 *fis;
785 int rc;
786
787 DPRINTK("ENTER\n");
788
81952c54 789 if (ata_port_offline(ap)) {
c2a65852
TH		 790 DPRINTK("PHY reports no device\n");
791 *class = ATA_DEV_NONE;
792 return 0;
793 }
794
4658f79b 795 /* prepare for SRST (AHCI-1.1 10.4.1) */
5457f219 796 rc = ahci_stop_engine(port_mmio);
4658f79b
TH		 797 if (rc) {
798 reason = "failed to stop engine";
799 goto fail_restart;
800 }
801
802 /* check BUSY/DRQ, perform Command List Override if necessary */
1244a19c 803 if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
bf2af2a2 804 rc = ahci_clo(ap);
4658f79b 805
bf2af2a2
BJ		 806 if (rc == -EOPNOTSUPP) {
807 reason = "port busy but CLO unavailable";
808 goto fail_restart;
809 } else if (rc) {
810 reason = "port busy but CLO failed";
4658f79b
TH		 811 goto fail_restart;
812 }
813 }
814
815 /* restart engine */
5457f219 816 ahci_start_engine(port_mmio);
4658f79b 817
3373efd8 818 ata_tf_init(ap->device, &tf);
4658f79b
TH		 819 fis = pp->cmd_tbl;
820
821 /* issue the first D2H Register FIS */
12fad3f9
TH		 822 ahci_fill_cmd_slot(pp, 0,
823 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
4658f79b
TH		 824
825 tf.ctl |= ATA_SRST;
826 ata_tf_to_fis(&tf, fis, 0);
827 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
828
829 writel(1, port_mmio + PORT_CMD_ISSUE);
4658f79b 830
75fe1806
TH		 831 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
832 if (tmp & 0x1) {
4658f79b
TH		 833 rc = -EIO;
834 reason = "1st FIS failed";
835 goto fail;
836 }
837
838 /* spec says at least 5us, but be generous and sleep for 1ms */
839 msleep(1);
840
841 /* issue the second D2H Register FIS */
12fad3f9 842 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
4658f79b
TH		 843
844 tf.ctl &= ~ATA_SRST;
845 ata_tf_to_fis(&tf, fis, 0);
846 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
847
848 writel(1, port_mmio + PORT_CMD_ISSUE);
849 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
850
851 /* spec mandates ">= 2ms" before checking status.
852 * We wait 150ms, because that was the magic delay used for
853 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
854 * between when the ATA command register is written, and then
855 * status is checked. Because waiting for "a while" before
856 * checking status is fine, post SRST, we perform this magic
857 * delay here as well.
858 */
859 msleep(150);
860
861 *class = ATA_DEV_NONE;
81952c54 862 if (ata_port_online(ap)) {
4658f79b
TH		 863 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
864 rc = -EIO;
865 reason = "device not ready";
866 goto fail;
867 }
868 *class = ahci_dev_classify(ap);
869 }
870
871 DPRINTK("EXIT, class=%u\n", *class);
872 return 0;
873
874 fail_restart:
5457f219 875 ahci_start_engine(port_mmio);
4658f79b 876 fail:
f15a1daf 877 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
4658f79b
TH		 878 return rc;
879}
880
2bf2cb26 881static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
422b7595 882{
4296971d
TH		 883 struct ahci_port_priv *pp = ap->private_data;
884 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
885 struct ata_taskfile tf;
0d5ff566 886 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
5457f219 887 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
4bd00f6a
TH		 888 int rc;
889
890 DPRINTK("ENTER\n");
1da177e4 891
5457f219 892 ahci_stop_engine(port_mmio);
4296971d
TH		 893
894 /* clear D2H reception area to properly wait for D2H FIS */
895 ata_tf_init(ap->device, &tf);
dfd7a3db 896 tf.command = 0x80;
4296971d
TH		 897 ata_tf_to_fis(&tf, d2h_fis, 0);
898
2bf2cb26 899 rc = sata_std_hardreset(ap, class);
4296971d 900
5457f219 901 ahci_start_engine(port_mmio);
1da177e4 902
81952c54 903 if (rc == 0 && ata_port_online(ap))
4bd00f6a
TH		 904 *class = ahci_dev_classify(ap);
905 if (*class == ATA_DEV_UNKNOWN)
906 *class = ATA_DEV_NONE;
1da177e4 907
4bd00f6a
TH		 908 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
909 return rc;
910}
911
ad616ffb
TH		 912static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class)
913{
0d5ff566 914 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
ad616ffb
TH		 915 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
916 int rc;
917
918 DPRINTK("ENTER\n");
919
920 ahci_stop_engine(port_mmio);
921
922 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context));
923
924 /* vt8251 needs SError cleared for the port to operate */
925 ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR));
926
927 ahci_start_engine(port_mmio);
928
929 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
930
931 /* vt8251 doesn't clear BSY on signature FIS reception,
932 * request follow-up softreset.
933 */
934 return rc ?: -EAGAIN;
935}
936
4bd00f6a
TH		 937static void ahci_postreset(struct ata_port *ap, unsigned int *class)
938{
0d5ff566 939 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
4bd00f6a
TH		 940 u32 new_tmp, tmp;
941
942 ata_std_postreset(ap, class);
02eaa666
JG		 943
944 /* Make sure port's ATAPI bit is set appropriately */
945 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 946 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 947 new_tmp |= PORT_CMD_ATAPI;
948 else
949 new_tmp &= ~PORT_CMD_ATAPI;
950 if (new_tmp != tmp) {
951 writel(new_tmp, port_mmio + PORT_CMD);
952 readl(port_mmio + PORT_CMD); /* flush */
953 }
1da177e4
LT		 954}
955
956static u8 ahci_check_status(struct ata_port *ap)
957{
0d5ff566 958 void __iomem *mmio = ap->ioaddr.cmd_addr;
1da177e4
LT		 959
960 return readl(mmio + PORT_TFDATA) & 0xFF;
961}
962
1da177e4
LT		 963static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
964{
965 struct ahci_port_priv *pp = ap->private_data;
966 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
967
968 ata_tf_from_fis(d2h_fis, tf);
969}
970
12fad3f9 971static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1da177e4 972{
cedc9a47
JG		 973 struct scatterlist *sg;
974 struct ahci_sg *ahci_sg;
828d09de 975 unsigned int n_sg = 0;
1da177e4
LT		 976
977 VPRINTK("ENTER\n");
978
979 /*
980 * Next, the S/G list.
981 */
12fad3f9 982 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
cedc9a47
JG		 983 ata_for_each_sg(sg, qc) {
984 dma_addr_t addr = sg_dma_address(sg);
985 u32 sg_len = sg_dma_len(sg);
986
987 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
988 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
989 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
828d09de 990
cedc9a47 991 ahci_sg++;
828d09de 992 n_sg++;
1da177e4 993 }
828d09de
JG		 994
995 return n_sg;
1da177e4
LT		 996}
997
998static void ahci_qc_prep(struct ata_queued_cmd *qc)
999{
a0ea7328
JG		 1000 struct ata_port *ap = qc->ap;
1001 struct ahci_port_priv *pp = ap->private_data;
cc9278ed 1002 int is_atapi = is_atapi_taskfile(&qc->tf);
12fad3f9 1003 void *cmd_tbl;
1da177e4
LT		 1004 u32 opts;
1005 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 1006 unsigned int n_elem;
1da177e4 1007
1da177e4
LT		 1008 /*
1009 * Fill in command table information. First, the header,
1010 * a SATA Register - Host to Device command FIS.
1011 */
12fad3f9
TH		 1012 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1013
1014 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
cc9278ed 1015 if (is_atapi) {
12fad3f9
TH		 1016 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1017 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
a0ea7328 1018 }
1da177e4 1019
cc9278ed
TH		 1020 n_elem = 0;
1021 if (qc->flags & ATA_QCFLAG_DMAMAP)
12fad3f9 1022 n_elem = ahci_fill_sg(qc, cmd_tbl);
1da177e4 1023
cc9278ed
TH		 1024 /*
1025 * Fill in command slot information.
1026 */
1027 opts = cmd_fis_len | n_elem << 16;
1028 if (qc->tf.flags & ATA_TFLAG_WRITE)
1029 opts |= AHCI_CMD_WRITE;
1030 if (is_atapi)
4b10e559 1031 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 1032
12fad3f9 1033 ahci_fill_cmd_slot(pp, qc->tag, opts);
1da177e4
LT		 1034}
1035
78cd52d0 1036static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1da177e4 1037{
78cd52d0
TH		 1038 struct ahci_port_priv *pp = ap->private_data;
1039 struct ata_eh_info *ehi = &ap->eh_info;
1040 unsigned int err_mask = 0, action = 0;
1041 struct ata_queued_cmd *qc;
1042 u32 serror;
1da177e4 1043
78cd52d0 1044 ata_ehi_clear_desc(ehi);
1da177e4 1045
78cd52d0
TH		 1046 /* AHCI needs SError cleared; otherwise, it might lock up */
1047 serror = ahci_scr_read(ap, SCR_ERROR);
1048 ahci_scr_write(ap, SCR_ERROR, serror);
1da177e4 1049
78cd52d0
TH		 1050 /* analyze @irq_stat */
1051 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1052
41669553
TH		 1053 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1054 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1055 irq_stat &= ~PORT_IRQ_IF_ERR;
1056
78cd52d0
TH		 1057 if (irq_stat & PORT_IRQ_TF_ERR)
1058 err_mask |= AC_ERR_DEV;
1059
1060 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1061 err_mask |= AC_ERR_HOST_BUS;
1062 action |= ATA_EH_SOFTRESET;
1da177e4
LT		 1063 }
1064
78cd52d0
TH		 1065 if (irq_stat & PORT_IRQ_IF_ERR) {
1066 err_mask |= AC_ERR_ATA_BUS;
1067 action |= ATA_EH_SOFTRESET;
1068 ata_ehi_push_desc(ehi, ", interface fatal error");
1069 }
1da177e4 1070
78cd52d0 1071 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
4296971d 1072 ata_ehi_hotplugged(ehi);
78cd52d0
TH		 1073 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
1074 "connection status changed" : "PHY RDY changed");
1075 }
1076
1077 if (irq_stat & PORT_IRQ_UNK_FIS) {
1078 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1da177e4 1079
78cd52d0
TH		 1080 err_mask |= AC_ERR_HSM;
1081 action |= ATA_EH_SOFTRESET;
1082 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
1083 unk[0], unk[1], unk[2], unk[3]);
1084 }
1da177e4 1085
78cd52d0
TH		 1086 /* okay, let's hand over to EH */
1087 ehi->serror |= serror;
1088 ehi->action |= action;
b8f6153e 1089
1da177e4 1090 qc = ata_qc_from_tag(ap, ap->active_tag);
78cd52d0
TH		 1091 if (qc)
1092 qc->err_mask |= err_mask;
1093 else
1094 ehi->err_mask |= err_mask;
a72ec4ce 1095
78cd52d0
TH		 1096 if (irq_stat & PORT_IRQ_FREEZE)
1097 ata_port_freeze(ap);
1098 else
1099 ata_port_abort(ap);
1da177e4
LT		 1100}
1101
78cd52d0 1102static void ahci_host_intr(struct ata_port *ap)
1da177e4 1103{
0d5ff566 1104 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
ea6ba10b 1105 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
12fad3f9 1106 struct ata_eh_info *ehi = &ap->eh_info;
0291f95f 1107 struct ahci_port_priv *pp = ap->private_data;
12fad3f9 1108 u32 status, qc_active;
0291f95f 1109 int rc, known_irq = 0;
1da177e4
LT		 1110
1111 status = readl(port_mmio + PORT_IRQ_STAT);
1112 writel(status, port_mmio + PORT_IRQ_STAT);
1113
78cd52d0
TH		 1114 if (unlikely(status & PORT_IRQ_ERROR)) {
1115 ahci_error_intr(ap, status);
1116 return;
1da177e4
LT		 1117 }
1118
12fad3f9
TH		 1119 if (ap->sactive)
1120 qc_active = readl(port_mmio + PORT_SCR_ACT);
1121 else
1122 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1123
1124 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1125 if (rc > 0)
1126 return;
1127 if (rc < 0) {
1128 ehi->err_mask |= AC_ERR_HSM;
1129 ehi->action |= ATA_EH_SOFTRESET;
1130 ata_port_freeze(ap);
1131 return;
1da177e4
LT		 1132 }
1133
2a3917a8
TH		 1134 /* hmmm... a spurious interupt */
1135
0291f95f
TH		 1136 /* if !NCQ, ignore. No modern ATA device has broken HSM
1137 * implementation for non-NCQ commands.
1138 */
1139 if (!ap->sactive)
12fad3f9
TH		 1140 return;
1141
0291f95f
TH		 1142 if (status & PORT_IRQ_D2H_REG_FIS) {
1143 if (!pp->ncq_saw_d2h)
1144 ata_port_printk(ap, KERN_INFO,
1145 "D2H reg with I during NCQ, "
1146 "this message won't be printed again\n");
1147 pp->ncq_saw_d2h = 1;
1148 known_irq = 1;
1149 }
1150
1151 if (status & PORT_IRQ_DMAS_FIS) {
1152 if (!pp->ncq_saw_dmas)
1153 ata_port_printk(ap, KERN_INFO,
1154 "DMAS FIS during NCQ, "
1155 "this message won't be printed again\n");
1156 pp->ncq_saw_dmas = 1;
1157 known_irq = 1;
1158 }
1159
a2bbd0c9 1160 if (status & PORT_IRQ_SDB_FIS) {
04d4f7a1 1161 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
0291f95f 1162
afb2d552
TH		 1163 if (le32_to_cpu(f[1])) {
1164 /* SDB FIS containing spurious completions
1165 * might be dangerous, whine and fail commands
1166 * with HSM violation. EH will turn off NCQ
1167 * after several such failures.
1168 */
1169 ata_ehi_push_desc(ehi,
1170 "spurious completions during NCQ "
1171 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1172 readl(port_mmio + PORT_CMD_ISSUE),
1173 readl(port_mmio + PORT_SCR_ACT),
1174 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1175 ehi->err_mask |= AC_ERR_HSM;
1176 ehi->action |= ATA_EH_SOFTRESET;
1177 ata_port_freeze(ap);
1178 } else {
1179 if (!pp->ncq_saw_sdb)
1180 ata_port_printk(ap, KERN_INFO,
1181 "spurious SDB FIS %08x:%08x during NCQ, "
1182 "this message won't be printed again\n",
1183 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1184 pp->ncq_saw_sdb = 1;
1185 }
0291f95f
TH		 1186 known_irq = 1;
1187 }
2a3917a8 1188
0291f95f 1189 if (!known_irq)
78cd52d0 1190 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
0291f95f 1191 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
12fad3f9 1192 status, ap->active_tag, ap->sactive);
1da177e4
LT		 1193}
1194
1195static void ahci_irq_clear(struct ata_port *ap)
1196{
1197 /* TODO */
1198}
1199
7d12e780 1200static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1da177e4 1201{
cca3974e 1202 struct ata_host *host = dev_instance;
1da177e4
LT		 1203 struct ahci_host_priv *hpriv;
1204 unsigned int i, handled = 0;
ea6ba10b 1205 void __iomem *mmio;
1da177e4
LT		 1206 u32 irq_stat, irq_ack = 0;
1207
1208 VPRINTK("ENTER\n");
1209
cca3974e 1210 hpriv = host->private_data;
0d5ff566 1211 mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 1212
1213 /* sigh. 0xffffffff is a valid return from h/w */
1214 irq_stat = readl(mmio + HOST_IRQ_STAT);
1215 irq_stat &= hpriv->port_map;
1216 if (!irq_stat)
1217 return IRQ_NONE;
1218
cca3974e 1219 spin_lock(&host->lock);
1da177e4 1220
cca3974e 1221 for (i = 0; i < host->n_ports; i++) {
1da177e4 1222 struct ata_port *ap;
1da177e4 1223
67846b30
JG		 1224 if (!(irq_stat & (1 << i)))
1225 continue;
1226
cca3974e 1227 ap = host->ports[i];
67846b30 1228 if (ap) {
78cd52d0 1229 ahci_host_intr(ap);
67846b30
JG		 1230 VPRINTK("port %u\n", i);
1231 } else {
1232 VPRINTK("port %u (no irq)\n", i);
6971ed1f 1233 if (ata_ratelimit())
cca3974e 1234 dev_printk(KERN_WARNING, host->dev,
a9524a76 1235 "interrupt on disabled port %u\n", i);
1da177e4 1236 }
67846b30
JG		 1237
1238 irq_ack |= (1 << i);
1da177e4
LT		 1239 }
1240
1241 if (irq_ack) {
1242 writel(irq_ack, mmio + HOST_IRQ_STAT);
1243 handled = 1;
1244 }
1245
cca3974e 1246 spin_unlock(&host->lock);
1da177e4
LT		 1247
1248 VPRINTK("EXIT\n");
1249
1250 return IRQ_RETVAL(handled);
1251}
1252
9a3d9eb0 1253static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 1254{
1255 struct ata_port *ap = qc->ap;
0d5ff566 1256 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1da177e4 1257
12fad3f9
TH		 1258 if (qc->tf.protocol == ATA_PROT_NCQ)
1259 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1260 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1da177e4
LT		 1261 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1262
1263 return 0;
1264}
1265
78cd52d0
TH		 1266static void ahci_freeze(struct ata_port *ap)
1267{
0d5ff566 1268 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
78cd52d0
TH		 1269 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1270
1271 /* turn IRQ off */
1272 writel(0, port_mmio + PORT_IRQ_MASK);
1273}
1274
1275static void ahci_thaw(struct ata_port *ap)
1276{
0d5ff566 1277 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
78cd52d0
TH		 1278 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1279 u32 tmp;
1280
1281 /* clear IRQ */
1282 tmp = readl(port_mmio + PORT_IRQ_STAT);
1283 writel(tmp, port_mmio + PORT_IRQ_STAT);
a718728f 1284 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
78cd52d0
TH		 1285
1286 /* turn IRQ back on */
1287 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1288}
1289
1290static void ahci_error_handler(struct ata_port *ap)
1291{
0d5ff566 1292 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
5457f219 1293 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1294
b51e9e5d 1295 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
78cd52d0 1296 /* restart engine */
5457f219 1297 ahci_stop_engine(port_mmio);
1298 ahci_start_engine(port_mmio);
78cd52d0
TH		 1299 }
1300
1301 /* perform recovery */
4aeb0e32 1302 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
f5914a46 1303 ahci_postreset);
78cd52d0
TH		 1304}
1305
ad616ffb
TH		 1306static void ahci_vt8251_error_handler(struct ata_port *ap)
1307{
0d5ff566 1308 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
ad616ffb
TH		 1309 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1310
1311 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1312 /* restart engine */
1313 ahci_stop_engine(port_mmio);
1314 ahci_start_engine(port_mmio);
1315 }
1316
1317 /* perform recovery */
1318 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1319 ahci_postreset);
1320}
1321
78cd52d0
TH		 1322static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1323{
1324 struct ata_port *ap = qc->ap;
0d5ff566 1325 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
5457f219 1326 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
78cd52d0
TH		 1327
1328 if (qc->flags & ATA_QCFLAG_FAILED)
1329 qc->err_mask |= AC_ERR_OTHER;
1330
1331 if (qc->err_mask) {
1332 /* make DMA engine forget about the failed command */
5457f219 1333 ahci_stop_engine(port_mmio);
1334 ahci_start_engine(port_mmio);
78cd52d0
TH		 1335 }
1336}
1337
c1332875
TH		 1338static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1339{
cca3974e 1340 struct ahci_host_priv *hpriv = ap->host->private_data;
c1332875 1341 struct ahci_port_priv *pp = ap->private_data;
0d5ff566 1342 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
c1332875
TH		 1343 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1344 const char *emsg = NULL;
1345 int rc;
1346
1347 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
8e16f941
TH		 1348 if (rc == 0)
1349 ahci_power_down(port_mmio, hpriv->cap);
1350 else {
c1332875
TH		 1351 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1352 ahci_init_port(port_mmio, hpriv->cap,
1353 pp->cmd_slot_dma, pp->rx_fis_dma);
1354 }
1355
1356 return rc;
1357}
1358
1359static int ahci_port_resume(struct ata_port *ap)
1360{
1361 struct ahci_port_priv *pp = ap->private_data;
cca3974e 1362 struct ahci_host_priv *hpriv = ap->host->private_data;
0d5ff566 1363 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
c1332875
TH		 1364 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1365
8e16f941 1366 ahci_power_up(port_mmio, hpriv->cap);
c1332875
TH		 1367 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1368
1369 return 0;
1370}
1371
1372static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1373{
cca3974e 1374 struct ata_host *host = dev_get_drvdata(&pdev->dev);
0d5ff566 1375 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
c1332875
TH		 1376 u32 ctl;
1377
1378 if (mesg.event == PM_EVENT_SUSPEND) {
1379 /* AHCI spec rev1.1 section 8.3.3:
1380 * Software must disable interrupts prior to requesting a
1381 * transition of the HBA to D3 state.
1382 */
1383 ctl = readl(mmio + HOST_CTL);
1384 ctl &= ~HOST_IRQ_EN;
1385 writel(ctl, mmio + HOST_CTL);
1386 readl(mmio + HOST_CTL); /* flush */
1387 }
1388
1389 return ata_pci_device_suspend(pdev, mesg);
1390}
1391
1392static int ahci_pci_device_resume(struct pci_dev *pdev)
1393{
cca3974e
JG		 1394 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1395 struct ahci_host_priv *hpriv = host->private_data;
0d5ff566 1396 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
c1332875
TH		 1397 int rc;
1398
553c4aa6
TH		 1399 rc = ata_pci_device_do_resume(pdev);
1400 if (rc)
1401 return rc;
c1332875
TH		 1402
1403 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1404 rc = ahci_reset_controller(mmio, pdev);
1405 if (rc)
1406 return rc;
1407
648a88be
TH		 1408 ahci_init_controller(mmio, pdev, host->n_ports,
1409 host->ports[0]->flags, hpriv);
c1332875
TH		 1410 }
1411
cca3974e 1412 ata_host_resume(host);
c1332875
TH		 1413
1414 return 0;
1415}
1416
254950cd
TH		 1417static int ahci_port_start(struct ata_port *ap)
1418{
cca3974e
JG		 1419 struct device *dev = ap->host->dev;
1420 struct ahci_host_priv *hpriv = ap->host->private_data;
254950cd 1421 struct ahci_port_priv *pp;
0d5ff566 1422 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
254950cd
TH		 1423 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1424 void *mem;
1425 dma_addr_t mem_dma;
1426 int rc;
1427
24dc5f33 1428 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
254950cd
TH		 1429 if (!pp)
1430 return -ENOMEM;
254950cd
TH		 1431
1432 rc = ata_pad_alloc(ap, dev);
24dc5f33 1433 if (rc)
254950cd 1434 return rc;
254950cd 1435
24dc5f33
TH		 1436 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1437 GFP_KERNEL);
1438 if (!mem)
254950cd 1439 return -ENOMEM;
254950cd
TH		 1440 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1441
1442 /*
1443 * First item in chunk of DMA memory: 32-slot command table,
1444 * 32 bytes each in size
1445 */
1446 pp->cmd_slot = mem;
1447 pp->cmd_slot_dma = mem_dma;
1448
1449 mem += AHCI_CMD_SLOT_SZ;
1450 mem_dma += AHCI_CMD_SLOT_SZ;
1451
1452 /*
1453 * Second item: Received-FIS area
1454 */
1455 pp->rx_fis = mem;
1456 pp->rx_fis_dma = mem_dma;
1457
1458 mem += AHCI_RX_FIS_SZ;
1459 mem_dma += AHCI_RX_FIS_SZ;
1460
1461 /*
1462 * Third item: data area for storing a single command
1463 * and its scatter-gather table
1464 */
1465 pp->cmd_tbl = mem;
1466 pp->cmd_tbl_dma = mem_dma;
1467
1468 ap->private_data = pp;
1469
8e16f941
TH		 1470 /* power up port */
1471 ahci_power_up(port_mmio, hpriv->cap);
1472
0be0aa98
TH		 1473 /* initialize port */
1474 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
254950cd
TH		 1475
1476 return 0;
1477}
1478
1479static void ahci_port_stop(struct ata_port *ap)
1480{
cca3974e 1481 struct ahci_host_priv *hpriv = ap->host->private_data;
0d5ff566 1482 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
254950cd 1483 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
0be0aa98
TH		 1484 const char *emsg = NULL;
1485 int rc;
254950cd 1486
0be0aa98
TH		 1487 /* de-initialize port */
1488 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1489 if (rc)
1490 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
254950cd
TH		 1491}
1492
0d5ff566 1493static void ahci_setup_port(struct ata_ioports *port, void __iomem *base,
1da177e4
LT		 1494 unsigned int port_idx)
1495{
1496 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
0d5ff566 1497 base = ahci_port_base(base, port_idx);
1da177e4
LT		 1498 VPRINTK("base now==0x%lx\n", base);
1499
1500 port->cmd_addr = base;
1501 port->scr_addr = base + PORT_SCR;
1502
1503 VPRINTK("EXIT\n");
1504}
1505
1506static int ahci_host_init(struct ata_probe_ent *probe_ent)
1507{
1508 struct ahci_host_priv *hpriv = probe_ent->private_data;
1509 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
0d5ff566 1510 void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR];
648a88be 1511 unsigned int i, cap_n_ports, using_dac;
1da177e4 1512 int rc;
1da177e4 1513
d91542c1
TH		 1514 rc = ahci_reset_controller(mmio, pdev);
1515 if (rc)
1516 return rc;
1da177e4
LT		 1517
1518 hpriv->cap = readl(mmio + HOST_CAP);
1519 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
648a88be 1520 cap_n_ports = ahci_nr_ports(hpriv->cap);
1da177e4
LT		 1521
1522 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
648a88be
TH		 1523 hpriv->cap, hpriv->port_map, cap_n_ports);
1524
1525 if (probe_ent->port_flags & AHCI_FLAG_HONOR_PI) {
1526 unsigned int n_ports = cap_n_ports;
1527 u32 port_map = hpriv->port_map;
1528 int max_port = 0;
1529
1530 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
1531 if (port_map & (1 << i)) {
1532 n_ports--;
1533 port_map &= ~(1 << i);
1534 max_port = i;
1535 } else
1536 probe_ent->dummy_port_mask |= 1 << i;
1537 }
1538
1539 if (n_ports || port_map)
1540 dev_printk(KERN_WARNING, &pdev->dev,
1541 "nr_ports (%u) and implemented port map "
1542 "(0x%x) don't match\n",
1543 cap_n_ports, hpriv->port_map);
1544
1545 probe_ent->n_ports = max_port + 1;
1546 } else
1547 probe_ent->n_ports = cap_n_ports;
1da177e4
LT		 1548
1549 using_dac = hpriv->cap & HOST_CAP_64;
1550 if (using_dac &&
1551 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1552 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1553 if (rc) {
1554 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1555 if (rc) {
a9524a76
JG		 1556 dev_printk(KERN_ERR, &pdev->dev,
1557 "64-bit DMA enable failed\n");
1da177e4
LT		 1558 return rc;
1559 }
1560 }
1da177e4
LT		 1561 } else {
1562 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1563 if (rc) {
a9524a76
JG		 1564 dev_printk(KERN_ERR, &pdev->dev,
1565 "32-bit DMA enable failed\n");
1da177e4
LT		 1566 return rc;
1567 }
1568 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1569 if (rc) {
a9524a76
JG		 1570 dev_printk(KERN_ERR, &pdev->dev,
1571 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 1572 return rc;
1573 }
1574 }
1575
d91542c1 1576 for (i = 0; i < probe_ent->n_ports; i++)
0d5ff566 1577 ahci_setup_port(&probe_ent->port[i], mmio, i);
1da177e4 1578
648a88be
TH		 1579 ahci_init_controller(mmio, pdev, probe_ent->n_ports,
1580 probe_ent->port_flags, hpriv);
1da177e4
LT		 1581
1582 pci_set_master(pdev);
1583
1584 return 0;
1585}
1586
1da177e4
LT		 1587static void ahci_print_info(struct ata_probe_ent *probe_ent)
1588{
1589 struct ahci_host_priv *hpriv = probe_ent->private_data;
1590 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
0d5ff566 1591 void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR];
1da177e4
LT		 1592 u32 vers, cap, impl, speed;
1593 const char *speed_s;
1594 u16 cc;
1595 const char *scc_s;
1596
1597 vers = readl(mmio + HOST_VERSION);
1598 cap = hpriv->cap;
1599 impl = hpriv->port_map;
1600
1601 speed = (cap >> 20) & 0xf;
1602 if (speed == 1)
1603 speed_s = "1.5";
1604 else if (speed == 2)
1605 speed_s = "3";
1606 else
1607 speed_s = "?";
1608
1609 pci_read_config_word(pdev, 0x0a, &cc);
c9f89475 1610 if (cc == PCI_CLASS_STORAGE_IDE)
1da177e4 1611 scc_s = "IDE";
c9f89475 1612 else if (cc == PCI_CLASS_STORAGE_SATA)
1da177e4 1613 scc_s = "SATA";
c9f89475 1614 else if (cc == PCI_CLASS_STORAGE_RAID)
1da177e4
LT		 1615 scc_s = "RAID";
1616 else
1617 scc_s = "unknown";
1618
a9524a76
JG		 1619 dev_printk(KERN_INFO, &pdev->dev,
1620 "AHCI %02x%02x.%02x%02x "
1da177e4
LT		 1621 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1622 ,
1da177e4
LT		 1623
1624 (vers >> 24) & 0xff,
1625 (vers >> 16) & 0xff,
1626 (vers >> 8) & 0xff,
1627 vers & 0xff,
1628
1629 ((cap >> 8) & 0x1f) + 1,
1630 (cap & 0x1f) + 1,
1631 speed_s,
1632 impl,
1633 scc_s);
1634
a9524a76
JG		 1635 dev_printk(KERN_INFO, &pdev->dev,
1636 "flags: "
1da177e4
LT		 1637 "%s%s%s%s%s%s"
1638 "%s%s%s%s%s%s%s\n"
1639 ,
1da177e4
LT		 1640
1641 cap & (1 << 31) ? "64bit " : "",
1642 cap & (1 << 30) ? "ncq " : "",
1643 cap & (1 << 28) ? "ilck " : "",
1644 cap & (1 << 27) ? "stag " : "",
1645 cap & (1 << 26) ? "pm " : "",
1646 cap & (1 << 25) ? "led " : "",
1647
1648 cap & (1 << 24) ? "clo " : "",
1649 cap & (1 << 19) ? "nz " : "",
1650 cap & (1 << 18) ? "only " : "",
1651 cap & (1 << 17) ? "pmp " : "",
1652 cap & (1 << 15) ? "pio " : "",
1653 cap & (1 << 14) ? "slum " : "",
1654 cap & (1 << 13) ? "part " : ""
1655 );
1656}
1657
24dc5f33 1658static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 1659{
1660 static int printed_version;
24dc5f33
TH		 1661 unsigned int board_idx = (unsigned int) ent->driver_data;
1662 struct device *dev = &pdev->dev;
1663 struct ata_probe_ent *probe_ent;
1da177e4 1664 struct ahci_host_priv *hpriv;
1da177e4
LT		 1665 int rc;
1666
1667 VPRINTK("ENTER\n");
1668
12fad3f9
TH		 1669 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1670
1da177e4 1671 if (!printed_version++)
a9524a76 1672 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 1673
24dc5f33 1674 rc = pcim_enable_device(pdev);
1da177e4
LT		 1675 if (rc)
1676 return rc;
1677
0d5ff566
TH		 1678 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1679 if (rc == -EBUSY)
24dc5f33 1680 pcim_pin_device(pdev);
0d5ff566 1681 if (rc)
24dc5f33 1682 return rc;
1da177e4 1683
24dc5f33 1684 if (pci_enable_msi(pdev))
907f4678 1685 pci_intx(pdev, 1);
1da177e4 1686
24dc5f33
TH		 1687 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
1688 if (probe_ent == NULL)
1689 return -ENOMEM;
1da177e4 1690
1da177e4
LT		 1691 probe_ent->dev = pci_dev_to_dev(pdev);
1692 INIT_LIST_HEAD(&probe_ent->node);
1693
24dc5f33
TH		 1694 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1695 if (!hpriv)
1696 return -ENOMEM;
1da177e4
LT		 1697
1698 probe_ent->sht = ahci_port_info[board_idx].sht;
cca3974e 1699 probe_ent->port_flags = ahci_port_info[board_idx].flags;
1da177e4
LT		 1700 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1701 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1702 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1703
1704 probe_ent->irq = pdev->irq;
1d6f359a 1705 probe_ent->irq_flags = IRQF_SHARED;
0d5ff566 1706 probe_ent->iomap = pcim_iomap_table(pdev);
1da177e4
LT		 1707 probe_ent->private_data = hpriv;
1708
1709 /* initialize adapter */
1710 rc = ahci_host_init(probe_ent);
1711 if (rc)
24dc5f33 1712 return rc;
1da177e4 1713
cca3974e 1714 if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) &&
71f0737b 1715 (hpriv->cap & HOST_CAP_NCQ))
cca3974e 1716 probe_ent->port_flags |= ATA_FLAG_NCQ;
12fad3f9 1717
1da177e4
LT		 1718 ahci_print_info(probe_ent);
1719
24dc5f33
TH		 1720 if (!ata_device_add(probe_ent))
1721 return -ENODEV;
1da177e4 1722
24dc5f33 1723 devm_kfree(dev, probe_ent);
1da177e4 1724 return 0;
907f4678 1725}
1da177e4
LT		 1726
1727static int __init ahci_init(void)
1728{
b7887196 1729 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 1730}
1731
1da177e4
LT		 1732static void __exit ahci_exit(void)
1733{
1734 pci_unregister_driver(&ahci_pci_driver);
1735}
1736
1737
1738MODULE_AUTHOR("Jeff Garzik");
1739MODULE_DESCRIPTION("AHCI SATA low-level driver");
1740MODULE_LICENSE("GPL");
1741MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1742MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1743
1744module_init(ahci_init);
1745module_exit(ahci_exit);
Linux 6.x block layer and io_uring tree(s)