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ahci: Add PCI ids for Intel Bay Trail, Cherry Trail and Apollo Lake AHCI
[linux-block.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <tj@kernel.org>
af36d7f0
JG		 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
19285f3c 27 * as Documentation/driver-api/libata.rst
af36d7f0
JG		 28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
1da177e4
LT		 38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
87507cfd 41#include <linux/dma-mapping.h>
a9524a76 42#include <linux/device.h>
edc93052 43#include <linux/dmi.h>
5a0e3ad6 44#include <linux/gfp.h>
ee2aad42 45#include <linux/msi.h>
1da177e4 46#include <scsi/scsi_host.h>
193515d5 47#include <scsi/scsi_cmnd.h>
1da177e4 48#include <linux/libata.h>
aecec8b6
CH		 49#include <linux/ahci-remap.h>
50#include <linux/io-64-nonatomic-lo-hi.h>
365cfa1e 51#include "ahci.h"
1da177e4
LT		 52
53#define DRV_NAME "ahci"
7d50b60b 54#define DRV_VERSION "3.0"
1da177e4 55
1da177e4 56enum {
318893e1 57 AHCI_PCI_BAR_STA2X11 = 0,
b7ae128d 58 AHCI_PCI_BAR_CAVIUM = 0,
7f9c9f8e 59 AHCI_PCI_BAR_ENMOTUS = 2,
b1314e3f 60 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
318893e1 61 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 62};
63
64enum board_ids {
65 /* board IDs by feature in alphabetical order */
66 board_ahci,
67 board_ahci_ign_iferr,
66a7cbc3 68 board_ahci_nomsi,
67809f85 69 board_ahci_noncq,
441577ef 70 board_ahci_nosntf,
5f173107 71 board_ahci_yes_fbs,
1da177e4 72
441577ef 73 /* board IDs for specific chipsets in alphabetical order */
dbfe8ef5 74 board_ahci_avn,
441577ef 75 board_ahci_mcp65,
83f2b963
TH		 76 board_ahci_mcp77,
77 board_ahci_mcp89,
441577ef
TH		 78 board_ahci_mv,
79 board_ahci_sb600,
80 board_ahci_sb700, /* for SB700 and SB800 */
81 board_ahci_vt8251,
82
83 /* aliases */
84 board_ahci_mcp_linux = board_ahci_mcp65,
85 board_ahci_mcp67 = board_ahci_mcp65,
86 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 87 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 88};
89
2dcb407e 90static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
02e53293 91static void ahci_remove_one(struct pci_dev *dev);
a1efdaba
TH		 92static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
93 unsigned long deadline);
dbfe8ef5
DW		 94static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
95 unsigned long deadline);
cb85696d
JL		 96static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
97static bool is_mcp89_apple(struct pci_dev *pdev);
a1efdaba
TH		 98static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
99 unsigned long deadline);
02e53293
MW		 100#ifdef CONFIG_PM
101static int ahci_pci_device_runtime_suspend(struct device *dev);
102static int ahci_pci_device_runtime_resume(struct device *dev);
f1d848f9
MW		 103#ifdef CONFIG_PM_SLEEP
104static int ahci_pci_device_suspend(struct device *dev);
105static int ahci_pci_device_resume(struct device *dev);
438ac6d5 106#endif
02e53293 107#endif /* CONFIG_PM */
ad616ffb 108
fad16e7a
TH		 109static struct scsi_host_template ahci_sht = {
110 AHCI_SHT("ahci"),
111};
112
029cfd6b
TH		 113static struct ata_port_operations ahci_vt8251_ops = {
114 .inherits = &ahci_ops,
a1efdaba 115 .hardreset = ahci_vt8251_hardreset,
029cfd6b 116};
edc93052 117
029cfd6b
TH		 118static struct ata_port_operations ahci_p5wdh_ops = {
119 .inherits = &ahci_ops,
a1efdaba 120 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 121};
122
dbfe8ef5
DW		 123static struct ata_port_operations ahci_avn_ops = {
124 .inherits = &ahci_ops,
125 .hardreset = ahci_avn_hardreset,
126};
127
98ac62de 128static const struct ata_port_info ahci_port_info[] = {
441577ef 129 /* by features */
facb8fa6 130 [board_ahci] = {
1188c0d8 131 .flags = AHCI_FLAG_COMMON,
14bdef98 132 .pio_mask = ATA_PIO4,
469248ab 133 .udma_mask = ATA_UDMA6,
1da177e4
LT		 134 .port_ops = &ahci_ops,
135 },
facb8fa6 136 [board_ahci_ign_iferr] = {
441577ef 137 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 138 .flags = AHCI_FLAG_COMMON,
14bdef98 139 .pio_mask = ATA_PIO4,
469248ab 140 .udma_mask = ATA_UDMA6,
441577ef 141 .port_ops = &ahci_ops,
bf2af2a2 142 },
66a7cbc3
TH		 143 [board_ahci_nomsi] = {
144 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
145 .flags = AHCI_FLAG_COMMON,
146 .pio_mask = ATA_PIO4,
147 .udma_mask = ATA_UDMA6,
148 .port_ops = &ahci_ops,
149 },
67809f85
LK		 150 [board_ahci_noncq] = {
151 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
152 .flags = AHCI_FLAG_COMMON,
153 .pio_mask = ATA_PIO4,
154 .udma_mask = ATA_UDMA6,
155 .port_ops = &ahci_ops,
156 },
facb8fa6 157 [board_ahci_nosntf] = {
441577ef 158 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 159 .flags = AHCI_FLAG_COMMON,
14bdef98 160 .pio_mask = ATA_PIO4,
469248ab 161 .udma_mask = ATA_UDMA6,
41669553
TH		 162 .port_ops = &ahci_ops,
163 },
facb8fa6 164 [board_ahci_yes_fbs] = {
5f173107
TH		 165 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
166 .flags = AHCI_FLAG_COMMON,
167 .pio_mask = ATA_PIO4,
168 .udma_mask = ATA_UDMA6,
169 .port_ops = &ahci_ops,
170 },
441577ef 171 /* by chipsets */
dbfe8ef5
DW		 172 [board_ahci_avn] = {
173 .flags = AHCI_FLAG_COMMON,
174 .pio_mask = ATA_PIO4,
175 .udma_mask = ATA_UDMA6,
176 .port_ops = &ahci_avn_ops,
177 },
facb8fa6 178 [board_ahci_mcp65] = {
83f2b963
TH		 179 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
180 AHCI_HFLAG_YES_NCQ),
ae01b249 181 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 182 .pio_mask = ATA_PIO4,
183 .udma_mask = ATA_UDMA6,
184 .port_ops = &ahci_ops,
185 },
facb8fa6 186 [board_ahci_mcp77] = {
83f2b963
TH		 187 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_ops,
192 },
facb8fa6 193 [board_ahci_mcp89] = {
83f2b963 194 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 195 .flags = AHCI_FLAG_COMMON,
14bdef98 196 .pio_mask = ATA_PIO4,
469248ab 197 .udma_mask = ATA_UDMA6,
441577ef 198 .port_ops = &ahci_ops,
55a61604 199 },
facb8fa6 200 [board_ahci_mv] = {
417a1a6d 201 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 202 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 203 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 204 .pio_mask = ATA_PIO4,
cd70c266
JG		 205 .udma_mask = ATA_UDMA6,
206 .port_ops = &ahci_ops,
207 },
facb8fa6 208 [board_ahci_sb600] = {
441577ef
TH		 209 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
210 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
211 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 212 .flags = AHCI_FLAG_COMMON,
14bdef98 213 .pio_mask = ATA_PIO4,
e39fc8c9 214 .udma_mask = ATA_UDMA6,
345347c5 215 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 216 },
facb8fa6 217 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 218 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 219 .flags = AHCI_FLAG_COMMON,
220 .pio_mask = ATA_PIO4,
221 .udma_mask = ATA_UDMA6,
345347c5 222 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 223 },
facb8fa6 224 [board_ahci_vt8251] = {
441577ef 225 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 226 .flags = AHCI_FLAG_COMMON,
227 .pio_mask = ATA_PIO4,
228 .udma_mask = ATA_UDMA6,
441577ef 229 .port_ops = &ahci_vt8251_ops,
1b677afd 230 },
1da177e4
LT		 231};
232
3b7d697d 233static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 234 /* Intel */
54bb3a94
JG		 235 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
236 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
237 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
238 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
239 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 240 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 241 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
242 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
243 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
244 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 245 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 246 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 247 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
248 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
249 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
250 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
251 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
252 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
253 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
254 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
255 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
256 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
257 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
258 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
259 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
260 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
261 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 262 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
263 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 264 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 265 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 266 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 267 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
268 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 269 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 270 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
ca1b4974 271 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH M AHCI */
adcb5308 272 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
ca1b4974 273 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH M RAID */
c1f57d9b 274 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
342decff
AY		 275 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
276 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
277 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
278 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
279 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
280 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
281 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
282 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
283 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
284 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
285 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
286 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
287 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
288 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
289 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
290 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
294 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
5623cab8 295 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
ca1b4974 296 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT M AHCI */
5623cab8 297 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
ca1b4974 298 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT M RAID */
5623cab8
SH		 299 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
300 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 301 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
302 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
303 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 304 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 305 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea 306 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
ca1b4974 307 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point M AHCI */
181e3cea
SH		 308 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
309 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
310 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
ca1b4974 311 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point M RAID */
2cab7a4c 312 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66 313 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
ca1b4974 314 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point M AHCI */
ea4ace66 315 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
ca1b4974 316 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point M RAID */
ea4ace66 317 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
ca1b4974 318 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point M RAID */
ea4ace66 319 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
ca1b4974 320 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point M RAID */
77b12bc9
JR		 321 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
322 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
323 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
324 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
325 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
326 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
327 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
328 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
29e674dd
SH		 329 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
330 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
331 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
332 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
333 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
334 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
335 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
336 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
dbfe8ef5
DW		 337 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
338 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
339 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
340 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
341 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
342 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
343 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
344 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
efda332c
JR		 345 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
346 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
151743fd
JR		 347 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
348 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
349 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
350 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
351 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
352 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
353 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
354 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
1cfc7df3 355 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
9f961a5f
JR		 356 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
357 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
358 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
359 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
1b071a09 360 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
ca1b4974 361 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series M AHCI */
1b071a09 362 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
ca1b4974 363 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series M RAID */
1b071a09 364 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
ca1b4974 365 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series M RAID */
1b071a09 366 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
ca1b4974 367 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series M RAID */
249cd0a1
DR		 368 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
369 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
370 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
c5967b79 371 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
ca1b4974 372 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H M AHCI */
690000b9 373 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
c5967b79 374 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
ca1b4974 375 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H M RAID */
690000b9 376 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
4d92f009 377 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
f5bdd66c 378 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
4d92f009 379 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
f5bdd66c 380 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
4d92f009 381 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
4d92f009 382 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
f5bdd66c
AY		 383 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
384 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
4d92f009 385 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
4d92f009 386 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
f5bdd66c
AY		 387 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
388 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
998008b7
HG		 389 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci }, /* Bay Trail AHCI */
390 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci }, /* Bay Trail AHCI */
391 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci }, /* Cherry Trail AHCI */
392 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci }, /* Apollo Lake AHCI */
fe7fa31a 393
e34bb370
TH		 394 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
395 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
396 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
1fefb8fd
BH		 397 /* JMicron 362B and 362C have an AHCI function with IDE class code */
398 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
399 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
91f15fb3 400 /* May need to update quirk_jmicron_async_suspend() for additions */
fe7fa31a
JG		 401
402 /* ATI */
c65ec1c2 403 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 404 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
405 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
406 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
407 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
408 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
409 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 410
e2dd90b1 411 /* AMD */
5deab536 412 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
fafe5c3d 413 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
e2dd90b1
SH		 414 /* AMD is using RAID class only for ahci controllers */
415 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
416 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
417
fe7fa31a 418 /* VIA */
54bb3a94 419 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 420 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 421
422 /* NVIDIA */
e297d99e
TH		 423 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
424 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
425 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
426 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
427 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
428 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
429 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
430 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 431 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
432 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
433 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
434 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
435 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
436 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
437 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
438 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
439 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
440 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
441 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
442 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
443 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
444 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
445 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
446 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
447 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
448 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
449 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
450 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
451 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
452 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
453 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
454 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
455 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
456 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
457 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
458 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
459 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
460 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
461 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
462 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
463 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
464 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
465 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
466 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
467 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
468 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
469 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
470 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
471 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
472 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
473 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
474 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
475 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
476 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
477 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
478 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
479 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
480 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
481 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
482 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
483 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
484 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
485 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
486 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
487 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
488 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
489 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
490 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
491 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
492 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
493 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
494 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
495 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
496 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
497 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
498 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
499 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
500 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
501 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
502 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
503 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
504 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
505 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
506 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 507
95916edd 508 /* SiS */
20e2de4a
TH		 509 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
510 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
511 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 512
318893e1
AR		 513 /* ST Microelectronics */
514 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
515
cd70c266
JG		 516 /* Marvell */
517 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 518 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
69fd3157 519 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
10aca06c
AH		 520 .class = PCI_CLASS_STORAGE_SATA_AHCI,
521 .class_mask = 0xffffff,
5f173107 522 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
69fd3157 523 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
467b41c6 524 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
e098f5cb
SG		 525 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
526 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
527 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
69fd3157 528 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
642d8925 529 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
fcce9a35 530 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
c5edfff9
MK		 531 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
532 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
fcce9a35 533 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
69fd3157 534 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
17c60c6b 535 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
754a292f
AS		 536 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
537 .driver_data = board_ahci_yes_fbs },
a40cf3f3
JT		 538 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
539 .driver_data = board_ahci_yes_fbs },
69fd3157 540 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
50be5e36 541 .driver_data = board_ahci_yes_fbs },
6d5278a6
SB		 542 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
543 .driver_data = board_ahci_yes_fbs },
d2518365
JC		 544 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
545 .driver_data = board_ahci_yes_fbs },
cd70c266 546
c77a036b
MN		 547 /* Promise */
548 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
b32bfc06 549 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
c77a036b 550
c9703765 551 /* Asmedia */
7b4f6eca
AC		 552 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
553 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
554 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
555 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
0ce968f3
SL		 556 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
557 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
c9703765 558
67809f85 559 /*
66a7cbc3
TH		 560 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
561 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
67809f85 562 */
66a7cbc3 563 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
2b21ef0a 564 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
67809f85 565
7f9c9f8e
HD		 566 /* Enmotus */
567 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
568
415ae2b5
JG		 569 /* Generic, PCI class code for AHCI */
570 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 571 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 572
1da177e4
LT		 573 { } /* terminate list */
574};
575
f1d848f9
MW		 576static const struct dev_pm_ops ahci_pci_pm_ops = {
577 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
02e53293
MW		 578 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
579 ahci_pci_device_runtime_resume, NULL)
f1d848f9 580};
1da177e4
LT		 581
582static struct pci_driver ahci_pci_driver = {
583 .name = DRV_NAME,
584 .id_table = ahci_pci_tbl,
585 .probe = ahci_init_one,
02e53293 586 .remove = ahci_remove_one,
f1d848f9
MW		 587 .driver = {
588 .pm = &ahci_pci_pm_ops,
589 },
365cfa1e 590};
1da177e4 591
5219d653 592#if IS_ENABLED(CONFIG_PATA_MARVELL)
365cfa1e
AV		 593static int marvell_enable;
594#else
595static int marvell_enable = 1;
596#endif
597module_param(marvell_enable, int, 0644);
598MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 599
1da177e4 600
365cfa1e
AV		 601static void ahci_pci_save_initial_config(struct pci_dev *pdev,
602 struct ahci_host_priv *hpriv)
603{
365cfa1e
AV		 604 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
605 dev_info(&pdev->dev, "JMB361 has only one port\n");
9a23c1d6 606 hpriv->force_port_map = 1;
1da177e4
LT		 607 }
608
365cfa1e
AV		 609 /*
610 * Temporary Marvell 6145 hack: PATA port presence
611 * is asserted through the standard AHCI port
612 * presence register, as bit 4 (counting from 0)
d28f87aa 613 */
365cfa1e
AV		 614 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
615 if (pdev->device == 0x6121)
9a23c1d6 616 hpriv->mask_port_map = 0x3;
365cfa1e 617 else
9a23c1d6 618 hpriv->mask_port_map = 0xf;
365cfa1e
AV		 619 dev_info(&pdev->dev,
620 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
621 }
1da177e4 622
725c7b57 623 ahci_save_initial_config(&pdev->dev, hpriv);
1da177e4
LT		 624}
625
365cfa1e 626static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 627{
365cfa1e 628 struct pci_dev *pdev = to_pci_dev(host->dev);
d312fefe 629 int rc;
7d50b60b 630
d312fefe
AB		 631 rc = ahci_reset_controller(host);
632 if (rc)
633 return rc;
1da177e4 634
365cfa1e
AV		 635 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
636 struct ahci_host_priv *hpriv = host->private_data;
637 u16 tmp16;
d6ef3153 638
365cfa1e
AV		 639 /* configure PCS */
640 pci_read_config_word(pdev, 0x92, &tmp16);
641 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
642 tmp16 |= hpriv->port_map;
643 pci_write_config_word(pdev, 0x92, tmp16);
644 }
d6ef3153
SH		 645 }
646
1da177e4
LT		 647 return 0;
648}
649
365cfa1e 650static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 651{
365cfa1e
AV		 652 struct ahci_host_priv *hpriv = host->private_data;
653 struct pci_dev *pdev = to_pci_dev(host->dev);
654 void __iomem *port_mmio;
78cd52d0 655 u32 tmp;
365cfa1e 656 int mv;
78cd52d0 657
365cfa1e
AV		 658 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
659 if (pdev->device == 0x6121)
660 mv = 2;
661 else
662 mv = 4;
663 port_mmio = __ahci_port_base(host, mv);
78cd52d0 664
365cfa1e 665 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 666
365cfa1e
AV		 667 /* clear port IRQ */
668 tmp = readl(port_mmio + PORT_IRQ_STAT);
669 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
670 if (tmp)
671 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 672 }
673
365cfa1e 674 ahci_init_controller(host);
edc93052
TH		 675}
676
365cfa1e
AV		 677static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
678 unsigned long deadline)
d6ef3153 679{
365cfa1e 680 struct ata_port *ap = link->ap;
039ece38 681 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 682 bool online;
d6ef3153
SH		 683 int rc;
684
365cfa1e 685 DPRINTK("ENTER\n");
d6ef3153 686
365cfa1e 687 ahci_stop_engine(ap);
d6ef3153 688
365cfa1e
AV		 689 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
690 deadline, &online, NULL);
d6ef3153 691
039ece38 692 hpriv->start_engine(ap);
d6ef3153 693
365cfa1e 694 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 695
365cfa1e
AV		 696 /* vt8251 doesn't clear BSY on signature FIS reception,
697 * request follow-up softreset.
698 */
699 return online ? -EAGAIN : rc;
7d50b60b
TH		 700}
701
365cfa1e
AV		 702static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
703 unsigned long deadline)
7d50b60b 704{
365cfa1e 705 struct ata_port *ap = link->ap;
1c954a4d 706 struct ahci_port_priv *pp = ap->private_data;
039ece38 707 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 708 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
709 struct ata_taskfile tf;
710 bool online;
711 int rc;
7d50b60b 712
365cfa1e 713 ahci_stop_engine(ap);
028a2596 714
365cfa1e
AV		 715 /* clear D2H reception area to properly wait for D2H FIS */
716 ata_tf_init(link->device, &tf);
9bbb1b0e 717 tf.command = ATA_BUSY;
365cfa1e 718 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 719
365cfa1e
AV		 720 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
721 deadline, &online, NULL);
028a2596 722
039ece38 723 hpriv->start_engine(ap);
c1332875 724
365cfa1e
AV		 725 /* The pseudo configuration device on SIMG4726 attached to
726 * ASUS P5W-DH Deluxe doesn't send signature FIS after
727 * hardreset if no device is attached to the first downstream
728 * port && the pseudo device locks up on SRST w/ PMP==0. To
729 * work around this, wait for !BSY only briefly. If BSY isn't
730 * cleared, perform CLO and proceed to IDENTIFY (achieved by
731 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
732 *
733 * Wait for two seconds. Devices attached to downstream port
734 * which can't process the following IDENTIFY after this will
735 * have to be reset again. For most cases, this should
736 * suffice while making probing snappish enough.
737 */
738 if (online) {
739 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
740 ahci_check_ready);
741 if (rc)
742 ahci_kick_engine(ap);
c1332875 743 }
c1332875
TH		 744 return rc;
745}
746
dbfe8ef5
DW		 747/*
748 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
749 *
750 * It has been observed with some SSDs that the timing of events in the
751 * link synchronization phase can leave the port in a state that can not
752 * be recovered by a SATA-hard-reset alone. The failing signature is
753 * SStatus.DET stuck at 1 ("Device presence detected but Phy
754 * communication not established"). It was found that unloading and
755 * reloading the driver when this problem occurs allows the drive
756 * connection to be recovered (DET advanced to 0x3). The critical
757 * component of reloading the driver is that the port state machines are
758 * reset by bouncing "port enable" in the AHCI PCS configuration
759 * register. So, reproduce that effect by bouncing a port whenever we
760 * see DET==1 after a reset.
761 */
762static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
763 unsigned long deadline)
764{
765 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
766 struct ata_port *ap = link->ap;
767 struct ahci_port_priv *pp = ap->private_data;
768 struct ahci_host_priv *hpriv = ap->host->private_data;
769 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
770 unsigned long tmo = deadline - jiffies;
771 struct ata_taskfile tf;
772 bool online;
773 int rc, i;
774
775 DPRINTK("ENTER\n");
776
777 ahci_stop_engine(ap);
778
779 for (i = 0; i < 2; i++) {
780 u16 val;
781 u32 sstatus;
782 int port = ap->port_no;
783 struct ata_host *host = ap->host;
784 struct pci_dev *pdev = to_pci_dev(host->dev);
785
786 /* clear D2H reception area to properly wait for D2H FIS */
787 ata_tf_init(link->device, &tf);
788 tf.command = ATA_BUSY;
789 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
790
791 rc = sata_link_hardreset(link, timing, deadline, &online,
792 ahci_check_ready);
793
794 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
795 (sstatus & 0xf) != 1)
796 break;
797
798 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
799 port);
800
801 pci_read_config_word(pdev, 0x92, &val);
802 val &= ~(1 << port);
803 pci_write_config_word(pdev, 0x92, val);
804 ata_msleep(ap, 1000);
805 val |= 1 << port;
806 pci_write_config_word(pdev, 0x92, val);
807 deadline += tmo;
808 }
809
810 hpriv->start_engine(ap);
811
812 if (online)
813 *class = ahci_dev_classify(ap);
814
815 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
816 return rc;
817}
818
819
02e53293
MW		 820#ifdef CONFIG_PM
821static void ahci_pci_disable_interrupts(struct ata_host *host)
c1332875 822{
9b10ae86 823 struct ahci_host_priv *hpriv = host->private_data;
d8993349 824 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 825 u32 ctl;
826
f1d848f9
MW		 827 /* AHCI spec rev1.1 section 8.3.3:
828 * Software must disable interrupts prior to requesting a
829 * transition of the HBA to D3 state.
830 */
831 ctl = readl(mmio + HOST_CTL);
832 ctl &= ~HOST_IRQ_EN;
833 writel(ctl, mmio + HOST_CTL);
834 readl(mmio + HOST_CTL); /* flush */
02e53293
MW		 835}
836
837static int ahci_pci_device_runtime_suspend(struct device *dev)
838{
839 struct pci_dev *pdev = to_pci_dev(dev);
840 struct ata_host *host = pci_get_drvdata(pdev);
c1332875 841
02e53293
MW		 842 ahci_pci_disable_interrupts(host);
843 return 0;
844}
845
846static int ahci_pci_device_runtime_resume(struct device *dev)
847{
848 struct pci_dev *pdev = to_pci_dev(dev);
849 struct ata_host *host = pci_get_drvdata(pdev);
850 int rc;
851
852 rc = ahci_pci_reset_controller(host);
853 if (rc)
854 return rc;
855 ahci_pci_init_controller(host);
856 return 0;
857}
858
859#ifdef CONFIG_PM_SLEEP
860static int ahci_pci_device_suspend(struct device *dev)
861{
862 struct pci_dev *pdev = to_pci_dev(dev);
863 struct ata_host *host = pci_get_drvdata(pdev);
864 struct ahci_host_priv *hpriv = host->private_data;
865
866 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
867 dev_err(&pdev->dev,
868 "BIOS update required for suspend/resume\n");
869 return -EIO;
870 }
871
872 ahci_pci_disable_interrupts(host);
f1d848f9 873 return ata_host_suspend(host, PMSG_SUSPEND);
c1332875
TH		 874}
875
f1d848f9 876static int ahci_pci_device_resume(struct device *dev)
c1332875 877{
f1d848f9 878 struct pci_dev *pdev = to_pci_dev(dev);
0a86e1c8 879 struct ata_host *host = pci_get_drvdata(pdev);
c1332875
TH		 880 int rc;
881
cb85696d
JL		 882 /* Apple BIOS helpfully mangles the registers on resume */
883 if (is_mcp89_apple(pdev))
884 ahci_mcp89_apple_enable(pdev);
885
c1332875 886 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 887 rc = ahci_pci_reset_controller(host);
c1332875
TH		 888 if (rc)
889 return rc;
890
781d6550 891 ahci_pci_init_controller(host);
c1332875
TH		 892 }
893
cca3974e 894 ata_host_resume(host);
c1332875
TH		 895
896 return 0;
897}
438ac6d5 898#endif
c1332875 899
02e53293
MW		 900#endif /* CONFIG_PM */
901
4447d351 902static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 903{
1da177e4 904 int rc;
1da177e4 905
318893e1
AR		 906 /*
907 * If the device fixup already set the dma_mask to some non-standard
908 * value, don't extend it here. This happens on STA2X11, for example.
909 */
910 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
911 return 0;
912
1da177e4 913 if (using_dac &&
c54c719b
QL		 914 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
915 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1da177e4 916 if (rc) {
c54c719b 917 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1da177e4 918 if (rc) {
a44fec1f
JP		 919 dev_err(&pdev->dev,
920 "64-bit DMA enable failed\n");
1da177e4
LT		 921 return rc;
922 }
923 }
1da177e4 924 } else {
c54c719b 925 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1da177e4 926 if (rc) {
a44fec1f 927 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 928 return rc;
929 }
c54c719b 930 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1da177e4 931 if (rc) {
a44fec1f
JP		 932 dev_err(&pdev->dev,
933 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 934 return rc;
935 }
936 }
1da177e4
LT		 937 return 0;
938}
939
439fcaec
AV		 940static void ahci_pci_print_info(struct ata_host *host)
941{
942 struct pci_dev *pdev = to_pci_dev(host->dev);
943 u16 cc;
944 const char *scc_s;
945
946 pci_read_config_word(pdev, 0x0a, &cc);
947 if (cc == PCI_CLASS_STORAGE_IDE)
948 scc_s = "IDE";
949 else if (cc == PCI_CLASS_STORAGE_SATA)
950 scc_s = "SATA";
951 else if (cc == PCI_CLASS_STORAGE_RAID)
952 scc_s = "RAID";
953 else
954 scc_s = "unknown";
955
956 ahci_print_info(host, scc_s);
957}
958
edc93052
TH		 959/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
960 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
961 * support PMP and the 4726 either directly exports the device
962 * attached to the first downstream port or acts as a hardware storage
963 * controller and emulate a single ATA device (can be RAID 0/1 or some
964 * other configuration).
965 *
966 * When there's no device attached to the first downstream port of the
967 * 4726, "Config Disk" appears, which is a pseudo ATA device to
968 * configure the 4726. However, ATA emulation of the device is very
969 * lame. It doesn't send signature D2H Reg FIS after the initial
970 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
971 *
972 * The following function works around the problem by always using
973 * hardreset on the port and not depending on receiving signature FIS
974 * afterward. If signature FIS isn't received soon, ATA class is
975 * assumed without follow-up softreset.
976 */
977static void ahci_p5wdh_workaround(struct ata_host *host)
978{
1bd06867 979 static const struct dmi_system_id sysids[] = {
edc93052
TH		 980 {
981 .ident = "P5W DH Deluxe",
982 .matches = {
983 DMI_MATCH(DMI_SYS_VENDOR,
984 "ASUSTEK COMPUTER INC"),
985 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
986 },
987 },
988 { }
989 };
990 struct pci_dev *pdev = to_pci_dev(host->dev);
991
992 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
993 dmi_check_system(sysids)) {
994 struct ata_port *ap = host->ports[1];
995
a44fec1f
JP		 996 dev_info(&pdev->dev,
997 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 998
999 ap->ops = &ahci_p5wdh_ops;
1000 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1001 }
1002}
1003
cb85696d
JL		 1004/*
1005 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1006 * booting in BIOS compatibility mode. We restore the registers but not ID.
1007 */
1008static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1009{
1010 u32 val;
1011
1012 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1013
1014 pci_read_config_dword(pdev, 0xf8, &val);
1015 val |= 1 << 0x1b;
1016 /* the following changes the device ID, but appears not to affect function */
1017 /* val = (val & ~0xf0000000) | 0x80000000; */
1018 pci_write_config_dword(pdev, 0xf8, val);
1019
1020 pci_read_config_dword(pdev, 0x54c, &val);
1021 val |= 1 << 0xc;
1022 pci_write_config_dword(pdev, 0x54c, val);
1023
1024 pci_read_config_dword(pdev, 0x4a4, &val);
1025 val &= 0xff;
1026 val |= 0x01060100;
1027 pci_write_config_dword(pdev, 0x4a4, val);
1028
1029 pci_read_config_dword(pdev, 0x54c, &val);
1030 val &= ~(1 << 0xc);
1031 pci_write_config_dword(pdev, 0x54c, val);
1032
1033 pci_read_config_dword(pdev, 0xf8, &val);
1034 val &= ~(1 << 0x1b);
1035 pci_write_config_dword(pdev, 0xf8, val);
1036}
1037
1038static bool is_mcp89_apple(struct pci_dev *pdev)
1039{
1040 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1041 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1042 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1043 pdev->subsystem_device == 0xcb89;
1044}
1045
2fcad9d2
TH		 1046/* only some SB600 ahci controllers can do 64bit DMA */
1047static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 1048{
1049 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 1050 /*
1051 * The oldest version known to be broken is 0901 and
1052 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 1053 * Enable 64bit DMA on 1501 and anything newer.
1054 *
03d783bf
TH		 1055 * Please read bko#9412 for more info.
1056 */
58a09b38
SH		 1057 {
1058 .ident = "ASUS M2A-VM",
1059 .matches = {
1060 DMI_MATCH(DMI_BOARD_VENDOR,
1061 "ASUSTeK Computer INC."),
1062 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1063 },
03d783bf 1064 .driver_data = "20071026", /* yyyymmdd */
58a09b38 1065 },
e65cc194
MN		 1066 /*
1067 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1068 * support 64bit DMA.
1069 *
1070 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1071 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1072 * This spelling mistake was fixed in BIOS version 1.5, so
1073 * 1.5 and later have the Manufacturer as
1074 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1075 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1076 *
1077 * BIOS versions earlier than 1.9 had a Board Product Name
1078 * DMI field of "MS-7376". This was changed to be
1079 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1080 * match on DMI_BOARD_NAME of "MS-7376".
1081 */
1082 {
1083 .ident = "MSI K9A2 Platinum",
1084 .matches = {
1085 DMI_MATCH(DMI_BOARD_VENDOR,
1086 "MICRO-STAR INTER"),
1087 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1088 },
1089 },
ff0173c1
MN		 1090 /*
1091 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1092 * 64bit DMA.
1093 *
1094 * This board also had the typo mentioned above in the
1095 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1096 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1097 */
1098 {
1099 .ident = "MSI K9AGM2",
1100 .matches = {
1101 DMI_MATCH(DMI_BOARD_VENDOR,
1102 "MICRO-STAR INTER"),
1103 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1104 },
1105 },
3c4aa91f
MN		 1106 /*
1107 * All BIOS versions for the Asus M3A support 64bit DMA.
1108 * (all release versions from 0301 to 1206 were tested)
1109 */
1110 {
1111 .ident = "ASUS M3A",
1112 .matches = {
1113 DMI_MATCH(DMI_BOARD_VENDOR,
1114 "ASUSTeK Computer INC."),
1115 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1116 },
1117 },
58a09b38
SH		 1118 { }
1119 };
03d783bf 1120 const struct dmi_system_id *match;
2fcad9d2
TH		 1121 int year, month, date;
1122 char buf[9];
58a09b38 1123
03d783bf 1124 match = dmi_first_match(sysids);
58a09b38 1125 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 1126 !match)
58a09b38
SH		 1127 return false;
1128
e65cc194
MN		 1129 if (!match->driver_data)
1130 goto enable_64bit;
1131
2fcad9d2
TH		 1132 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1133 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 1134
e65cc194
MN		 1135 if (strcmp(buf, match->driver_data) >= 0)
1136 goto enable_64bit;
1137 else {
a44fec1f
JP		 1138 dev_warn(&pdev->dev,
1139 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1140 match->ident);
2fcad9d2
TH		 1141 return false;
1142 }
e65cc194
MN		 1143
1144enable_64bit:
a44fec1f 1145 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 1146 return true;
58a09b38
SH		 1147}
1148
1fd68434
RW		 1149static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1150{
1151 static const struct dmi_system_id broken_systems[] = {
1152 {
1153 .ident = "HP Compaq nx6310",
1154 .matches = {
1155 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1156 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1157 },
1158 /* PCI slot number of the controller */
1159 .driver_data = (void *)0x1FUL,
1160 },
d2f9c061
MR		 1161 {
1162 .ident = "HP Compaq 6720s",
1163 .matches = {
1164 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1165 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1166 },
1167 /* PCI slot number of the controller */
1168 .driver_data = (void *)0x1FUL,
1169 },
1fd68434
RW		 1170
1171 { } /* terminate list */
1172 };
1173 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1174
1175 if (dmi) {
1176 unsigned long slot = (unsigned long)dmi->driver_data;
1177 /* apply the quirk only to on-board controllers */
1178 return slot == PCI_SLOT(pdev->devfn);
1179 }
1180
1181 return false;
1182}
1183
9b10ae86
TH		 1184static bool ahci_broken_suspend(struct pci_dev *pdev)
1185{
1186 static const struct dmi_system_id sysids[] = {
1187 /*
1188 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1189 * to the harddisk doesn't become online after
1190 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 1191 *
1192 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1193 *
1194 * Use dates instead of versions to match as HP is
1195 * apparently recycling both product and version
1196 * strings.
1197 *
1198 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 1199 */
1200 {
1201 .ident = "dv4",
1202 .matches = {
1203 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1204 DMI_MATCH(DMI_PRODUCT_NAME,
1205 "HP Pavilion dv4 Notebook PC"),
1206 },
9deb3431 1207 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 1208 },
1209 {
1210 .ident = "dv5",
1211 .matches = {
1212 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1213 DMI_MATCH(DMI_PRODUCT_NAME,
1214 "HP Pavilion dv5 Notebook PC"),
1215 },
9deb3431 1216 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 1217 },
1218 {
1219 .ident = "dv6",
1220 .matches = {
1221 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1222 DMI_MATCH(DMI_PRODUCT_NAME,
1223 "HP Pavilion dv6 Notebook PC"),
1224 },
9deb3431 1225 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 1226 },
1227 {
1228 .ident = "HDX18",
1229 .matches = {
1230 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1231 DMI_MATCH(DMI_PRODUCT_NAME,
1232 "HP HDX18 Notebook PC"),
1233 },
9deb3431 1234 .driver_data = "20090430", /* F.23 */
9b10ae86 1235 },
cedc9bf9
TH		 1236 /*
1237 * Acer eMachines G725 has the same problem. BIOS
1238 * V1.03 is known to be broken. V3.04 is known to
25985edc 1239 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 1240 * that we don't have much idea about. For now,
1241 * blacklist anything older than V3.04.
9deb3431
TH		 1242 *
1243 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 1244 */
1245 {
1246 .ident = "G725",
1247 .matches = {
1248 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1249 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1250 },
9deb3431 1251 .driver_data = "20091216", /* V3.04 */
cedc9bf9 1252 },
9b10ae86
TH		 1253 { } /* terminate list */
1254 };
1255 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 1256 int year, month, date;
1257 char buf[9];
9b10ae86
TH		 1258
1259 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1260 return false;
1261
9deb3431
TH		 1262 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1263 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 1264
9deb3431 1265 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 1266}
1267
5594639a
TH		 1268static bool ahci_broken_online(struct pci_dev *pdev)
1269{
1270#define ENCODE_BUSDEVFN(bus, slot, func) \
1271 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1272 static const struct dmi_system_id sysids[] = {
1273 /*
1274 * There are several gigabyte boards which use
1275 * SIMG5723s configured as hardware RAID. Certain
1276 * 5723 firmware revisions shipped there keep the link
1277 * online but fail to answer properly to SRST or
1278 * IDENTIFY when no device is attached downstream
1279 * causing libata to retry quite a few times leading
1280 * to excessive detection delay.
1281 *
1282 * As these firmwares respond to the second reset try
1283 * with invalid device signature, considering unknown
1284 * sig as offline works around the problem acceptably.
1285 */
1286 {
1287 .ident = "EP45-DQ6",
1288 .matches = {
1289 DMI_MATCH(DMI_BOARD_VENDOR,
1290 "Gigabyte Technology Co., Ltd."),
1291 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1292 },
1293 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1294 },
1295 {
1296 .ident = "EP45-DS5",
1297 .matches = {
1298 DMI_MATCH(DMI_BOARD_VENDOR,
1299 "Gigabyte Technology Co., Ltd."),
1300 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1301 },
1302 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1303 },
1304 { } /* terminate list */
1305 };
1306#undef ENCODE_BUSDEVFN
1307 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1308 unsigned int val;
1309
1310 if (!dmi)
1311 return false;
1312
1313 val = (unsigned long)dmi->driver_data;
1314
1315 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1316}
1317
0cf4a7d6
JP		 1318static bool ahci_broken_devslp(struct pci_dev *pdev)
1319{
1320 /* device with broken DEVSLP but still showing SDS capability */
1321 static const struct pci_device_id ids[] = {
1322 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1323 {}
1324 };
1325
1326 return pci_match_id(ids, pdev);
1327}
1328
8e513217 1329#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1330static void ahci_gtf_filter_workaround(struct ata_host *host)
1331{
1332 static const struct dmi_system_id sysids[] = {
1333 /*
1334 * Aspire 3810T issues a bunch of SATA enable commands
1335 * via _GTF including an invalid one and one which is
1336 * rejected by the device. Among the successful ones
1337 * is FPDMA non-zero offset enable which when enabled
1338 * only on the drive side leads to NCQ command
1339 * failures. Filter it out.
1340 */
1341 {
1342 .ident = "Aspire 3810T",
1343 .matches = {
1344 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1345 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1346 },
1347 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1348 },
1349 { }
1350 };
1351 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1352 unsigned int filter;
1353 int i;
1354
1355 if (!dmi)
1356 return;
1357
1358 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1359 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1360 filter, dmi->ident);
f80ae7e4
TH		 1361
1362 for (i = 0; i < host->n_ports; i++) {
1363 struct ata_port *ap = host->ports[i];
1364 struct ata_link *link;
1365 struct ata_device *dev;
1366
1367 ata_for_each_link(link, ap, EDGE)
1368 ata_for_each_dev(dev, link, ALL)
1369 dev->gtf_filter |= filter;
1370 }
1371}
8e513217
MT		 1372#else
1373static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1374{}
1375#endif
f80ae7e4 1376
8bfd1743
SC		 1377/*
1378 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1379 * as DUMMY, or detected but eventually get a "link down" and never get up
1380 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1381 * port_map may hold a value of 0x00.
1382 *
1383 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1384 * and can significantly reduce the occurrence of the problem.
1385 *
1386 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1387 */
1388static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1389 struct pci_dev *pdev)
1390{
1391 static const struct dmi_system_id sysids[] = {
1392 {
1393 .ident = "Acer Switch Alpha 12",
1394 .matches = {
1395 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1396 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1397 },
1398 },
1399 { }
1400 };
1401
1402 if (dmi_check_system(sysids)) {
1403 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1404 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1405 hpriv->port_map = 0x7;
1406 hpriv->cap = 0xC734FF02;
1407 }
1408 }
1409}
1410
d243bed3
TC		 1411#ifdef CONFIG_ARM64
1412/*
1413 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1414 * Workaround is to make sure all pending IRQs are served before leaving
1415 * handler.
1416 */
1417static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1418{
1419 struct ata_host *host = dev_instance;
1420 struct ahci_host_priv *hpriv;
1421 unsigned int rc = 0;
1422 void __iomem *mmio;
1423 u32 irq_stat, irq_masked;
1424 unsigned int handled = 1;
1425
1426 VPRINTK("ENTER\n");
1427 hpriv = host->private_data;
1428 mmio = hpriv->mmio;
1429 irq_stat = readl(mmio + HOST_IRQ_STAT);
1430 if (!irq_stat)
1431 return IRQ_NONE;
1432
1433 do {
1434 irq_masked = irq_stat & hpriv->port_map;
1435 spin_lock(&host->lock);
1436 rc = ahci_handle_port_intr(host, irq_masked);
1437 if (!rc)
1438 handled = 0;
1439 writel(irq_stat, mmio + HOST_IRQ_STAT);
1440 irq_stat = readl(mmio + HOST_IRQ_STAT);
1441 spin_unlock(&host->lock);
1442 } while (irq_stat);
1443 VPRINTK("EXIT\n");
1444
1445 return IRQ_RETVAL(handled);
1446}
1447#endif
1448
aecec8b6
CH		 1449static void ahci_remap_check(struct pci_dev *pdev, int bar,
1450 struct ahci_host_priv *hpriv)
1451{
1452 int i, count = 0;
1453 u32 cap;
1454
1455 /*
1456 * Check if this device might have remapped nvme devices.
1457 */
1458 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1459 pci_resource_len(pdev, bar) < SZ_512K ||
1460 bar != AHCI_PCI_BAR_STANDARD ||
1461 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1462 return;
1463
1464 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1465 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1466 if ((cap & (1 << i)) == 0)
1467 continue;
1468 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1469 != PCI_CLASS_STORAGE_EXPRESS)
1470 continue;
1471
1472 /* We've found a remapped device */
1473 count++;
1474 }
1475
1476 if (!count)
1477 return;
1478
1479 dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count);
f723fa4e
CH		 1480 dev_warn(&pdev->dev,
1481 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1482
1483 /*
1484 * Don't rely on the msi-x capability in the remap case,
1485 * share the legacy interrupt across ahci and remapped devices.
1486 */
1487 hpriv->flags |= AHCI_HFLAG_NO_MSI;
aecec8b6
CH		 1488}
1489
0b9e2988 1490static int ahci_get_irq_vector(struct ata_host *host, int port)
5ca72c4f 1491{
0b9e2988 1492 return pci_irq_vector(to_pci_dev(host->dev), port);
ee2aad42
RR		 1493}
1494
a1c82311
RR		 1495static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1496 struct ahci_host_priv *hpriv)
5ca72c4f 1497{
0b9e2988 1498 int nvec;
5ca72c4f 1499
7b92b4f6 1500 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
a1c82311 1501 return -ENODEV;
7b92b4f6 1502
7b92b4f6
AG		 1503 /*
1504 * If number of MSIs is less than number of ports then Sharing Last
1505 * Message mode could be enforced. In this case assume that advantage
1506 * of multipe MSIs is negated and use single MSI mode instead.
1507 */
17a51f12
CH		 1508 if (n_ports > 1) {
1509 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1510 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1511 if (nvec > 0) {
1512 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1513 hpriv->get_irq_vector = ahci_get_irq_vector;
1514 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1515 return nvec;
1516 }
5ca72c4f 1517
17a51f12
CH		 1518 /*
1519 * Fallback to single MSI mode if the controller
1520 * enforced MRSM mode.
1521 */
1522 printk(KERN_INFO
1523 "ahci: MRSM is on, fallback to single MSI\n");
1524 pci_free_irq_vectors(pdev);
1525 }
a478b097 1526 }
d684a90d 1527
0b9e2988
CH		 1528 /*
1529 * If the host is not capable of supporting per-port vectors, fall
1530 * back to single MSI before finally attempting single MSI-X.
1531 */
1532 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1533 if (nvec == 1)
ee2aad42 1534 return nvec;
0b9e2988 1535 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
5ca72c4f
AG		 1536}
1537
24dc5f33 1538static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1539{
e297d99e
TH		 1540 unsigned int board_id = ent->driver_data;
1541 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1542 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1543 struct device *dev = &pdev->dev;
1da177e4 1544 struct ahci_host_priv *hpriv;
4447d351 1545 struct ata_host *host;
c3ebd6a9 1546 int n_ports, i, rc;
318893e1 1547 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1548
1549 VPRINTK("ENTER\n");
1550
b429dd59 1551 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1552
06296a1e 1553 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1554
5b66c829
AC		 1555 /* The AHCI driver can only drive the SATA ports, the PATA driver
1556 can drive them all so if both drivers are selected make sure
1557 AHCI stays out of the way */
1558 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1559 return -ENODEV;
1560
cb85696d
JL		 1561 /* Apple BIOS on MCP89 prevents us using AHCI */
1562 if (is_mcp89_apple(pdev))
1563 ahci_mcp89_apple_enable(pdev);
c6353b45 1564
7a02267e
MN		 1565 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1566 * At the moment, we can only use the AHCI mode. Let the users know
1567 * that for SAS drives they're out of luck.
1568 */
1569 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1570 dev_info(&pdev->dev,
1571 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1572
b7ae128d 1573 /* Some devices use non-standard BARs */
318893e1
AR		 1574 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1575 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
7f9c9f8e
HD		 1576 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1577 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
b1314e3f
RMC		 1578 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1579 if (pdev->device == 0xa01c)
1580 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1581 if (pdev->device == 0xa084)
1582 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1583 }
318893e1 1584
4447d351 1585 /* acquire resources */
24dc5f33 1586 rc = pcim_enable_device(pdev);
1da177e4
LT		 1587 if (rc)
1588 return rc;
1589
c4f7792c
TH		 1590 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1591 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1592 u8 map;
1593
1594 /* ICH6s share the same PCI ID for both piix and ahci
1595 * modes. Enabling ahci mode while MAP indicates
1596 * combined mode is a bad idea. Yield to ata_piix.
1597 */
1598 pci_read_config_byte(pdev, ICH_MAP, &map);
1599 if (map & 0x3) {
a44fec1f
JP		 1600 dev_info(&pdev->dev,
1601 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1602 return -ENODEV;
1603 }
1604 }
1605
6fec8871
PB		 1606 /* AHCI controllers often implement SFF compatible interface.
1607 * Grab all PCI BARs just in case.
1608 */
1609 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1610 if (rc == -EBUSY)
1611 pcim_pin_device(pdev);
1612 if (rc)
1613 return rc;
1614
24dc5f33
TH		 1615 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1616 if (!hpriv)
1617 return -ENOMEM;
417a1a6d
TH		 1618 hpriv->flags |= (unsigned long)pi.private_data;
1619
e297d99e
TH		 1620 /* MCP65 revision A1 and A2 can't do MSI */
1621 if (board_id == board_ahci_mcp65 &&
1622 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1623 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1624
e427fe04
SH		 1625 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1626 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1627 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1628
2fcad9d2
TH		 1629 /* only some SB600s can do 64bit DMA */
1630 if (ahci_sb600_enable_64bit(pdev))
1631 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1632
318893e1 1633 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1634
aecec8b6
CH		 1635 /* detect remapped nvme devices */
1636 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1637
0cf4a7d6
JP		 1638 /* must set flag prior to save config in order to take effect */
1639 if (ahci_broken_devslp(pdev))
1640 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1641
d243bed3
TC		 1642#ifdef CONFIG_ARM64
1643 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1644 hpriv->irq_handler = ahci_thunderx_irq_handler;
1645#endif
1646
4447d351 1647 /* save initial config */
394d6e53 1648 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1649
4447d351 1650 /* prepare host */
453d3131
RH		 1651 if (hpriv->cap & HOST_CAP_NCQ) {
1652 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1653 /*
1654 * Auto-activate optimization is supposed to be
1655 * supported on all AHCI controllers indicating NCQ
1656 * capability, but it seems to be broken on some
1657 * chipsets including NVIDIAs.
1658 */
1659 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131 1660 pi.flags |= ATA_FLAG_FPDMA_AA;
40fb59e7
MC		 1661
1662 /*
1663 * All AHCI controllers should be forward-compatible
1664 * with the new auxiliary field. This code should be
1665 * conditionalized if any buggy AHCI controllers are
1666 * encountered.
1667 */
1668 pi.flags |= ATA_FLAG_FPDMA_AUX;
453d3131 1669 }
1da177e4 1670
7d50b60b
TH		 1671 if (hpriv->cap & HOST_CAP_PMP)
1672 pi.flags |= ATA_FLAG_PMP;
1673
0cbb0e77 1674 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1675
1fd68434
RW		 1676 if (ahci_broken_system_poweroff(pdev)) {
1677 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1678 dev_info(&pdev->dev,
1679 "quirky BIOS, skipping spindown on poweroff\n");
1680 }
1681
9b10ae86
TH		 1682 if (ahci_broken_suspend(pdev)) {
1683 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1684 dev_warn(&pdev->dev,
1685 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1686 }
1687
5594639a
TH		 1688 if (ahci_broken_online(pdev)) {
1689 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1690 dev_info(&pdev->dev,
1691 "online status unreliable, applying workaround\n");
1692 }
1693
8bfd1743
SC		 1694
1695 /* Acer SA5-271 workaround modifies private_data */
1696 acer_sa5_271_workaround(hpriv, pdev);
1697
837f5f8f
TH		 1698 /* CAP.NP sometimes indicate the index of the last enabled
1699 * port, at other times, that of the last possible port, so
1700 * determining the maximum port number requires looking at
1701 * both CAP.NP and port_map.
1702 */
1703 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1704
1705 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1706 if (!host)
1707 return -ENOMEM;
4447d351 1708 host->private_data = hpriv;
0b9e2988
CH		 1709
1710 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1711 /* legacy intx interrupts */
1712 pci_intx(pdev, 1);
1713 }
0ce57f8a 1714 hpriv->irq = pci_irq_vector(pdev, 0);
21bfd1aa 1715
f3d7f23f 1716 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1717 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f 1718 else
d2782d96 1719 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
886ad09f 1720
18f7ba4c
KCA		 1721 if (pi.flags & ATA_FLAG_EM)
1722 ahci_reset_em(host);
1723
4447d351 1724 for (i = 0; i < host->n_ports; i++) {
dab632e8 1725 struct ata_port *ap = host->ports[i];
4447d351 1726
318893e1
AR		 1727 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1728 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1729 0x100 + ap->port_no * 0x80, "port");
1730
18f7ba4c
KCA		 1731 /* set enclosure management message type */
1732 if (ap->flags & ATA_FLAG_EM)
008dbd61 1733 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1734
1735
dab632e8 1736 /* disabled/not-implemented port */
350756f6 1737 if (!(hpriv->port_map & (1 << i)))
dab632e8 1738 ap->ops = &ata_dummy_port_ops;
4447d351 1739 }
d447df14 1740
edc93052
TH		 1741 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1742 ahci_p5wdh_workaround(host);
1743
f80ae7e4
TH		 1744 /* apply gtf filter quirk */
1745 ahci_gtf_filter_workaround(host);
1746
4447d351
TH		 1747 /* initialize adapter */
1748 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1749 if (rc)
24dc5f33 1750 return rc;
1da177e4 1751
3303040d 1752 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1753 if (rc)
1754 return rc;
1da177e4 1755
781d6550 1756 ahci_pci_init_controller(host);
439fcaec 1757 ahci_pci_print_info(host);
1da177e4 1758
4447d351 1759 pci_set_master(pdev);
5ca72c4f 1760
02e53293
MW		 1761 rc = ahci_host_activate(host, &ahci_sht);
1762 if (rc)
1763 return rc;
1764
1765 pm_runtime_put_noidle(&pdev->dev);
1766 return 0;
1767}
1768
1769static void ahci_remove_one(struct pci_dev *pdev)
1770{
1771 pm_runtime_get_noresume(&pdev->dev);
1772 ata_pci_remove_one(pdev);
907f4678 1773}
1da177e4 1774
2fc75da0 1775module_pci_driver(ahci_pci_driver);
1da177e4
LT		 1776
1777MODULE_AUTHOR("Jeff Garzik");
1778MODULE_DESCRIPTION("AHCI SATA low-level driver");
1779MODULE_LICENSE("GPL");
1780MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1781MODULE_VERSION(DRV_VERSION);
Linux 6.x block layer and io_uring tree(s)