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ata: ahci: Add sysfs attribute to show remapped NVMe device count
[linux-block.git] / drivers / ata / ahci.c
CommitLineData
c82ee6d3 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4
LT		 2/*
3 * ahci.c - AHCI SATA support
4 *
8c3d3d4b 5 * Maintained by: Tejun Heo <tj@kernel.org>
af36d7f0
JG		 6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
af36d7f0 11 * libata documentation is available via 'make {ps|pdf}docs',
19285f3c 12 * as Documentation/driver-api/libata.rst
af36d7f0
JG		 13 *
14 * AHCI hardware documentation:
1da177e4 15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
1da177e4
LT		 22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <linux/interrupt.h>
87507cfd 25#include <linux/dma-mapping.h>
a9524a76 26#include <linux/device.h>
edc93052 27#include <linux/dmi.h>
5a0e3ad6 28#include <linux/gfp.h>
ee2aad42 29#include <linux/msi.h>
1da177e4 30#include <scsi/scsi_host.h>
193515d5 31#include <scsi/scsi_cmnd.h>
1da177e4 32#include <linux/libata.h>
aecec8b6
CH		 33#include <linux/ahci-remap.h>
34#include <linux/io-64-nonatomic-lo-hi.h>
365cfa1e 35#include "ahci.h"
1da177e4
LT		 36
37#define DRV_NAME "ahci"
7d50b60b 38#define DRV_VERSION "3.0"
1da177e4 39
1da177e4 40enum {
318893e1 41 AHCI_PCI_BAR_STA2X11 = 0,
b7ae128d 42 AHCI_PCI_BAR_CAVIUM = 0,
e49bd683 43 AHCI_PCI_BAR_LOONGSON = 0,
7f9c9f8e 44 AHCI_PCI_BAR_ENMOTUS = 2,
b1314e3f 45 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
318893e1 46 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 47};
48
49enum board_ids {
50 /* board IDs by feature in alphabetical order */
51 board_ahci,
52 board_ahci_ign_iferr,
ebb82e3c 53 board_ahci_mobile,
66a7cbc3 54 board_ahci_nomsi,
67809f85 55 board_ahci_noncq,
441577ef 56 board_ahci_nosntf,
5f173107 57 board_ahci_yes_fbs,
1da177e4 58
441577ef 59 /* board IDs for specific chipsets in alphabetical order */
7d523bdc 60 board_ahci_al,
dbfe8ef5 61 board_ahci_avn,
441577ef 62 board_ahci_mcp65,
83f2b963
TH		 63 board_ahci_mcp77,
64 board_ahci_mcp89,
441577ef
TH		 65 board_ahci_mv,
66 board_ahci_sb600,
67 board_ahci_sb700, /* for SB700 and SB800 */
68 board_ahci_vt8251,
69
c312ef17
DW		 70 /*
71 * board IDs for Intel chipsets that support more than 6 ports
72 * *and* end up needing the PCS quirk.
73 */
74 board_ahci_pcs7,
75
441577ef
TH		 76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 80 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 81};
82
2dcb407e 83static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
02e53293 84static void ahci_remove_one(struct pci_dev *dev);
10a663a1 85static void ahci_shutdown_one(struct pci_dev *dev);
a1efdaba
TH		 86static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
dbfe8ef5
DW		 88static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
cb85696d
JL		 90static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
91static bool is_mcp89_apple(struct pci_dev *pdev);
a1efdaba
TH		 92static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
93 unsigned long deadline);
02e53293
MW		 94#ifdef CONFIG_PM
95static int ahci_pci_device_runtime_suspend(struct device *dev);
96static int ahci_pci_device_runtime_resume(struct device *dev);
f1d848f9
MW		 97#ifdef CONFIG_PM_SLEEP
98static int ahci_pci_device_suspend(struct device *dev);
99static int ahci_pci_device_resume(struct device *dev);
438ac6d5 100#endif
02e53293 101#endif /* CONFIG_PM */
ad616ffb 102
fad16e7a
TH		 103static struct scsi_host_template ahci_sht = {
104 AHCI_SHT("ahci"),
105};
106
029cfd6b
TH		 107static struct ata_port_operations ahci_vt8251_ops = {
108 .inherits = &ahci_ops,
a1efdaba 109 .hardreset = ahci_vt8251_hardreset,
029cfd6b 110};
edc93052 111
029cfd6b
TH		 112static struct ata_port_operations ahci_p5wdh_ops = {
113 .inherits = &ahci_ops,
a1efdaba 114 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 115};
116
dbfe8ef5
DW		 117static struct ata_port_operations ahci_avn_ops = {
118 .inherits = &ahci_ops,
119 .hardreset = ahci_avn_hardreset,
120};
121
98ac62de 122static const struct ata_port_info ahci_port_info[] = {
441577ef 123 /* by features */
facb8fa6 124 [board_ahci] = {
1188c0d8 125 .flags = AHCI_FLAG_COMMON,
14bdef98 126 .pio_mask = ATA_PIO4,
469248ab 127 .udma_mask = ATA_UDMA6,
1da177e4
LT		 128 .port_ops = &ahci_ops,
129 },
facb8fa6 130 [board_ahci_ign_iferr] = {
441577ef 131 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 132 .flags = AHCI_FLAG_COMMON,
14bdef98 133 .pio_mask = ATA_PIO4,
469248ab 134 .udma_mask = ATA_UDMA6,
441577ef 135 .port_ops = &ahci_ops,
bf2af2a2 136 },
ebb82e3c
HG		 137 [board_ahci_mobile] = {
138 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
139 .flags = AHCI_FLAG_COMMON,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
143 },
66a7cbc3
TH		 144 [board_ahci_nomsi] = {
145 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
146 .flags = AHCI_FLAG_COMMON,
147 .pio_mask = ATA_PIO4,
148 .udma_mask = ATA_UDMA6,
149 .port_ops = &ahci_ops,
150 },
67809f85
LK		 151 [board_ahci_noncq] = {
152 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
facb8fa6 158 [board_ahci_nosntf] = {
441577ef 159 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 160 .flags = AHCI_FLAG_COMMON,
14bdef98 161 .pio_mask = ATA_PIO4,
469248ab 162 .udma_mask = ATA_UDMA6,
41669553
TH		 163 .port_ops = &ahci_ops,
164 },
facb8fa6 165 [board_ahci_yes_fbs] = {
5f173107
TH		 166 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
167 .flags = AHCI_FLAG_COMMON,
168 .pio_mask = ATA_PIO4,
169 .udma_mask = ATA_UDMA6,
170 .port_ops = &ahci_ops,
171 },
441577ef 172 /* by chipsets */
7d523bdc
HH		 173 [board_ahci_al] = {
174 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
175 .flags = AHCI_FLAG_COMMON,
176 .pio_mask = ATA_PIO4,
177 .udma_mask = ATA_UDMA6,
178 .port_ops = &ahci_ops,
179 },
dbfe8ef5
DW		 180 [board_ahci_avn] = {
181 .flags = AHCI_FLAG_COMMON,
182 .pio_mask = ATA_PIO4,
183 .udma_mask = ATA_UDMA6,
184 .port_ops = &ahci_avn_ops,
185 },
facb8fa6 186 [board_ahci_mcp65] = {
83f2b963
TH		 187 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
188 AHCI_HFLAG_YES_NCQ),
ae01b249 189 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 190 .pio_mask = ATA_PIO4,
191 .udma_mask = ATA_UDMA6,
192 .port_ops = &ahci_ops,
193 },
facb8fa6 194 [board_ahci_mcp77] = {
83f2b963
TH		 195 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_ops,
200 },
facb8fa6 201 [board_ahci_mcp89] = {
83f2b963 202 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 203 .flags = AHCI_FLAG_COMMON,
14bdef98 204 .pio_mask = ATA_PIO4,
469248ab 205 .udma_mask = ATA_UDMA6,
441577ef 206 .port_ops = &ahci_ops,
55a61604 207 },
facb8fa6 208 [board_ahci_mv] = {
417a1a6d 209 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 210 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 211 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 212 .pio_mask = ATA_PIO4,
cd70c266
JG		 213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_ops,
215 },
facb8fa6 216 [board_ahci_sb600] = {
441577ef
TH		 217 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
218 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
219 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 220 .flags = AHCI_FLAG_COMMON,
14bdef98 221 .pio_mask = ATA_PIO4,
e39fc8c9 222 .udma_mask = ATA_UDMA6,
345347c5 223 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 224 },
facb8fa6 225 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 226 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 227 .flags = AHCI_FLAG_COMMON,
228 .pio_mask = ATA_PIO4,
229 .udma_mask = ATA_UDMA6,
345347c5 230 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 231 },
facb8fa6 232 [board_ahci_vt8251] = {
441577ef 233 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 234 .flags = AHCI_FLAG_COMMON,
235 .pio_mask = ATA_PIO4,
236 .udma_mask = ATA_UDMA6,
441577ef 237 .port_ops = &ahci_vt8251_ops,
1b677afd 238 },
c312ef17
DW		 239 [board_ahci_pcs7] = {
240 .flags = AHCI_FLAG_COMMON,
241 .pio_mask = ATA_PIO4,
242 .udma_mask = ATA_UDMA6,
243 .port_ops = &ahci_ops,
244 },
1da177e4
LT		 245};
246
3b7d697d 247static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 248 /* Intel */
5e125d13 249 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
54bb3a94
JG		 250 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
251 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
252 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
253 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
254 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 255 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 256 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
257 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
258 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
259 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 260 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 261 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 262 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
263 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
264 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
265 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
266 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
267 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
268 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
269 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
ebb82e3c
HG		 270 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
271 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
272 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
273 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
274 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
7a234aff 275 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
ebb82e3c 276 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
d4155e6f
JG		 277 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
278 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 279 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 280 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 281 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 282 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
283 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 284 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 285 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
ebb82e3c 286 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
adcb5308 287 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
ebb82e3c 288 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
c1f57d9b 289 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
c312ef17
DW		 290 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
294 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
295 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
296 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
297 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
298 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
299 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
300 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
301 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
302 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
303 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
304 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
305 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
306 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
309 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
5623cab8 310 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
ebb82e3c 311 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
5623cab8 312 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
ebb82e3c 313 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
5623cab8
SH		 314 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
315 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 316 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
317 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
318 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 319 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 320 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea 321 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
ebb82e3c 322 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
181e3cea
SH		 323 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
324 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
325 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
ebb82e3c 326 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
2cab7a4c 327 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66 328 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
ebb82e3c 329 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
ea4ace66 330 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
ebb82e3c 331 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
ea4ace66 332 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
ebb82e3c 333 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
ea4ace66 334 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
ebb82e3c
HG		 335 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
336 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
337 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
338 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
339 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
340 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
341 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
342 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
343 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
4544e403 344 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
29e674dd
SH		 345 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
346 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
347 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
348 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
349 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
350 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
351 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
352 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
dbfe8ef5
DW		 353 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
354 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
355 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
356 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
357 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
358 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
359 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
360 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
efda332c
JR		 361 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
362 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
151743fd
JR		 363 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
364 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
365 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
366 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
367 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
368 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
369 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
370 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
1cfc7df3 371 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
ebb82e3c
HG		 372 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
373 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
374 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
375 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
1b071a09 376 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
ebb82e3c 377 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
1b071a09 378 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
ebb82e3c 379 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
1b071a09 380 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
ebb82e3c 381 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
1b071a09 382 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
ebb82e3c
HG		 383 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
384 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
385 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
386 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
c5967b79 387 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
ebb82e3c 388 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
690000b9 389 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
c5967b79 390 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
ebb82e3c 391 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
690000b9 392 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
4d92f009 393 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
f5bdd66c 394 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
4d92f009 395 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
f5bdd66c 396 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
4d92f009 397 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
4d92f009 398 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
f5bdd66c
AY		 399 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
400 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
4d92f009 401 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
4d92f009 402 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
f5bdd66c
AY		 403 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
404 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
f919dde0 405 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
32d25454 406 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
58c42b0b 407 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
ebb82e3c
HG		 408 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
409 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
410 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
411 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
ba445791 412 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
fe7fa31a 413
e34bb370
TH		 414 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
415 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
416 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
1fefb8fd
BH		 417 /* JMicron 362B and 362C have an AHCI function with IDE class code */
418 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
419 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
91f15fb3 420 /* May need to update quirk_jmicron_async_suspend() for additions */
fe7fa31a
JG		 421
422 /* ATI */
c65ec1c2 423 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 424 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
425 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
426 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
427 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
428 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
429 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 430
7d523bdc
HH		 431 /* Amazon's Annapurna Labs support */
432 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
433 .class = PCI_CLASS_STORAGE_SATA_AHCI,
434 .class_mask = 0xffffff,
435 board_ahci_al },
e2dd90b1 436 /* AMD */
5deab536 437 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
fafe5c3d 438 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
e2dd90b1
SH		 439 /* AMD is using RAID class only for ahci controllers */
440 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
441 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
442
fe7fa31a 443 /* VIA */
54bb3a94 444 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 445 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 446
447 /* NVIDIA */
e297d99e
TH		 448 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
449 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
450 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
451 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
452 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
453 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
454 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
455 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 456 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
457 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
458 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
459 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
460 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
461 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
462 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
463 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
464 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
465 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
466 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
467 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
468 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
469 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
470 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
471 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
472 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
473 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
474 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
475 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
476 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
477 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
478 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
479 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
480 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
481 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
482 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
483 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
484 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
485 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
486 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
487 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
488 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
489 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
490 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
491 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
492 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
493 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
494 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
495 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
496 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
497 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
498 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
499 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
500 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
501 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
502 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
503 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
504 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
505 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
506 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
507 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
508 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
509 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
510 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
511 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
512 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
513 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
514 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
515 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
516 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
517 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
518 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
519 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
520 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
521 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
522 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
523 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
524 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
525 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
526 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
527 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
528 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
529 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
530 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
531 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 532
95916edd 533 /* SiS */
20e2de4a
TH		 534 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
535 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
536 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 537
318893e1
AR		 538 /* ST Microelectronics */
539 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
540
cd70c266
JG		 541 /* Marvell */
542 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 543 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
69fd3157 544 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
10aca06c
AH		 545 .class = PCI_CLASS_STORAGE_SATA_AHCI,
546 .class_mask = 0xffffff,
5f173107 547 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
69fd3157 548 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
467b41c6 549 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
e098f5cb
SG		 550 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
551 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
552 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
69fd3157 553 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
642d8925 554 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
fcce9a35 555 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
c5edfff9
MK		 556 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
557 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
fcce9a35 558 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
69fd3157 559 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
17c60c6b 560 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
754a292f
AS		 561 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
562 .driver_data = board_ahci_yes_fbs },
a40cf3f3
JT		 563 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
564 .driver_data = board_ahci_yes_fbs },
69fd3157 565 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
50be5e36 566 .driver_data = board_ahci_yes_fbs },
6d5278a6
SB		 567 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
568 .driver_data = board_ahci_yes_fbs },
28b2182d
HG		 569 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
570 .driver_data = board_ahci_yes_fbs },
571 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
d2518365 572 .driver_data = board_ahci_yes_fbs },
cd70c266 573
c77a036b
MN		 574 /* Promise */
575 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
b32bfc06 576 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
c77a036b 577
c9703765 578 /* Asmedia */
7b4f6eca
AC		 579 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
580 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
581 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
582 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
0ce968f3
SL		 583 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
584 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
c9703765 585
67809f85 586 /*
66a7cbc3
TH		 587 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
588 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
67809f85 589 */
66a7cbc3 590 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
2b21ef0a 591 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
67809f85 592
7f9c9f8e
HD		 593 /* Enmotus */
594 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
595
e49bd683
TY		 596 /* Loongson */
597 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
598
415ae2b5
JG		 599 /* Generic, PCI class code for AHCI */
600 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 601 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 602
1da177e4
LT		 603 { } /* terminate list */
604};
605
f1d848f9
MW		 606static const struct dev_pm_ops ahci_pci_pm_ops = {
607 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
02e53293
MW		 608 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
609 ahci_pci_device_runtime_resume, NULL)
f1d848f9 610};
1da177e4
LT		 611
612static struct pci_driver ahci_pci_driver = {
613 .name = DRV_NAME,
614 .id_table = ahci_pci_tbl,
615 .probe = ahci_init_one,
02e53293 616 .remove = ahci_remove_one,
10a663a1 617 .shutdown = ahci_shutdown_one,
f1d848f9
MW		 618 .driver = {
619 .pm = &ahci_pci_pm_ops,
620 },
365cfa1e 621};
1da177e4 622
5219d653 623#if IS_ENABLED(CONFIG_PATA_MARVELL)
365cfa1e
AV		 624static int marvell_enable;
625#else
626static int marvell_enable = 1;
627#endif
628module_param(marvell_enable, int, 0644);
629MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 630
b1a9585c 631static int mobile_lpm_policy = -1;
ebb82e3c
HG		 632module_param(mobile_lpm_policy, int, 0644);
633MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
1da177e4 634
365cfa1e
AV		 635static void ahci_pci_save_initial_config(struct pci_dev *pdev,
636 struct ahci_host_priv *hpriv)
637{
365cfa1e
AV		 638 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
639 dev_info(&pdev->dev, "JMB361 has only one port\n");
9a23c1d6 640 hpriv->force_port_map = 1;
1da177e4
LT		 641 }
642
365cfa1e
AV		 643 /*
644 * Temporary Marvell 6145 hack: PATA port presence
645 * is asserted through the standard AHCI port
646 * presence register, as bit 4 (counting from 0)
d28f87aa 647 */
365cfa1e
AV		 648 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
649 if (pdev->device == 0x6121)
9a23c1d6 650 hpriv->mask_port_map = 0x3;
365cfa1e 651 else
9a23c1d6 652 hpriv->mask_port_map = 0xf;
365cfa1e
AV		 653 dev_info(&pdev->dev,
654 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
655 }
1da177e4 656
725c7b57 657 ahci_save_initial_config(&pdev->dev, hpriv);
1da177e4
LT		 658}
659
365cfa1e 660static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 661{
365cfa1e
AV		 662 struct ahci_host_priv *hpriv = host->private_data;
663 struct pci_dev *pdev = to_pci_dev(host->dev);
664 void __iomem *port_mmio;
78cd52d0 665 u32 tmp;
365cfa1e 666 int mv;
78cd52d0 667
365cfa1e
AV		 668 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
669 if (pdev->device == 0x6121)
670 mv = 2;
671 else
672 mv = 4;
673 port_mmio = __ahci_port_base(host, mv);
78cd52d0 674
365cfa1e 675 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 676
365cfa1e
AV		 677 /* clear port IRQ */
678 tmp = readl(port_mmio + PORT_IRQ_STAT);
679 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
680 if (tmp)
681 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 682 }
683
365cfa1e 684 ahci_init_controller(host);
edc93052
TH		 685}
686
365cfa1e
AV		 687static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
688 unsigned long deadline)
d6ef3153 689{
365cfa1e 690 struct ata_port *ap = link->ap;
039ece38 691 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 692 bool online;
d6ef3153
SH		 693 int rc;
694
365cfa1e 695 DPRINTK("ENTER\n");
d6ef3153 696
fa89f53b 697 hpriv->stop_engine(ap);
d6ef3153 698
365cfa1e
AV		 699 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
700 deadline, &online, NULL);
d6ef3153 701
039ece38 702 hpriv->start_engine(ap);
d6ef3153 703
365cfa1e 704 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 705
365cfa1e
AV		 706 /* vt8251 doesn't clear BSY on signature FIS reception,
707 * request follow-up softreset.
708 */
709 return online ? -EAGAIN : rc;
7d50b60b
TH		 710}
711
365cfa1e
AV		 712static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
713 unsigned long deadline)
7d50b60b 714{
365cfa1e 715 struct ata_port *ap = link->ap;
1c954a4d 716 struct ahci_port_priv *pp = ap->private_data;
039ece38 717 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 718 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
719 struct ata_taskfile tf;
720 bool online;
721 int rc;
7d50b60b 722
fa89f53b 723 hpriv->stop_engine(ap);
028a2596 724
365cfa1e
AV		 725 /* clear D2H reception area to properly wait for D2H FIS */
726 ata_tf_init(link->device, &tf);
9bbb1b0e 727 tf.command = ATA_BUSY;
365cfa1e 728 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 729
365cfa1e
AV		 730 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
731 deadline, &online, NULL);
028a2596 732
039ece38 733 hpriv->start_engine(ap);
c1332875 734
365cfa1e
AV		 735 /* The pseudo configuration device on SIMG4726 attached to
736 * ASUS P5W-DH Deluxe doesn't send signature FIS after
737 * hardreset if no device is attached to the first downstream
738 * port && the pseudo device locks up on SRST w/ PMP==0. To
739 * work around this, wait for !BSY only briefly. If BSY isn't
740 * cleared, perform CLO and proceed to IDENTIFY (achieved by
741 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
742 *
743 * Wait for two seconds. Devices attached to downstream port
744 * which can't process the following IDENTIFY after this will
745 * have to be reset again. For most cases, this should
746 * suffice while making probing snappish enough.
747 */
748 if (online) {
749 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
750 ahci_check_ready);
751 if (rc)
752 ahci_kick_engine(ap);
c1332875 753 }
c1332875
TH		 754 return rc;
755}
756
dbfe8ef5
DW		 757/*
758 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
759 *
760 * It has been observed with some SSDs that the timing of events in the
761 * link synchronization phase can leave the port in a state that can not
762 * be recovered by a SATA-hard-reset alone. The failing signature is
763 * SStatus.DET stuck at 1 ("Device presence detected but Phy
764 * communication not established"). It was found that unloading and
765 * reloading the driver when this problem occurs allows the drive
766 * connection to be recovered (DET advanced to 0x3). The critical
767 * component of reloading the driver is that the port state machines are
768 * reset by bouncing "port enable" in the AHCI PCS configuration
769 * register. So, reproduce that effect by bouncing a port whenever we
770 * see DET==1 after a reset.
771 */
772static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
773 unsigned long deadline)
774{
775 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
776 struct ata_port *ap = link->ap;
777 struct ahci_port_priv *pp = ap->private_data;
778 struct ahci_host_priv *hpriv = ap->host->private_data;
779 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
780 unsigned long tmo = deadline - jiffies;
781 struct ata_taskfile tf;
782 bool online;
783 int rc, i;
784
785 DPRINTK("ENTER\n");
786
fa89f53b 787 hpriv->stop_engine(ap);
dbfe8ef5
DW		 788
789 for (i = 0; i < 2; i++) {
790 u16 val;
791 u32 sstatus;
792 int port = ap->port_no;
793 struct ata_host *host = ap->host;
794 struct pci_dev *pdev = to_pci_dev(host->dev);
795
796 /* clear D2H reception area to properly wait for D2H FIS */
797 ata_tf_init(link->device, &tf);
798 tf.command = ATA_BUSY;
799 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
800
801 rc = sata_link_hardreset(link, timing, deadline, &online,
802 ahci_check_ready);
803
804 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
805 (sstatus & 0xf) != 1)
806 break;
807
808 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
809 port);
810
811 pci_read_config_word(pdev, 0x92, &val);
812 val &= ~(1 << port);
813 pci_write_config_word(pdev, 0x92, val);
814 ata_msleep(ap, 1000);
815 val |= 1 << port;
816 pci_write_config_word(pdev, 0x92, val);
817 deadline += tmo;
818 }
819
820 hpriv->start_engine(ap);
821
822 if (online)
823 *class = ahci_dev_classify(ap);
824
825 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
826 return rc;
827}
828
829
02e53293
MW		 830#ifdef CONFIG_PM
831static void ahci_pci_disable_interrupts(struct ata_host *host)
c1332875 832{
9b10ae86 833 struct ahci_host_priv *hpriv = host->private_data;
d8993349 834 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 835 u32 ctl;
836
f1d848f9
MW		 837 /* AHCI spec rev1.1 section 8.3.3:
838 * Software must disable interrupts prior to requesting a
839 * transition of the HBA to D3 state.
840 */
841 ctl = readl(mmio + HOST_CTL);
842 ctl &= ~HOST_IRQ_EN;
843 writel(ctl, mmio + HOST_CTL);
844 readl(mmio + HOST_CTL); /* flush */
02e53293
MW		 845}
846
847static int ahci_pci_device_runtime_suspend(struct device *dev)
848{
849 struct pci_dev *pdev = to_pci_dev(dev);
850 struct ata_host *host = pci_get_drvdata(pdev);
c1332875 851
02e53293
MW		 852 ahci_pci_disable_interrupts(host);
853 return 0;
854}
855
856static int ahci_pci_device_runtime_resume(struct device *dev)
857{
858 struct pci_dev *pdev = to_pci_dev(dev);
859 struct ata_host *host = pci_get_drvdata(pdev);
860 int rc;
861
c312ef17 862 rc = ahci_reset_controller(host);
02e53293
MW		 863 if (rc)
864 return rc;
865 ahci_pci_init_controller(host);
866 return 0;
867}
868
869#ifdef CONFIG_PM_SLEEP
870static int ahci_pci_device_suspend(struct device *dev)
871{
872 struct pci_dev *pdev = to_pci_dev(dev);
873 struct ata_host *host = pci_get_drvdata(pdev);
874 struct ahci_host_priv *hpriv = host->private_data;
875
876 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
877 dev_err(&pdev->dev,
878 "BIOS update required for suspend/resume\n");
879 return -EIO;
880 }
881
882 ahci_pci_disable_interrupts(host);
f1d848f9 883 return ata_host_suspend(host, PMSG_SUSPEND);
c1332875
TH		 884}
885
f1d848f9 886static int ahci_pci_device_resume(struct device *dev)
c1332875 887{
f1d848f9 888 struct pci_dev *pdev = to_pci_dev(dev);
0a86e1c8 889 struct ata_host *host = pci_get_drvdata(pdev);
c1332875
TH		 890 int rc;
891
cb85696d
JL		 892 /* Apple BIOS helpfully mangles the registers on resume */
893 if (is_mcp89_apple(pdev))
894 ahci_mcp89_apple_enable(pdev);
895
c1332875 896 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
c312ef17 897 rc = ahci_reset_controller(host);
c1332875
TH		 898 if (rc)
899 return rc;
900
781d6550 901 ahci_pci_init_controller(host);
c1332875
TH		 902 }
903
cca3974e 904 ata_host_resume(host);
c1332875
TH		 905
906 return 0;
907}
438ac6d5 908#endif
c1332875 909
02e53293
MW		 910#endif /* CONFIG_PM */
911
4447d351 912static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 913{
b1716871 914 const int dma_bits = using_dac ? 64 : 32;
1da177e4 915 int rc;
1da177e4 916
318893e1
AR		 917 /*
918 * If the device fixup already set the dma_mask to some non-standard
919 * value, don't extend it here. This happens on STA2X11, for example.
b1716871
CH		 920 *
921 * XXX: manipulating the DMA mask from platform code is completely
a7ba70f1 922 * bogus, platform code should use dev->bus_dma_limit instead..
318893e1
AR		 923 */
924 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
925 return 0;
926
b1716871
CH		 927 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
928 if (rc)
929 dev_err(&pdev->dev, "DMA enable failed\n");
930 return rc;
1da177e4
LT		 931}
932
439fcaec
AV		 933static void ahci_pci_print_info(struct ata_host *host)
934{
935 struct pci_dev *pdev = to_pci_dev(host->dev);
936 u16 cc;
937 const char *scc_s;
938
939 pci_read_config_word(pdev, 0x0a, &cc);
940 if (cc == PCI_CLASS_STORAGE_IDE)
941 scc_s = "IDE";
942 else if (cc == PCI_CLASS_STORAGE_SATA)
943 scc_s = "SATA";
944 else if (cc == PCI_CLASS_STORAGE_RAID)
945 scc_s = "RAID";
946 else
947 scc_s = "unknown";
948
949 ahci_print_info(host, scc_s);
950}
951
edc93052
TH		 952/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
953 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
954 * support PMP and the 4726 either directly exports the device
955 * attached to the first downstream port or acts as a hardware storage
956 * controller and emulate a single ATA device (can be RAID 0/1 or some
957 * other configuration).
958 *
959 * When there's no device attached to the first downstream port of the
960 * 4726, "Config Disk" appears, which is a pseudo ATA device to
961 * configure the 4726. However, ATA emulation of the device is very
962 * lame. It doesn't send signature D2H Reg FIS after the initial
963 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
964 *
965 * The following function works around the problem by always using
966 * hardreset on the port and not depending on receiving signature FIS
967 * afterward. If signature FIS isn't received soon, ATA class is
968 * assumed without follow-up softreset.
969 */
970static void ahci_p5wdh_workaround(struct ata_host *host)
971{
1bd06867 972 static const struct dmi_system_id sysids[] = {
edc93052
TH		 973 {
974 .ident = "P5W DH Deluxe",
975 .matches = {
976 DMI_MATCH(DMI_SYS_VENDOR,
977 "ASUSTEK COMPUTER INC"),
978 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
979 },
980 },
981 { }
982 };
983 struct pci_dev *pdev = to_pci_dev(host->dev);
984
985 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
986 dmi_check_system(sysids)) {
987 struct ata_port *ap = host->ports[1];
988
a44fec1f
JP		 989 dev_info(&pdev->dev,
990 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 991
992 ap->ops = &ahci_p5wdh_ops;
993 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
994 }
995}
996
cb85696d
JL		 997/*
998 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
999 * booting in BIOS compatibility mode. We restore the registers but not ID.
1000 */
1001static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1002{
1003 u32 val;
1004
1005 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1006
1007 pci_read_config_dword(pdev, 0xf8, &val);
1008 val |= 1 << 0x1b;
1009 /* the following changes the device ID, but appears not to affect function */
1010 /* val = (val & ~0xf0000000) | 0x80000000; */
1011 pci_write_config_dword(pdev, 0xf8, val);
1012
1013 pci_read_config_dword(pdev, 0x54c, &val);
1014 val |= 1 << 0xc;
1015 pci_write_config_dword(pdev, 0x54c, val);
1016
1017 pci_read_config_dword(pdev, 0x4a4, &val);
1018 val &= 0xff;
1019 val |= 0x01060100;
1020 pci_write_config_dword(pdev, 0x4a4, val);
1021
1022 pci_read_config_dword(pdev, 0x54c, &val);
1023 val &= ~(1 << 0xc);
1024 pci_write_config_dword(pdev, 0x54c, val);
1025
1026 pci_read_config_dword(pdev, 0xf8, &val);
1027 val &= ~(1 << 0x1b);
1028 pci_write_config_dword(pdev, 0xf8, val);
1029}
1030
1031static bool is_mcp89_apple(struct pci_dev *pdev)
1032{
1033 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1034 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1035 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1036 pdev->subsystem_device == 0xcb89;
1037}
1038
2fcad9d2
TH		 1039/* only some SB600 ahci controllers can do 64bit DMA */
1040static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 1041{
1042 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 1043 /*
1044 * The oldest version known to be broken is 0901 and
1045 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 1046 * Enable 64bit DMA on 1501 and anything newer.
1047 *
03d783bf
TH		 1048 * Please read bko#9412 for more info.
1049 */
58a09b38
SH		 1050 {
1051 .ident = "ASUS M2A-VM",
1052 .matches = {
1053 DMI_MATCH(DMI_BOARD_VENDOR,
1054 "ASUSTeK Computer INC."),
1055 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1056 },
03d783bf 1057 .driver_data = "20071026", /* yyyymmdd */
58a09b38 1058 },
e65cc194
MN		 1059 /*
1060 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1061 * support 64bit DMA.
1062 *
1063 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1064 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1065 * This spelling mistake was fixed in BIOS version 1.5, so
1066 * 1.5 and later have the Manufacturer as
1067 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1068 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1069 *
1070 * BIOS versions earlier than 1.9 had a Board Product Name
1071 * DMI field of "MS-7376". This was changed to be
1072 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1073 * match on DMI_BOARD_NAME of "MS-7376".
1074 */
1075 {
1076 .ident = "MSI K9A2 Platinum",
1077 .matches = {
1078 DMI_MATCH(DMI_BOARD_VENDOR,
1079 "MICRO-STAR INTER"),
1080 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1081 },
1082 },
ff0173c1
MN		 1083 /*
1084 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1085 * 64bit DMA.
1086 *
1087 * This board also had the typo mentioned above in the
1088 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1089 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1090 */
1091 {
1092 .ident = "MSI K9AGM2",
1093 .matches = {
1094 DMI_MATCH(DMI_BOARD_VENDOR,
1095 "MICRO-STAR INTER"),
1096 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1097 },
1098 },
3c4aa91f
MN		 1099 /*
1100 * All BIOS versions for the Asus M3A support 64bit DMA.
1101 * (all release versions from 0301 to 1206 were tested)
1102 */
1103 {
1104 .ident = "ASUS M3A",
1105 .matches = {
1106 DMI_MATCH(DMI_BOARD_VENDOR,
1107 "ASUSTeK Computer INC."),
1108 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1109 },
1110 },
58a09b38
SH		 1111 { }
1112 };
03d783bf 1113 const struct dmi_system_id *match;
2fcad9d2
TH		 1114 int year, month, date;
1115 char buf[9];
58a09b38 1116
03d783bf 1117 match = dmi_first_match(sysids);
58a09b38 1118 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 1119 !match)
58a09b38
SH		 1120 return false;
1121
e65cc194
MN		 1122 if (!match->driver_data)
1123 goto enable_64bit;
1124
2fcad9d2
TH		 1125 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1126 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 1127
e65cc194
MN		 1128 if (strcmp(buf, match->driver_data) >= 0)
1129 goto enable_64bit;
1130 else {
a44fec1f
JP		 1131 dev_warn(&pdev->dev,
1132 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1133 match->ident);
2fcad9d2
TH		 1134 return false;
1135 }
e65cc194
MN		 1136
1137enable_64bit:
a44fec1f 1138 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 1139 return true;
58a09b38
SH		 1140}
1141
1fd68434
RW		 1142static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1143{
1144 static const struct dmi_system_id broken_systems[] = {
1145 {
1146 .ident = "HP Compaq nx6310",
1147 .matches = {
1148 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1149 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1150 },
1151 /* PCI slot number of the controller */
1152 .driver_data = (void *)0x1FUL,
1153 },
d2f9c061
MR		 1154 {
1155 .ident = "HP Compaq 6720s",
1156 .matches = {
1157 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1158 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1159 },
1160 /* PCI slot number of the controller */
1161 .driver_data = (void *)0x1FUL,
1162 },
1fd68434
RW		 1163
1164 { } /* terminate list */
1165 };
1166 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1167
1168 if (dmi) {
1169 unsigned long slot = (unsigned long)dmi->driver_data;
1170 /* apply the quirk only to on-board controllers */
1171 return slot == PCI_SLOT(pdev->devfn);
1172 }
1173
1174 return false;
1175}
1176
9b10ae86
TH		 1177static bool ahci_broken_suspend(struct pci_dev *pdev)
1178{
1179 static const struct dmi_system_id sysids[] = {
1180 /*
1181 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1182 * to the harddisk doesn't become online after
1183 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 1184 *
1185 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1186 *
1187 * Use dates instead of versions to match as HP is
1188 * apparently recycling both product and version
1189 * strings.
1190 *
1191 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 1192 */
1193 {
1194 .ident = "dv4",
1195 .matches = {
1196 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1197 DMI_MATCH(DMI_PRODUCT_NAME,
1198 "HP Pavilion dv4 Notebook PC"),
1199 },
9deb3431 1200 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 1201 },
1202 {
1203 .ident = "dv5",
1204 .matches = {
1205 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1206 DMI_MATCH(DMI_PRODUCT_NAME,
1207 "HP Pavilion dv5 Notebook PC"),
1208 },
9deb3431 1209 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 1210 },
1211 {
1212 .ident = "dv6",
1213 .matches = {
1214 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1215 DMI_MATCH(DMI_PRODUCT_NAME,
1216 "HP Pavilion dv6 Notebook PC"),
1217 },
9deb3431 1218 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 1219 },
1220 {
1221 .ident = "HDX18",
1222 .matches = {
1223 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1224 DMI_MATCH(DMI_PRODUCT_NAME,
1225 "HP HDX18 Notebook PC"),
1226 },
9deb3431 1227 .driver_data = "20090430", /* F.23 */
9b10ae86 1228 },
cedc9bf9
TH		 1229 /*
1230 * Acer eMachines G725 has the same problem. BIOS
1231 * V1.03 is known to be broken. V3.04 is known to
25985edc 1232 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 1233 * that we don't have much idea about. For now,
1234 * blacklist anything older than V3.04.
9deb3431
TH		 1235 *
1236 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 1237 */
1238 {
1239 .ident = "G725",
1240 .matches = {
1241 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1242 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1243 },
9deb3431 1244 .driver_data = "20091216", /* V3.04 */
cedc9bf9 1245 },
9b10ae86
TH		 1246 { } /* terminate list */
1247 };
1248 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 1249 int year, month, date;
1250 char buf[9];
9b10ae86
TH		 1251
1252 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1253 return false;
1254
9deb3431
TH		 1255 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1256 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 1257
9deb3431 1258 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 1259}
1260
240630e6
HG		 1261static bool ahci_broken_lpm(struct pci_dev *pdev)
1262{
1263 static const struct dmi_system_id sysids[] = {
1264 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1265 {
1266 .matches = {
1267 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1268 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1269 },
1270 .driver_data = "20180406", /* 1.31 */
1271 },
1272 {
1273 .matches = {
1274 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1275 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1276 },
1277 .driver_data = "20180420", /* 1.28 */
1278 },
1279 {
1280 .matches = {
1281 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1282 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1283 },
1284 .driver_data = "20180315", /* 1.33 */
1285 },
1286 {
1287 .matches = {
1288 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1289 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1290 },
1291 /*
1292 * Note date based on release notes, 2.35 has been
1293 * reported to be good, but I've been unable to get
1294 * a hold of the reporter to get the DMI BIOS date.
1295 * TODO: fix this.
1296 */
1297 .driver_data = "20180310", /* 2.35 */
1298 },
1299 { } /* terminate list */
1300 };
1301 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1302 int year, month, date;
1303 char buf[9];
1304
1305 if (!dmi)
1306 return false;
1307
1308 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1309 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1310
1311 return strcmp(buf, dmi->driver_data) < 0;
1312}
1313
5594639a
TH		 1314static bool ahci_broken_online(struct pci_dev *pdev)
1315{
1316#define ENCODE_BUSDEVFN(bus, slot, func) \
1317 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1318 static const struct dmi_system_id sysids[] = {
1319 /*
1320 * There are several gigabyte boards which use
1321 * SIMG5723s configured as hardware RAID. Certain
1322 * 5723 firmware revisions shipped there keep the link
1323 * online but fail to answer properly to SRST or
1324 * IDENTIFY when no device is attached downstream
1325 * causing libata to retry quite a few times leading
1326 * to excessive detection delay.
1327 *
1328 * As these firmwares respond to the second reset try
1329 * with invalid device signature, considering unknown
1330 * sig as offline works around the problem acceptably.
1331 */
1332 {
1333 .ident = "EP45-DQ6",
1334 .matches = {
1335 DMI_MATCH(DMI_BOARD_VENDOR,
1336 "Gigabyte Technology Co., Ltd."),
1337 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1338 },
1339 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1340 },
1341 {
1342 .ident = "EP45-DS5",
1343 .matches = {
1344 DMI_MATCH(DMI_BOARD_VENDOR,
1345 "Gigabyte Technology Co., Ltd."),
1346 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1347 },
1348 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1349 },
1350 { } /* terminate list */
1351 };
1352#undef ENCODE_BUSDEVFN
1353 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1354 unsigned int val;
1355
1356 if (!dmi)
1357 return false;
1358
1359 val = (unsigned long)dmi->driver_data;
1360
1361 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1362}
1363
0cf4a7d6
JP		 1364static bool ahci_broken_devslp(struct pci_dev *pdev)
1365{
1366 /* device with broken DEVSLP but still showing SDS capability */
1367 static const struct pci_device_id ids[] = {
1368 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1369 {}
1370 };
1371
1372 return pci_match_id(ids, pdev);
1373}
1374
8e513217 1375#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1376static void ahci_gtf_filter_workaround(struct ata_host *host)
1377{
1378 static const struct dmi_system_id sysids[] = {
1379 /*
1380 * Aspire 3810T issues a bunch of SATA enable commands
1381 * via _GTF including an invalid one and one which is
1382 * rejected by the device. Among the successful ones
1383 * is FPDMA non-zero offset enable which when enabled
1384 * only on the drive side leads to NCQ command
1385 * failures. Filter it out.
1386 */
1387 {
1388 .ident = "Aspire 3810T",
1389 .matches = {
1390 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1391 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1392 },
1393 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1394 },
1395 { }
1396 };
1397 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1398 unsigned int filter;
1399 int i;
1400
1401 if (!dmi)
1402 return;
1403
1404 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1405 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1406 filter, dmi->ident);
f80ae7e4
TH		 1407
1408 for (i = 0; i < host->n_ports; i++) {
1409 struct ata_port *ap = host->ports[i];
1410 struct ata_link *link;
1411 struct ata_device *dev;
1412
1413 ata_for_each_link(link, ap, EDGE)
1414 ata_for_each_dev(dev, link, ALL)
1415 dev->gtf_filter |= filter;
1416 }
1417}
8e513217
MT		 1418#else
1419static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1420{}
1421#endif
f80ae7e4 1422
8bfd1743
SC		 1423/*
1424 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1425 * as DUMMY, or detected but eventually get a "link down" and never get up
1426 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1427 * port_map may hold a value of 0x00.
1428 *
1429 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1430 * and can significantly reduce the occurrence of the problem.
1431 *
1432 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1433 */
1434static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1435 struct pci_dev *pdev)
1436{
1437 static const struct dmi_system_id sysids[] = {
1438 {
1439 .ident = "Acer Switch Alpha 12",
1440 .matches = {
1441 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1442 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1443 },
1444 },
1445 { }
1446 };
1447
1448 if (dmi_check_system(sysids)) {
1449 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1450 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1451 hpriv->port_map = 0x7;
1452 hpriv->cap = 0xC734FF02;
1453 }
1454 }
1455}
1456
d243bed3
TC		 1457#ifdef CONFIG_ARM64
1458/*
1459 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1460 * Workaround is to make sure all pending IRQs are served before leaving
1461 * handler.
1462 */
1463static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1464{
1465 struct ata_host *host = dev_instance;
1466 struct ahci_host_priv *hpriv;
1467 unsigned int rc = 0;
1468 void __iomem *mmio;
1469 u32 irq_stat, irq_masked;
1470 unsigned int handled = 1;
1471
1472 VPRINTK("ENTER\n");
1473 hpriv = host->private_data;
1474 mmio = hpriv->mmio;
1475 irq_stat = readl(mmio + HOST_IRQ_STAT);
1476 if (!irq_stat)
1477 return IRQ_NONE;
1478
1479 do {
1480 irq_masked = irq_stat & hpriv->port_map;
1481 spin_lock(&host->lock);
1482 rc = ahci_handle_port_intr(host, irq_masked);
1483 if (!rc)
1484 handled = 0;
1485 writel(irq_stat, mmio + HOST_IRQ_STAT);
1486 irq_stat = readl(mmio + HOST_IRQ_STAT);
1487 spin_unlock(&host->lock);
1488 } while (irq_stat);
1489 VPRINTK("EXIT\n");
1490
1491 return IRQ_RETVAL(handled);
1492}
1493#endif
1494
aecec8b6
CH		 1495static void ahci_remap_check(struct pci_dev *pdev, int bar,
1496 struct ahci_host_priv *hpriv)
1497{
894fba7f 1498 int i;
aecec8b6
CH		 1499 u32 cap;
1500
1501 /*
1502 * Check if this device might have remapped nvme devices.
1503 */
1504 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1505 pci_resource_len(pdev, bar) < SZ_512K ||
1506 bar != AHCI_PCI_BAR_STANDARD ||
1507 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1508 return;
1509
1510 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1511 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1512 if ((cap & (1 << i)) == 0)
1513 continue;
1514 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1515 != PCI_CLASS_STORAGE_EXPRESS)
1516 continue;
1517
1518 /* We've found a remapped device */
894fba7f 1519 hpriv->remapped_nvme++;
aecec8b6
CH		 1520 }
1521
894fba7f 1522 if (!hpriv->remapped_nvme)
aecec8b6
CH		 1523 return;
1524
894fba7f
KHF		 1525 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1526 hpriv->remapped_nvme);
f723fa4e
CH		 1527 dev_warn(&pdev->dev,
1528 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1529
1530 /*
1531 * Don't rely on the msi-x capability in the remap case,
1532 * share the legacy interrupt across ahci and remapped devices.
1533 */
1534 hpriv->flags |= AHCI_HFLAG_NO_MSI;
aecec8b6
CH		 1535}
1536
0b9e2988 1537static int ahci_get_irq_vector(struct ata_host *host, int port)
5ca72c4f 1538{
0b9e2988 1539 return pci_irq_vector(to_pci_dev(host->dev), port);
ee2aad42
RR		 1540}
1541
a1c82311
RR		 1542static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1543 struct ahci_host_priv *hpriv)
5ca72c4f 1544{
0b9e2988 1545 int nvec;
5ca72c4f 1546
7b92b4f6 1547 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
a1c82311 1548 return -ENODEV;
7b92b4f6 1549
7b92b4f6
AG		 1550 /*
1551 * If number of MSIs is less than number of ports then Sharing Last
1552 * Message mode could be enforced. In this case assume that advantage
1553 * of multipe MSIs is negated and use single MSI mode instead.
1554 */
17a51f12
CH		 1555 if (n_ports > 1) {
1556 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1557 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1558 if (nvec > 0) {
1559 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1560 hpriv->get_irq_vector = ahci_get_irq_vector;
1561 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1562 return nvec;
1563 }
5ca72c4f 1564
17a51f12
CH		 1565 /*
1566 * Fallback to single MSI mode if the controller
1567 * enforced MRSM mode.
1568 */
1569 printk(KERN_INFO
1570 "ahci: MRSM is on, fallback to single MSI\n");
1571 pci_free_irq_vectors(pdev);
1572 }
a478b097 1573 }
d684a90d 1574
0b9e2988
CH		 1575 /*
1576 * If the host is not capable of supporting per-port vectors, fall
1577 * back to single MSI before finally attempting single MSI-X.
1578 */
1579 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1580 if (nvec == 1)
ee2aad42 1581 return nvec;
0b9e2988 1582 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
5ca72c4f
AG		 1583}
1584
b1a9585c
SP		 1585static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1586 struct ahci_host_priv *hpriv)
1587{
1588 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1589
1590
1591 /* Ignore processing for non mobile platforms */
1592 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
1593 return;
1594
1595 /* user modified policy via module param */
1596 if (mobile_lpm_policy != -1) {
1597 policy = mobile_lpm_policy;
1598 goto update_policy;
1599 }
1600
1601#ifdef CONFIG_ACPI
1602 if (policy > ATA_LPM_MED_POWER &&
1603 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1604 if (hpriv->cap & HOST_CAP_PART)
1605 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1606 else if (hpriv->cap & HOST_CAP_SSC)
1607 policy = ATA_LPM_MIN_POWER;
1608 }
1609#endif
1610
1611update_policy:
1612 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1613 ap->target_lpm_policy = policy;
1614}
1615
c312ef17
DW		 1616static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1617{
1618 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1619 u16 tmp16;
1620
1621 /*
1622 * Only apply the 6-port PCS quirk for known legacy platforms.
1623 */
1624 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1625 return;
09d6ac8d
DW		 1626
1627 /* Skip applying the quirk on Denverton and beyond */
1628 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
c312ef17
DW		 1629 return;
1630
1631 /*
1632 * port_map is determined from PORTS_IMPL PCI register which is
1633 * implemented as write or write-once register. If the register
1634 * isn't programmed, ahci automatically generates it from number
1635 * of ports, which is good enough for PCS programming. It is
1636 * otherwise expected that platform firmware enables the ports
1637 * before the OS boots.
1638 */
1639 pci_read_config_word(pdev, PCS_6, &tmp16);
1640 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1641 tmp16 |= hpriv->port_map;
1642 pci_write_config_word(pdev, PCS_6, tmp16);
1643 }
1644}
1645
894fba7f
KHF		 1646static ssize_t remapped_nvme_show(struct device *dev,
1647 struct device_attribute *attr,
1648 char *buf)
1649{
1650 struct ata_host *host = dev_get_drvdata(dev);
1651 struct ahci_host_priv *hpriv = host->private_data;
1652
1653 return sprintf(buf, "%u\n", hpriv->remapped_nvme);
1654}
1655
1656static DEVICE_ATTR_RO(remapped_nvme);
1657
24dc5f33 1658static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1659{
e297d99e
TH		 1660 unsigned int board_id = ent->driver_data;
1661 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1662 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1663 struct device *dev = &pdev->dev;
1da177e4 1664 struct ahci_host_priv *hpriv;
4447d351 1665 struct ata_host *host;
c3ebd6a9 1666 int n_ports, i, rc;
318893e1 1667 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1668
1669 VPRINTK("ENTER\n");
1670
b429dd59 1671 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1672
06296a1e 1673 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1674
5b66c829
AC		 1675 /* The AHCI driver can only drive the SATA ports, the PATA driver
1676 can drive them all so if both drivers are selected make sure
1677 AHCI stays out of the way */
1678 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1679 return -ENODEV;
1680
cb85696d
JL		 1681 /* Apple BIOS on MCP89 prevents us using AHCI */
1682 if (is_mcp89_apple(pdev))
1683 ahci_mcp89_apple_enable(pdev);
c6353b45 1684
7a02267e
MN		 1685 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1686 * At the moment, we can only use the AHCI mode. Let the users know
1687 * that for SAS drives they're out of luck.
1688 */
1689 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1690 dev_info(&pdev->dev,
1691 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1692
b7ae128d 1693 /* Some devices use non-standard BARs */
318893e1
AR		 1694 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1695 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
7f9c9f8e
HD		 1696 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1697 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
b1314e3f
RMC		 1698 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1699 if (pdev->device == 0xa01c)
1700 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1701 if (pdev->device == 0xa084)
1702 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
e49bd683
TY		 1703 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1704 if (pdev->device == 0x7a08)
1705 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
b1314e3f 1706 }
318893e1 1707
4447d351 1708 /* acquire resources */
24dc5f33 1709 rc = pcim_enable_device(pdev);
1da177e4
LT		 1710 if (rc)
1711 return rc;
1712
c4f7792c
TH		 1713 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1714 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1715 u8 map;
1716
1717 /* ICH6s share the same PCI ID for both piix and ahci
1718 * modes. Enabling ahci mode while MAP indicates
1719 * combined mode is a bad idea. Yield to ata_piix.
1720 */
1721 pci_read_config_byte(pdev, ICH_MAP, &map);
1722 if (map & 0x3) {
a44fec1f
JP		 1723 dev_info(&pdev->dev,
1724 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1725 return -ENODEV;
1726 }
1727 }
1728
6fec8871
PB		 1729 /* AHCI controllers often implement SFF compatible interface.
1730 * Grab all PCI BARs just in case.
1731 */
1732 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1733 if (rc == -EBUSY)
1734 pcim_pin_device(pdev);
1735 if (rc)
1736 return rc;
1737
24dc5f33
TH		 1738 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1739 if (!hpriv)
1740 return -ENOMEM;
417a1a6d
TH		 1741 hpriv->flags |= (unsigned long)pi.private_data;
1742
e297d99e
TH		 1743 /* MCP65 revision A1 and A2 can't do MSI */
1744 if (board_id == board_ahci_mcp65 &&
1745 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1746 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1747
e427fe04
SH		 1748 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1749 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1750 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1751
2fcad9d2
TH		 1752 /* only some SB600s can do 64bit DMA */
1753 if (ahci_sb600_enable_64bit(pdev))
1754 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1755
318893e1 1756 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1757
aecec8b6
CH		 1758 /* detect remapped nvme devices */
1759 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1760
894fba7f
KHF		 1761 sysfs_add_file_to_group(&pdev->dev.kobj,
1762 &dev_attr_remapped_nvme.attr,
1763 NULL);
1764
0cf4a7d6
JP		 1765 /* must set flag prior to save config in order to take effect */
1766 if (ahci_broken_devslp(pdev))
1767 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1768
d243bed3
TC		 1769#ifdef CONFIG_ARM64
1770 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1771 hpriv->irq_handler = ahci_thunderx_irq_handler;
1772#endif
1773
4447d351 1774 /* save initial config */
394d6e53 1775 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1776
c312ef17
DW		 1777 /*
1778 * If platform firmware failed to enable ports, try to enable
1779 * them here.
1780 */
1781 ahci_intel_pcs_quirk(pdev, hpriv);
1782
4447d351 1783 /* prepare host */
453d3131
RH		 1784 if (hpriv->cap & HOST_CAP_NCQ) {
1785 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1786 /*
1787 * Auto-activate optimization is supposed to be
1788 * supported on all AHCI controllers indicating NCQ
1789 * capability, but it seems to be broken on some
1790 * chipsets including NVIDIAs.
1791 */
1792 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131 1793 pi.flags |= ATA_FLAG_FPDMA_AA;
40fb59e7
MC		 1794
1795 /*
1796 * All AHCI controllers should be forward-compatible
1797 * with the new auxiliary field. This code should be
1798 * conditionalized if any buggy AHCI controllers are
1799 * encountered.
1800 */
1801 pi.flags |= ATA_FLAG_FPDMA_AUX;
453d3131 1802 }
1da177e4 1803
7d50b60b
TH		 1804 if (hpriv->cap & HOST_CAP_PMP)
1805 pi.flags |= ATA_FLAG_PMP;
1806
0cbb0e77 1807 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1808
1fd68434
RW		 1809 if (ahci_broken_system_poweroff(pdev)) {
1810 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1811 dev_info(&pdev->dev,
1812 "quirky BIOS, skipping spindown on poweroff\n");
1813 }
1814
240630e6
HG		 1815 if (ahci_broken_lpm(pdev)) {
1816 pi.flags |= ATA_FLAG_NO_LPM;
1817 dev_warn(&pdev->dev,
1818 "BIOS update required for Link Power Management support\n");
1819 }
1820
9b10ae86
TH		 1821 if (ahci_broken_suspend(pdev)) {
1822 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1823 dev_warn(&pdev->dev,
1824 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1825 }
1826
5594639a
TH		 1827 if (ahci_broken_online(pdev)) {
1828 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1829 dev_info(&pdev->dev,
1830 "online status unreliable, applying workaround\n");
1831 }
1832
8bfd1743
SC		 1833
1834 /* Acer SA5-271 workaround modifies private_data */
1835 acer_sa5_271_workaround(hpriv, pdev);
1836
837f5f8f
TH		 1837 /* CAP.NP sometimes indicate the index of the last enabled
1838 * port, at other times, that of the last possible port, so
1839 * determining the maximum port number requires looking at
1840 * both CAP.NP and port_map.
1841 */
1842 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1843
1844 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1845 if (!host)
1846 return -ENOMEM;
4447d351 1847 host->private_data = hpriv;
0b9e2988
CH		 1848
1849 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1850 /* legacy intx interrupts */
1851 pci_intx(pdev, 1);
1852 }
0ce57f8a 1853 hpriv->irq = pci_irq_vector(pdev, 0);
21bfd1aa 1854
f3d7f23f 1855 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1856 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f 1857 else
d2782d96 1858 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
886ad09f 1859
18f7ba4c
KCA		 1860 if (pi.flags & ATA_FLAG_EM)
1861 ahci_reset_em(host);
1862
4447d351 1863 for (i = 0; i < host->n_ports; i++) {
dab632e8 1864 struct ata_port *ap = host->ports[i];
4447d351 1865
318893e1
AR		 1866 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1867 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1868 0x100 + ap->port_no * 0x80, "port");
1869
18f7ba4c
KCA		 1870 /* set enclosure management message type */
1871 if (ap->flags & ATA_FLAG_EM)
008dbd61 1872 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c 1873
b1a9585c 1874 ahci_update_initial_lpm_policy(ap, hpriv);
18f7ba4c 1875
dab632e8 1876 /* disabled/not-implemented port */
350756f6 1877 if (!(hpriv->port_map & (1 << i)))
dab632e8 1878 ap->ops = &ata_dummy_port_ops;
4447d351 1879 }
d447df14 1880
edc93052
TH		 1881 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1882 ahci_p5wdh_workaround(host);
1883
f80ae7e4
TH		 1884 /* apply gtf filter quirk */
1885 ahci_gtf_filter_workaround(host);
1886
4447d351
TH		 1887 /* initialize adapter */
1888 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1889 if (rc)
24dc5f33 1890 return rc;
1da177e4 1891
c312ef17 1892 rc = ahci_reset_controller(host);
4447d351
TH		 1893 if (rc)
1894 return rc;
1da177e4 1895
781d6550 1896 ahci_pci_init_controller(host);
439fcaec 1897 ahci_pci_print_info(host);
1da177e4 1898
4447d351 1899 pci_set_master(pdev);
5ca72c4f 1900
02e53293
MW		 1901 rc = ahci_host_activate(host, &ahci_sht);
1902 if (rc)
1903 return rc;
1904
1905 pm_runtime_put_noidle(&pdev->dev);
1906 return 0;
1907}
1908
10a663a1
PK		 1909static void ahci_shutdown_one(struct pci_dev *pdev)
1910{
1911 ata_pci_shutdown_one(pdev);
1912}
1913
02e53293
MW		 1914static void ahci_remove_one(struct pci_dev *pdev)
1915{
894fba7f
KHF		 1916 sysfs_remove_file_from_group(&pdev->dev.kobj,
1917 &dev_attr_remapped_nvme.attr,
1918 NULL);
02e53293
MW		 1919 pm_runtime_get_noresume(&pdev->dev);
1920 ata_pci_remove_one(pdev);
907f4678 1921}
1da177e4 1922
2fc75da0 1923module_pci_driver(ahci_pci_driver);
1da177e4
LT		 1924
1925MODULE_AUTHOR("Jeff Garzik");
1926MODULE_DESCRIPTION("AHCI SATA low-level driver");
1927MODULE_LICENSE("GPL");
1928MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1929MODULE_VERSION(DRV_VERSION);
Linux 6.x block layer and io_uring tree(s)