Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * ahci.c - AHCI SATA support | |
3 | * | |
af36d7f0 JG |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004-2005 Red Hat, Inc. | |
9 | * | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * AHCI hardware documentation: | |
1da177e4 | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
af36d7f0 | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
1da177e4 LT |
32 | * |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/blkdev.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/interrupt.h> | |
87507cfd | 42 | #include <linux/dma-mapping.h> |
a9524a76 | 43 | #include <linux/device.h> |
1da177e4 | 44 | #include <scsi/scsi_host.h> |
193515d5 | 45 | #include <scsi/scsi_cmnd.h> |
1da177e4 | 46 | #include <linux/libata.h> |
1da177e4 LT |
47 | |
48 | #define DRV_NAME "ahci" | |
7d50b60b | 49 | #define DRV_VERSION "3.0" |
1da177e4 LT |
50 | |
51 | ||
52 | enum { | |
53 | AHCI_PCI_BAR = 5, | |
648a88be | 54 | AHCI_MAX_PORTS = 32, |
1da177e4 LT |
55 | AHCI_MAX_SG = 168, /* hardware max is 64K */ |
56 | AHCI_DMA_BOUNDARY = 0xffffffff, | |
be5d8218 | 57 | AHCI_USE_CLUSTERING = 1, |
12fad3f9 | 58 | AHCI_MAX_CMDS = 32, |
dd410ff1 | 59 | AHCI_CMD_SZ = 32, |
12fad3f9 | 60 | AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
1da177e4 | 61 | AHCI_RX_FIS_SZ = 256, |
a0ea7328 | 62 | AHCI_CMD_TBL_CDB = 0x40, |
dd410ff1 TH |
63 | AHCI_CMD_TBL_HDR_SZ = 0x80, |
64 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), | |
65 | AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, | |
66 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + | |
1da177e4 LT |
67 | AHCI_RX_FIS_SZ, |
68 | AHCI_IRQ_ON_SG = (1 << 31), | |
69 | AHCI_CMD_ATAPI = (1 << 5), | |
70 | AHCI_CMD_WRITE = (1 << 6), | |
4b10e559 | 71 | AHCI_CMD_PREFETCH = (1 << 7), |
22b49985 TH |
72 | AHCI_CMD_RESET = (1 << 8), |
73 | AHCI_CMD_CLR_BUSY = (1 << 10), | |
1da177e4 LT |
74 | |
75 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ | |
0291f95f | 76 | RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ |
78cd52d0 | 77 | RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
1da177e4 LT |
78 | |
79 | board_ahci = 0, | |
7a234aff TH |
80 | board_ahci_vt8251 = 1, |
81 | board_ahci_ign_iferr = 2, | |
82 | board_ahci_sb600 = 3, | |
83 | board_ahci_mv = 4, | |
1da177e4 LT |
84 | |
85 | /* global controller registers */ | |
86 | HOST_CAP = 0x00, /* host capabilities */ | |
87 | HOST_CTL = 0x04, /* global host control */ | |
88 | HOST_IRQ_STAT = 0x08, /* interrupt status */ | |
89 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ | |
90 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ | |
91 | ||
92 | /* HOST_CTL bits */ | |
93 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ | |
94 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ | |
95 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ | |
96 | ||
97 | /* HOST_CAP bits */ | |
0be0aa98 | 98 | HOST_CAP_SSC = (1 << 14), /* Slumber capable */ |
7d50b60b | 99 | HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */ |
22b49985 | 100 | HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
0be0aa98 | 101 | HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ |
203ef6c4 | 102 | HOST_CAP_SNTF = (1 << 29), /* SNotification register */ |
979db803 | 103 | HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ |
dd410ff1 | 104 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
1da177e4 LT |
105 | |
106 | /* registers for each SATA port */ | |
107 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ | |
108 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ | |
109 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ | |
110 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ | |
111 | PORT_IRQ_STAT = 0x10, /* interrupt status */ | |
112 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ | |
113 | PORT_CMD = 0x18, /* port command */ | |
114 | PORT_TFDATA = 0x20, /* taskfile data */ | |
115 | PORT_SIG = 0x24, /* device TF signature */ | |
116 | PORT_CMD_ISSUE = 0x38, /* command issue */ | |
1da177e4 LT |
117 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ |
118 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ | |
119 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ | |
120 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ | |
203ef6c4 | 121 | PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */ |
1da177e4 LT |
122 | |
123 | /* PORT_IRQ_{STAT,MASK} bits */ | |
124 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ | |
125 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ | |
126 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ | |
127 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ | |
128 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ | |
129 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ | |
130 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ | |
131 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ | |
132 | ||
133 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ | |
134 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ | |
135 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ | |
136 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ | |
137 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ | |
138 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ | |
139 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ | |
140 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ | |
141 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ | |
142 | ||
78cd52d0 TH |
143 | PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
144 | PORT_IRQ_IF_ERR | | |
145 | PORT_IRQ_CONNECT | | |
4296971d | 146 | PORT_IRQ_PHYRDY | |
7d50b60b TH |
147 | PORT_IRQ_UNK_FIS | |
148 | PORT_IRQ_BAD_PMP, | |
78cd52d0 TH |
149 | PORT_IRQ_ERROR = PORT_IRQ_FREEZE | |
150 | PORT_IRQ_TF_ERR | | |
151 | PORT_IRQ_HBUS_DATA_ERR, | |
152 | DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | | |
153 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | | |
154 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, | |
1da177e4 LT |
155 | |
156 | /* PORT_CMD bits */ | |
02eaa666 | 157 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
7d50b60b | 158 | PORT_CMD_PMP = (1 << 17), /* PMP attached */ |
1da177e4 LT |
159 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
160 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ | |
161 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ | |
22b49985 | 162 | PORT_CMD_CLO = (1 << 3), /* Command list override */ |
1da177e4 LT |
163 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
164 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ | |
165 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ | |
166 | ||
0be0aa98 | 167 | PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ |
1da177e4 LT |
168 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ |
169 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ | |
170 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ | |
4b0060f4 | 171 | |
417a1a6d TH |
172 | /* hpriv->flags bits */ |
173 | AHCI_HFLAG_NO_NCQ = (1 << 0), | |
174 | AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */ | |
175 | AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */ | |
176 | AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */ | |
177 | AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */ | |
178 | AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */ | |
6949b914 | 179 | AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ |
417a1a6d | 180 | |
bf2af2a2 | 181 | /* ap->flags bits */ |
417a1a6d | 182 | AHCI_FLAG_NO_HOTPLUG = (1 << 24), /* ignore PxSERR.DIAG.N */ |
1188c0d8 TH |
183 | |
184 | AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
185 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | |
854c73a2 | 186 | ATA_FLAG_ACPI_SATA | ATA_FLAG_AN, |
0c88758b | 187 | AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY, |
1da177e4 LT |
188 | }; |
189 | ||
190 | struct ahci_cmd_hdr { | |
191 | u32 opts; | |
192 | u32 status; | |
193 | u32 tbl_addr; | |
194 | u32 tbl_addr_hi; | |
195 | u32 reserved[4]; | |
196 | }; | |
197 | ||
198 | struct ahci_sg { | |
199 | u32 addr; | |
200 | u32 addr_hi; | |
201 | u32 reserved; | |
202 | u32 flags_size; | |
203 | }; | |
204 | ||
205 | struct ahci_host_priv { | |
417a1a6d | 206 | unsigned int flags; /* AHCI_HFLAG_* */ |
d447df14 TH |
207 | u32 cap; /* cap to use */ |
208 | u32 port_map; /* port map to use */ | |
209 | u32 saved_cap; /* saved initial cap */ | |
210 | u32 saved_port_map; /* saved initial port_map */ | |
1da177e4 LT |
211 | }; |
212 | ||
213 | struct ahci_port_priv { | |
7d50b60b | 214 | struct ata_link *active_link; |
1da177e4 LT |
215 | struct ahci_cmd_hdr *cmd_slot; |
216 | dma_addr_t cmd_slot_dma; | |
217 | void *cmd_tbl; | |
218 | dma_addr_t cmd_tbl_dma; | |
1da177e4 LT |
219 | void *rx_fis; |
220 | dma_addr_t rx_fis_dma; | |
0291f95f | 221 | /* for NCQ spurious interrupt analysis */ |
0291f95f TH |
222 | unsigned int ncq_saw_d2h:1; |
223 | unsigned int ncq_saw_dmas:1; | |
afb2d552 | 224 | unsigned int ncq_saw_sdb:1; |
a7384925 | 225 | u32 intr_mask; /* interrupts to enable */ |
1da177e4 LT |
226 | }; |
227 | ||
da3dbb17 TH |
228 | static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val); |
229 | static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val); | |
1da177e4 | 230 | static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); |
9a3d9eb0 | 231 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
1da177e4 | 232 | static void ahci_irq_clear(struct ata_port *ap); |
1da177e4 LT |
233 | static int ahci_port_start(struct ata_port *ap); |
234 | static void ahci_port_stop(struct ata_port *ap); | |
1da177e4 LT |
235 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
236 | static void ahci_qc_prep(struct ata_queued_cmd *qc); | |
237 | static u8 ahci_check_status(struct ata_port *ap); | |
78cd52d0 TH |
238 | static void ahci_freeze(struct ata_port *ap); |
239 | static void ahci_thaw(struct ata_port *ap); | |
7d50b60b TH |
240 | static void ahci_pmp_attach(struct ata_port *ap); |
241 | static void ahci_pmp_detach(struct ata_port *ap); | |
242 | static int ahci_pmp_read(struct ata_device *dev, int pmp, int reg, u32 *r_val); | |
243 | static int ahci_pmp_write(struct ata_device *dev, int pmp, int reg, u32 val); | |
78cd52d0 | 244 | static void ahci_error_handler(struct ata_port *ap); |
ad616ffb | 245 | static void ahci_vt8251_error_handler(struct ata_port *ap); |
78cd52d0 | 246 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); |
df69c9c5 | 247 | static int ahci_port_resume(struct ata_port *ap); |
dab632e8 JG |
248 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl); |
249 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, | |
250 | u32 opts); | |
438ac6d5 | 251 | #ifdef CONFIG_PM |
c1332875 | 252 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); |
c1332875 TH |
253 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); |
254 | static int ahci_pci_device_resume(struct pci_dev *pdev); | |
438ac6d5 | 255 | #endif |
1da177e4 | 256 | |
193515d5 | 257 | static struct scsi_host_template ahci_sht = { |
1da177e4 LT |
258 | .module = THIS_MODULE, |
259 | .name = DRV_NAME, | |
260 | .ioctl = ata_scsi_ioctl, | |
261 | .queuecommand = ata_scsi_queuecmd, | |
12fad3f9 TH |
262 | .change_queue_depth = ata_scsi_change_queue_depth, |
263 | .can_queue = AHCI_MAX_CMDS - 1, | |
1da177e4 LT |
264 | .this_id = ATA_SHT_THIS_ID, |
265 | .sg_tablesize = AHCI_MAX_SG, | |
1da177e4 LT |
266 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
267 | .emulated = ATA_SHT_EMULATED, | |
268 | .use_clustering = AHCI_USE_CLUSTERING, | |
269 | .proc_name = DRV_NAME, | |
270 | .dma_boundary = AHCI_DMA_BOUNDARY, | |
271 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 272 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 273 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
274 | }; |
275 | ||
057ace5e | 276 | static const struct ata_port_operations ahci_ops = { |
1da177e4 LT |
277 | .check_status = ahci_check_status, |
278 | .check_altstatus = ahci_check_status, | |
1da177e4 LT |
279 | .dev_select = ata_noop_dev_select, |
280 | ||
281 | .tf_read = ahci_tf_read, | |
282 | ||
7d50b60b | 283 | .qc_defer = sata_pmp_qc_defer_cmd_switch, |
1da177e4 LT |
284 | .qc_prep = ahci_qc_prep, |
285 | .qc_issue = ahci_qc_issue, | |
286 | ||
1da177e4 LT |
287 | .irq_clear = ahci_irq_clear, |
288 | ||
289 | .scr_read = ahci_scr_read, | |
290 | .scr_write = ahci_scr_write, | |
291 | ||
78cd52d0 TH |
292 | .freeze = ahci_freeze, |
293 | .thaw = ahci_thaw, | |
294 | ||
295 | .error_handler = ahci_error_handler, | |
296 | .post_internal_cmd = ahci_post_internal_cmd, | |
297 | ||
7d50b60b TH |
298 | .pmp_attach = ahci_pmp_attach, |
299 | .pmp_detach = ahci_pmp_detach, | |
300 | .pmp_read = ahci_pmp_read, | |
301 | .pmp_write = ahci_pmp_write, | |
302 | ||
438ac6d5 | 303 | #ifdef CONFIG_PM |
c1332875 TH |
304 | .port_suspend = ahci_port_suspend, |
305 | .port_resume = ahci_port_resume, | |
438ac6d5 | 306 | #endif |
c1332875 | 307 | |
1da177e4 LT |
308 | .port_start = ahci_port_start, |
309 | .port_stop = ahci_port_stop, | |
1da177e4 LT |
310 | }; |
311 | ||
ad616ffb | 312 | static const struct ata_port_operations ahci_vt8251_ops = { |
ad616ffb TH |
313 | .check_status = ahci_check_status, |
314 | .check_altstatus = ahci_check_status, | |
315 | .dev_select = ata_noop_dev_select, | |
316 | ||
317 | .tf_read = ahci_tf_read, | |
318 | ||
7d50b60b | 319 | .qc_defer = sata_pmp_qc_defer_cmd_switch, |
ad616ffb TH |
320 | .qc_prep = ahci_qc_prep, |
321 | .qc_issue = ahci_qc_issue, | |
322 | ||
ad616ffb TH |
323 | .irq_clear = ahci_irq_clear, |
324 | ||
325 | .scr_read = ahci_scr_read, | |
326 | .scr_write = ahci_scr_write, | |
327 | ||
328 | .freeze = ahci_freeze, | |
329 | .thaw = ahci_thaw, | |
330 | ||
331 | .error_handler = ahci_vt8251_error_handler, | |
332 | .post_internal_cmd = ahci_post_internal_cmd, | |
333 | ||
7d50b60b TH |
334 | .pmp_attach = ahci_pmp_attach, |
335 | .pmp_detach = ahci_pmp_detach, | |
336 | .pmp_read = ahci_pmp_read, | |
337 | .pmp_write = ahci_pmp_write, | |
338 | ||
438ac6d5 | 339 | #ifdef CONFIG_PM |
ad616ffb TH |
340 | .port_suspend = ahci_port_suspend, |
341 | .port_resume = ahci_port_resume, | |
438ac6d5 | 342 | #endif |
ad616ffb TH |
343 | |
344 | .port_start = ahci_port_start, | |
345 | .port_stop = ahci_port_stop, | |
346 | }; | |
347 | ||
417a1a6d TH |
348 | #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) |
349 | ||
98ac62de | 350 | static const struct ata_port_info ahci_port_info[] = { |
1da177e4 LT |
351 | /* board_ahci */ |
352 | { | |
1188c0d8 | 353 | .flags = AHCI_FLAG_COMMON, |
0c88758b | 354 | .link_flags = AHCI_LFLAG_COMMON, |
7da79312 | 355 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 356 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
357 | .port_ops = &ahci_ops, |
358 | }, | |
bf2af2a2 BJ |
359 | /* board_ahci_vt8251 */ |
360 | { | |
6949b914 | 361 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), |
417a1a6d | 362 | .flags = AHCI_FLAG_COMMON, |
0c88758b | 363 | .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME, |
bf2af2a2 | 364 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 365 | .udma_mask = ATA_UDMA6, |
ad616ffb | 366 | .port_ops = &ahci_vt8251_ops, |
bf2af2a2 | 367 | }, |
41669553 TH |
368 | /* board_ahci_ign_iferr */ |
369 | { | |
417a1a6d TH |
370 | AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), |
371 | .flags = AHCI_FLAG_COMMON, | |
0c88758b | 372 | .link_flags = AHCI_LFLAG_COMMON, |
41669553 | 373 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 374 | .udma_mask = ATA_UDMA6, |
41669553 TH |
375 | .port_ops = &ahci_ops, |
376 | }, | |
55a61604 CH |
377 | /* board_ahci_sb600 */ |
378 | { | |
417a1a6d | 379 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | |
6949b914 | 380 | AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_PMP), |
417a1a6d | 381 | .flags = AHCI_FLAG_COMMON, |
0c88758b | 382 | .link_flags = AHCI_LFLAG_COMMON, |
55a61604 | 383 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 384 | .udma_mask = ATA_UDMA6, |
55a61604 CH |
385 | .port_ops = &ahci_ops, |
386 | }, | |
cd70c266 JG |
387 | /* board_ahci_mv */ |
388 | { | |
417a1a6d TH |
389 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | |
390 | AHCI_HFLAG_MV_PATA), | |
cd70c266 | 391 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
417a1a6d | 392 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA, |
0c88758b | 393 | .link_flags = AHCI_LFLAG_COMMON, |
cd70c266 JG |
394 | .pio_mask = 0x1f, /* pio0-4 */ |
395 | .udma_mask = ATA_UDMA6, | |
396 | .port_ops = &ahci_ops, | |
397 | }, | |
1da177e4 LT |
398 | }; |
399 | ||
3b7d697d | 400 | static const struct pci_device_id ahci_pci_tbl[] = { |
fe7fa31a | 401 | /* Intel */ |
54bb3a94 JG |
402 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ |
403 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ | |
404 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ | |
405 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ | |
406 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ | |
82490c09 | 407 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ |
54bb3a94 JG |
408 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ |
409 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ | |
410 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ | |
411 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ | |
7a234aff TH |
412 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ |
413 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */ | |
414 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ | |
415 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ | |
416 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ | |
417 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ | |
418 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ | |
419 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ | |
420 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ | |
421 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ | |
422 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */ | |
423 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */ | |
424 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */ | |
425 | { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */ | |
426 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */ | |
427 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ | |
428 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */ | |
d4155e6f JG |
429 | { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ |
430 | { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ | |
fe7fa31a | 431 | |
e34bb370 TH |
432 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ |
433 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
434 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, | |
fe7fa31a JG |
435 | |
436 | /* ATI */ | |
c65ec1c2 | 437 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ |
c69c0892 | 438 | { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */ |
439 | { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */ | |
440 | { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */ | |
441 | { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */ | |
442 | { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */ | |
443 | { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */ | |
fe7fa31a JG |
444 | |
445 | /* VIA */ | |
54bb3a94 | 446 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
bf335542 | 447 | { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ |
fe7fa31a JG |
448 | |
449 | /* NVIDIA */ | |
54bb3a94 JG |
450 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */ |
451 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */ | |
452 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */ | |
453 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */ | |
6fbf5ba4 PC |
454 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */ |
455 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */ | |
456 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */ | |
457 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */ | |
458 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */ | |
459 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */ | |
460 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */ | |
461 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */ | |
895663cd PC |
462 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */ |
463 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */ | |
464 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */ | |
465 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */ | |
466 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */ | |
467 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */ | |
468 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */ | |
469 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */ | |
0522b286 PC |
470 | { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */ |
471 | { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */ | |
472 | { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */ | |
473 | { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */ | |
474 | { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */ | |
475 | { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */ | |
476 | { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */ | |
477 | { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */ | |
478 | { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */ | |
479 | { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */ | |
480 | { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */ | |
481 | { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */ | |
482 | { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */ | |
483 | { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */ | |
484 | { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */ | |
485 | { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */ | |
486 | { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */ | |
487 | { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */ | |
488 | { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */ | |
489 | { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */ | |
490 | { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */ | |
491 | { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */ | |
492 | { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */ | |
493 | { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */ | |
7100819f PC |
494 | { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */ |
495 | { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */ | |
496 | { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */ | |
497 | { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */ | |
498 | { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */ | |
499 | { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */ | |
500 | { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */ | |
501 | { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */ | |
fe7fa31a | 502 | |
95916edd | 503 | /* SiS */ |
54bb3a94 JG |
504 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ |
505 | { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */ | |
506 | { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ | |
95916edd | 507 | |
cd70c266 JG |
508 | /* Marvell */ |
509 | { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ | |
510 | ||
415ae2b5 JG |
511 | /* Generic, PCI class code for AHCI */ |
512 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
c9f89475 | 513 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, |
415ae2b5 | 514 | |
1da177e4 LT |
515 | { } /* terminate list */ |
516 | }; | |
517 | ||
518 | ||
519 | static struct pci_driver ahci_pci_driver = { | |
520 | .name = DRV_NAME, | |
521 | .id_table = ahci_pci_tbl, | |
522 | .probe = ahci_init_one, | |
24dc5f33 | 523 | .remove = ata_pci_remove_one, |
438ac6d5 | 524 | #ifdef CONFIG_PM |
c1332875 TH |
525 | .suspend = ahci_pci_device_suspend, |
526 | .resume = ahci_pci_device_resume, | |
438ac6d5 | 527 | #endif |
1da177e4 LT |
528 | }; |
529 | ||
530 | ||
98fa4b60 TH |
531 | static inline int ahci_nr_ports(u32 cap) |
532 | { | |
533 | return (cap & 0x1f) + 1; | |
534 | } | |
535 | ||
dab632e8 JG |
536 | static inline void __iomem *__ahci_port_base(struct ata_host *host, |
537 | unsigned int port_no) | |
1da177e4 | 538 | { |
dab632e8 | 539 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
4447d351 | 540 | |
dab632e8 JG |
541 | return mmio + 0x100 + (port_no * 0x80); |
542 | } | |
543 | ||
544 | static inline void __iomem *ahci_port_base(struct ata_port *ap) | |
545 | { | |
546 | return __ahci_port_base(ap->host, ap->port_no); | |
1da177e4 LT |
547 | } |
548 | ||
d447df14 TH |
549 | /** |
550 | * ahci_save_initial_config - Save and fixup initial config values | |
4447d351 | 551 | * @pdev: target PCI device |
4447d351 | 552 | * @hpriv: host private area to store config values |
d447df14 TH |
553 | * |
554 | * Some registers containing configuration info might be setup by | |
555 | * BIOS and might be cleared on reset. This function saves the | |
556 | * initial values of those registers into @hpriv such that they | |
557 | * can be restored after controller reset. | |
558 | * | |
559 | * If inconsistent, config values are fixed up by this function. | |
560 | * | |
561 | * LOCKING: | |
562 | * None. | |
563 | */ | |
4447d351 | 564 | static void ahci_save_initial_config(struct pci_dev *pdev, |
4447d351 | 565 | struct ahci_host_priv *hpriv) |
d447df14 | 566 | { |
4447d351 | 567 | void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; |
d447df14 | 568 | u32 cap, port_map; |
17199b18 | 569 | int i; |
d447df14 TH |
570 | |
571 | /* Values prefixed with saved_ are written back to host after | |
572 | * reset. Values without are used for driver operation. | |
573 | */ | |
574 | hpriv->saved_cap = cap = readl(mmio + HOST_CAP); | |
575 | hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); | |
576 | ||
274c1fde | 577 | /* some chips have errata preventing 64bit use */ |
417a1a6d | 578 | if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { |
c7a42156 TH |
579 | dev_printk(KERN_INFO, &pdev->dev, |
580 | "controller can't do 64bit DMA, forcing 32bit\n"); | |
581 | cap &= ~HOST_CAP_64; | |
582 | } | |
583 | ||
417a1a6d | 584 | if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { |
274c1fde TH |
585 | dev_printk(KERN_INFO, &pdev->dev, |
586 | "controller can't do NCQ, turning off CAP_NCQ\n"); | |
587 | cap &= ~HOST_CAP_NCQ; | |
588 | } | |
589 | ||
6949b914 TH |
590 | if ((cap && HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { |
591 | dev_printk(KERN_INFO, &pdev->dev, | |
592 | "controller can't do PMP, turning off CAP_PMP\n"); | |
593 | cap &= ~HOST_CAP_PMP; | |
594 | } | |
595 | ||
cd70c266 JG |
596 | /* |
597 | * Temporary Marvell 6145 hack: PATA port presence | |
598 | * is asserted through the standard AHCI port | |
599 | * presence register, as bit 4 (counting from 0) | |
600 | */ | |
417a1a6d | 601 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
cd70c266 JG |
602 | dev_printk(KERN_ERR, &pdev->dev, |
603 | "MV_AHCI HACK: port_map %x -> %x\n", | |
604 | hpriv->port_map, | |
605 | hpriv->port_map & 0xf); | |
606 | ||
607 | port_map &= 0xf; | |
608 | } | |
609 | ||
17199b18 | 610 | /* cross check port_map and cap.n_ports */ |
7a234aff | 611 | if (port_map) { |
17199b18 TH |
612 | u32 tmp_port_map = port_map; |
613 | int n_ports = ahci_nr_ports(cap); | |
614 | ||
615 | for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) { | |
616 | if (tmp_port_map & (1 << i)) { | |
617 | n_ports--; | |
618 | tmp_port_map &= ~(1 << i); | |
619 | } | |
620 | } | |
621 | ||
7a234aff TH |
622 | /* If n_ports and port_map are inconsistent, whine and |
623 | * clear port_map and let it be generated from n_ports. | |
17199b18 | 624 | */ |
7a234aff | 625 | if (n_ports || tmp_port_map) { |
4447d351 | 626 | dev_printk(KERN_WARNING, &pdev->dev, |
17199b18 | 627 | "nr_ports (%u) and implemented port map " |
7a234aff | 628 | "(0x%x) don't match, using nr_ports\n", |
17199b18 | 629 | ahci_nr_ports(cap), port_map); |
7a234aff TH |
630 | port_map = 0; |
631 | } | |
632 | } | |
633 | ||
634 | /* fabricate port_map from cap.nr_ports */ | |
635 | if (!port_map) { | |
17199b18 | 636 | port_map = (1 << ahci_nr_ports(cap)) - 1; |
7a234aff TH |
637 | dev_printk(KERN_WARNING, &pdev->dev, |
638 | "forcing PORTS_IMPL to 0x%x\n", port_map); | |
639 | ||
640 | /* write the fixed up value to the PI register */ | |
641 | hpriv->saved_port_map = port_map; | |
17199b18 TH |
642 | } |
643 | ||
d447df14 TH |
644 | /* record values to use during operation */ |
645 | hpriv->cap = cap; | |
646 | hpriv->port_map = port_map; | |
647 | } | |
648 | ||
649 | /** | |
650 | * ahci_restore_initial_config - Restore initial config | |
4447d351 | 651 | * @host: target ATA host |
d447df14 TH |
652 | * |
653 | * Restore initial config stored by ahci_save_initial_config(). | |
654 | * | |
655 | * LOCKING: | |
656 | * None. | |
657 | */ | |
4447d351 | 658 | static void ahci_restore_initial_config(struct ata_host *host) |
d447df14 | 659 | { |
4447d351 TH |
660 | struct ahci_host_priv *hpriv = host->private_data; |
661 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
662 | ||
d447df14 TH |
663 | writel(hpriv->saved_cap, mmio + HOST_CAP); |
664 | writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); | |
665 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ | |
666 | } | |
667 | ||
203ef6c4 | 668 | static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) |
1da177e4 | 669 | { |
203ef6c4 TH |
670 | static const int offset[] = { |
671 | [SCR_STATUS] = PORT_SCR_STAT, | |
672 | [SCR_CONTROL] = PORT_SCR_CTL, | |
673 | [SCR_ERROR] = PORT_SCR_ERR, | |
674 | [SCR_ACTIVE] = PORT_SCR_ACT, | |
675 | [SCR_NOTIFICATION] = PORT_SCR_NTF, | |
676 | }; | |
677 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
1da177e4 | 678 | |
203ef6c4 TH |
679 | if (sc_reg < ARRAY_SIZE(offset) && |
680 | (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) | |
681 | return offset[sc_reg]; | |
da3dbb17 | 682 | return 0; |
1da177e4 LT |
683 | } |
684 | ||
203ef6c4 | 685 | static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) |
1da177e4 | 686 | { |
203ef6c4 TH |
687 | void __iomem *port_mmio = ahci_port_base(ap); |
688 | int offset = ahci_scr_offset(ap, sc_reg); | |
689 | ||
690 | if (offset) { | |
691 | *val = readl(port_mmio + offset); | |
692 | return 0; | |
1da177e4 | 693 | } |
203ef6c4 TH |
694 | return -EINVAL; |
695 | } | |
1da177e4 | 696 | |
203ef6c4 TH |
697 | static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) |
698 | { | |
699 | void __iomem *port_mmio = ahci_port_base(ap); | |
700 | int offset = ahci_scr_offset(ap, sc_reg); | |
701 | ||
702 | if (offset) { | |
703 | writel(val, port_mmio + offset); | |
704 | return 0; | |
705 | } | |
706 | return -EINVAL; | |
1da177e4 LT |
707 | } |
708 | ||
4447d351 | 709 | static void ahci_start_engine(struct ata_port *ap) |
7c76d1e8 | 710 | { |
4447d351 | 711 | void __iomem *port_mmio = ahci_port_base(ap); |
7c76d1e8 TH |
712 | u32 tmp; |
713 | ||
d8fcd116 | 714 | /* start DMA */ |
9f592056 | 715 | tmp = readl(port_mmio + PORT_CMD); |
7c76d1e8 TH |
716 | tmp |= PORT_CMD_START; |
717 | writel(tmp, port_mmio + PORT_CMD); | |
718 | readl(port_mmio + PORT_CMD); /* flush */ | |
719 | } | |
720 | ||
4447d351 | 721 | static int ahci_stop_engine(struct ata_port *ap) |
254950cd | 722 | { |
4447d351 | 723 | void __iomem *port_mmio = ahci_port_base(ap); |
254950cd TH |
724 | u32 tmp; |
725 | ||
726 | tmp = readl(port_mmio + PORT_CMD); | |
727 | ||
d8fcd116 | 728 | /* check if the HBA is idle */ |
254950cd TH |
729 | if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) |
730 | return 0; | |
731 | ||
d8fcd116 | 732 | /* setting HBA to idle */ |
254950cd TH |
733 | tmp &= ~PORT_CMD_START; |
734 | writel(tmp, port_mmio + PORT_CMD); | |
735 | ||
d8fcd116 | 736 | /* wait for engine to stop. This could be as long as 500 msec */ |
254950cd TH |
737 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
738 | PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); | |
d8fcd116 | 739 | if (tmp & PORT_CMD_LIST_ON) |
254950cd TH |
740 | return -EIO; |
741 | ||
742 | return 0; | |
743 | } | |
744 | ||
4447d351 | 745 | static void ahci_start_fis_rx(struct ata_port *ap) |
0be0aa98 | 746 | { |
4447d351 TH |
747 | void __iomem *port_mmio = ahci_port_base(ap); |
748 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
749 | struct ahci_port_priv *pp = ap->private_data; | |
0be0aa98 TH |
750 | u32 tmp; |
751 | ||
752 | /* set FIS registers */ | |
4447d351 TH |
753 | if (hpriv->cap & HOST_CAP_64) |
754 | writel((pp->cmd_slot_dma >> 16) >> 16, | |
755 | port_mmio + PORT_LST_ADDR_HI); | |
756 | writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); | |
0be0aa98 | 757 | |
4447d351 TH |
758 | if (hpriv->cap & HOST_CAP_64) |
759 | writel((pp->rx_fis_dma >> 16) >> 16, | |
760 | port_mmio + PORT_FIS_ADDR_HI); | |
761 | writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); | |
0be0aa98 TH |
762 | |
763 | /* enable FIS reception */ | |
764 | tmp = readl(port_mmio + PORT_CMD); | |
765 | tmp |= PORT_CMD_FIS_RX; | |
766 | writel(tmp, port_mmio + PORT_CMD); | |
767 | ||
768 | /* flush */ | |
769 | readl(port_mmio + PORT_CMD); | |
770 | } | |
771 | ||
4447d351 | 772 | static int ahci_stop_fis_rx(struct ata_port *ap) |
0be0aa98 | 773 | { |
4447d351 | 774 | void __iomem *port_mmio = ahci_port_base(ap); |
0be0aa98 TH |
775 | u32 tmp; |
776 | ||
777 | /* disable FIS reception */ | |
778 | tmp = readl(port_mmio + PORT_CMD); | |
779 | tmp &= ~PORT_CMD_FIS_RX; | |
780 | writel(tmp, port_mmio + PORT_CMD); | |
781 | ||
782 | /* wait for completion, spec says 500ms, give it 1000 */ | |
783 | tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, | |
784 | PORT_CMD_FIS_ON, 10, 1000); | |
785 | if (tmp & PORT_CMD_FIS_ON) | |
786 | return -EBUSY; | |
787 | ||
788 | return 0; | |
789 | } | |
790 | ||
4447d351 | 791 | static void ahci_power_up(struct ata_port *ap) |
0be0aa98 | 792 | { |
4447d351 TH |
793 | struct ahci_host_priv *hpriv = ap->host->private_data; |
794 | void __iomem *port_mmio = ahci_port_base(ap); | |
0be0aa98 TH |
795 | u32 cmd; |
796 | ||
797 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
798 | ||
799 | /* spin up device */ | |
4447d351 | 800 | if (hpriv->cap & HOST_CAP_SSS) { |
0be0aa98 TH |
801 | cmd |= PORT_CMD_SPIN_UP; |
802 | writel(cmd, port_mmio + PORT_CMD); | |
803 | } | |
804 | ||
805 | /* wake up link */ | |
806 | writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); | |
807 | } | |
808 | ||
438ac6d5 | 809 | #ifdef CONFIG_PM |
4447d351 | 810 | static void ahci_power_down(struct ata_port *ap) |
0be0aa98 | 811 | { |
4447d351 TH |
812 | struct ahci_host_priv *hpriv = ap->host->private_data; |
813 | void __iomem *port_mmio = ahci_port_base(ap); | |
0be0aa98 TH |
814 | u32 cmd, scontrol; |
815 | ||
4447d351 | 816 | if (!(hpriv->cap & HOST_CAP_SSS)) |
07c53dac | 817 | return; |
0be0aa98 | 818 | |
07c53dac TH |
819 | /* put device into listen mode, first set PxSCTL.DET to 0 */ |
820 | scontrol = readl(port_mmio + PORT_SCR_CTL); | |
821 | scontrol &= ~0xf; | |
822 | writel(scontrol, port_mmio + PORT_SCR_CTL); | |
0be0aa98 | 823 | |
07c53dac TH |
824 | /* then set PxCMD.SUD to 0 */ |
825 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
826 | cmd &= ~PORT_CMD_SPIN_UP; | |
827 | writel(cmd, port_mmio + PORT_CMD); | |
0be0aa98 | 828 | } |
438ac6d5 | 829 | #endif |
0be0aa98 | 830 | |
df69c9c5 | 831 | static void ahci_start_port(struct ata_port *ap) |
0be0aa98 | 832 | { |
0be0aa98 | 833 | /* enable FIS reception */ |
4447d351 | 834 | ahci_start_fis_rx(ap); |
0be0aa98 TH |
835 | |
836 | /* enable DMA */ | |
4447d351 | 837 | ahci_start_engine(ap); |
0be0aa98 TH |
838 | } |
839 | ||
4447d351 | 840 | static int ahci_deinit_port(struct ata_port *ap, const char **emsg) |
0be0aa98 TH |
841 | { |
842 | int rc; | |
843 | ||
844 | /* disable DMA */ | |
4447d351 | 845 | rc = ahci_stop_engine(ap); |
0be0aa98 TH |
846 | if (rc) { |
847 | *emsg = "failed to stop engine"; | |
848 | return rc; | |
849 | } | |
850 | ||
851 | /* disable FIS reception */ | |
4447d351 | 852 | rc = ahci_stop_fis_rx(ap); |
0be0aa98 TH |
853 | if (rc) { |
854 | *emsg = "failed stop FIS RX"; | |
855 | return rc; | |
856 | } | |
857 | ||
0be0aa98 TH |
858 | return 0; |
859 | } | |
860 | ||
4447d351 | 861 | static int ahci_reset_controller(struct ata_host *host) |
d91542c1 | 862 | { |
4447d351 TH |
863 | struct pci_dev *pdev = to_pci_dev(host->dev); |
864 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
d447df14 | 865 | u32 tmp; |
d91542c1 | 866 | |
3cc3eb11 JG |
867 | /* we must be in AHCI mode, before using anything |
868 | * AHCI-specific, such as HOST_RESET. | |
869 | */ | |
d91542c1 | 870 | tmp = readl(mmio + HOST_CTL); |
3cc3eb11 JG |
871 | if (!(tmp & HOST_AHCI_EN)) |
872 | writel(tmp | HOST_AHCI_EN, mmio + HOST_CTL); | |
873 | ||
874 | /* global controller reset */ | |
d91542c1 TH |
875 | if ((tmp & HOST_RESET) == 0) { |
876 | writel(tmp | HOST_RESET, mmio + HOST_CTL); | |
877 | readl(mmio + HOST_CTL); /* flush */ | |
878 | } | |
879 | ||
880 | /* reset must complete within 1 second, or | |
881 | * the hardware should be considered fried. | |
882 | */ | |
883 | ssleep(1); | |
884 | ||
885 | tmp = readl(mmio + HOST_CTL); | |
886 | if (tmp & HOST_RESET) { | |
4447d351 | 887 | dev_printk(KERN_ERR, host->dev, |
d91542c1 TH |
888 | "controller reset failed (0x%x)\n", tmp); |
889 | return -EIO; | |
890 | } | |
891 | ||
98fa4b60 | 892 | /* turn on AHCI mode */ |
d91542c1 TH |
893 | writel(HOST_AHCI_EN, mmio + HOST_CTL); |
894 | (void) readl(mmio + HOST_CTL); /* flush */ | |
98fa4b60 | 895 | |
d447df14 | 896 | /* some registers might be cleared on reset. restore initial values */ |
4447d351 | 897 | ahci_restore_initial_config(host); |
d91542c1 TH |
898 | |
899 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { | |
900 | u16 tmp16; | |
901 | ||
902 | /* configure PCS */ | |
903 | pci_read_config_word(pdev, 0x92, &tmp16); | |
904 | tmp16 |= 0xf; | |
905 | pci_write_config_word(pdev, 0x92, tmp16); | |
906 | } | |
907 | ||
908 | return 0; | |
909 | } | |
910 | ||
2bcd866b JG |
911 | static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap, |
912 | int port_no, void __iomem *mmio, | |
913 | void __iomem *port_mmio) | |
914 | { | |
915 | const char *emsg = NULL; | |
916 | int rc; | |
917 | u32 tmp; | |
918 | ||
919 | /* make sure port is not active */ | |
920 | rc = ahci_deinit_port(ap, &emsg); | |
921 | if (rc) | |
922 | dev_printk(KERN_WARNING, &pdev->dev, | |
923 | "%s (%d)\n", emsg, rc); | |
924 | ||
925 | /* clear SError */ | |
926 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
927 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); | |
928 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
929 | ||
930 | /* clear port IRQ */ | |
931 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
932 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
933 | if (tmp) | |
934 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
935 | ||
936 | writel(1 << port_no, mmio + HOST_IRQ_STAT); | |
937 | } | |
938 | ||
4447d351 | 939 | static void ahci_init_controller(struct ata_host *host) |
d91542c1 | 940 | { |
417a1a6d | 941 | struct ahci_host_priv *hpriv = host->private_data; |
4447d351 TH |
942 | struct pci_dev *pdev = to_pci_dev(host->dev); |
943 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
2bcd866b | 944 | int i; |
cd70c266 | 945 | void __iomem *port_mmio; |
d91542c1 TH |
946 | u32 tmp; |
947 | ||
417a1a6d | 948 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
cd70c266 JG |
949 | port_mmio = __ahci_port_base(host, 4); |
950 | ||
951 | writel(0, port_mmio + PORT_IRQ_MASK); | |
952 | ||
953 | /* clear port IRQ */ | |
954 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
955 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
956 | if (tmp) | |
957 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
958 | } | |
959 | ||
4447d351 TH |
960 | for (i = 0; i < host->n_ports; i++) { |
961 | struct ata_port *ap = host->ports[i]; | |
d91542c1 | 962 | |
cd70c266 | 963 | port_mmio = ahci_port_base(ap); |
4447d351 | 964 | if (ata_port_is_dummy(ap)) |
d91542c1 | 965 | continue; |
d91542c1 | 966 | |
2bcd866b | 967 | ahci_port_init(pdev, ap, i, mmio, port_mmio); |
d91542c1 TH |
968 | } |
969 | ||
970 | tmp = readl(mmio + HOST_CTL); | |
971 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
972 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); | |
973 | tmp = readl(mmio + HOST_CTL); | |
974 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
975 | } | |
976 | ||
422b7595 | 977 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
1da177e4 | 978 | { |
4447d351 | 979 | void __iomem *port_mmio = ahci_port_base(ap); |
1da177e4 | 980 | struct ata_taskfile tf; |
422b7595 TH |
981 | u32 tmp; |
982 | ||
983 | tmp = readl(port_mmio + PORT_SIG); | |
984 | tf.lbah = (tmp >> 24) & 0xff; | |
985 | tf.lbam = (tmp >> 16) & 0xff; | |
986 | tf.lbal = (tmp >> 8) & 0xff; | |
987 | tf.nsect = (tmp) & 0xff; | |
988 | ||
989 | return ata_dev_classify(&tf); | |
990 | } | |
991 | ||
12fad3f9 TH |
992 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
993 | u32 opts) | |
cc9278ed | 994 | { |
12fad3f9 TH |
995 | dma_addr_t cmd_tbl_dma; |
996 | ||
997 | cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; | |
998 | ||
999 | pp->cmd_slot[tag].opts = cpu_to_le32(opts); | |
1000 | pp->cmd_slot[tag].status = 0; | |
1001 | pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); | |
1002 | pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); | |
cc9278ed TH |
1003 | } |
1004 | ||
d2e75dff | 1005 | static int ahci_kick_engine(struct ata_port *ap, int force_restart) |
4658f79b | 1006 | { |
0d5ff566 | 1007 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
cca3974e | 1008 | struct ahci_host_priv *hpriv = ap->host->private_data; |
bf2af2a2 | 1009 | u32 tmp; |
d2e75dff | 1010 | int busy, rc; |
bf2af2a2 | 1011 | |
d2e75dff TH |
1012 | /* do we need to kick the port? */ |
1013 | busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ); | |
1014 | if (!busy && !force_restart) | |
1015 | return 0; | |
1016 | ||
1017 | /* stop engine */ | |
1018 | rc = ahci_stop_engine(ap); | |
1019 | if (rc) | |
1020 | goto out_restart; | |
1021 | ||
1022 | /* need to do CLO? */ | |
1023 | if (!busy) { | |
1024 | rc = 0; | |
1025 | goto out_restart; | |
1026 | } | |
1027 | ||
1028 | if (!(hpriv->cap & HOST_CAP_CLO)) { | |
1029 | rc = -EOPNOTSUPP; | |
1030 | goto out_restart; | |
1031 | } | |
bf2af2a2 | 1032 | |
d2e75dff | 1033 | /* perform CLO */ |
bf2af2a2 BJ |
1034 | tmp = readl(port_mmio + PORT_CMD); |
1035 | tmp |= PORT_CMD_CLO; | |
1036 | writel(tmp, port_mmio + PORT_CMD); | |
1037 | ||
d2e75dff | 1038 | rc = 0; |
bf2af2a2 BJ |
1039 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
1040 | PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); | |
1041 | if (tmp & PORT_CMD_CLO) | |
d2e75dff | 1042 | rc = -EIO; |
bf2af2a2 | 1043 | |
d2e75dff TH |
1044 | /* restart engine */ |
1045 | out_restart: | |
1046 | ahci_start_engine(ap); | |
1047 | return rc; | |
bf2af2a2 BJ |
1048 | } |
1049 | ||
91c4a2e0 TH |
1050 | static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, |
1051 | struct ata_taskfile *tf, int is_cmd, u16 flags, | |
1052 | unsigned long timeout_msec) | |
bf2af2a2 | 1053 | { |
91c4a2e0 | 1054 | const u32 cmd_fis_len = 5; /* five dwords */ |
4658f79b | 1055 | struct ahci_port_priv *pp = ap->private_data; |
4447d351 | 1056 | void __iomem *port_mmio = ahci_port_base(ap); |
91c4a2e0 TH |
1057 | u8 *fis = pp->cmd_tbl; |
1058 | u32 tmp; | |
1059 | ||
1060 | /* prep the command */ | |
1061 | ata_tf_to_fis(tf, pmp, is_cmd, fis); | |
1062 | ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); | |
1063 | ||
1064 | /* issue & wait */ | |
1065 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
1066 | ||
1067 | if (timeout_msec) { | |
1068 | tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, | |
1069 | 1, timeout_msec); | |
1070 | if (tmp & 0x1) { | |
1071 | ahci_kick_engine(ap, 1); | |
1072 | return -EBUSY; | |
1073 | } | |
1074 | } else | |
1075 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ | |
1076 | ||
1077 | return 0; | |
1078 | } | |
1079 | ||
cc0680a5 | 1080 | static int ahci_do_softreset(struct ata_link *link, unsigned int *class, |
a9cf5e85 | 1081 | int pmp, unsigned long deadline) |
91c4a2e0 | 1082 | { |
cc0680a5 | 1083 | struct ata_port *ap = link->ap; |
4658f79b | 1084 | const char *reason = NULL; |
2cbb79eb | 1085 | unsigned long now, msecs; |
4658f79b | 1086 | struct ata_taskfile tf; |
4658f79b TH |
1087 | int rc; |
1088 | ||
1089 | DPRINTK("ENTER\n"); | |
1090 | ||
cc0680a5 | 1091 | if (ata_link_offline(link)) { |
c2a65852 TH |
1092 | DPRINTK("PHY reports no device\n"); |
1093 | *class = ATA_DEV_NONE; | |
1094 | return 0; | |
1095 | } | |
1096 | ||
4658f79b | 1097 | /* prepare for SRST (AHCI-1.1 10.4.1) */ |
d2e75dff TH |
1098 | rc = ahci_kick_engine(ap, 1); |
1099 | if (rc) | |
cc0680a5 | 1100 | ata_link_printk(link, KERN_WARNING, |
d2e75dff | 1101 | "failed to reset engine (errno=%d)", rc); |
4658f79b | 1102 | |
cc0680a5 | 1103 | ata_tf_init(link->device, &tf); |
4658f79b TH |
1104 | |
1105 | /* issue the first D2H Register FIS */ | |
2cbb79eb TH |
1106 | msecs = 0; |
1107 | now = jiffies; | |
1108 | if (time_after(now, deadline)) | |
1109 | msecs = jiffies_to_msecs(deadline - now); | |
1110 | ||
4658f79b | 1111 | tf.ctl |= ATA_SRST; |
a9cf5e85 | 1112 | if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, |
91c4a2e0 | 1113 | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { |
4658f79b TH |
1114 | rc = -EIO; |
1115 | reason = "1st FIS failed"; | |
1116 | goto fail; | |
1117 | } | |
1118 | ||
1119 | /* spec says at least 5us, but be generous and sleep for 1ms */ | |
1120 | msleep(1); | |
1121 | ||
1122 | /* issue the second D2H Register FIS */ | |
4658f79b | 1123 | tf.ctl &= ~ATA_SRST; |
a9cf5e85 | 1124 | ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); |
4658f79b TH |
1125 | |
1126 | /* spec mandates ">= 2ms" before checking status. | |
1127 | * We wait 150ms, because that was the magic delay used for | |
1128 | * ATAPI devices in Hale Landis's ATADRVR, for the period of time | |
1129 | * between when the ATA command register is written, and then | |
1130 | * status is checked. Because waiting for "a while" before | |
1131 | * checking status is fine, post SRST, we perform this magic | |
1132 | * delay here as well. | |
1133 | */ | |
1134 | msleep(150); | |
1135 | ||
9b89391c TH |
1136 | rc = ata_wait_ready(ap, deadline); |
1137 | /* link occupied, -ENODEV too is an error */ | |
1138 | if (rc) { | |
1139 | reason = "device not ready"; | |
1140 | goto fail; | |
4658f79b | 1141 | } |
9b89391c | 1142 | *class = ahci_dev_classify(ap); |
4658f79b TH |
1143 | |
1144 | DPRINTK("EXIT, class=%u\n", *class); | |
1145 | return 0; | |
1146 | ||
4658f79b | 1147 | fail: |
cc0680a5 | 1148 | ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); |
4658f79b TH |
1149 | return rc; |
1150 | } | |
1151 | ||
cc0680a5 | 1152 | static int ahci_softreset(struct ata_link *link, unsigned int *class, |
a9cf5e85 TH |
1153 | unsigned long deadline) |
1154 | { | |
7d50b60b TH |
1155 | int pmp = 0; |
1156 | ||
1157 | if (link->ap->flags & ATA_FLAG_PMP) | |
1158 | pmp = SATA_PMP_CTRL_PORT; | |
1159 | ||
1160 | return ahci_do_softreset(link, class, pmp, deadline); | |
a9cf5e85 TH |
1161 | } |
1162 | ||
cc0680a5 | 1163 | static int ahci_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 1164 | unsigned long deadline) |
422b7595 | 1165 | { |
cc0680a5 | 1166 | struct ata_port *ap = link->ap; |
4296971d TH |
1167 | struct ahci_port_priv *pp = ap->private_data; |
1168 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1169 | struct ata_taskfile tf; | |
4bd00f6a TH |
1170 | int rc; |
1171 | ||
1172 | DPRINTK("ENTER\n"); | |
1da177e4 | 1173 | |
4447d351 | 1174 | ahci_stop_engine(ap); |
4296971d TH |
1175 | |
1176 | /* clear D2H reception area to properly wait for D2H FIS */ | |
cc0680a5 | 1177 | ata_tf_init(link->device, &tf); |
dfd7a3db | 1178 | tf.command = 0x80; |
9977126c | 1179 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); |
4296971d | 1180 | |
cc0680a5 | 1181 | rc = sata_std_hardreset(link, class, deadline); |
4296971d | 1182 | |
4447d351 | 1183 | ahci_start_engine(ap); |
1da177e4 | 1184 | |
cc0680a5 | 1185 | if (rc == 0 && ata_link_online(link)) |
4bd00f6a | 1186 | *class = ahci_dev_classify(ap); |
7d50b60b | 1187 | if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN) |
4bd00f6a | 1188 | *class = ATA_DEV_NONE; |
1da177e4 | 1189 | |
4bd00f6a TH |
1190 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
1191 | return rc; | |
1192 | } | |
1193 | ||
cc0680a5 | 1194 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 1195 | unsigned long deadline) |
ad616ffb | 1196 | { |
cc0680a5 | 1197 | struct ata_port *ap = link->ap; |
da3dbb17 | 1198 | u32 serror; |
ad616ffb TH |
1199 | int rc; |
1200 | ||
1201 | DPRINTK("ENTER\n"); | |
1202 | ||
4447d351 | 1203 | ahci_stop_engine(ap); |
ad616ffb | 1204 | |
cc0680a5 | 1205 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), |
d4b2bab4 | 1206 | deadline); |
ad616ffb TH |
1207 | |
1208 | /* vt8251 needs SError cleared for the port to operate */ | |
da3dbb17 TH |
1209 | ahci_scr_read(ap, SCR_ERROR, &serror); |
1210 | ahci_scr_write(ap, SCR_ERROR, serror); | |
ad616ffb | 1211 | |
4447d351 | 1212 | ahci_start_engine(ap); |
ad616ffb TH |
1213 | |
1214 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); | |
1215 | ||
1216 | /* vt8251 doesn't clear BSY on signature FIS reception, | |
1217 | * request follow-up softreset. | |
1218 | */ | |
1219 | return rc ?: -EAGAIN; | |
1220 | } | |
1221 | ||
cc0680a5 | 1222 | static void ahci_postreset(struct ata_link *link, unsigned int *class) |
4bd00f6a | 1223 | { |
cc0680a5 | 1224 | struct ata_port *ap = link->ap; |
4447d351 | 1225 | void __iomem *port_mmio = ahci_port_base(ap); |
4bd00f6a TH |
1226 | u32 new_tmp, tmp; |
1227 | ||
cc0680a5 | 1228 | ata_std_postreset(link, class); |
02eaa666 JG |
1229 | |
1230 | /* Make sure port's ATAPI bit is set appropriately */ | |
1231 | new_tmp = tmp = readl(port_mmio + PORT_CMD); | |
4bd00f6a | 1232 | if (*class == ATA_DEV_ATAPI) |
02eaa666 JG |
1233 | new_tmp |= PORT_CMD_ATAPI; |
1234 | else | |
1235 | new_tmp &= ~PORT_CMD_ATAPI; | |
1236 | if (new_tmp != tmp) { | |
1237 | writel(new_tmp, port_mmio + PORT_CMD); | |
1238 | readl(port_mmio + PORT_CMD); /* flush */ | |
1239 | } | |
1da177e4 LT |
1240 | } |
1241 | ||
7d50b60b TH |
1242 | static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class, |
1243 | unsigned long deadline) | |
1244 | { | |
1245 | return ahci_do_softreset(link, class, link->pmp, deadline); | |
1246 | } | |
1247 | ||
1da177e4 LT |
1248 | static u8 ahci_check_status(struct ata_port *ap) |
1249 | { | |
0d5ff566 | 1250 | void __iomem *mmio = ap->ioaddr.cmd_addr; |
1da177e4 LT |
1251 | |
1252 | return readl(mmio + PORT_TFDATA) & 0xFF; | |
1253 | } | |
1254 | ||
1da177e4 LT |
1255 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
1256 | { | |
1257 | struct ahci_port_priv *pp = ap->private_data; | |
1258 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1259 | ||
1260 | ata_tf_from_fis(d2h_fis, tf); | |
1261 | } | |
1262 | ||
12fad3f9 | 1263 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) |
1da177e4 | 1264 | { |
cedc9a47 JG |
1265 | struct scatterlist *sg; |
1266 | struct ahci_sg *ahci_sg; | |
828d09de | 1267 | unsigned int n_sg = 0; |
1da177e4 LT |
1268 | |
1269 | VPRINTK("ENTER\n"); | |
1270 | ||
1271 | /* | |
1272 | * Next, the S/G list. | |
1273 | */ | |
12fad3f9 | 1274 | ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; |
cedc9a47 JG |
1275 | ata_for_each_sg(sg, qc) { |
1276 | dma_addr_t addr = sg_dma_address(sg); | |
1277 | u32 sg_len = sg_dma_len(sg); | |
1278 | ||
1279 | ahci_sg->addr = cpu_to_le32(addr & 0xffffffff); | |
1280 | ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); | |
1281 | ahci_sg->flags_size = cpu_to_le32(sg_len - 1); | |
828d09de | 1282 | |
cedc9a47 | 1283 | ahci_sg++; |
828d09de | 1284 | n_sg++; |
1da177e4 | 1285 | } |
828d09de JG |
1286 | |
1287 | return n_sg; | |
1da177e4 LT |
1288 | } |
1289 | ||
1290 | static void ahci_qc_prep(struct ata_queued_cmd *qc) | |
1291 | { | |
a0ea7328 JG |
1292 | struct ata_port *ap = qc->ap; |
1293 | struct ahci_port_priv *pp = ap->private_data; | |
cc9278ed | 1294 | int is_atapi = is_atapi_taskfile(&qc->tf); |
12fad3f9 | 1295 | void *cmd_tbl; |
1da177e4 LT |
1296 | u32 opts; |
1297 | const u32 cmd_fis_len = 5; /* five dwords */ | |
828d09de | 1298 | unsigned int n_elem; |
1da177e4 | 1299 | |
1da177e4 LT |
1300 | /* |
1301 | * Fill in command table information. First, the header, | |
1302 | * a SATA Register - Host to Device command FIS. | |
1303 | */ | |
12fad3f9 TH |
1304 | cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; |
1305 | ||
7d50b60b | 1306 | ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); |
cc9278ed | 1307 | if (is_atapi) { |
12fad3f9 TH |
1308 | memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); |
1309 | memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); | |
a0ea7328 | 1310 | } |
1da177e4 | 1311 | |
cc9278ed TH |
1312 | n_elem = 0; |
1313 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
12fad3f9 | 1314 | n_elem = ahci_fill_sg(qc, cmd_tbl); |
1da177e4 | 1315 | |
cc9278ed TH |
1316 | /* |
1317 | * Fill in command slot information. | |
1318 | */ | |
7d50b60b | 1319 | opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); |
cc9278ed TH |
1320 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
1321 | opts |= AHCI_CMD_WRITE; | |
1322 | if (is_atapi) | |
4b10e559 | 1323 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; |
828d09de | 1324 | |
12fad3f9 | 1325 | ahci_fill_cmd_slot(pp, qc->tag, opts); |
1da177e4 LT |
1326 | } |
1327 | ||
78cd52d0 | 1328 | static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) |
1da177e4 | 1329 | { |
417a1a6d | 1330 | struct ahci_host_priv *hpriv = ap->host->private_data; |
78cd52d0 | 1331 | struct ahci_port_priv *pp = ap->private_data; |
7d50b60b TH |
1332 | struct ata_eh_info *host_ehi = &ap->link.eh_info; |
1333 | struct ata_link *link = NULL; | |
1334 | struct ata_queued_cmd *active_qc; | |
1335 | struct ata_eh_info *active_ehi; | |
78cd52d0 | 1336 | u32 serror; |
1da177e4 | 1337 | |
7d50b60b TH |
1338 | /* determine active link */ |
1339 | ata_port_for_each_link(link, ap) | |
1340 | if (ata_link_active(link)) | |
1341 | break; | |
1342 | if (!link) | |
1343 | link = &ap->link; | |
1344 | ||
1345 | active_qc = ata_qc_from_tag(ap, link->active_tag); | |
1346 | active_ehi = &link->eh_info; | |
1347 | ||
1348 | /* record irq stat */ | |
1349 | ata_ehi_clear_desc(host_ehi); | |
1350 | ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); | |
1da177e4 | 1351 | |
78cd52d0 | 1352 | /* AHCI needs SError cleared; otherwise, it might lock up */ |
da3dbb17 | 1353 | ahci_scr_read(ap, SCR_ERROR, &serror); |
78cd52d0 | 1354 | ahci_scr_write(ap, SCR_ERROR, serror); |
7d50b60b | 1355 | host_ehi->serror |= serror; |
78cd52d0 | 1356 | |
41669553 | 1357 | /* some controllers set IRQ_IF_ERR on device errors, ignore it */ |
417a1a6d | 1358 | if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) |
41669553 TH |
1359 | irq_stat &= ~PORT_IRQ_IF_ERR; |
1360 | ||
55a61604 | 1361 | if (irq_stat & PORT_IRQ_TF_ERR) { |
7d50b60b TH |
1362 | /* If qc is active, charge it; otherwise, the active |
1363 | * link. There's no active qc on NCQ errors. It will | |
1364 | * be determined by EH by reading log page 10h. | |
1365 | */ | |
1366 | if (active_qc) | |
1367 | active_qc->err_mask |= AC_ERR_DEV; | |
1368 | else | |
1369 | active_ehi->err_mask |= AC_ERR_DEV; | |
1370 | ||
417a1a6d | 1371 | if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) |
7d50b60b TH |
1372 | host_ehi->serror &= ~SERR_INTERNAL; |
1373 | } | |
1374 | ||
1375 | if (irq_stat & PORT_IRQ_UNK_FIS) { | |
1376 | u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); | |
1377 | ||
1378 | active_ehi->err_mask |= AC_ERR_HSM; | |
1379 | active_ehi->action |= ATA_EH_SOFTRESET; | |
1380 | ata_ehi_push_desc(active_ehi, | |
1381 | "unknown FIS %08x %08x %08x %08x" , | |
1382 | unk[0], unk[1], unk[2], unk[3]); | |
1383 | } | |
1384 | ||
1385 | if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) { | |
1386 | active_ehi->err_mask |= AC_ERR_HSM; | |
1387 | active_ehi->action |= ATA_EH_SOFTRESET; | |
1388 | ata_ehi_push_desc(active_ehi, "incorrect PMP"); | |
55a61604 | 1389 | } |
78cd52d0 TH |
1390 | |
1391 | if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { | |
7d50b60b TH |
1392 | host_ehi->err_mask |= AC_ERR_HOST_BUS; |
1393 | host_ehi->action |= ATA_EH_SOFTRESET; | |
1394 | ata_ehi_push_desc(host_ehi, "host bus error"); | |
1da177e4 LT |
1395 | } |
1396 | ||
78cd52d0 | 1397 | if (irq_stat & PORT_IRQ_IF_ERR) { |
7d50b60b TH |
1398 | host_ehi->err_mask |= AC_ERR_ATA_BUS; |
1399 | host_ehi->action |= ATA_EH_SOFTRESET; | |
1400 | ata_ehi_push_desc(host_ehi, "interface fatal error"); | |
78cd52d0 | 1401 | } |
1da177e4 | 1402 | |
78cd52d0 | 1403 | if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { |
7d50b60b TH |
1404 | ata_ehi_hotplugged(host_ehi); |
1405 | ata_ehi_push_desc(host_ehi, "%s", | |
1406 | irq_stat & PORT_IRQ_CONNECT ? | |
78cd52d0 TH |
1407 | "connection status changed" : "PHY RDY changed"); |
1408 | } | |
1409 | ||
78cd52d0 | 1410 | /* okay, let's hand over to EH */ |
a72ec4ce | 1411 | |
78cd52d0 TH |
1412 | if (irq_stat & PORT_IRQ_FREEZE) |
1413 | ata_port_freeze(ap); | |
1414 | else | |
1415 | ata_port_abort(ap); | |
1da177e4 LT |
1416 | } |
1417 | ||
df69c9c5 | 1418 | static void ahci_port_intr(struct ata_port *ap) |
1da177e4 | 1419 | { |
4447d351 | 1420 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
9af5c9c9 | 1421 | struct ata_eh_info *ehi = &ap->link.eh_info; |
0291f95f | 1422 | struct ahci_port_priv *pp = ap->private_data; |
12fad3f9 | 1423 | u32 status, qc_active; |
0291f95f | 1424 | int rc, known_irq = 0; |
1da177e4 LT |
1425 | |
1426 | status = readl(port_mmio + PORT_IRQ_STAT); | |
1427 | writel(status, port_mmio + PORT_IRQ_STAT); | |
1428 | ||
78cd52d0 TH |
1429 | if (unlikely(status & PORT_IRQ_ERROR)) { |
1430 | ahci_error_intr(ap, status); | |
1431 | return; | |
1da177e4 LT |
1432 | } |
1433 | ||
2f294968 | 1434 | if (status & PORT_IRQ_SDB_FIS) { |
7d77b247 TH |
1435 | /* If the 'N' bit in word 0 of the FIS is set, we just |
1436 | * received asynchronous notification. Tell libata | |
1437 | * about it. Note that as the SDB FIS itself is | |
1438 | * accessible, SNotification can be emulated by the | |
1439 | * driver but don't bother for the time being. | |
2f294968 KCA |
1440 | */ |
1441 | const __le32 *f = pp->rx_fis + RX_FIS_SDB; | |
1442 | u32 f0 = le32_to_cpu(f[0]); | |
1443 | ||
7d77b247 TH |
1444 | if (f0 & (1 << 15)) |
1445 | sata_async_notification(ap); | |
2f294968 KCA |
1446 | } |
1447 | ||
7d50b60b TH |
1448 | /* pp->active_link is valid iff any command is in flight */ |
1449 | if (ap->qc_active && pp->active_link->sactive) | |
12fad3f9 TH |
1450 | qc_active = readl(port_mmio + PORT_SCR_ACT); |
1451 | else | |
1452 | qc_active = readl(port_mmio + PORT_CMD_ISSUE); | |
1453 | ||
1454 | rc = ata_qc_complete_multiple(ap, qc_active, NULL); | |
1455 | if (rc > 0) | |
1456 | return; | |
1457 | if (rc < 0) { | |
1458 | ehi->err_mask |= AC_ERR_HSM; | |
1459 | ehi->action |= ATA_EH_SOFTRESET; | |
1460 | ata_port_freeze(ap); | |
1461 | return; | |
1da177e4 LT |
1462 | } |
1463 | ||
2a3917a8 TH |
1464 | /* hmmm... a spurious interupt */ |
1465 | ||
0291f95f TH |
1466 | /* if !NCQ, ignore. No modern ATA device has broken HSM |
1467 | * implementation for non-NCQ commands. | |
1468 | */ | |
9af5c9c9 | 1469 | if (!ap->link.sactive) |
12fad3f9 TH |
1470 | return; |
1471 | ||
0291f95f TH |
1472 | if (status & PORT_IRQ_D2H_REG_FIS) { |
1473 | if (!pp->ncq_saw_d2h) | |
1474 | ata_port_printk(ap, KERN_INFO, | |
1475 | "D2H reg with I during NCQ, " | |
1476 | "this message won't be printed again\n"); | |
1477 | pp->ncq_saw_d2h = 1; | |
1478 | known_irq = 1; | |
1479 | } | |
1480 | ||
1481 | if (status & PORT_IRQ_DMAS_FIS) { | |
1482 | if (!pp->ncq_saw_dmas) | |
1483 | ata_port_printk(ap, KERN_INFO, | |
1484 | "DMAS FIS during NCQ, " | |
1485 | "this message won't be printed again\n"); | |
1486 | pp->ncq_saw_dmas = 1; | |
1487 | known_irq = 1; | |
1488 | } | |
1489 | ||
a2bbd0c9 | 1490 | if (status & PORT_IRQ_SDB_FIS) { |
04d4f7a1 | 1491 | const __le32 *f = pp->rx_fis + RX_FIS_SDB; |
0291f95f | 1492 | |
afb2d552 TH |
1493 | if (le32_to_cpu(f[1])) { |
1494 | /* SDB FIS containing spurious completions | |
1495 | * might be dangerous, whine and fail commands | |
1496 | * with HSM violation. EH will turn off NCQ | |
1497 | * after several such failures. | |
1498 | */ | |
1499 | ata_ehi_push_desc(ehi, | |
1500 | "spurious completions during NCQ " | |
1501 | "issue=0x%x SAct=0x%x FIS=%08x:%08x", | |
1502 | readl(port_mmio + PORT_CMD_ISSUE), | |
1503 | readl(port_mmio + PORT_SCR_ACT), | |
1504 | le32_to_cpu(f[0]), le32_to_cpu(f[1])); | |
1505 | ehi->err_mask |= AC_ERR_HSM; | |
1506 | ehi->action |= ATA_EH_SOFTRESET; | |
1507 | ata_port_freeze(ap); | |
1508 | } else { | |
1509 | if (!pp->ncq_saw_sdb) | |
1510 | ata_port_printk(ap, KERN_INFO, | |
1511 | "spurious SDB FIS %08x:%08x during NCQ, " | |
1512 | "this message won't be printed again\n", | |
1513 | le32_to_cpu(f[0]), le32_to_cpu(f[1])); | |
1514 | pp->ncq_saw_sdb = 1; | |
1515 | } | |
0291f95f TH |
1516 | known_irq = 1; |
1517 | } | |
2a3917a8 | 1518 | |
0291f95f | 1519 | if (!known_irq) |
78cd52d0 | 1520 | ata_port_printk(ap, KERN_INFO, "spurious interrupt " |
0291f95f | 1521 | "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n", |
9af5c9c9 | 1522 | status, ap->link.active_tag, ap->link.sactive); |
1da177e4 LT |
1523 | } |
1524 | ||
1525 | static void ahci_irq_clear(struct ata_port *ap) | |
1526 | { | |
1527 | /* TODO */ | |
1528 | } | |
1529 | ||
7d12e780 | 1530 | static irqreturn_t ahci_interrupt(int irq, void *dev_instance) |
1da177e4 | 1531 | { |
cca3974e | 1532 | struct ata_host *host = dev_instance; |
1da177e4 LT |
1533 | struct ahci_host_priv *hpriv; |
1534 | unsigned int i, handled = 0; | |
ea6ba10b | 1535 | void __iomem *mmio; |
1da177e4 LT |
1536 | u32 irq_stat, irq_ack = 0; |
1537 | ||
1538 | VPRINTK("ENTER\n"); | |
1539 | ||
cca3974e | 1540 | hpriv = host->private_data; |
0d5ff566 | 1541 | mmio = host->iomap[AHCI_PCI_BAR]; |
1da177e4 LT |
1542 | |
1543 | /* sigh. 0xffffffff is a valid return from h/w */ | |
1544 | irq_stat = readl(mmio + HOST_IRQ_STAT); | |
1545 | irq_stat &= hpriv->port_map; | |
1546 | if (!irq_stat) | |
1547 | return IRQ_NONE; | |
1548 | ||
cca3974e | 1549 | spin_lock(&host->lock); |
1da177e4 | 1550 | |
cca3974e | 1551 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 1552 | struct ata_port *ap; |
1da177e4 | 1553 | |
67846b30 JG |
1554 | if (!(irq_stat & (1 << i))) |
1555 | continue; | |
1556 | ||
cca3974e | 1557 | ap = host->ports[i]; |
67846b30 | 1558 | if (ap) { |
df69c9c5 | 1559 | ahci_port_intr(ap); |
67846b30 JG |
1560 | VPRINTK("port %u\n", i); |
1561 | } else { | |
1562 | VPRINTK("port %u (no irq)\n", i); | |
6971ed1f | 1563 | if (ata_ratelimit()) |
cca3974e | 1564 | dev_printk(KERN_WARNING, host->dev, |
a9524a76 | 1565 | "interrupt on disabled port %u\n", i); |
1da177e4 | 1566 | } |
67846b30 JG |
1567 | |
1568 | irq_ack |= (1 << i); | |
1da177e4 LT |
1569 | } |
1570 | ||
1571 | if (irq_ack) { | |
1572 | writel(irq_ack, mmio + HOST_IRQ_STAT); | |
1573 | handled = 1; | |
1574 | } | |
1575 | ||
cca3974e | 1576 | spin_unlock(&host->lock); |
1da177e4 LT |
1577 | |
1578 | VPRINTK("EXIT\n"); | |
1579 | ||
1580 | return IRQ_RETVAL(handled); | |
1581 | } | |
1582 | ||
9a3d9eb0 | 1583 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
1da177e4 LT |
1584 | { |
1585 | struct ata_port *ap = qc->ap; | |
4447d351 | 1586 | void __iomem *port_mmio = ahci_port_base(ap); |
7d50b60b TH |
1587 | struct ahci_port_priv *pp = ap->private_data; |
1588 | ||
1589 | /* Keep track of the currently active link. It will be used | |
1590 | * in completion path to determine whether NCQ phase is in | |
1591 | * progress. | |
1592 | */ | |
1593 | pp->active_link = qc->dev->link; | |
1da177e4 | 1594 | |
12fad3f9 TH |
1595 | if (qc->tf.protocol == ATA_PROT_NCQ) |
1596 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); | |
1597 | writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); | |
1da177e4 LT |
1598 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
1599 | ||
1600 | return 0; | |
1601 | } | |
1602 | ||
78cd52d0 TH |
1603 | static void ahci_freeze(struct ata_port *ap) |
1604 | { | |
4447d351 | 1605 | void __iomem *port_mmio = ahci_port_base(ap); |
78cd52d0 TH |
1606 | |
1607 | /* turn IRQ off */ | |
1608 | writel(0, port_mmio + PORT_IRQ_MASK); | |
1609 | } | |
1610 | ||
1611 | static void ahci_thaw(struct ata_port *ap) | |
1612 | { | |
0d5ff566 | 1613 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
4447d351 | 1614 | void __iomem *port_mmio = ahci_port_base(ap); |
78cd52d0 | 1615 | u32 tmp; |
a7384925 | 1616 | struct ahci_port_priv *pp = ap->private_data; |
78cd52d0 TH |
1617 | |
1618 | /* clear IRQ */ | |
1619 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1620 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
a718728f | 1621 | writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); |
78cd52d0 | 1622 | |
7d50b60b TH |
1623 | /* turn IRQ back on, ignore BAD_PMP if PMP isn't attached */ |
1624 | tmp = pp->intr_mask; | |
1625 | if (!ap->nr_pmp_links) | |
1626 | tmp &= ~PORT_IRQ_BAD_PMP; | |
1627 | writel(tmp, port_mmio + PORT_IRQ_MASK); | |
78cd52d0 TH |
1628 | } |
1629 | ||
1630 | static void ahci_error_handler(struct ata_port *ap) | |
1631 | { | |
b51e9e5d | 1632 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
78cd52d0 | 1633 | /* restart engine */ |
4447d351 TH |
1634 | ahci_stop_engine(ap); |
1635 | ahci_start_engine(ap); | |
78cd52d0 TH |
1636 | } |
1637 | ||
1638 | /* perform recovery */ | |
7d50b60b TH |
1639 | sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset, |
1640 | ahci_hardreset, ahci_postreset, | |
1641 | sata_pmp_std_prereset, ahci_pmp_softreset, | |
1642 | sata_pmp_std_hardreset, sata_pmp_std_postreset); | |
78cd52d0 TH |
1643 | } |
1644 | ||
ad616ffb TH |
1645 | static void ahci_vt8251_error_handler(struct ata_port *ap) |
1646 | { | |
ad616ffb TH |
1647 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
1648 | /* restart engine */ | |
4447d351 TH |
1649 | ahci_stop_engine(ap); |
1650 | ahci_start_engine(ap); | |
ad616ffb TH |
1651 | } |
1652 | ||
1653 | /* perform recovery */ | |
1654 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset, | |
1655 | ahci_postreset); | |
1656 | } | |
1657 | ||
78cd52d0 TH |
1658 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) |
1659 | { | |
1660 | struct ata_port *ap = qc->ap; | |
1661 | ||
d2e75dff TH |
1662 | /* make DMA engine forget about the failed command */ |
1663 | if (qc->flags & ATA_QCFLAG_FAILED) | |
1664 | ahci_kick_engine(ap, 1); | |
78cd52d0 TH |
1665 | } |
1666 | ||
7d50b60b TH |
1667 | static void ahci_pmp_attach(struct ata_port *ap) |
1668 | { | |
1669 | void __iomem *port_mmio = ahci_port_base(ap); | |
1670 | u32 cmd; | |
1671 | ||
1672 | cmd = readl(port_mmio + PORT_CMD); | |
1673 | cmd |= PORT_CMD_PMP; | |
1674 | writel(cmd, port_mmio + PORT_CMD); | |
1675 | } | |
1676 | ||
1677 | static void ahci_pmp_detach(struct ata_port *ap) | |
1678 | { | |
1679 | void __iomem *port_mmio = ahci_port_base(ap); | |
7d50b60b TH |
1680 | u32 cmd; |
1681 | ||
1682 | cmd = readl(port_mmio + PORT_CMD); | |
1683 | cmd &= ~PORT_CMD_PMP; | |
1684 | writel(cmd, port_mmio + PORT_CMD); | |
7d50b60b TH |
1685 | } |
1686 | ||
1687 | static int ahci_pmp_read(struct ata_device *dev, int pmp, int reg, u32 *r_val) | |
1688 | { | |
1689 | struct ata_port *ap = dev->link->ap; | |
1690 | struct ata_taskfile tf; | |
1691 | int rc; | |
1692 | ||
1693 | ahci_kick_engine(ap, 0); | |
1694 | ||
1695 | sata_pmp_read_init_tf(&tf, dev, pmp, reg); | |
1696 | rc = ahci_exec_polled_cmd(ap, SATA_PMP_CTRL_PORT, &tf, 1, 0, | |
1697 | SATA_PMP_SCR_TIMEOUT); | |
1698 | if (rc == 0) { | |
1699 | ahci_tf_read(ap, &tf); | |
1700 | *r_val = sata_pmp_read_val(&tf); | |
1701 | } | |
1702 | return rc; | |
1703 | } | |
1704 | ||
1705 | static int ahci_pmp_write(struct ata_device *dev, int pmp, int reg, u32 val) | |
1706 | { | |
1707 | struct ata_port *ap = dev->link->ap; | |
1708 | struct ata_taskfile tf; | |
1709 | ||
1710 | ahci_kick_engine(ap, 0); | |
1711 | ||
1712 | sata_pmp_write_init_tf(&tf, dev, pmp, reg, val); | |
1713 | return ahci_exec_polled_cmd(ap, SATA_PMP_CTRL_PORT, &tf, 1, 0, | |
1714 | SATA_PMP_SCR_TIMEOUT); | |
1715 | } | |
1716 | ||
028a2596 AD |
1717 | static int ahci_port_resume(struct ata_port *ap) |
1718 | { | |
1719 | ahci_power_up(ap); | |
1720 | ahci_start_port(ap); | |
1721 | ||
7d50b60b TH |
1722 | if (ap->nr_pmp_links) |
1723 | ahci_pmp_attach(ap); | |
1724 | else | |
1725 | ahci_pmp_detach(ap); | |
1726 | ||
028a2596 AD |
1727 | return 0; |
1728 | } | |
1729 | ||
438ac6d5 | 1730 | #ifdef CONFIG_PM |
c1332875 TH |
1731 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) |
1732 | { | |
c1332875 TH |
1733 | const char *emsg = NULL; |
1734 | int rc; | |
1735 | ||
4447d351 | 1736 | rc = ahci_deinit_port(ap, &emsg); |
8e16f941 | 1737 | if (rc == 0) |
4447d351 | 1738 | ahci_power_down(ap); |
8e16f941 | 1739 | else { |
c1332875 | 1740 | ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); |
df69c9c5 | 1741 | ahci_start_port(ap); |
c1332875 TH |
1742 | } |
1743 | ||
1744 | return rc; | |
1745 | } | |
1746 | ||
c1332875 TH |
1747 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) |
1748 | { | |
cca3974e | 1749 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
0d5ff566 | 1750 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
c1332875 TH |
1751 | u32 ctl; |
1752 | ||
1753 | if (mesg.event == PM_EVENT_SUSPEND) { | |
1754 | /* AHCI spec rev1.1 section 8.3.3: | |
1755 | * Software must disable interrupts prior to requesting a | |
1756 | * transition of the HBA to D3 state. | |
1757 | */ | |
1758 | ctl = readl(mmio + HOST_CTL); | |
1759 | ctl &= ~HOST_IRQ_EN; | |
1760 | writel(ctl, mmio + HOST_CTL); | |
1761 | readl(mmio + HOST_CTL); /* flush */ | |
1762 | } | |
1763 | ||
1764 | return ata_pci_device_suspend(pdev, mesg); | |
1765 | } | |
1766 | ||
1767 | static int ahci_pci_device_resume(struct pci_dev *pdev) | |
1768 | { | |
cca3974e | 1769 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
c1332875 TH |
1770 | int rc; |
1771 | ||
553c4aa6 TH |
1772 | rc = ata_pci_device_do_resume(pdev); |
1773 | if (rc) | |
1774 | return rc; | |
c1332875 TH |
1775 | |
1776 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { | |
4447d351 | 1777 | rc = ahci_reset_controller(host); |
c1332875 TH |
1778 | if (rc) |
1779 | return rc; | |
1780 | ||
4447d351 | 1781 | ahci_init_controller(host); |
c1332875 TH |
1782 | } |
1783 | ||
cca3974e | 1784 | ata_host_resume(host); |
c1332875 TH |
1785 | |
1786 | return 0; | |
1787 | } | |
438ac6d5 | 1788 | #endif |
c1332875 | 1789 | |
254950cd TH |
1790 | static int ahci_port_start(struct ata_port *ap) |
1791 | { | |
cca3974e | 1792 | struct device *dev = ap->host->dev; |
254950cd | 1793 | struct ahci_port_priv *pp; |
254950cd TH |
1794 | void *mem; |
1795 | dma_addr_t mem_dma; | |
1796 | int rc; | |
1797 | ||
24dc5f33 | 1798 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
254950cd TH |
1799 | if (!pp) |
1800 | return -ENOMEM; | |
254950cd TH |
1801 | |
1802 | rc = ata_pad_alloc(ap, dev); | |
24dc5f33 | 1803 | if (rc) |
254950cd | 1804 | return rc; |
254950cd | 1805 | |
24dc5f33 TH |
1806 | mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, |
1807 | GFP_KERNEL); | |
1808 | if (!mem) | |
254950cd | 1809 | return -ENOMEM; |
254950cd TH |
1810 | memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); |
1811 | ||
1812 | /* | |
1813 | * First item in chunk of DMA memory: 32-slot command table, | |
1814 | * 32 bytes each in size | |
1815 | */ | |
1816 | pp->cmd_slot = mem; | |
1817 | pp->cmd_slot_dma = mem_dma; | |
1818 | ||
1819 | mem += AHCI_CMD_SLOT_SZ; | |
1820 | mem_dma += AHCI_CMD_SLOT_SZ; | |
1821 | ||
1822 | /* | |
1823 | * Second item: Received-FIS area | |
1824 | */ | |
1825 | pp->rx_fis = mem; | |
1826 | pp->rx_fis_dma = mem_dma; | |
1827 | ||
1828 | mem += AHCI_RX_FIS_SZ; | |
1829 | mem_dma += AHCI_RX_FIS_SZ; | |
1830 | ||
1831 | /* | |
1832 | * Third item: data area for storing a single command | |
1833 | * and its scatter-gather table | |
1834 | */ | |
1835 | pp->cmd_tbl = mem; | |
1836 | pp->cmd_tbl_dma = mem_dma; | |
1837 | ||
a7384925 KCA |
1838 | /* |
1839 | * Save off initial list of interrupts to be enabled. | |
1840 | * This could be changed later | |
1841 | */ | |
1842 | pp->intr_mask = DEF_PORT_IRQ; | |
1843 | ||
254950cd TH |
1844 | ap->private_data = pp; |
1845 | ||
df69c9c5 JG |
1846 | /* engage engines, captain */ |
1847 | return ahci_port_resume(ap); | |
254950cd TH |
1848 | } |
1849 | ||
1850 | static void ahci_port_stop(struct ata_port *ap) | |
1851 | { | |
0be0aa98 TH |
1852 | const char *emsg = NULL; |
1853 | int rc; | |
254950cd | 1854 | |
0be0aa98 | 1855 | /* de-initialize port */ |
4447d351 | 1856 | rc = ahci_deinit_port(ap, &emsg); |
0be0aa98 TH |
1857 | if (rc) |
1858 | ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); | |
254950cd TH |
1859 | } |
1860 | ||
4447d351 | 1861 | static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) |
1da177e4 | 1862 | { |
1da177e4 | 1863 | int rc; |
1da177e4 | 1864 | |
1da177e4 LT |
1865 | if (using_dac && |
1866 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { | |
1867 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
1868 | if (rc) { | |
1869 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1870 | if (rc) { | |
a9524a76 JG |
1871 | dev_printk(KERN_ERR, &pdev->dev, |
1872 | "64-bit DMA enable failed\n"); | |
1da177e4 LT |
1873 | return rc; |
1874 | } | |
1875 | } | |
1da177e4 LT |
1876 | } else { |
1877 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
1878 | if (rc) { | |
a9524a76 JG |
1879 | dev_printk(KERN_ERR, &pdev->dev, |
1880 | "32-bit DMA enable failed\n"); | |
1da177e4 LT |
1881 | return rc; |
1882 | } | |
1883 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1884 | if (rc) { | |
a9524a76 JG |
1885 | dev_printk(KERN_ERR, &pdev->dev, |
1886 | "32-bit consistent DMA enable failed\n"); | |
1da177e4 LT |
1887 | return rc; |
1888 | } | |
1889 | } | |
1da177e4 LT |
1890 | return 0; |
1891 | } | |
1892 | ||
4447d351 | 1893 | static void ahci_print_info(struct ata_host *host) |
1da177e4 | 1894 | { |
4447d351 TH |
1895 | struct ahci_host_priv *hpriv = host->private_data; |
1896 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
1897 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
1da177e4 LT |
1898 | u32 vers, cap, impl, speed; |
1899 | const char *speed_s; | |
1900 | u16 cc; | |
1901 | const char *scc_s; | |
1902 | ||
1903 | vers = readl(mmio + HOST_VERSION); | |
1904 | cap = hpriv->cap; | |
1905 | impl = hpriv->port_map; | |
1906 | ||
1907 | speed = (cap >> 20) & 0xf; | |
1908 | if (speed == 1) | |
1909 | speed_s = "1.5"; | |
1910 | else if (speed == 2) | |
1911 | speed_s = "3"; | |
1912 | else | |
1913 | speed_s = "?"; | |
1914 | ||
1915 | pci_read_config_word(pdev, 0x0a, &cc); | |
c9f89475 | 1916 | if (cc == PCI_CLASS_STORAGE_IDE) |
1da177e4 | 1917 | scc_s = "IDE"; |
c9f89475 | 1918 | else if (cc == PCI_CLASS_STORAGE_SATA) |
1da177e4 | 1919 | scc_s = "SATA"; |
c9f89475 | 1920 | else if (cc == PCI_CLASS_STORAGE_RAID) |
1da177e4 LT |
1921 | scc_s = "RAID"; |
1922 | else | |
1923 | scc_s = "unknown"; | |
1924 | ||
a9524a76 JG |
1925 | dev_printk(KERN_INFO, &pdev->dev, |
1926 | "AHCI %02x%02x.%02x%02x " | |
1da177e4 LT |
1927 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
1928 | , | |
1da177e4 LT |
1929 | |
1930 | (vers >> 24) & 0xff, | |
1931 | (vers >> 16) & 0xff, | |
1932 | (vers >> 8) & 0xff, | |
1933 | vers & 0xff, | |
1934 | ||
1935 | ((cap >> 8) & 0x1f) + 1, | |
1936 | (cap & 0x1f) + 1, | |
1937 | speed_s, | |
1938 | impl, | |
1939 | scc_s); | |
1940 | ||
a9524a76 JG |
1941 | dev_printk(KERN_INFO, &pdev->dev, |
1942 | "flags: " | |
203ef6c4 TH |
1943 | "%s%s%s%s%s%s%s" |
1944 | "%s%s%s%s%s%s%s\n" | |
1da177e4 | 1945 | , |
1da177e4 LT |
1946 | |
1947 | cap & (1 << 31) ? "64bit " : "", | |
1948 | cap & (1 << 30) ? "ncq " : "", | |
203ef6c4 | 1949 | cap & (1 << 29) ? "sntf " : "", |
1da177e4 LT |
1950 | cap & (1 << 28) ? "ilck " : "", |
1951 | cap & (1 << 27) ? "stag " : "", | |
1952 | cap & (1 << 26) ? "pm " : "", | |
1953 | cap & (1 << 25) ? "led " : "", | |
1954 | ||
1955 | cap & (1 << 24) ? "clo " : "", | |
1956 | cap & (1 << 19) ? "nz " : "", | |
1957 | cap & (1 << 18) ? "only " : "", | |
1958 | cap & (1 << 17) ? "pmp " : "", | |
1959 | cap & (1 << 15) ? "pio " : "", | |
1960 | cap & (1 << 14) ? "slum " : "", | |
1961 | cap & (1 << 13) ? "part " : "" | |
1962 | ); | |
1963 | } | |
1964 | ||
24dc5f33 | 1965 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 LT |
1966 | { |
1967 | static int printed_version; | |
4447d351 TH |
1968 | struct ata_port_info pi = ahci_port_info[ent->driver_data]; |
1969 | const struct ata_port_info *ppi[] = { &pi, NULL }; | |
24dc5f33 | 1970 | struct device *dev = &pdev->dev; |
1da177e4 | 1971 | struct ahci_host_priv *hpriv; |
4447d351 TH |
1972 | struct ata_host *host; |
1973 | int i, rc; | |
1da177e4 LT |
1974 | |
1975 | VPRINTK("ENTER\n"); | |
1976 | ||
12fad3f9 TH |
1977 | WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
1978 | ||
1da177e4 | 1979 | if (!printed_version++) |
a9524a76 | 1980 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 1981 | |
4447d351 | 1982 | /* acquire resources */ |
24dc5f33 | 1983 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
1984 | if (rc) |
1985 | return rc; | |
1986 | ||
0d5ff566 TH |
1987 | rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); |
1988 | if (rc == -EBUSY) | |
24dc5f33 | 1989 | pcim_pin_device(pdev); |
0d5ff566 | 1990 | if (rc) |
24dc5f33 | 1991 | return rc; |
1da177e4 | 1992 | |
24dc5f33 TH |
1993 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
1994 | if (!hpriv) | |
1995 | return -ENOMEM; | |
417a1a6d TH |
1996 | hpriv->flags |= (unsigned long)pi.private_data; |
1997 | ||
1998 | if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev)) | |
1999 | pci_intx(pdev, 1); | |
1da177e4 | 2000 | |
4447d351 | 2001 | /* save initial config */ |
417a1a6d | 2002 | ahci_save_initial_config(pdev, hpriv); |
1da177e4 | 2003 | |
4447d351 | 2004 | /* prepare host */ |
274c1fde | 2005 | if (hpriv->cap & HOST_CAP_NCQ) |
4447d351 | 2006 | pi.flags |= ATA_FLAG_NCQ; |
1da177e4 | 2007 | |
7d50b60b TH |
2008 | if (hpriv->cap & HOST_CAP_PMP) |
2009 | pi.flags |= ATA_FLAG_PMP; | |
2010 | ||
4447d351 TH |
2011 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map)); |
2012 | if (!host) | |
2013 | return -ENOMEM; | |
2014 | host->iomap = pcim_iomap_table(pdev); | |
2015 | host->private_data = hpriv; | |
2016 | ||
2017 | for (i = 0; i < host->n_ports; i++) { | |
dab632e8 JG |
2018 | struct ata_port *ap = host->ports[i]; |
2019 | void __iomem *port_mmio = ahci_port_base(ap); | |
4447d351 | 2020 | |
cbcdd875 TH |
2021 | ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar"); |
2022 | ata_port_pbar_desc(ap, AHCI_PCI_BAR, | |
2023 | 0x100 + ap->port_no * 0x80, "port"); | |
2024 | ||
dab632e8 | 2025 | /* standard SATA port setup */ |
203ef6c4 | 2026 | if (hpriv->port_map & (1 << i)) |
4447d351 | 2027 | ap->ioaddr.cmd_addr = port_mmio; |
dab632e8 JG |
2028 | |
2029 | /* disabled/not-implemented port */ | |
2030 | else | |
2031 | ap->ops = &ata_dummy_port_ops; | |
4447d351 | 2032 | } |
d447df14 | 2033 | |
4447d351 TH |
2034 | /* initialize adapter */ |
2035 | rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); | |
1da177e4 | 2036 | if (rc) |
24dc5f33 | 2037 | return rc; |
1da177e4 | 2038 | |
4447d351 TH |
2039 | rc = ahci_reset_controller(host); |
2040 | if (rc) | |
2041 | return rc; | |
1da177e4 | 2042 | |
4447d351 TH |
2043 | ahci_init_controller(host); |
2044 | ahci_print_info(host); | |
1da177e4 | 2045 | |
4447d351 TH |
2046 | pci_set_master(pdev); |
2047 | return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED, | |
2048 | &ahci_sht); | |
907f4678 | 2049 | } |
1da177e4 LT |
2050 | |
2051 | static int __init ahci_init(void) | |
2052 | { | |
b7887196 | 2053 | return pci_register_driver(&ahci_pci_driver); |
1da177e4 LT |
2054 | } |
2055 | ||
1da177e4 LT |
2056 | static void __exit ahci_exit(void) |
2057 | { | |
2058 | pci_unregister_driver(&ahci_pci_driver); | |
2059 | } | |
2060 | ||
2061 | ||
2062 | MODULE_AUTHOR("Jeff Garzik"); | |
2063 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); | |
2064 | MODULE_LICENSE("GPL"); | |
2065 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); | |
6885433c | 2066 | MODULE_VERSION(DRV_VERSION); |
1da177e4 LT |
2067 | |
2068 | module_init(ahci_init); | |
2069 | module_exit(ahci_exit); |